#ifndef EAGLE_H
#define EAGLE_H

#define  BCH_SYNDRM_ADDR 0xE084
    #define SYNDRM_ADDR_MASK 0x7FFFFFF0
    #define SYNDRM_ADDR_SHIFT 4
#define  BKD0_STATUS 0xA140
    #define BKD0_STATUS_DONE_MASK 0x00000001
    #define BKD0_STATUS_DONE_SHIFT 0
    #define BKD0_STATUS_DIP_END_MASK 0x07FFFFFC
    #define BKD0_STATUS_DIP_END_SHIFT 2
    #define BKD0_STATUS_ERROR_MASK 0xF0000000
    #define BKD0_STATUS_ERROR_SHIFT 28
#define  BKD0_TRIG 0xA13C
    #define BKD0_TRIG_INTRA_MASK 0x00000001
    #define BKD0_TRIG_INTRA_SHIFT 0
    #define BKD0_TRIG_CBP_MASK 0xFC000000
    #define BKD0_TRIG_CBP_SHIFT 26
#define  BKD1_STATUS 0xA540
    #define BKD1_STATUS_DONE_MASK 0x00000001
    #define BKD1_STATUS_DONE_SHIFT 0
    #define BKD1_STATUS_DIP_END_MASK 0x07FFFFFC
    #define BKD1_STATUS_DIP_END_SHIFT 2
    #define BKD1_STATUS_ERROR_MASK 0xF0000000
    #define BKD1_STATUS_ERROR_SHIFT 28
#define  BKD1_TRIG 0xA53C
    #define BKD1_TRIG_INTRA_MASK 0x00000001
    #define BKD1_TRIG_INTRA_SHIFT 0
    #define BKD1_TRIG_CBP_MASK 0xFC000000
    #define BKD1_TRIG_CBP_SHIFT 26
#define  CCSPI_HOST_READY_EN 0x10D8
    #define CCSPI_HOST_READY_EN_MASK 0x00000001
    #define CCSPI_HOST_READY_EN_SHIFT 0
#define  CCSPI_OPTIONS 0x10E4
    #define CCSPI_ALLOW_RX_PKT_WO_CR_MASK 0x00000001
    #define CCSPI_ALLOW_RX_PKT_WO_CR_SHIFT 0
    #define CCSPI_ALLOW_RX_PKT_WO_HR_MASK 0x00000002
    #define CCSPI_ALLOW_RX_PKT_WO_HR_SHIFT 1
#define  CCSPI_PORT_CTRL 0x10DC
    #define CCSPI_PORT_CTRL_MASK 0x00000001
    #define CCSPI_PORT_CTRL_SHIFT 0
#define  CCSPI_QB_TIMEOUT 0x10E0
    #define CCSPI_QB_TIMEOUT_LIMIT_MASK 0x0000FFFF
    #define CCSPI_QB_TIMEOUT_LIMIT_SHIFT 0
    #define CCSPI_QB_TIMEOUT_ENABLE_MASK 0x00010000
    #define CCSPI_QB_TIMEOUT_ENABLE_SHIFT 16
#define  CCSPI_RX_ADDR 0x10D4
    #define CCSPI_RX_PACKET_TOP_ADDR_MASK 0x00FFFFFF
    #define CCSPI_RX_PACKET_TOP_ADDR_SHIFT 0
#define  CCSPI_RX_STATUS 0x10D0
    #define CCSPI_RX_PACKET_SIZE_MASK 0x00001FFF
    #define CCSPI_RX_PACKET_SIZE_SHIFT 0
    #define CCSPI_RX_PACKET_FIRST_MASK 0x00002000
    #define CCSPI_RX_PACKET_FIRST_SHIFT 13
    #define CCSPI_RX_PACKET_LAST_MASK 0x00004000
    #define CCSPI_RX_PACKET_LAST_SHIFT 14
    #define CCSPI_RX_PACKET_CHANNEL_MASK 0x00008000
    #define CCSPI_RX_PACKET_CHANNEL_SHIFT 15
    #define CCSPI_MCARD_ERROR_MASK 0x00010000
    #define CCSPI_MCARD_ERROR_SHIFT 16
    #define CCSPI_MCARD_DATA_AVAILABLE_MASK 0x00020000
    #define CCSPI_MCARD_DATA_AVAILABLE_SHIFT 17
    #define CCSPI_MCARD_FIRST_PACKET_MASK 0x00040000
    #define CCSPI_MCARD_FIRST_PACKET_SHIFT 18
    #define CCSPI_MCARD_LAST_PACKET_MASK 0x00080000
    #define CCSPI_MCARD_LAST_PACKET_SHIFT 19
    #define CCSPI_MCARD_EXTENDED_CHANNEL_MASK 0x00100000
    #define CCSPI_MCARD_EXTENDED_CHANNEL_SHIFT 20
    #define CCSPI_MCARD_READY_MASK 0x00200000
    #define CCSPI_MCARD_READY_SHIFT 21
    #define CCSPI_HOST_ERROR_MASK 0x00400000
    #define CCSPI_HOST_ERROR_SHIFT 22
    #define CCSPI_HOST_DATA_AVAILABLE_MASK 0x00800000
    #define CCSPI_HOST_DATA_AVAILABLE_SHIFT 23
    #define CCSPI_HOST_FIRST_PACKET_MASK 0x01000000
    #define CCSPI_HOST_FIRST_PACKET_SHIFT 24
    #define CCSPI_HOST_LAST_PACKET_MASK 0x02000000
    #define CCSPI_HOST_LAST_PACKET_SHIFT 25
    #define CCSPI_HOST_EXTENDED_CHANNEL_MASK 0x04000000
    #define CCSPI_HOST_EXTENDED_CHANNEL_SHIFT 26
    #define CCSPI_HOST_READY_MASK 0x08000000
    #define CCSPI_HOST_READY_SHIFT 27
#define  CCSPI_TX_ADDR 0x10CC
    #define CCSPI_TX_PACKET_TOP_ADDR_MASK 0x00FFFFFF
    #define CCSPI_TX_PACKET_TOP_ADDR_SHIFT 0
#define  CCSPI_TX_CONTROL 0x10C8
    #define CCSPI_TX_PACKET_SIZE_MASK 0x00001FFF
    #define CCSPI_TX_PACKET_SIZE_SHIFT 0
    #define CCSPI_TX_PACKET_FIRST_MASK 0x00002000
    #define CCSPI_TX_PACKET_FIRST_SHIFT 13
    #define CCSPI_TX_PACKET_LAST_MASK 0x00004000
    #define CCSPI_TX_PACKET_LAST_SHIFT 14
    #define CCSPI_TX_PACKET_CHANNEL_MASK 0x00008000
    #define CCSPI_TX_PACKET_CHANNEL_SHIFT 15
#define  CG_BLK_CLK_STOP0 0x0130
    #define DMA_MCLK_STOP_MASK 0x00000001
    #define DMA_MCLK_STOP_SHIFT 0
    #define TSD_MCLK_STOP_MASK 0x00000004
    #define TSD_MCLK_STOP_SHIFT 2
    #define TSD_SCLK_STOP_MASK 0x00000008
    #define TSD_SCLK_STOP_SHIFT 3
    #define TSD_DCLK_STOP_MASK 0x00000010
    #define TSD_DCLK_STOP_SHIFT 4
    #define MPP_ENC_MCLK_STOP_MASK 0x00000020
    #define MPP_ENC_MCLK_STOP_SHIFT 5
    #define MPP_ENC_ECLK_STOP_MASK 0x00000040
    #define MPP_ENC_ECLK_STOP_SHIFT 6
    #define MPP_DEC_MCLK_STOP_MASK 0x00000080
    #define MPP_DEC_MCLK_STOP_SHIFT 7
    #define MPP_DEC_ECLK_STOP_MASK 0x00000100
    #define MPP_DEC_ECLK_STOP_SHIFT 8
    #define VHE_MCLK_STOP_MASK 0x00000200
    #define VHE_MCLK_STOP_SHIFT 9
    #define VHE_SCLK_STOP_MASK 0x00000400
    #define VHE_SCLK_STOP_SHIFT 10
    #define VHE_HCLK_STOP_MASK 0x00000800
    #define VHE_HCLK_STOP_SHIFT 11
    #define PROC0_MCLK_STOP_MASK 0x00010000
    #define PROC0_MCLK_STOP_SHIFT 16
    #define PROC0_SCLK_STOP_MASK 0x00020000
    #define PROC0_SCLK_STOP_SHIFT 17
    #define PROC1_MCLK_STOP_MASK 0x00040000
    #define PROC1_MCLK_STOP_SHIFT 18
    #define PROC1_SCLK_STOP_MASK 0x00080000
    #define PROC1_SCLK_STOP_SHIFT 19
    #define PROC2_MCLK_STOP_MASK 0x00100000
    #define PROC2_MCLK_STOP_SHIFT 20
    #define PROC2_SCLK_STOP_MASK 0x00200000
    #define PROC2_SCLK_STOP_SHIFT 21
    #define PROC3_MCLK_STOP_MASK 0x00400000
    #define PROC3_MCLK_STOP_SHIFT 22
    #define PROC3_SCLK_STOP_MASK 0x00800000
    #define PROC3_SCLK_STOP_SHIFT 23
    #define PROC4_MCLK_STOP_MASK 0x01000000
    #define PROC4_MCLK_STOP_SHIFT 24
    #define PROC4_SCLK_STOP_MASK 0x02000000
    #define PROC4_SCLK_STOP_SHIFT 25
    #define SEQ0_MCLK_STOP_MASK 0x04000000
    #define SEQ0_MCLK_STOP_SHIFT 26
    #define SEQ1_MCLK_STOP_MASK 0x08000000
    #define SEQ1_MCLK_STOP_SHIFT 27
    #define DMACLK_STOP_MASK 0x20000000
    #define DMACLK_STOP_SHIFT 29
    #define ECCCLK_STOP_MASK 0x80000000
    #define ECCCLK_STOP_SHIFT 31
#define  CG_BLK_CLK_STOP1 0x0134
    #define USBD_MCLK_STOP_MASK 0x00000001
    #define USBD_MCLK_STOP_SHIFT 0
    #define USBH_MCLK_STOP_MASK 0x00000004
    #define USBH_MCLK_STOP_SHIFT 2
    #define USBH_SCLK_STOP_MASK 0x00000008
    #define USBH_SCLK_STOP_SHIFT 3
    #define ETH0_MCLK_STOP_MASK 0x00000010
    #define ETH0_MCLK_STOP_SHIFT 4
    #define ETH0_SCLK_STOP_MASK 0x00000020
    #define ETH0_SCLK_STOP_SHIFT 5
    #define SATA_MCLK_STOP_MASK 0x00000800
    #define SATA_MCLK_STOP_SHIFT 11
    #define BCLK1_STOP_MASK 0x00002000
    #define BCLK1_STOP_SHIFT 13
    #define HCLK_STOP_MASK 0x00004000
    #define HCLK_STOP_SHIFT 14
    #define SPDIFRX_MCLK_STOP_MASK 0x00040000
    #define SPDIFRX_MCLK_STOP_SHIFT 18
    #define SPDIFRX_SCLK_STOP_MASK 0x00080000
    #define SPDIFRX_SCLK_STOP_SHIFT 19
    #define SPDIFRX_CLK_STOP_MASK 0x00100000
    #define SPDIFRX_CLK_STOP_SHIFT 20
    #define FCLK_STOP_MASK 0x10000000
    #define FCLK_STOP_SHIFT 28
    #define MAFE0_CLK_STOP_MASK 0x20000000
    #define MAFE0_CLK_STOP_SHIFT 29
    #define MAFE1_CLK_STOP_MASK 0x40000000
    #define MAFE1_CLK_STOP_SHIFT 30
#define  CG_BLK_CLK_STOP2 0x0138
    #define FES_FCLK_STOP_MASK 0x00000080
    #define FES_FCLK_STOP_SHIFT 7
    #define FES_MCLK_STOP_MASK 0x00000100
    #define FES_MCLK_STOP_SHIFT 8
    #define FES_SCLK_STOP_MASK 0x00000200
    #define FES_SCLK_STOP_SHIFT 9
    #define SMCC0_CLK_STOP_MASK 0x00000800
    #define SMCC0_CLK_STOP_SHIFT 11
    #define SMCC1_CLK_STOP_MASK 0x00040000
    #define SMCC1_CLK_STOP_SHIFT 18
    #define SMCCCLK_STOP_MASK 0x00100000
    #define SMCCCLK_STOP_SHIFT 20
    #define NFC_MCLK_STOP_MASK 0x00400000
    #define NFC_MCLK_STOP_SHIFT 22
    #define NFC_SCLK_STOP_MASK 0x00800000
    #define NFC_SCLK_STOP_SHIFT 23
#define  CG_CLK_SRC_EN0 0x0120
    #define MCLK_SRC_EN_MASK 0x00000001
    #define MCLK_SRC_EN_SHIFT 0
    #define SCLK_SRC_EN_MASK 0x00000002
    #define SCLK_SRC_EN_SHIFT 1
    #define SEQ0CLK_SRC_EN_MASK 0x00000004
    #define SEQ0CLK_SRC_EN_SHIFT 2
    #define SEQ1CLK_SRC_EN_MASK 0x00000008
    #define SEQ1CLK_SRC_EN_SHIFT 3
    #define CALCLK_SRC_EN_MASK 0x00000010
    #define CALCLK_SRC_EN_SHIFT 4
    #define MRCLK_SRC_EN_MASK 0x00000020
    #define MRCLK_SRC_EN_SHIFT 5
    #define XCLK_SRC_EN_MASK 0x00000040
    #define XCLK_SRC_EN_SHIFT 6
    #define BCLK_SRC_EN_MASK 0x00000080
    #define BCLK_SRC_EN_SHIFT 7
    #define DCLK_SRC_EN_MASK 0x00000100
    #define DCLK_SRC_EN_SHIFT 8
    #define ECLK_SRC_EN_MASK 0x00000400
    #define ECLK_SRC_EN_SHIFT 10
    #define VCLK_SRC_EN_MASK 0x00000800
    #define VCLK_SRC_EN_SHIFT 11
    #define CCLK_SRC_EN_MASK 0x00001000
    #define CCLK_SRC_EN_SHIFT 12
    #define UCLK_SRC_EN_MASK 0x00002000
    #define UCLK_SRC_EN_SHIFT 13
    #define HUECLK_SRC_EN_MASK 0x00004000
    #define HUECLK_SRC_EN_SHIFT 14
    #define GVPCLK_SRC_EN_MASK 0x00008000
    #define GVPCLK_SRC_EN_SHIFT 15
    #define GVDCLK_SRC_EN_MASK 0x00010000
    #define GVDCLK_SRC_EN_SHIFT 16
    #define PROC0CLK_SRC_EN_MASK 0x00020000
    #define PROC0CLK_SRC_EN_SHIFT 17
    #define PROC1CLK_SRC_EN_MASK 0x00040000
    #define PROC1CLK_SRC_EN_SHIFT 18
    #define PROC2CLK_SRC_EN_MASK 0x00080000
    #define PROC2CLK_SRC_EN_SHIFT 19
    #define PROC3CLK_SRC_EN_MASK 0x00100000
    #define PROC3CLK_SRC_EN_SHIFT 20
    #define PROC4CLK_SRC_EN_MASK 0x00200000
    #define PROC4CLK_SRC_EN_SHIFT 21
    #define I2SSYSCLK_SRC_EN_MASK 0x02000000
    #define I2SSYSCLK_SRC_EN_SHIFT 25
    #define SATACLK_SRC_EN_MASK 0x08000000
    #define SATACLK_SRC_EN_SHIFT 27
    #define ETHR0CLK_SRC_EN_MASK 0x10000000
    #define ETHR0CLK_SRC_EN_SHIFT 28
#define  CG_CLK_SRC_EN1 0x0124
    #define ECCCLK_SRC_EN_MASK 0x00000002
    #define ECCCLK_SRC_EN_SHIFT 1
    #define DMACLK_SRC_EN_MASK 0x00000004
    #define DMACLK_SRC_EN_SHIFT 2
    #define BCLK1_SRC_EN_MASK 0x00000020
    #define BCLK1_SRC_EN_SHIFT 5
    #define HCLK_SRC_EN_MASK 0x00000040
    #define HCLK_SRC_EN_SHIFT 6
    #define FCLK_SRC_EN_MASK 0x00000200
    #define FCLK_SRC_EN_SHIFT 9
    #define SMCCCLK_SRC_EN_MASK 0x00000800
    #define SMCCCLK_SRC_EN_SHIFT 11
    #define FREECLK_SRC_EN_MASK 0x00001000
    #define FREECLK_SRC_EN_SHIFT 12
#define  CG_CLK_SRC_EN2 0x0128
    #define I2SXTL_CLR_MASK 0x10000000
    #define I2SXTL_CLR_SHIFT 28
    #define I2SXTL_CKE_MASK 0x20000000
    #define I2SXTL_CKE_SHIFT 29
    #define XTL_CLR_MASK 0x40000000
    #define XTL_CLR_SHIFT 30
    #define XTL_CKE_MASK 0x80000000
    #define XTL_CKE_SHIFT 31
#define  CG_CLK_SRC_SEL0 0x0140
    #define SEQ0CLK_SRC_SEL_MASK 0x000000FF
    #define SEQ0CLK_SRC_SEL_SHIFT 0
    #define SEQ1CLK_SRC_SEL_MASK 0x0000FF00
    #define SEQ1CLK_SRC_SEL_SHIFT 8
    #define CALCLK_SRC_SEL_MASK 0x00FF0000
    #define CALCLK_SRC_SEL_SHIFT 16
#define  CG_CLK_SRC_SEL1 0x0144
    #define MCLK_SRC_SEL_MASK 0x000000FF
    #define MCLK_SRC_SEL_SHIFT 0
    #define SCLK_SRC_SEL_MASK 0x0000FF00
    #define SCLK_SRC_SEL_SHIFT 8
    #define MRCLK_SRC_SEL_MASK 0x00FF0000
    #define MRCLK_SRC_SEL_SHIFT 16
#define  CG_CLK_SRC_SEL10 0x0168
    #define ECCCLK_SRC_SEL_MASK 0x0000FF00
    #define ECCCLK_SRC_SEL_SHIFT 8
    #define DMACLK_SRC_SEL_MASK 0x00FF0000
    #define DMACLK_SRC_SEL_SHIFT 16
    #define BCLK1_SRC_SEL_MASK 0xFF000000
    #define BCLK1_SRC_SEL_SHIFT 24
#define  CG_CLK_SRC_SEL11 0x016C
    #define HCLK_SRC_SEL_MASK 0x000000FF
    #define HCLK_SRC_SEL_SHIFT 0
    #define FCLK_SRC_SEL_MASK 0xFF000000
    #define FCLK_SRC_SEL_SHIFT 24
#define  CG_CLK_SRC_SEL2 0x0148
    #define XCLK_SRC_SEL_MASK 0x000000FF
    #define XCLK_SRC_SEL_SHIFT 0
    #define BCLK_SRC_SEL_MASK 0x0000FF00
    #define BCLK_SRC_SEL_SHIFT 8
    #define DCLK_SRC_SEL_MASK 0x00FF0000
    #define DCLK_SRC_SEL_SHIFT 16
#define  CG_CLK_SRC_SEL3 0x014C
    #define ECLK_SRC_SEL_MASK 0x000000FF
    #define ECLK_SRC_SEL_SHIFT 0
    #define VCLK_SRC_SEL_MASK 0x0000FF00
    #define VCLK_SRC_SEL_SHIFT 8
    #define CCLK_SRC_SEL_MASK 0x00FF0000
    #define CCLK_SRC_SEL_SHIFT 16
    #define UCLK_SRC_SEL_MASK 0xFF000000
    #define UCLK_SRC_SEL_SHIFT 24
#define  CG_CLK_SRC_SEL4 0x0150
    #define HUECLK_SRC_SEL_MASK 0x000000FF
    #define HUECLK_SRC_SEL_SHIFT 0
    #define GVPCLK_SRC_SEL_MASK 0x0000FF00
    #define GVPCLK_SRC_SEL_SHIFT 8
    #define GVDCLK_SRC_SEL_MASK 0x00FF0000
    #define GVDCLK_SRC_SEL_SHIFT 16
#define  CG_CLK_SRC_SEL5 0x0154
    #define PROC0CLK_SRC_SEL_MASK 0x000000FF
    #define PROC0CLK_SRC_SEL_SHIFT 0
    #define PROC1CLK_SRC_SEL_MASK 0x0000FF00
    #define PROC1CLK_SRC_SEL_SHIFT 8
#define  CG_CLK_SRC_SEL6 0x0158
    #define PROC2CLK_SRC_SEL_MASK 0x000000FF
    #define PROC2CLK_SRC_SEL_SHIFT 0
    #define PROC3CLK_SRC_SEL_MASK 0x0000FF00
    #define PROC3CLK_SRC_SEL_SHIFT 8
    #define PROC4CLK_SRC_SEL_MASK 0x00FF0000
    #define PROC4CLK_SRC_SEL_SHIFT 16
#define  CG_CLK_SRC_SEL7 0x015C
    #define I2SSYSCLK_SRC_SEL_MASK 0x0000F000
    #define I2SSYSCLK_SRC_SEL_SHIFT 12
#define  CG_CLK_SRC_SEL9 0x0164
    #define ETHR0CLK_SRC_SEL_MASK 0x0000000F
    #define ETHR0CLK_SRC_SEL_SHIFT 0
    #define SATACLK_SRC_SEL_MASK 0x0000F000
    #define SATACLK_SRC_SEL_SHIFT 12
    #define SMCCCLK_SRC_SEL_MASK 0x0F000000
    #define SMCCCLK_SRC_SEL_SHIFT 24
#define  CG_CLK_STOP0 0x012C
    #define MCLK_STOP_MASK 0x00000001
    #define MCLK_STOP_SHIFT 0
    #define SEQ0CLK_STOP_MASK 0x00000004
    #define SEQ0CLK_STOP_SHIFT 2
    #define SEQ1CLK_STOP_MASK 0x00000008
    #define SEQ1CLK_STOP_SHIFT 3
    #define CALCLK_STOP_MASK 0x00000010
    #define CALCLK_STOP_SHIFT 4
    #define MRCLK_STOP_MASK 0x00000020
    #define MRCLK_STOP_SHIFT 5
    #define XCLK_STOP_MASK 0x00000040
    #define XCLK_STOP_SHIFT 6
    #define BCLK_STOP_MASK 0x00000080
    #define BCLK_STOP_SHIFT 7
    #define DCLK_STOP_MASK 0x00000100
    #define DCLK_STOP_SHIFT 8
    #define ECLK_STOP_MASK 0x00000400
    #define ECLK_STOP_SHIFT 10
    #define VCLK_STOP_MASK 0x00000800
    #define VCLK_STOP_SHIFT 11
    #define CCLK_STOP_MASK 0x00001000
    #define CCLK_STOP_SHIFT 12
    #define UCLK_STOP_MASK 0x00002000
    #define UCLK_STOP_SHIFT 13
    #define HUECLK_STOP_MASK 0x00004000
    #define HUECLK_STOP_SHIFT 14
    #define GVPCLK_STOP_MASK 0x00008000
    #define GVPCLK_STOP_SHIFT 15
    #define GVDCLK_STOP_MASK 0x00010000
    #define GVDCLK_STOP_SHIFT 16
    #define PROC0CLK_STOP_MASK 0x00020000
    #define PROC0CLK_STOP_SHIFT 17
    #define PROC1CLK_STOP_MASK 0x00040000
    #define PROC1CLK_STOP_SHIFT 18
    #define PROC2CLK_STOP_MASK 0x00080000
    #define PROC2CLK_STOP_SHIFT 19
    #define PROC3CLK_STOP_MASK 0x00100000
    #define PROC3CLK_STOP_SHIFT 20
    #define PROC4CLK_STOP_MASK 0x00200000
    #define PROC4CLK_STOP_SHIFT 21
    #define I2SSYSCLK_STOP_MASK 0x02000000
    #define I2SSYSCLK_STOP_SHIFT 25
    #define SATACLK_STOP_MASK 0x08000000
    #define SATACLK_STOP_SHIFT 27
    #define ETHR0CLK_STOP_MASK 0x10000000
    #define ETHR0CLK_STOP_SHIFT 28
    #define VHE_INPUT0_EN_MASK 0x40000000
    #define VHE_INPUT0_EN_SHIFT 30
    #define VHE_INPUT1_EN_MASK 0x80000000
    #define VHE_INPUT1_EN_SHIFT 31
#define  CG_DBUS_CLK_SEL 0x0090
    #define DBCLK0_SEL_MASK 0x000000FF
    #define DBCLK0_SEL_SHIFT 0
    #define DBCLK1_SEL_MASK 0x0000FF00
    #define DBCLK1_SEL_SHIFT 8
#define  CG_DFT 0x0110
    #define REG_TRIG_DIS_MASK 0x00000001
    #define REG_TRIG_DIS_SHIFT 0
    #define TEST_CNT_STOP_MASK 0x40000000
    #define TEST_CNT_STOP_SHIFT 30
    #define TEST_CNT_START_MASK 0x80000000
    #define TEST_CNT_START_SHIFT 31
#define  CG_DUMMY_REG 0x00FC
    #define CG_DUMMY_REG_DUMMY_BITS_MASK 0xFFFFFFFF
    #define CG_DUMMY_REG_DUMMY_BITS_SHIFT 0
#define  CG_DYNAMIC_BLK_STOP 0x0068
    #define SMS_SMSCLK_GATE_MASK 0x00000001
    #define SMS_SMSCLK_GATE_SHIFT 0
    #define VNE_VCLK_GATE_MASK 0x00000004
    #define VNE_VCLK_GATE_SHIFT 2
    #define FES_FCLK_GATE_MASK 0x00000008
    #define FES_FCLK_GATE_SHIFT 3
#define  CG_GENLOCK_CTRL 0x0084
    #define CG_GENLOCK_CTRL_VHE0_CLR_CNT_MASK 0x00000001
    #define CG_GENLOCK_CTRL_VHE0_CLR_CNT_SHIFT 0
    #define CG_GENLOCK_CTRL_VHE1_CLR_CNT_MASK 0x00000002
    #define CG_GENLOCK_CTRL_VHE1_CLR_CNT_SHIFT 1
    #define CG_GENLOCK_CTRL_I2S0_CLR_CNT_MASK 0x00000004
    #define CG_GENLOCK_CTRL_I2S0_CLR_CNT_SHIFT 2
    #define CG_GENLOCK_CTRL_I2S1_CLR_CNT_MASK 0x00000008
    #define CG_GENLOCK_CTRL_I2S1_CLR_CNT_SHIFT 3
    #define CG_GENLOCK_CTRL_SPDIF_RX_CLR_CNT_MASK 0x00000010
    #define CG_GENLOCK_CTRL_SPDIF_RX_CLR_CNT_SHIFT 4
    #define TSD_CLR_CNT_MASK 0x00000100
    #define TSD_CLR_CNT_SHIFT 8
    #define CG_GENLOCK_CTRL_VHE0_EN_CNT_MASK 0x00000400
    #define CG_GENLOCK_CTRL_VHE0_EN_CNT_SHIFT 10
    #define CG_GENLOCK_CTRL_VHE1_EN_CNT_MASK 0x00000800
    #define CG_GENLOCK_CTRL_VHE1_EN_CNT_SHIFT 11
    #define CG_GENLOCK_CTRL_I2S0_EN_CNT_MASK 0x00001000
    #define CG_GENLOCK_CTRL_I2S0_EN_CNT_SHIFT 12
    #define CG_GENLOCK_CTRL_I2S1_EN_CNT_MASK 0x00002000
    #define CG_GENLOCK_CTRL_I2S1_EN_CNT_SHIFT 13
    #define CG_GENLOCK_CTRL_SPDIF_RX_EN_CNT_MASK 0x00004000
    #define CG_GENLOCK_CTRL_SPDIF_RX_EN_CNT_SHIFT 14
    #define TSD_EN_CNT_MASK 0x00020000
    #define TSD_EN_CNT_SHIFT 17
    #define VHE0_SAMPLE_CNT_MASK 0x00100000
    #define VHE0_SAMPLE_CNT_SHIFT 20
    #define VHE1_SAMPLE_CNT_MASK 0x00200000
    #define VHE1_SAMPLE_CNT_SHIFT 21
    #define I2S0_SAMPLE_CNT_MASK 0x00400000
    #define I2S0_SAMPLE_CNT_SHIFT 22
    #define I2S1_SAMPLE_CNT_MASK 0x00800000
    #define I2S1_SAMPLE_CNT_SHIFT 23
    #define SPDIF_RX_SAMPLE_CNT_MASK 0x01000000
    #define SPDIF_RX_SAMPLE_CNT_SHIFT 24
    #define TSD_SAMPLE_CNT_MASK 0x10000000
    #define TSD_SAMPLE_CNT_SHIFT 28
#define  CG_I2SSYSCLK_FREQ 0x01A0
    #define I2SSYSCLK_DIV_MASK 0x0000000E
    #define I2SSYSCLK_DIV_SHIFT 1
    #define I2SSYSCLK_DIV_SEL_MASK 0x00010000
    #define I2SSYSCLK_DIV_SEL_SHIFT 16
    #define I2SSYSCLK_DIV_RST_MASK 0x01000000
    #define I2SSYSCLK_DIV_RST_SHIFT 24
#define  CG_LPCLK_CTRL 0x0070
    #define LPCLK_DIV_MASK 0x000003FE
    #define LPCLK_DIV_SHIFT 1
    #define LPCLK_SRC_SEL_MASK 0x00010000
    #define LPCLK_SRC_SEL_SHIFT 16
    #define LPCLK_RST_MASK 0x01000000
    #define LPCLK_RST_SHIFT 24
#define  CG_MCIF_RESET 0x0108
    #define MCIF_RING1_RESET_MASK 0x00000002
    #define MCIF_RING1_RESET_SHIFT 1
    #define MCIF_RING2_RESET_MASK 0x00000004
    #define MCIF_RING2_RESET_SHIFT 2
    #define MCIF_RING3_RESET_MASK 0x00000008
    #define MCIF_RING3_RESET_SHIFT 3
    #define MCIF_RING4_RESET_MASK 0x00000010
    #define MCIF_RING4_RESET_SHIFT 4
#define  CG_MODDIV_CTRL 0x02A8
    #define CG_MODDIV_CTRL_RESET_MASK 0x00000001
    #define CG_MODDIV_CTRL_RESET_SHIFT 0
    #define CG_MODDIV_CTRL_ENABLE_MASK 0x00000002
    #define CG_MODDIV_CTRL_ENABLE_SHIFT 1
#define  CG_MODDIV_DEN 0x02A4
    #define MODDIV_DEN_MASK 0x03FFFFFF
    #define MODDIV_DEN_SHIFT 0
#define  CG_MODDIV_NUM 0x02A0
    #define MODDIV_NUM_MASK 0x003FFFFF
    #define MODDIV_NUM_SHIFT 0
#define  CG_PLL0_CTRL 0x0208
    #define CG_PLL0_CTRL_ENABLE_MASK 0x00000001
    #define CG_PLL0_CTRL_ENABLE_SHIFT 0
    #define CG_PLL0_CTRL_LOOP_INIT_MASK 0x00000002
    #define CG_PLL0_CTRL_LOOP_INIT_SHIFT 1
    #define CG_PLL0_CTRL_REFCLK_SEL_MASK 0x0000000C
    #define CG_PLL0_CTRL_REFCLK_SEL_SHIFT 2
    #define CG_PLL0_CTRL_VCO_IBIAS_IDN_MASK 0x00000010
    #define CG_PLL0_CTRL_VCO_IBIAS_IDN_SHIFT 4
    #define CG_PLL0_CTRL_VCO_IBIAS_IUP_MASK 0x00000020
    #define CG_PLL0_CTRL_VCO_IBIAS_IUP_SHIFT 5
    #define CG_PLL0_CTRL_VCO_PCASC_IDN_MASK 0x00000040
    #define CG_PLL0_CTRL_VCO_PCASC_IDN_SHIFT 6
    #define CG_PLL0_CTRL_VCO_PCASC_IUP_MASK 0x00000080
    #define CG_PLL0_CTRL_VCO_PCASC_IUP_SHIFT 7
    #define CG_PLL0_CTRL_VCO_NCASC_IDN_MASK 0x00000100
    #define CG_PLL0_CTRL_VCO_NCASC_IDN_SHIFT 8
    #define CG_PLL0_CTRL_VCO_NCASC_IUP_MASK 0x00000200
    #define CG_PLL0_CTRL_VCO_NCASC_IUP_SHIFT 9
    #define CG_PLL0_CTRL_LFSR_ENABLE_MASK 0x00000800
    #define CG_PLL0_CTRL_LFSR_ENABLE_SHIFT 11
    #define CG_PLL0_CTRL_ICPHALF_MASK 0x00001000
    #define CG_PLL0_CTRL_ICPHALF_SHIFT 12
    #define CG_PLL0_CTRL_ICP2X_MASK 0x00002000
    #define CG_PLL0_CTRL_ICP2X_SHIFT 13
    #define CG_PLL0_CTRL_SELFBIAS_MASK 0x00008000
    #define CG_PLL0_CTRL_SELFBIAS_SHIFT 15
    #define CG_PLL0_CTRL_FRAC_ENABLE_MASK 0x02000000
    #define CG_PLL0_CTRL_FRAC_ENABLE_SHIFT 25
    #define CG_PLL0_CTRL_CONT_LOCK_MON_MASK 0x04000000
    #define CG_PLL0_CTRL_CONT_LOCK_MON_SHIFT 26
    #define CG_PLL0_CTRL_IDISDCLD_MASK 0x08000000
    #define CG_PLL0_CTRL_IDISDCLD_SHIFT 27
    #define CG_PLL0_CTRL_TSTSEL_MASK 0xF0000000
    #define CG_PLL0_CTRL_TSTSEL_SHIFT 28
#define  CG_PLL0_FREQ 0x0200
    #define CG_PLL0_FREQ_FB_DIV_FRAC_MASK 0x000FFFFF
    #define CG_PLL0_FREQ_FB_DIV_FRAC_SHIFT 0
    #define CG_PLL0_FREQ_FB_DIV_INT_MASK 0x01F00000
    #define CG_PLL0_FREQ_FB_DIV_INT_SHIFT 20
    #define CG_PLL0_FREQ_PRE_DIV_MASK 0x10000000
    #define CG_PLL0_FREQ_PRE_DIV_SHIFT 28
#define  CG_PLL1_CTRL 0x0218
    #define CG_PLL1_CTRL_ENABLE_MASK 0x00000001
    #define CG_PLL1_CTRL_ENABLE_SHIFT 0
    #define CG_PLL1_CTRL_LOOP_INIT_MASK 0x00000002
    #define CG_PLL1_CTRL_LOOP_INIT_SHIFT 1
    #define CG_PLL1_CTRL_REFCLK_SEL_MASK 0x0000000C
    #define CG_PLL1_CTRL_REFCLK_SEL_SHIFT 2
    #define CG_PLL1_CTRL_VCO_IBIAS_IDN_MASK 0x00000010
    #define CG_PLL1_CTRL_VCO_IBIAS_IDN_SHIFT 4
    #define CG_PLL1_CTRL_VCO_IBIAS_IUP_MASK 0x00000020
    #define CG_PLL1_CTRL_VCO_IBIAS_IUP_SHIFT 5
    #define CG_PLL1_CTRL_VCO_PCASC_IDN_MASK 0x00000040
    #define CG_PLL1_CTRL_VCO_PCASC_IDN_SHIFT 6
    #define CG_PLL1_CTRL_VCO_PCASC_IUP_MASK 0x00000080
    #define CG_PLL1_CTRL_VCO_PCASC_IUP_SHIFT 7
    #define CG_PLL1_CTRL_VCO_NCASC_IDN_MASK 0x00000100
    #define CG_PLL1_CTRL_VCO_NCASC_IDN_SHIFT 8
    #define CG_PLL1_CTRL_VCO_NCASC_IUP_MASK 0x00000200
    #define CG_PLL1_CTRL_VCO_NCASC_IUP_SHIFT 9
    #define CG_PLL1_CTRL_LFSR_ENABLE_MASK 0x00000800
    #define CG_PLL1_CTRL_LFSR_ENABLE_SHIFT 11
    #define CG_PLL1_CTRL_ICPHALF_MASK 0x00001000
    #define CG_PLL1_CTRL_ICPHALF_SHIFT 12
    #define CG_PLL1_CTRL_ICP2X_MASK 0x00002000
    #define CG_PLL1_CTRL_ICP2X_SHIFT 13
    #define CG_PLL1_CTRL_SELFBIAS_MASK 0x00008000
    #define CG_PLL1_CTRL_SELFBIAS_SHIFT 15
    #define CG_PLL1_CTRL_FRAC_ENABLE_MASK 0x02000000
    #define CG_PLL1_CTRL_FRAC_ENABLE_SHIFT 25
    #define CG_PLL1_CTRL_CONT_LOCK_MON_MASK 0x04000000
    #define CG_PLL1_CTRL_CONT_LOCK_MON_SHIFT 26
    #define CG_PLL1_CTRL_IDISDCLD_MASK 0x08000000
    #define CG_PLL1_CTRL_IDISDCLD_SHIFT 27
    #define CG_PLL1_CTRL_TSTSEL_MASK 0xF0000000
    #define CG_PLL1_CTRL_TSTSEL_SHIFT 28
#define  CG_PLL1_FREQ 0x0210
    #define CG_PLL1_FREQ_FB_DIV_FRAC_MASK 0x000FFFFF
    #define CG_PLL1_FREQ_FB_DIV_FRAC_SHIFT 0
    #define CG_PLL1_FREQ_FB_DIV_INT_MASK 0x01F00000
    #define CG_PLL1_FREQ_FB_DIV_INT_SHIFT 20
    #define CG_PLL1_FREQ_PRE_DIV_MASK 0x10000000
    #define CG_PLL1_FREQ_PRE_DIV_SHIFT 28
#define  CG_PLL2_CTRL 0x0228
    #define CG_PLL2_CTRL_ENABLE_MASK 0x00000001
    #define CG_PLL2_CTRL_ENABLE_SHIFT 0
    #define CG_PLL2_CTRL_LOOP_INIT_MASK 0x00000002
    #define CG_PLL2_CTRL_LOOP_INIT_SHIFT 1
    #define CG_PLL2_CTRL_REFCLK_SEL_MASK 0x0000000C
    #define CG_PLL2_CTRL_REFCLK_SEL_SHIFT 2
    #define CG_PLL2_CTRL_VCO_IBIAS_IDN_MASK 0x00000010
    #define CG_PLL2_CTRL_VCO_IBIAS_IDN_SHIFT 4
    #define CG_PLL2_CTRL_VCO_IBIAS_IUP_MASK 0x00000020
    #define CG_PLL2_CTRL_VCO_IBIAS_IUP_SHIFT 5
    #define CG_PLL2_CTRL_VCO_PCASC_IDN_MASK 0x00000040
    #define CG_PLL2_CTRL_VCO_PCASC_IDN_SHIFT 6
    #define CG_PLL2_CTRL_VCO_PCASC_IUP_MASK 0x00000080
    #define CG_PLL2_CTRL_VCO_PCASC_IUP_SHIFT 7
    #define CG_PLL2_CTRL_VCO_NCASC_IDN_MASK 0x00000100
    #define CG_PLL2_CTRL_VCO_NCASC_IDN_SHIFT 8
    #define CG_PLL2_CTRL_VCO_NCASC_IUP_MASK 0x00000200
    #define CG_PLL2_CTRL_VCO_NCASC_IUP_SHIFT 9
    #define CG_PLL2_CTRL_LFSR_ENABLE_MASK 0x00000800
    #define CG_PLL2_CTRL_LFSR_ENABLE_SHIFT 11
    #define CG_PLL2_CTRL_ICPHALF_MASK 0x00001000
    #define CG_PLL2_CTRL_ICPHALF_SHIFT 12
    #define CG_PLL2_CTRL_ICP2X_MASK 0x00002000
    #define CG_PLL2_CTRL_ICP2X_SHIFT 13
    #define CG_PLL2_CTRL_SELFBIAS_MASK 0x00008000
    #define CG_PLL2_CTRL_SELFBIAS_SHIFT 15
    #define CG_PLL2_CTRL_FRAC_ENABLE_MASK 0x02000000
    #define CG_PLL2_CTRL_FRAC_ENABLE_SHIFT 25
    #define CG_PLL2_CTRL_CONT_LOCK_MON_MASK 0x04000000
    #define CG_PLL2_CTRL_CONT_LOCK_MON_SHIFT 26
    #define CG_PLL2_CTRL_IDISDCLD_MASK 0x08000000
    #define CG_PLL2_CTRL_IDISDCLD_SHIFT 27
    #define CG_PLL2_CTRL_TSTSEL_MASK 0xF0000000
    #define CG_PLL2_CTRL_TSTSEL_SHIFT 28
#define  CG_PLL2_FREQ 0x0220
    #define CG_PLL2_FREQ_FB_DIV_FRAC_MASK 0x000FFFFF
    #define CG_PLL2_FREQ_FB_DIV_FRAC_SHIFT 0
    #define CG_PLL2_FREQ_FB_DIV_INT_MASK 0x01F00000
    #define CG_PLL2_FREQ_FB_DIV_INT_SHIFT 20
    #define CG_PLL2_FREQ_PRE_DIV_MASK 0x10000000
    #define CG_PLL2_FREQ_PRE_DIV_SHIFT 28
#define  CG_PLL3_CTRL 0x0238
    #define CG_PLL3_CTRL_ENABLE_MASK 0x00000001
    #define CG_PLL3_CTRL_ENABLE_SHIFT 0
    #define CG_PLL3_CTRL_LOOP_INIT_MASK 0x00000002
    #define CG_PLL3_CTRL_LOOP_INIT_SHIFT 1
    #define CG_PLL3_CTRL_REFCLK_SEL_MASK 0x0000000C
    #define CG_PLL3_CTRL_REFCLK_SEL_SHIFT 2
    #define CG_PLL3_CTRL_VCO_IBIAS_IDN_MASK 0x00000010
    #define CG_PLL3_CTRL_VCO_IBIAS_IDN_SHIFT 4
    #define CG_PLL3_CTRL_VCO_IBIAS_IUP_MASK 0x00000020
    #define CG_PLL3_CTRL_VCO_IBIAS_IUP_SHIFT 5
    #define CG_PLL3_CTRL_VCO_PCASC_IDN_MASK 0x00000040
    #define CG_PLL3_CTRL_VCO_PCASC_IDN_SHIFT 6
    #define CG_PLL3_CTRL_VCO_PCASC_IUP_MASK 0x00000080
    #define CG_PLL3_CTRL_VCO_PCASC_IUP_SHIFT 7
    #define CG_PLL3_CTRL_VCO_NCASC_IDN_MASK 0x00000100
    #define CG_PLL3_CTRL_VCO_NCASC_IDN_SHIFT 8
    #define CG_PLL3_CTRL_VCO_NCASC_IUP_MASK 0x00000200
    #define CG_PLL3_CTRL_VCO_NCASC_IUP_SHIFT 9
    #define CG_PLL3_CTRL_LFSR_ENABLE_MASK 0x00000800
    #define CG_PLL3_CTRL_LFSR_ENABLE_SHIFT 11
    #define CG_PLL3_CTRL_ICPHALF_MASK 0x00001000
    #define CG_PLL3_CTRL_ICPHALF_SHIFT 12
    #define CG_PLL3_CTRL_ICP2X_MASK 0x00002000
    #define CG_PLL3_CTRL_ICP2X_SHIFT 13
    #define CG_PLL3_CTRL_SELFBIAS_MASK 0x00008000
    #define CG_PLL3_CTRL_SELFBIAS_SHIFT 15
    #define CG_PLL3_CTRL_FRAC_ENABLE_MASK 0x02000000
    #define CG_PLL3_CTRL_FRAC_ENABLE_SHIFT 25
    #define CG_PLL3_CTRL_CONT_LOCK_MON_MASK 0x04000000
    #define CG_PLL3_CTRL_CONT_LOCK_MON_SHIFT 26
    #define CG_PLL3_CTRL_IDISDCLD_MASK 0x08000000
    #define CG_PLL3_CTRL_IDISDCLD_SHIFT 27
    #define CG_PLL3_CTRL_TSTSEL_MASK 0xF0000000
    #define CG_PLL3_CTRL_TSTSEL_SHIFT 28
#define  CG_PLL3_FREQ 0x0230
    #define CG_PLL3_FREQ_FB_DIV_FRAC_MASK 0x000FFFFF
    #define CG_PLL3_FREQ_FB_DIV_FRAC_SHIFT 0
    #define CG_PLL3_FREQ_FB_DIV_INT_MASK 0x01F00000
    #define CG_PLL3_FREQ_FB_DIV_INT_SHIFT 20
    #define CG_PLL3_FREQ_PRE_DIV_MASK 0x10000000
    #define CG_PLL3_FREQ_PRE_DIV_SHIFT 28
#define  CG_PLL4_CTRL 0x0248
    #define CG_PLL4_CTRL_ENABLE_MASK 0x00000001
    #define CG_PLL4_CTRL_ENABLE_SHIFT 0
    #define CG_PLL4_CTRL_LOOP_INIT_MASK 0x00000002
    #define CG_PLL4_CTRL_LOOP_INIT_SHIFT 1
    #define CG_PLL4_CTRL_REFCLK_SEL_MASK 0x0000000C
    #define CG_PLL4_CTRL_REFCLK_SEL_SHIFT 2
    #define CG_PLL4_CTRL_VCO_IBIAS_IDN_MASK 0x00000010
    #define CG_PLL4_CTRL_VCO_IBIAS_IDN_SHIFT 4
    #define CG_PLL4_CTRL_VCO_IBIAS_IUP_MASK 0x00000020
    #define CG_PLL4_CTRL_VCO_IBIAS_IUP_SHIFT 5
    #define CG_PLL4_CTRL_VCO_PCASC_IDN_MASK 0x00000040
    #define CG_PLL4_CTRL_VCO_PCASC_IDN_SHIFT 6
    #define CG_PLL4_CTRL_VCO_PCASC_IUP_MASK 0x00000080
    #define CG_PLL4_CTRL_VCO_PCASC_IUP_SHIFT 7
    #define CG_PLL4_CTRL_VCO_NCASC_IDN_MASK 0x00000100
    #define CG_PLL4_CTRL_VCO_NCASC_IDN_SHIFT 8
    #define CG_PLL4_CTRL_VCO_NCASC_IUP_MASK 0x00000200
    #define CG_PLL4_CTRL_VCO_NCASC_IUP_SHIFT 9
    #define CG_PLL4_CTRL_LFSR_ENABLE_MASK 0x00000800
    #define CG_PLL4_CTRL_LFSR_ENABLE_SHIFT 11
    #define CG_PLL4_CTRL_ICPHALF_MASK 0x00001000
    #define CG_PLL4_CTRL_ICPHALF_SHIFT 12
    #define CG_PLL4_CTRL_ICP2X_MASK 0x00002000
    #define CG_PLL4_CTRL_ICP2X_SHIFT 13
    #define CG_PLL4_CTRL_SELFBIAS_MASK 0x00008000
    #define CG_PLL4_CTRL_SELFBIAS_SHIFT 15
    #define CG_PLL4_CTRL_FRAC_ENABLE_MASK 0x02000000
    #define CG_PLL4_CTRL_FRAC_ENABLE_SHIFT 25
    #define CG_PLL4_CTRL_CONT_LOCK_MON_MASK 0x04000000
    #define CG_PLL4_CTRL_CONT_LOCK_MON_SHIFT 26
    #define CG_PLL4_CTRL_IDISDCLD_MASK 0x08000000
    #define CG_PLL4_CTRL_IDISDCLD_SHIFT 27
    #define CG_PLL4_CTRL_TSTSEL_MASK 0xF0000000
    #define CG_PLL4_CTRL_TSTSEL_SHIFT 28
#define  CG_PLL4_FREQ 0x0240
    #define CG_PLL4_FREQ_FB_DIV_FRAC_MASK 0x000FFFFF
    #define CG_PLL4_FREQ_FB_DIV_FRAC_SHIFT 0
    #define CG_PLL4_FREQ_FB_DIV_INT_MASK 0x01F00000
    #define CG_PLL4_FREQ_FB_DIV_INT_SHIFT 20
    #define CG_PLL4_FREQ_PRE_DIV_MASK 0x10000000
    #define CG_PLL4_FREQ_PRE_DIV_SHIFT 28
#define  CG_PLL5_CTRL 0x0258
    #define CG_PLL5_CTRL_ENABLE_MASK 0x00000001
    #define CG_PLL5_CTRL_ENABLE_SHIFT 0
    #define CG_PLL5_CTRL_LOOP_INIT_MASK 0x00000002
    #define CG_PLL5_CTRL_LOOP_INIT_SHIFT 1
    #define CG_PLL5_CTRL_REFCLK_SEL_MASK 0x0000000C
    #define CG_PLL5_CTRL_REFCLK_SEL_SHIFT 2
    #define CG_PLL5_CTRL_VCO_IBIAS_IDN_MASK 0x00000010
    #define CG_PLL5_CTRL_VCO_IBIAS_IDN_SHIFT 4
    #define CG_PLL5_CTRL_VCO_IBIAS_IUP_MASK 0x00000020
    #define CG_PLL5_CTRL_VCO_IBIAS_IUP_SHIFT 5
    #define CG_PLL5_CTRL_VCO_PCASC_IDN_MASK 0x00000040
    #define CG_PLL5_CTRL_VCO_PCASC_IDN_SHIFT 6
    #define CG_PLL5_CTRL_VCO_PCASC_IUP_MASK 0x00000080
    #define CG_PLL5_CTRL_VCO_PCASC_IUP_SHIFT 7
    #define CG_PLL5_CTRL_VCO_NCASC_IDN_MASK 0x00000100
    #define CG_PLL5_CTRL_VCO_NCASC_IDN_SHIFT 8
    #define CG_PLL5_CTRL_VCO_NCASC_IUP_MASK 0x00000200
    #define CG_PLL5_CTRL_VCO_NCASC_IUP_SHIFT 9
    #define CG_PLL5_CTRL_LFSR_ENABLE_MASK 0x00000800
    #define CG_PLL5_CTRL_LFSR_ENABLE_SHIFT 11
    #define CG_PLL5_CTRL_ICPHALF_MASK 0x00001000
    #define CG_PLL5_CTRL_ICPHALF_SHIFT 12
    #define CG_PLL5_CTRL_ICP2X_MASK 0x00002000
    #define CG_PLL5_CTRL_ICP2X_SHIFT 13
    #define CG_PLL5_CTRL_SELFBIAS_MASK 0x00008000
    #define CG_PLL5_CTRL_SELFBIAS_SHIFT 15
    #define CG_PLL5_CTRL_FRAC_ENABLE_MASK 0x02000000
    #define CG_PLL5_CTRL_FRAC_ENABLE_SHIFT 25
    #define CG_PLL5_CTRL_CONT_LOCK_MON_MASK 0x04000000
    #define CG_PLL5_CTRL_CONT_LOCK_MON_SHIFT 26
    #define CG_PLL5_CTRL_IDISDCLD_MASK 0x08000000
    #define CG_PLL5_CTRL_IDISDCLD_SHIFT 27
    #define CG_PLL5_CTRL_TSTSEL_MASK 0xF0000000
    #define CG_PLL5_CTRL_TSTSEL_SHIFT 28
#define  CG_PLL5_FREQ 0x0250
    #define CG_PLL5_FREQ_FB_DIV_FRAC_MASK 0x000FFFFF
    #define CG_PLL5_FREQ_FB_DIV_FRAC_SHIFT 0
    #define CG_PLL5_FREQ_FB_DIV_INT_MASK 0x01F00000
    #define CG_PLL5_FREQ_FB_DIV_INT_SHIFT 20
    #define CG_PLL5_FREQ_PRE_DIV_MASK 0x10000000
    #define CG_PLL5_FREQ_PRE_DIV_SHIFT 28
#define  CG_PLL6_CTRL 0x0268
    #define CG_PLL6_CTRL_ENABLE_MASK 0x00000001
    #define CG_PLL6_CTRL_ENABLE_SHIFT 0
    #define CG_PLL6_CTRL_LOOP_INIT_MASK 0x00000002
    #define CG_PLL6_CTRL_LOOP_INIT_SHIFT 1
    #define CG_PLL6_CTRL_REFCLK_SEL_MASK 0x0000000C
    #define CG_PLL6_CTRL_REFCLK_SEL_SHIFT 2
    #define CG_PLL6_CTRL_VCO_IBIAS_IDN_MASK 0x00000010
    #define CG_PLL6_CTRL_VCO_IBIAS_IDN_SHIFT 4
    #define CG_PLL6_CTRL_VCO_IBIAS_IUP_MASK 0x00000020
    #define CG_PLL6_CTRL_VCO_IBIAS_IUP_SHIFT 5
    #define CG_PLL6_CTRL_VCO_PCASC_IDN_MASK 0x00000040
    #define CG_PLL6_CTRL_VCO_PCASC_IDN_SHIFT 6
    #define CG_PLL6_CTRL_VCO_PCASC_IUP_MASK 0x00000080
    #define CG_PLL6_CTRL_VCO_PCASC_IUP_SHIFT 7
    #define CG_PLL6_CTRL_VCO_NCASC_IDN_MASK 0x00000100
    #define CG_PLL6_CTRL_VCO_NCASC_IDN_SHIFT 8
    #define CG_PLL6_CTRL_VCO_NCASC_IUP_MASK 0x00000200
    #define CG_PLL6_CTRL_VCO_NCASC_IUP_SHIFT 9
    #define CG_PLL6_CTRL_LFSR_ENABLE_MASK 0x00000800
    #define CG_PLL6_CTRL_LFSR_ENABLE_SHIFT 11
    #define CG_PLL6_CTRL_ICPHALF_MASK 0x00001000
    #define CG_PLL6_CTRL_ICPHALF_SHIFT 12
    #define CG_PLL6_CTRL_ICP2X_MASK 0x00002000
    #define CG_PLL6_CTRL_ICP2X_SHIFT 13
    #define CG_PLL6_CTRL_SELFBIAS_MASK 0x00008000
    #define CG_PLL6_CTRL_SELFBIAS_SHIFT 15
    #define CG_PLL6_CTRL_FRAC_ENABLE_MASK 0x02000000
    #define CG_PLL6_CTRL_FRAC_ENABLE_SHIFT 25
    #define CG_PLL6_CTRL_CONT_LOCK_MON_MASK 0x04000000
    #define CG_PLL6_CTRL_CONT_LOCK_MON_SHIFT 26
    #define CG_PLL6_CTRL_IDISDCLD_MASK 0x08000000
    #define CG_PLL6_CTRL_IDISDCLD_SHIFT 27
    #define CG_PLL6_CTRL_TSTSEL_MASK 0xF0000000
    #define CG_PLL6_CTRL_TSTSEL_SHIFT 28
#define  CG_PLL6_FREQ 0x0260
    #define CG_PLL6_FREQ_FB_DIV_FRAC_MASK 0x000FFFFF
    #define CG_PLL6_FREQ_FB_DIV_FRAC_SHIFT 0
    #define CG_PLL6_FREQ_FB_DIV_INT_MASK 0x01F00000
    #define CG_PLL6_FREQ_FB_DIV_INT_SHIFT 20
    #define CG_PLL6_FREQ_PRE_DIV_MASK 0x10000000
    #define CG_PLL6_FREQ_PRE_DIV_SHIFT 28
#define  CG_PLL7_CTRL 0x0278
    #define CG_PLL7_CTRL_ENABLE_MASK 0x00000001
    #define CG_PLL7_CTRL_ENABLE_SHIFT 0
    #define CG_PLL7_CTRL_LOOP_INIT_MASK 0x00000002
    #define CG_PLL7_CTRL_LOOP_INIT_SHIFT 1
    #define CG_PLL7_CTRL_REFCLK_SEL_MASK 0x0000000C
    #define CG_PLL7_CTRL_REFCLK_SEL_SHIFT 2
    #define CG_PLL7_CTRL_VCO_IBIAS_IDN_MASK 0x00000010
    #define CG_PLL7_CTRL_VCO_IBIAS_IDN_SHIFT 4
    #define CG_PLL7_CTRL_VCO_IBIAS_IUP_MASK 0x00000020
    #define CG_PLL7_CTRL_VCO_IBIAS_IUP_SHIFT 5
    #define CG_PLL7_CTRL_VCO_PCASC_IDN_MASK 0x00000040
    #define CG_PLL7_CTRL_VCO_PCASC_IDN_SHIFT 6
    #define CG_PLL7_CTRL_VCO_PCASC_IUP_MASK 0x00000080
    #define CG_PLL7_CTRL_VCO_PCASC_IUP_SHIFT 7
    #define CG_PLL7_CTRL_VCO_NCASC_IDN_MASK 0x00000100
    #define CG_PLL7_CTRL_VCO_NCASC_IDN_SHIFT 8
    #define CG_PLL7_CTRL_VCO_NCASC_IUP_MASK 0x00000200
    #define CG_PLL7_CTRL_VCO_NCASC_IUP_SHIFT 9
    #define CG_PLL7_CTRL_LFSR_ENABLE_MASK 0x00000800
    #define CG_PLL7_CTRL_LFSR_ENABLE_SHIFT 11
    #define CG_PLL7_CTRL_ICPHALF_MASK 0x00001000
    #define CG_PLL7_CTRL_ICPHALF_SHIFT 12
    #define CG_PLL7_CTRL_ICP2X_MASK 0x00002000
    #define CG_PLL7_CTRL_ICP2X_SHIFT 13
    #define CG_PLL7_CTRL_SELFBIAS_MASK 0x00008000
    #define CG_PLL7_CTRL_SELFBIAS_SHIFT 15
    #define CG_PLL7_CTRL_FRAC_ENABLE_MASK 0x02000000
    #define CG_PLL7_CTRL_FRAC_ENABLE_SHIFT 25
    #define CG_PLL7_CTRL_CONT_LOCK_MON_MASK 0x04000000
    #define CG_PLL7_CTRL_CONT_LOCK_MON_SHIFT 26
    #define CG_PLL7_CTRL_IDISDCLD_MASK 0x08000000
    #define CG_PLL7_CTRL_IDISDCLD_SHIFT 27
    #define CG_PLL7_CTRL_TSTSEL_MASK 0xF0000000
    #define CG_PLL7_CTRL_TSTSEL_SHIFT 28
#define  CG_PLL7_FREQ 0x0270
    #define CG_PLL7_FREQ_FB_DIV_FRAC_MASK 0x000FFFFF
    #define CG_PLL7_FREQ_FB_DIV_FRAC_SHIFT 0
    #define CG_PLL7_FREQ_FB_DIV_INT_MASK 0x01F00000
    #define CG_PLL7_FREQ_FB_DIV_INT_SHIFT 20
    #define CG_PLL7_FREQ_PRE_DIV_MASK 0x10000000
    #define CG_PLL7_FREQ_PRE_DIV_SHIFT 28
#define  CG_PLL_MISC_CTRL0 0x01E8
    #define CG_PLL_MISC_CTRL0_RESET_MASK 0x00000001
    #define CG_PLL_MISC_CTRL0_RESET_SHIFT 0
    #define BG_PD_MASK 0x00000002
    #define BG_PD_SHIFT 1
    #define REG_ENABLE_MASK 0x00000004
    #define REG_ENABLE_SHIFT 2
    #define BGCORE_NBIAS_IDN_MASK 0x00000010
    #define BGCORE_NBIAS_IDN_SHIFT 4
    #define BGCORE_NBIAS_IUP_MASK 0x00000020
    #define BGCORE_NBIAS_IUP_SHIFT 5
    #define BGCORE_PCASC_IDN_MASK 0x00000040
    #define BGCORE_PCASC_IDN_SHIFT 6
    #define BGCORE_PCASC_IUP_MASK 0x00000080
    #define BGCORE_PCASC_IUP_SHIFT 7
    #define BGRG_NBIAS_IDN_MASK 0x00000100
    #define BGRG_NBIAS_IDN_SHIFT 8
    #define BGRG_NBIAS_IUP_MASK 0x00000200
    #define BGRG_NBIAS_IUP_SHIFT 9
    #define BGRG_PCASC_IDN_MASK 0x00000400
    #define BGRG_PCASC_IDN_SHIFT 10
    #define BGRG_PCASC_IUP_MASK 0x00000800
    #define BGRG_PCASC_IUP_SHIFT 11
    #define BGRG_PWD_MASK 0x00001000
    #define BGRG_PWD_SHIFT 12
    #define REG_IBIAS_IDN_MASK 0x00010000
    #define REG_IBIAS_IDN_SHIFT 16
    #define REG_IBIAS_IUP_MASK 0x00020000
    #define REG_IBIAS_IUP_SHIFT 17
    #define REG_PCASC_IDN_MASK 0x00040000
    #define REG_PCASC_IDN_SHIFT 18
    #define REG_PCASC_IUP_MASK 0x00080000
    #define REG_PCASC_IUP_SHIFT 19
    #define CG_PLL_MISC_CTRL0_TSTSEL_MASK 0x07000000
    #define CG_PLL_MISC_CTRL0_TSTSEL_SHIFT 24
#define  CG_PLL_STATUS0 0x01E0
    #define PLL0_LOCK_MASK 0x00000001
    #define PLL0_LOCK_SHIFT 0
    #define PLL1_LOCK_MASK 0x00000002
    #define PLL1_LOCK_SHIFT 1
    #define PLL2_LOCK_MASK 0x00000004
    #define PLL2_LOCK_SHIFT 2
    #define PLL3_LOCK_MASK 0x00000008
    #define PLL3_LOCK_SHIFT 3
    #define PLL4_LOCK_MASK 0x00000010
    #define PLL4_LOCK_SHIFT 4
    #define PLL5_LOCK_MASK 0x00000020
    #define PLL5_LOCK_SHIFT 5
    #define PLL6_LOCK_MASK 0x00000040
    #define PLL6_LOCK_SHIFT 6
    #define PLL7_LOCK_MASK 0x00000080
    #define PLL7_LOCK_SHIFT 7
#define  CG_PWM_CTRL 0x02C4
    #define PWMCLK_SRC_SEL_MASK 0x00F00000
    #define PWMCLK_SRC_SEL_SHIFT 20
    #define PWM_RST_MASK 0x01000000
    #define PWM_RST_SHIFT 24
#define  CG_PWM_DC 0x02C0
    #define PWM_PULSE_LO_CNT_MASK 0x00000FFF
    #define PWM_PULSE_LO_CNT_SHIFT 0
    #define PWM_PULSE_HI_CNT_MASK 0x0FFF0000
    #define PWM_PULSE_HI_CNT_SHIFT 16
#define  CG_RESET_REG 0x0000
    #define DMA_RESET_MASK 0x00000002
    #define DMA_RESET_SHIFT 1
    #define TSD_RESET_MASK 0x00000004
    #define TSD_RESET_SHIFT 2
    #define MC_RESET_MASK 0x00000010
    #define MC_RESET_SHIFT 4
    #define SATA_RESET_MASK 0x00000080
    #define SATA_RESET_SHIFT 7
    #define PPC_RESET_MASK 0x00000200
    #define PPC_RESET_SHIFT 9
    #define RSA_RESET_MASK 0x00000400
    #define RSA_RESET_SHIFT 10
    #define MPP_RESET_MASK 0x00001000
    #define MPP_RESET_SHIFT 12
    #define I2S_RESET_MASK 0x00002000
    #define I2S_RESET_SHIFT 13
    #define VHE_RESET_MASK 0x00004000
    #define VHE_RESET_SHIFT 14
    #define VNE_RESET_MASK 0x00010000
    #define VNE_RESET_SHIFT 16
    #define GVP_RESET_MASK 0x00020000
    #define GVP_RESET_SHIFT 17
    #define PROC0_RESET_MASK 0x00040000
    #define PROC0_RESET_SHIFT 18
    #define PROC1_RESET_MASK 0x00080000
    #define PROC1_RESET_SHIFT 19
    #define PROC2_RESET_MASK 0x00100000
    #define PROC2_RESET_SHIFT 20
    #define PROC3_RESET_MASK 0x00200000
    #define PROC3_RESET_SHIFT 21
    #define PROC4_RESET_MASK 0x00400000
    #define PROC4_RESET_SHIFT 22
    #define USBH_RESET_MASK 0x00800000
    #define USBH_RESET_SHIFT 23
    #define ETH0_RESET_MASK 0x01000000
    #define ETH0_RESET_SHIFT 24
    #define USBD_RESET_MASK 0x04000000
    #define USBD_RESET_SHIFT 26
    #define GVD_RESET_MASK 0x08000000
    #define GVD_RESET_SHIFT 27
    #define SPDIF_RX_RESET_MASK 0x40000000
    #define SPDIF_RX_RESET_SHIFT 30
#define  CG_RESET_REG1 0x0004
    #define SMS_RESET_MASK 0x00000001
    #define SMS_RESET_SHIFT 0
    #define FES_RESET_MASK 0x00000020
    #define FES_RESET_SHIFT 5
    #define UART_RESET_MASK 0x00000400
    #define UART_RESET_SHIFT 10
    #define MAFE0_RESET_MASK 0x00000800
    #define MAFE0_RESET_SHIFT 11
    #define MAFE1_RESET_MASK 0x00001000
    #define MAFE1_RESET_SHIFT 12
    #define SMCC0_RESET_MASK 0x00002000
    #define SMCC0_RESET_SHIFT 13
    #define SMCC1_RESET_MASK 0x00004000
    #define SMCC1_RESET_SHIFT 14
    #define NFC0_RESET_MASK 0x00008000
    #define NFC0_RESET_SHIFT 15
    #define SEQ2X_RESET_MASK 0x00010000
    #define SEQ2X_RESET_SHIFT 16
#define  CG_SYSTEM_CNT 0x00F8
    #define SYSTEM_CNT_MASK 0xFFFFFFFF
    #define SYSTEM_CNT_SHIFT 0
#define  CG_TIMESTAMP_CTRL 0x0080
    #define CG_TIMESTAMP_CTRL_VHE0_CLR_CNT_MASK 0x00000001
    #define CG_TIMESTAMP_CTRL_VHE0_CLR_CNT_SHIFT 0
    #define CG_TIMESTAMP_CTRL_VHE1_CLR_CNT_MASK 0x00000002
    #define CG_TIMESTAMP_CTRL_VHE1_CLR_CNT_SHIFT 1
    #define CG_TIMESTAMP_CTRL_I2S0_CLR_CNT_MASK 0x00000004
    #define CG_TIMESTAMP_CTRL_I2S0_CLR_CNT_SHIFT 2
    #define CG_TIMESTAMP_CTRL_I2S1_CLR_CNT_MASK 0x00000008
    #define CG_TIMESTAMP_CTRL_I2S1_CLR_CNT_SHIFT 3
    #define CG_TIMESTAMP_CTRL_SPDIF_RX_CLR_CNT_MASK 0x00000010
    #define CG_TIMESTAMP_CTRL_SPDIF_RX_CLR_CNT_SHIFT 4
    #define CG_TIMESTAMP_CTRL_VHE0_EN_CNT_MASK 0x00000100
    #define CG_TIMESTAMP_CTRL_VHE0_EN_CNT_SHIFT 8
    #define CG_TIMESTAMP_CTRL_VHE1_EN_CNT_MASK 0x00000200
    #define CG_TIMESTAMP_CTRL_VHE1_EN_CNT_SHIFT 9
    #define CG_TIMESTAMP_CTRL_I2S0_EN_CNT_MASK 0x00000400
    #define CG_TIMESTAMP_CTRL_I2S0_EN_CNT_SHIFT 10
    #define CG_TIMESTAMP_CTRL_I2S1_EN_CNT_MASK 0x00000800
    #define CG_TIMESTAMP_CTRL_I2S1_EN_CNT_SHIFT 11
    #define CG_TIMESTAMP_CTRL_SPDIF_RX_EN_CNT_MASK 0x00001000
    #define CG_TIMESTAMP_CTRL_SPDIF_RX_EN_CNT_SHIFT 12
#define  DEBUG_BUS_CTRL 0x0438
    #define MUX_SEL_MASK 0x00007F00
    #define MUX_SEL_SHIFT 8
    #define DC_SEL_MASK 0x00070000
    #define DC_SEL_SHIFT 16
#define  DEBUG_BUS_WATCH 0x10F8
    #define DEBUG_BUS_WATCH_MASK 0xFFFFFFFF
    #define DEBUG_BUS_WATCH_SHIFT 0
#define  DEC0_DIP_ADR 0xA120
    #define DEC0_DIP_ADR_BASE_MASK 0x07FFFFFC
    #define DEC0_DIP_ADR_BASE_SHIFT 2
#define  DEC0_DIP_LIMIT 0xA094
    #define DEC0_DIP_LIMIT_BASE_MASK 0x07FFFFFC
    #define DEC0_DIP_LIMIT_BASE_SHIFT 2
    #define DEC0_DIP_LIMIT_LIMIT_EN_MASK 0x80000000
    #define DEC0_DIP_LIMIT_LIMIT_EN_SHIFT 31
#define  DEC1_DIP_ADR 0xA520
    #define DEC1_DIP_ADR_BASE_MASK 0x07FFFFFC
    #define DEC1_DIP_ADR_BASE_SHIFT 2
#define  DEC1_DIP_LIMIT 0xA494
    #define DEC1_DIP_LIMIT_BASE_MASK 0x07FFFFFC
    #define DEC1_DIP_LIMIT_BASE_SHIFT 2
    #define DEC1_DIP_LIMIT_LIMIT_EN_MASK 0x80000000
    #define DEC1_DIP_LIMIT_LIMIT_EN_SHIFT 31
#define  DEC_ARB_CTRL 0x74AC
    #define DIP_TIMER_MASK 0x0000000F
    #define DIP_TIMER_SHIFT 0
    #define MSCMVF_TIMER_MASK 0x000000F0
    #define MSCMVF_TIMER_SHIFT 4
    #define MSCREF_TIMER_MASK 0x00000F00
    #define MSCREF_TIMER_SHIFT 8
    #define SCLR_TIMER_MASK 0x0000F000
    #define SCLR_TIMER_SHIFT 12
    #define MSCRFM_TIMER_MASK 0x000F0000
    #define MSCRFM_TIMER_SHIFT 16
    #define SCLW_TIMER_MASK 0x00F00000
    #define SCLW_TIMER_SHIFT 20
    #define SCLW_BOT_TIMER_MASK 0x0F000000
    #define SCLW_BOT_TIMER_SHIFT 24
    #define VAR_TIMER_MASK 0xF0000000
    #define VAR_TIMER_SHIFT 28
#define  DEC_BWD_C_ADR 0x7380
    #define DEC_BWD_C_ADR_BASE_MASK 0x7FFFE000
    #define DEC_BWD_C_ADR_BASE_SHIFT 13
#define  DEC_BWD_Y_ADR 0x737C
    #define DEC_BWD_Y_ADR_BASE_MASK 0x7FFFE000
    #define DEC_BWD_Y_ADR_BASE_SHIFT 13
#define  DEC_CTRL 0x735C
    #define DEC_CTRL_MISMATCH_MASK 0x00000003
    #define DEC_CTRL_MISMATCH_SHIFT 0
    #define DEC_CTRL_SCAN_ORDER_MASK 0x0000000C
    #define DEC_CTRL_SCAN_ORDER_SHIFT 2
    #define DEC_CTRL_DC_SCALE_MASK 0x00000030
    #define DEC_CTRL_DC_SCALE_SHIFT 4
    #define DEC_CTRL_QSCALE_METHOD_MASK 0x00000040
    #define DEC_CTRL_QSCALE_METHOD_SHIFT 6
    #define DEC_CTRL_SATURATE_MASK 0x00000F00
    #define DEC_CTRL_SATURATE_SHIFT 8
    #define DEC_CTRL_QSCALE_TYPE_MASK 0x00001000
    #define DEC_CTRL_QSCALE_TYPE_SHIFT 12
#define  DEC_FWD_C_ADR 0x7378
    #define DEC_FWD_C_ADR_BASE_MASK 0x7FFFE000
    #define DEC_FWD_C_ADR_BASE_SHIFT 13
#define  DEC_FWD_Y_ADR 0x7374
    #define DEC_FWD_Y_ADR_BASE_MASK 0x7FFFE000
    #define DEC_FWD_Y_ADR_BASE_SHIFT 13
#define  DEC_MVA_ADR 0x7384
    #define DEC_MVA_ADR_BASE_MASK 0x7FFFFC00
    #define DEC_MVA_ADR_BASE_SHIFT 10
#define  DEC_PICT_INFO 0x7350
    #define DEC_PICT_INFO_PICT_TYPE_MASK 0x00000003
    #define DEC_PICT_INFO_PICT_TYPE_SHIFT 0
    #define DEC_PICT_INFO_PICT_STRUCT_MASK 0x0000000C
    #define DEC_PICT_INFO_PICT_STRUCT_SHIFT 2
    #define DEC_PICT_INFO_MPEG_FRMT_MASK 0x00000030
    #define DEC_PICT_INFO_MPEG_FRMT_SHIFT 4
    #define DEC_PICT_INFO_SECOND_FLD_MASK 0x80000000
    #define DEC_PICT_INFO_SECOND_FLD_SHIFT 31
#define  DEC_PICT_SIZE 0x7354
    #define DEC_PICT_SIZE_SLICE_SIZE_MASK 0x0000007F
    #define DEC_PICT_SIZE_SLICE_SIZE_SHIFT 0
    #define DEC_PICT_SIZE_SLICE_CNT_MASK 0x00007F00
    #define DEC_PICT_SIZE_SLICE_CNT_SHIFT 8
#define  DEC_QMATRIX_0_3_INTRA 0x7100
    #define DEC_QM0_INT_MASK 0x000000FF
    #define DEC_QM0_INT_SHIFT 0
    #define DEC_QM1_INT_MASK 0x0000FF00
    #define DEC_QM1_INT_SHIFT 8
    #define DEC_QM2_INT_MASK 0x00FF0000
    #define DEC_QM2_INT_SHIFT 16
    #define DEC_QM3_INT_MASK 0xFF000000
    #define DEC_QM3_INT_SHIFT 24
#define  DEC_QMATRIX_0_3_NONINT 0x7140
    #define DEC_QM0_NONINT_MASK 0x000000FF
    #define DEC_QM0_NONINT_SHIFT 0
    #define DEC_QM1_NONINT_MASK 0x0000FF00
    #define DEC_QM1_NONINT_SHIFT 8
    #define DEC_QM2_NONINT_MASK 0x00FF0000
    #define DEC_QM2_NONINT_SHIFT 16
    #define DEC_QM3_NONINT_MASK 0xFF000000
    #define DEC_QM3_NONINT_SHIFT 24
#define  DEC_QMATRIX_12_15_INTRA 0x710C
    #define DEC_QM12_INT_MASK 0x000000FF
    #define DEC_QM12_INT_SHIFT 0
    #define DEC_QM13_INT_MASK 0x0000FF00
    #define DEC_QM13_INT_SHIFT 8
    #define DEC_QM14_INT_MASK 0x00FF0000
    #define DEC_QM14_INT_SHIFT 16
    #define DEC_QM15_INT_MASK 0xFF000000
    #define DEC_QM15_INT_SHIFT 24
#define  DEC_QMATRIX_12_15_NONINT 0x714C
    #define DEC_QM12_NONINT_MASK 0x000000FF
    #define DEC_QM12_NONINT_SHIFT 0
    #define DEC_QM13_NONINT_MASK 0x0000FF00
    #define DEC_QM13_NONINT_SHIFT 8
    #define DEC_QM14_NONINT_MASK 0x00FF0000
    #define DEC_QM14_NONINT_SHIFT 16
    #define DEC_QM15_NONINT_MASK 0xFF000000
    #define DEC_QM15_NONINT_SHIFT 24
#define  DEC_QMATRIX_16_19_INTRA 0x7110
    #define DEC_QM16_INT_MASK 0x000000FF
    #define DEC_QM16_INT_SHIFT 0
    #define DEC_QM17_INT_MASK 0x0000FF00
    #define DEC_QM17_INT_SHIFT 8
    #define DEC_QM18_INT_MASK 0x00FF0000
    #define DEC_QM18_INT_SHIFT 16
    #define DEC_QM19_INT_MASK 0xFF000000
    #define DEC_QM19_INT_SHIFT 24
#define  DEC_QMATRIX_16_19_NONINT 0x7150
    #define DEC_QM16_NONINT_MASK 0x000000FF
    #define DEC_QM16_NONINT_SHIFT 0
    #define DEC_QM17_NONINT_MASK 0x0000FF00
    #define DEC_QM17_NONINT_SHIFT 8
    #define DEC_QM18_NONINT_MASK 0x00FF0000
    #define DEC_QM18_NONINT_SHIFT 16
    #define DEC_QM19_NONINT_MASK 0xFF000000
    #define DEC_QM19_NONINT_SHIFT 24
#define  DEC_QMATRIX_20_23_INTRA 0x7114
    #define DEC_QM20_INT_MASK 0x000000FF
    #define DEC_QM20_INT_SHIFT 0
    #define DEC_QM21_INT_MASK 0x0000FF00
    #define DEC_QM21_INT_SHIFT 8
    #define DEC_QM22_INT_MASK 0x00FF0000
    #define DEC_QM22_INT_SHIFT 16
    #define DEC_QM23_INT_MASK 0xFF000000
    #define DEC_QM23_INT_SHIFT 24
#define  DEC_QMATRIX_20_23_NONINT 0x7154
    #define DEC_QM20_NONINT_MASK 0x000000FF
    #define DEC_QM20_NONINT_SHIFT 0
    #define DEC_QM21_NONINT_MASK 0x0000FF00
    #define DEC_QM21_NONINT_SHIFT 8
    #define DEC_QM22_NONINT_MASK 0x00FF0000
    #define DEC_QM22_NONINT_SHIFT 16
    #define DEC_QM23_NONINT_MASK 0xFF000000
    #define DEC_QM23_NONINT_SHIFT 24
#define  DEC_QMATRIX_24_27_INTRA 0x7118
    #define DEC_QM24_INT_MASK 0x000000FF
    #define DEC_QM24_INT_SHIFT 0
    #define DEC_QM25_INT_MASK 0x0000FF00
    #define DEC_QM25_INT_SHIFT 8
    #define DEC_QM26_INT_MASK 0x00FF0000
    #define DEC_QM26_INT_SHIFT 16
    #define DEC_QM27_INT_MASK 0xFF000000
    #define DEC_QM27_INT_SHIFT 24
#define  DEC_QMATRIX_24_27_NONINT 0x7158
    #define DEC_QM24_NONINT_MASK 0x000000FF
    #define DEC_QM24_NONINT_SHIFT 0
    #define DEC_QM25_NONINT_MASK 0x0000FF00
    #define DEC_QM25_NONINT_SHIFT 8
    #define DEC_QM26_NONINT_MASK 0x00FF0000
    #define DEC_QM26_NONINT_SHIFT 16
    #define DEC_QM27_NONINT_MASK 0xFF000000
    #define DEC_QM27_NONINT_SHIFT 24
#define  DEC_QMATRIX_28_31_INTRA 0x711C
    #define DEC_QM28_INT_MASK 0x000000FF
    #define DEC_QM28_INT_SHIFT 0
    #define DEC_QM29_INT_MASK 0x0000FF00
    #define DEC_QM29_INT_SHIFT 8
    #define DEC_QM30_INT_MASK 0x00FF0000
    #define DEC_QM30_INT_SHIFT 16
    #define DEC_QM31_INT_MASK 0xFF000000
    #define DEC_QM31_INT_SHIFT 24
#define  DEC_QMATRIX_28_31_NONINT 0x715C
    #define DEC_QM28_NONINT_MASK 0x000000FF
    #define DEC_QM28_NONINT_SHIFT 0
    #define DEC_QM29_NONINT_MASK 0x0000FF00
    #define DEC_QM29_NONINT_SHIFT 8
    #define DEC_QM30_NONINT_MASK 0x00FF0000
    #define DEC_QM30_NONINT_SHIFT 16
    #define DEC_QM31_NONINT_MASK 0xFF000000
    #define DEC_QM31_NONINT_SHIFT 24
#define  DEC_QMATRIX_32_35_INTRA 0x7120
    #define DEC_QM32_INT_MASK 0x000000FF
    #define DEC_QM32_INT_SHIFT 0
    #define DEC_QM33_INT_MASK 0x0000FF00
    #define DEC_QM33_INT_SHIFT 8
    #define DEC_QM34_INT_MASK 0x00FF0000
    #define DEC_QM34_INT_SHIFT 16
    #define DEC_QM35_INT_MASK 0xFF000000
    #define DEC_QM35_INT_SHIFT 24
#define  DEC_QMATRIX_32_35_NONINT 0x7160
    #define DEC_QM32_NONINT_MASK 0x000000FF
    #define DEC_QM32_NONINT_SHIFT 0
    #define DEC_QM33_NONINT_MASK 0x0000FF00
    #define DEC_QM33_NONINT_SHIFT 8
    #define DEC_QM34_NONINT_MASK 0x00FF0000
    #define DEC_QM34_NONINT_SHIFT 16
    #define DEC_QM35_NONINT_MASK 0xFF000000
    #define DEC_QM35_NONINT_SHIFT 24
#define  DEC_QMATRIX_36_39_INTRA 0x7124
    #define DEC_QM36_INT_MASK 0x000000FF
    #define DEC_QM36_INT_SHIFT 0
    #define DEC_QM37_INT_MASK 0x0000FF00
    #define DEC_QM37_INT_SHIFT 8
    #define DEC_QM38_INT_MASK 0x00FF0000
    #define DEC_QM38_INT_SHIFT 16
    #define DEC_QM39_INT_MASK 0xFF000000
    #define DEC_QM39_INT_SHIFT 24
#define  DEC_QMATRIX_36_39_NONINT 0x7164
    #define DEC_QM36_NONINT_MASK 0x000000FF
    #define DEC_QM36_NONINT_SHIFT 0
    #define DEC_QM37_NONINT_MASK 0x0000FF00
    #define DEC_QM37_NONINT_SHIFT 8
    #define DEC_QM38_NONINT_MASK 0x00FF0000
    #define DEC_QM38_NONINT_SHIFT 16
    #define DEC_QM39_NONINT_MASK 0xFF000000
    #define DEC_QM39_NONINT_SHIFT 24
#define  DEC_QMATRIX_40_43_INTRA 0x7128
    #define DEC_QM40_INT_MASK 0x000000FF
    #define DEC_QM40_INT_SHIFT 0
    #define DEC_QM41_INT_MASK 0x0000FF00
    #define DEC_QM41_INT_SHIFT 8
    #define DEC_QM42_INT_MASK 0x00FF0000
    #define DEC_QM42_INT_SHIFT 16
    #define DEC_QM43_INT_MASK 0xFF000000
    #define DEC_QM43_INT_SHIFT 24
#define  DEC_QMATRIX_40_43_NONINT 0x7168
    #define DEC_QM40_NONINT_MASK 0x000000FF
    #define DEC_QM40_NONINT_SHIFT 0
    #define DEC_QM41_NONINT_MASK 0x0000FF00
    #define DEC_QM41_NONINT_SHIFT 8
    #define DEC_QM42_NONINT_MASK 0x00FF0000
    #define DEC_QM42_NONINT_SHIFT 16
    #define DEC_QM43_NONINT_MASK 0xFF000000
    #define DEC_QM43_NONINT_SHIFT 24
#define  DEC_QMATRIX_44_47_INTRA 0x712C
    #define DEC_QM44_INT_MASK 0x000000FF
    #define DEC_QM44_INT_SHIFT 0
    #define DEC_QM45_INT_MASK 0x0000FF00
    #define DEC_QM45_INT_SHIFT 8
    #define DEC_QM46_INT_MASK 0x00FF0000
    #define DEC_QM46_INT_SHIFT 16
    #define DEC_QM47_INT_MASK 0xFF000000
    #define DEC_QM47_INT_SHIFT 24
#define  DEC_QMATRIX_44_47_NONINT 0x716C
    #define DEC_QM44_NONINT_MASK 0x000000FF
    #define DEC_QM44_NONINT_SHIFT 0
    #define DEC_QM45_NONINT_MASK 0x0000FF00
    #define DEC_QM45_NONINT_SHIFT 8
    #define DEC_QM46_NONINT_MASK 0x00FF0000
    #define DEC_QM46_NONINT_SHIFT 16
    #define DEC_QM47_NONINT_MASK 0xFF000000
    #define DEC_QM47_NONINT_SHIFT 24
#define  DEC_QMATRIX_48_51_INTRA 0x7130
    #define DEC_QM48_INT_MASK 0x000000FF
    #define DEC_QM48_INT_SHIFT 0
    #define DEC_QM49_INT_MASK 0x0000FF00
    #define DEC_QM49_INT_SHIFT 8
    #define DEC_QM50_INT_MASK 0x00FF0000
    #define DEC_QM50_INT_SHIFT 16
    #define DEC_QM51_INT_MASK 0xFF000000
    #define DEC_QM51_INT_SHIFT 24
#define  DEC_QMATRIX_48_51_NONINT 0x7170
    #define DEC_QM48_NONINT_MASK 0x000000FF
    #define DEC_QM48_NONINT_SHIFT 0
    #define DEC_QM49_NONINT_MASK 0x0000FF00
    #define DEC_QM49_NONINT_SHIFT 8
    #define DEC_QM50_NONINT_MASK 0x00FF0000
    #define DEC_QM50_NONINT_SHIFT 16
    #define DEC_QM51_NONINT_MASK 0xFF000000
    #define DEC_QM51_NONINT_SHIFT 24
#define  DEC_QMATRIX_4_7_INTRA 0x7104
    #define DEC_QM4_INT_MASK 0x000000FF
    #define DEC_QM4_INT_SHIFT 0
    #define DEC_QM5_INT_MASK 0x0000FF00
    #define DEC_QM5_INT_SHIFT 8
    #define DEC_QM6_INT_MASK 0x00FF0000
    #define DEC_QM6_INT_SHIFT 16
    #define DEC_QM7_INT_MASK 0xFF000000
    #define DEC_QM7_INT_SHIFT 24
#define  DEC_QMATRIX_4_7_NONINT 0x7144
    #define DEC_QM4_NONINT_MASK 0x000000FF
    #define DEC_QM4_NONINT_SHIFT 0
    #define DEC_QM5_NONINT_MASK 0x0000FF00
    #define DEC_QM5_NONINT_SHIFT 8
    #define DEC_QM6_NONINT_MASK 0x00FF0000
    #define DEC_QM6_NONINT_SHIFT 16
    #define DEC_QM7_NONINT_MASK 0xFF000000
    #define DEC_QM7_NONINT_SHIFT 24
#define  DEC_QMATRIX_52_55_INTRA 0x7134
    #define DEC_QM52_INT_MASK 0x000000FF
    #define DEC_QM52_INT_SHIFT 0
    #define DEC_QM53_INT_MASK 0x0000FF00
    #define DEC_QM53_INT_SHIFT 8
    #define DEC_QM54_INT_MASK 0x00FF0000
    #define DEC_QM54_INT_SHIFT 16
    #define DEC_QM55_INT_MASK 0xFF000000
    #define DEC_QM55_INT_SHIFT 24
#define  DEC_QMATRIX_52_55_NONINT 0x7174
    #define DEC_QM52_NONINT_MASK 0x000000FF
    #define DEC_QM52_NONINT_SHIFT 0
    #define DEC_QM53_NONINT_MASK 0x0000FF00
    #define DEC_QM53_NONINT_SHIFT 8
    #define DEC_QM54_NONINT_MASK 0x00FF0000
    #define DEC_QM54_NONINT_SHIFT 16
    #define DEC_QM55_NONINT_MASK 0xFF000000
    #define DEC_QM55_NONINT_SHIFT 24
#define  DEC_QMATRIX_56_59_INTRA 0x7138
    #define DEC_QM56_INT_MASK 0x000000FF
    #define DEC_QM56_INT_SHIFT 0
    #define DEC_QM57_INT_MASK 0x0000FF00
    #define DEC_QM57_INT_SHIFT 8
    #define DEC_QM58_INT_MASK 0x00FF0000
    #define DEC_QM58_INT_SHIFT 16
    #define DEC_QM59_INT_MASK 0xFF000000
    #define DEC_QM59_INT_SHIFT 24
#define  DEC_QMATRIX_56_59_NONINT 0x7178
    #define DEC_QM56_NONINT_MASK 0x000000FF
    #define DEC_QM56_NONINT_SHIFT 0
    #define DEC_QM57_NONINT_MASK 0x0000FF00
    #define DEC_QM57_NONINT_SHIFT 8
    #define DEC_QM58_NONINT_MASK 0x00FF0000
    #define DEC_QM58_NONINT_SHIFT 16
    #define DEC_QM59_NONINT_MASK 0xFF000000
    #define DEC_QM59_NONINT_SHIFT 24
#define  DEC_QMATRIX_60_63_INTRA 0x713C
    #define DEC_QM60_INT_MASK 0x000000FF
    #define DEC_QM60_INT_SHIFT 0
    #define DEC_QM61_INT_MASK 0x0000FF00
    #define DEC_QM61_INT_SHIFT 8
    #define DEC_QM62_INT_MASK 0x00FF0000
    #define DEC_QM62_INT_SHIFT 16
    #define DEC_QM63_INT_MASK 0xFF000000
    #define DEC_QM63_INT_SHIFT 24
#define  DEC_QMATRIX_60_63_NONINT 0x717C
    #define DEC_QM60_NONINT_MASK 0x000000FF
    #define DEC_QM60_NONINT_SHIFT 0
    #define DEC_QM61_NONINT_MASK 0x0000FF00
    #define DEC_QM61_NONINT_SHIFT 8
    #define DEC_QM62_NONINT_MASK 0x00FF0000
    #define DEC_QM62_NONINT_SHIFT 16
    #define DEC_QM63_NONINT_MASK 0xFF000000
    #define DEC_QM63_NONINT_SHIFT 24
#define  DEC_QMATRIX_8_11_INTRA 0x7108
    #define DEC_QM8_INT_MASK 0x000000FF
    #define DEC_QM8_INT_SHIFT 0
    #define DEC_QM9_INT_MASK 0x0000FF00
    #define DEC_QM9_INT_SHIFT 8
    #define DEC_QM10_INT_MASK 0x00FF0000
    #define DEC_QM10_INT_SHIFT 16
    #define DEC_QM11_INT_MASK 0xFF000000
    #define DEC_QM11_INT_SHIFT 24
#define  DEC_QMATRIX_8_11_NONINT 0x7148
    #define DEC_QM8_NONINT_MASK 0x000000FF
    #define DEC_QM8_NONINT_SHIFT 0
    #define DEC_QM9_NONINT_MASK 0x0000FF00
    #define DEC_QM9_NONINT_SHIFT 8
    #define DEC_QM10_NONINT_MASK 0x00FF0000
    #define DEC_QM10_NONINT_SHIFT 16
    #define DEC_QM11_NONINT_MASK 0xFF000000
    #define DEC_QM11_NONINT_SHIFT 24
#define  DEC_RUNLEVEL 0x7300
    #define DEC_RUNLEVEL_LEVEL_MASK 0x00007FFF
    #define DEC_RUNLEVEL_LEVEL_SHIFT 0
    #define DEC_RUNLEVEL_LEVEL_SIGN_MASK 0x00008000
    #define DEC_RUNLEVEL_LEVEL_SIGN_SHIFT 15
    #define DEC_RUNLEVEL_RUN_MASK 0x007F0000
    #define DEC_RUNLEVEL_RUN_SHIFT 16
    #define DEC_RUNLEVEL_LAST_MASK 0x00800000
    #define DEC_RUNLEVEL_LAST_SHIFT 23
#define  DEC_SURF_SIZE 0x7358
    #define DEC_SURF_SIZE_PITCH_MASK 0x00000FC0
    #define DEC_SURF_SIZE_PITCH_SHIFT 6
#define  DIP_CTRL 0x7040
    #define EN_MASK 0x00000001
    #define EN_SHIFT 0
#define  DIP_FETCHER_ADR_A 0x7000
    #define BASE_A_MASK 0x7FFFFFF0
    #define BASE_A_SHIFT 4
#define  DIP_FETCHER_ADR_B 0x7008
    #define BASE_B_MASK 0x7FFFFFF0
    #define BASE_B_SHIFT 4
#define  DIP_FETCHER_ADR_C 0x7010
    #define BASE_C_MASK 0x7FFFFFF0
    #define BASE_C_SHIFT 4
#define  DIP_FETCHER_ADR_D 0x7018
    #define BASE_D_MASK 0x7FFFFFF0
    #define BASE_D_SHIFT 4
#define  DIP_FETCHER_CNT_A 0x7004
    #define CNT_A_MASK 0x000FFFFF
    #define CNT_A_SHIFT 0
#define  DIP_FETCHER_CNT_B 0x700C
    #define CNT_B_MASK 0x000FFFFF
    #define CNT_B_SHIFT 0
#define  DIP_FETCHER_CNT_C 0x7014
    #define CNT_C_MASK 0x000FFFFF
    #define CNT_C_SHIFT 0
#define  DIP_FETCHER_CNT_D 0x701C
    #define CNT_D_MASK 0x000FFFFF
    #define CNT_D_SHIFT 0
#define  DIP_HOST_INT_MASK 0x7058
    #define DIP_HOST_INT_MASK_INT_EN_FETCH_A_DONE_MASK 0x00000001
    #define DIP_HOST_INT_MASK_INT_EN_FETCH_A_DONE_SHIFT 0
    #define DIP_HOST_INT_MASK_INT_EN_FETCH_B_DONE_MASK 0x00000002
    #define DIP_HOST_INT_MASK_INT_EN_FETCH_B_DONE_SHIFT 1
    #define DIP_HOST_INT_MASK_INT_EN_FETCH_C_DONE_MASK 0x00000004
    #define DIP_HOST_INT_MASK_INT_EN_FETCH_C_DONE_SHIFT 2
    #define DIP_HOST_INT_MASK_INT_EN_FETCH_D_DONE_MASK 0x00000008
    #define DIP_HOST_INT_MASK_INT_EN_FETCH_D_DONE_SHIFT 3
    #define DIP_HOST_INT_MASK_INT_EN_MPP_INT_MASK 0x00000010
    #define DIP_HOST_INT_MASK_INT_EN_MPP_INT_SHIFT 4
#define  DIP_INT_STATUS 0x7054
    #define FETCH_A_DONE_MASK 0x00000001
    #define FETCH_A_DONE_SHIFT 0
    #define FETCH_B_DONE_MASK 0x00000002
    #define FETCH_B_DONE_SHIFT 1
    #define FETCH_C_DONE_MASK 0x00000004
    #define FETCH_C_DONE_SHIFT 2
    #define FETCH_D_DONE_MASK 0x00000008
    #define FETCH_D_DONE_SHIFT 3
    #define DIP_INT_STATUS_MPP_INT_MASK 0x00000010
    #define DIP_INT_STATUS_MPP_INT_SHIFT 4
#define  DIP_MIPS_INT_MASK 0x705C
    #define DIP_MIPS_INT_MASK_INT_EN_FETCH_A_DONE_MASK 0x00000001
    #define DIP_MIPS_INT_MASK_INT_EN_FETCH_A_DONE_SHIFT 0
    #define DIP_MIPS_INT_MASK_INT_EN_FETCH_B_DONE_MASK 0x00000002
    #define DIP_MIPS_INT_MASK_INT_EN_FETCH_B_DONE_SHIFT 1
    #define DIP_MIPS_INT_MASK_INT_EN_FETCH_C_DONE_MASK 0x00000004
    #define DIP_MIPS_INT_MASK_INT_EN_FETCH_C_DONE_SHIFT 2
    #define DIP_MIPS_INT_MASK_INT_EN_FETCH_D_DONE_MASK 0x00000008
    #define DIP_MIPS_INT_MASK_INT_EN_FETCH_D_DONE_SHIFT 3
    #define DIP_MIPS_INT_MASK_INT_EN_MPP_INT_MASK 0x00000010
    #define DIP_MIPS_INT_MASK_INT_EN_MPP_INT_SHIFT 4
#define  DIP_STATUS 0x7060
    #define FETCH_ACTIVE_CNT_MASK 0x000FFFFF
    #define FETCH_ACTIVE_CNT_SHIFT 0
    #define FETCH_CHA_VALID_MASK 0x00100000
    #define FETCH_CHA_VALID_SHIFT 20
    #define FETCH_CHB_VALID_MASK 0x00200000
    #define FETCH_CHB_VALID_SHIFT 21
    #define FETCH_CHC_VALID_MASK 0x00400000
    #define FETCH_CHC_VALID_SHIFT 22
    #define FETCH_CHD_VALID_MASK 0x00800000
    #define FETCH_CHD_VALID_SHIFT 23
    #define FETCH_CHA_ACTIVE_MASK 0x01000000
    #define FETCH_CHA_ACTIVE_SHIFT 24
    #define FETCH_CHB_ACTIVE_MASK 0x02000000
    #define FETCH_CHB_ACTIVE_SHIFT 25
    #define FETCH_CHC_ACTIVE_MASK 0x04000000
    #define FETCH_CHC_ACTIVE_SHIFT 26
    #define FETCH_CHD_ACTIVE_MASK 0x08000000
    #define FETCH_CHD_ACTIVE_SHIFT 27
    #define FETCH_BUSY_MASK 0x10000000
    #define FETCH_BUSY_SHIFT 28
    #define MICRO_BUSY_MASK 0x20000000
    #define MICRO_BUSY_SHIFT 29
#define  DISP_ADAC_CNTL 0xDB3C
    #define DISP_ADAC_CNTL_MASK 0xFFFFFFFF
    #define DISP_ADAC_CNTL_SHIFT 0
#define  DISP_DEBUG_OUT 0xDB0C
    #define DEBUG_OUT_MASK 0xFFFFFFFF
    #define DEBUG_OUT_SHIFT 0
#define  DISP_GLOBAL_CONTROL 0xDB00
    #define MEM_RCLI_A_REQFIFO_FULL_MASK 0x0000003F
    #define MEM_RCLI_A_REQFIFO_FULL_SHIFT 0
    #define MEM_RCLI_B_REQFIFO_FULL_MASK 0x00000FC0
    #define MEM_RCLI_B_REQFIFO_FULL_SHIFT 6
    #define DEBUG_CTRL_MUX_MASK 0x0000F000
    #define DEBUG_CTRL_MUX_SHIFT 12
    #define DEBUG_CRC_VHDCLK_MUX_MASK 0x000F0000
    #define DEBUG_CRC_VHDCLK_MUX_SHIFT 16
    #define DEBUG_CRC_VSDCLK_MUX_MASK 0x00F00000
    #define DEBUG_CRC_VSDCLK_MUX_SHIFT 20
#define  DISP_HDMI_ADDR 0xDAB8
    #define DISP_HDMI_ADDR_ADDR_MASK 0x00007FFF
    #define DISP_HDMI_ADDR_ADDR_SHIFT 0
    #define DISP_HDMI_ADDR_WOP_MASK 0x80000000
    #define DISP_HDMI_ADDR_WOP_SHIFT 31
#define  DISP_HDMI_DHCPRNG0 0xDAD0
    #define RNGSEED0_MASK 0xFFFFFFFF
    #define RNGSEED0_SHIFT 0
#define  DISP_HDMI_DHCPRNG1 0xDAD4
    #define RNGSEED1_MASK 0xFFFFFFFF
    #define RNGSEED1_SHIFT 0
#define  DISP_HDMI_RDDATA 0xDACC
    #define RDDATA_MASK 0x000000FF
    #define RDDATA_SHIFT 0
#define  DISP_HDMI_SFRRAM_WR 0xDABC
    #define DISP_HDMI_SFRRAM_WR_DATA_MASK 0x000000FF
    #define DISP_HDMI_SFRRAM_WR_DATA_SHIFT 0
    #define DISP_HDMI_SFRRAM_WR_CLRPTR_MASK 0x40000000
    #define DISP_HDMI_SFRRAM_WR_CLRPTR_SHIFT 30
    #define DISP_HDMI_SFRRAM_WR_WOP_MASK 0x80000000
    #define DISP_HDMI_SFRRAM_WR_WOP_SHIFT 31
#define  DISP_HDMI_STATUS 0xDAC4
    #define DISP_HDMI_STATUS_BUSY_MASK 0x00000001
    #define DISP_HDMI_STATUS_BUSY_SHIFT 0
    #define DISP_HDMI_STATUS_ERROR_MASK 0x00000002
    #define DISP_HDMI_STATUS_ERROR_SHIFT 1
    #define SFRRAM_BUSY_MASK 0x00000004
    #define SFRRAM_BUSY_SHIFT 2
    #define UPRAM_BUSY_MASK 0x00000008
    #define UPRAM_BUSY_SHIFT 3
#define  DISP_HDMI_UPRAM_WR 0xDAC0
    #define DISP_HDMI_UPRAM_WR_DATA_MASK 0x000000FF
    #define DISP_HDMI_UPRAM_WR_DATA_SHIFT 0
    #define DISP_HDMI_UPRAM_WR_CLRPTR_MASK 0x40000000
    #define DISP_HDMI_UPRAM_WR_CLRPTR_SHIFT 30
    #define DISP_HDMI_UPRAM_WR_WOP_MASK 0x80000000
    #define DISP_HDMI_UPRAM_WR_WOP_SHIFT 31
#define  DISP_HDMI_WRDATA 0xDAC8
    #define DISP_HDMI_WRDATA_WRDATA_MASK 0x000000FF
    #define DISP_HDMI_WRDATA_WRDATA_SHIFT 0
#define  DISP_HD_CC 0xD9CC
    #define VID0_MODE_MASK 0x00000003
    #define VID0_MODE_SHIFT 0
    #define VID1_MODE_MASK 0x00000030
    #define VID1_MODE_SHIFT 4
    #define DISP_HD_CC_GRA0_MODE_MASK 0x00000F00
    #define DISP_HD_CC_GRA0_MODE_SHIFT 8
    #define GRA1_MODE_MASK 0x0000F000
    #define GRA1_MODE_SHIFT 12
#define  DISP_HD_CMD0_FIFO 0xD800
    #define HD_VBI0_BOT_IDX_MASK 0x0000003F
    #define HD_VBI0_BOT_IDX_SHIFT 0
    #define HD_VBI0_TOP_IDX_MASK 0x00000FC0
    #define HD_VBI0_TOP_IDX_SHIFT 6
    #define HD_VBI0_FLD_SEL_MASK 0x00003000
    #define HD_VBI0_FLD_SEL_SHIFT 12
    #define HD_VID0_BOT_IDX_MASK 0x000FC000
    #define HD_VID0_BOT_IDX_SHIFT 14
    #define HD_VID0_TOP_IDX_MASK 0x03F00000
    #define HD_VID0_TOP_IDX_SHIFT 20
    #define HD_VID0_FLD_SEL_MASK 0x1C000000
    #define HD_VID0_FLD_SEL_SHIFT 26
    #define DISP_HD_CMD0_FIFO_CMD0_FIFO_WE_MASK 0x40000000
    #define DISP_HD_CMD0_FIFO_CMD0_FIFO_WE_SHIFT 30
    #define DISP_HD_CMD0_FIFO_HD_UPDATE_CMD_MASK 0x80000000
    #define DISP_HD_CMD0_FIFO_HD_UPDATE_CMD_SHIFT 31
#define  DISP_HD_CMD1_FIFO 0xD804
    #define HD_ANC0_BOT_IDX_MASK 0x0000003F
    #define HD_ANC0_BOT_IDX_SHIFT 0
    #define HD_ANC0_TOP_IDX_MASK 0x00000FC0
    #define HD_ANC0_TOP_IDX_SHIFT 6
    #define HD_ANC0_FLD_SEL_MASK 0x00003000
    #define HD_ANC0_FLD_SEL_SHIFT 12
    #define HD_VID1_BOT_IDX_MASK 0x000FC000
    #define HD_VID1_BOT_IDX_SHIFT 14
    #define HD_VID1_TOP_IDX_MASK 0x03F00000
    #define HD_VID1_TOP_IDX_SHIFT 20
    #define HD_VID1_FLD_SEL_MASK 0x1C000000
    #define HD_VID1_FLD_SEL_SHIFT 26
    #define DISP_HD_CMD1_FIFO_CMD1_FIFO_WE_MASK 0x40000000
    #define DISP_HD_CMD1_FIFO_CMD1_FIFO_WE_SHIFT 30
    #define DISP_HD_CMD1_FIFO_HD_UPDATE_CMD_MASK 0x80000000
    #define DISP_HD_CMD1_FIFO_HD_UPDATE_CMD_SHIFT 31
#define  DISP_HD_CMD2_FIFO 0xD808
    #define HD_GRA0_IDX_MASK 0x0000003F
    #define HD_GRA0_IDX_SHIFT 0
    #define HD_GRA1_IDX_MASK 0x00000FC0
    #define HD_GRA1_IDX_SHIFT 6
    #define CMD2_FIFO_WE_MASK 0x40000000
    #define CMD2_FIFO_WE_SHIFT 30
    #define DISP_HD_CMD2_FIFO_HD_UPDATE_CMD_MASK 0x80000000
    #define DISP_HD_CMD2_FIFO_HD_UPDATE_CMD_SHIFT 31
#define  DISP_HD_COMP_ALPHA 0xD990
    #define ALPHA_V0_MASK 0x000000FF
    #define ALPHA_V0_SHIFT 0
    #define ALPHA_V1_MASK 0x0000FF00
    #define ALPHA_V1_SHIFT 8
    #define ALPHA_G0_MASK 0x00FF0000
    #define ALPHA_G0_SHIFT 16
    #define ALPHA_G1_MASK 0xFF000000
    #define ALPHA_G1_SHIFT 24
#define  DISP_HD_COMP_ALPHA_MODE 0xD994
    #define ALPHA_MODE_G0_MASK 0x00000001
    #define ALPHA_MODE_G0_SHIFT 0
    #define ALPHA_MODE_G1_MASK 0x00000002
    #define ALPHA_MODE_G1_SHIFT 1
    #define DISP_HD_COMP_ALPHA_MODE_PREMULT_DISABLE_G0_MASK 0x00000004
    #define DISP_HD_COMP_ALPHA_MODE_PREMULT_DISABLE_G0_SHIFT 2
    #define PREMULT_DISABLE_G1_MASK 0x00000008
    #define PREMULT_DISABLE_G1_SHIFT 3
    #define DISP_HD_COMP_ALPHA_MODE_BACKGROUND_Y_MASK 0x0000FF00
    #define DISP_HD_COMP_ALPHA_MODE_BACKGROUND_Y_SHIFT 8
    #define DISP_HD_COMP_ALPHA_MODE_BACKGROUND_CB_MASK 0x00FF0000
    #define DISP_HD_COMP_ALPHA_MODE_BACKGROUND_CB_SHIFT 16
    #define DISP_HD_COMP_ALPHA_MODE_BACKGROUND_CR_MASK 0xFF000000
    #define DISP_HD_COMP_ALPHA_MODE_BACKGROUND_CR_SHIFT 24
#define  DISP_HD_COMP_CTRL 0xD988
    #define VID0_MUX_MASK 0x00000003
    #define VID0_MUX_SHIFT 0
    #define GRA0_MUX_MASK 0x00000030
    #define GRA0_MUX_SHIFT 4
    #define VID1_MUX_MASK 0x00000300
    #define VID1_MUX_SHIFT 8
    #define GRA1_MUX_MASK 0x00003000
    #define GRA1_MUX_SHIFT 12
    #define DISP_HD_COMP_CTRL_GAMMA_EN_MASK 0x00010000
    #define DISP_HD_COMP_CTRL_GAMMA_EN_SHIFT 16
    #define DISP_HD_COMP_CTRL_DISABLE_SHADOW_MASK 0x00020000
    #define DISP_HD_COMP_CTRL_DISABLE_SHADOW_SHIFT 17
    #define DISP_HD_COMP_CTRL_DAC_ACTIVE_MASK 0x10000000
    #define DISP_HD_COMP_CTRL_DAC_ACTIVE_SHIFT 28
    #define DISP_HD_COMP_CTRL_COMP_MODE_MASK 0x60000000
    #define DISP_HD_COMP_CTRL_COMP_MODE_SHIFT 29
    #define DISP_HD_COMP_CTRL_COMP_EN_MASK 0x80000000
    #define DISP_HD_COMP_CTRL_COMP_EN_SHIFT 31
#define  DISP_HD_COMP_GLOBAL_SIZE 0xD9B0
    #define DISP_HD_COMP_GLOBAL_SIZE_SIZE_X_MASK 0x00000FFF
    #define DISP_HD_COMP_GLOBAL_SIZE_SIZE_X_SHIFT 0
    #define DISP_HD_COMP_GLOBAL_SIZE_SIZE_Y_MASK 0x00FFF000
    #define DISP_HD_COMP_GLOBAL_SIZE_SIZE_Y_SHIFT 12
#define  DISP_HD_COMP_GRA0_POS 0xD9A8
    #define DISP_HD_COMP_GRA0_POS_POS_X_MASK 0x00000FFF
    #define DISP_HD_COMP_GRA0_POS_POS_X_SHIFT 0
    #define DISP_HD_COMP_GRA0_POS_POS_Y_MASK 0x00FFF000
    #define DISP_HD_COMP_GRA0_POS_POS_Y_SHIFT 12
#define  DISP_HD_COMP_GRA1_POS 0xD9AC
    #define DISP_HD_COMP_GRA1_POS_POS_X_MASK 0x00000FFF
    #define DISP_HD_COMP_GRA1_POS_POS_X_SHIFT 0
    #define DISP_HD_COMP_GRA1_POS_POS_Y_MASK 0x00FFF000
    #define DISP_HD_COMP_GRA1_POS_POS_Y_SHIFT 12
#define  DISP_HD_COMP_LUMA_KEY0 0xD998
    #define VID0_KEY_LOW_MASK 0x00000FFF
    #define VID0_KEY_LOW_SHIFT 0
    #define VID0_KEY_HIGH_MASK 0x00FFF000
    #define VID0_KEY_HIGH_SHIFT 12
    #define VID0_KEY_BG_MASK 0x80000000
    #define VID0_KEY_BG_SHIFT 31
#define  DISP_HD_COMP_LUMA_KEY1 0xD99C
    #define VID1_KEY_LOW_MASK 0x00000FFF
    #define VID1_KEY_LOW_SHIFT 0
    #define VID1_KEY_HIGH_MASK 0x00FFF000
    #define VID1_KEY_HIGH_SHIFT 12
    #define VID1_KEY_BG_MASK 0x80000000
    #define VID1_KEY_BG_SHIFT 31
#define  DISP_HD_COMP_SIZE 0xD98C
    #define DISP_HD_COMP_SIZE_SIZE_X_MASK 0x00000FFF
    #define DISP_HD_COMP_SIZE_SIZE_X_SHIFT 0
    #define DISP_HD_COMP_SIZE_SIZE_Y_MASK 0x00FFF000
    #define DISP_HD_COMP_SIZE_SIZE_Y_SHIFT 12
    #define DISP_HD_COMP_SIZE_OSR_MASK 0x01000000
    #define DISP_HD_COMP_SIZE_OSR_SHIFT 24
    #define DISP_HD_COMP_SIZE_INTERLACED_MASK 0x80000000
    #define DISP_HD_COMP_SIZE_INTERLACED_SHIFT 31
#define  DISP_HD_COMP_START_FLD_POS 0xD9B8
    #define DISP_HD_COMP_START_FLD_POS_FLD1_POS_Y_MASK 0x00000FFF
    #define DISP_HD_COMP_START_FLD_POS_FLD1_POS_Y_SHIFT 0
    #define DISP_HD_COMP_START_FLD_POS_FLD2_POS_Y_MASK 0x00FFF000
    #define DISP_HD_COMP_START_FLD_POS_FLD2_POS_Y_SHIFT 12
#define  DISP_HD_COMP_START_HANC_POS 0xD9BC
    #define DISP_HD_COMP_START_HANC_POS_FLD1_POS_Y_MASK 0x00000FFF
    #define DISP_HD_COMP_START_HANC_POS_FLD1_POS_Y_SHIFT 0
    #define DISP_HD_COMP_START_HANC_POS_FLD2_POS_Y_MASK 0x00FFF000
    #define DISP_HD_COMP_START_HANC_POS_FLD2_POS_Y_SHIFT 12
#define  DISP_HD_COMP_START_PIX_POS 0xD9B4
    #define DISP_HD_COMP_START_PIX_POS_POS_X_MASK 0x00000FFF
    #define DISP_HD_COMP_START_PIX_POS_POS_X_SHIFT 0
#define  DISP_HD_COMP_START_VBI_POS 0xD9C4
    #define DISP_HD_COMP_START_VBI_POS_FLD1_POS_Y_MASK 0x00000FFF
    #define DISP_HD_COMP_START_VBI_POS_FLD1_POS_Y_SHIFT 0
    #define DISP_HD_COMP_START_VBI_POS_FLD2_POS_Y_MASK 0x00FFF000
    #define DISP_HD_COMP_START_VBI_POS_FLD2_POS_Y_SHIFT 12
#define  DISP_HD_COMP_STOP_HANC_POS 0xD9C0
    #define DISP_HD_COMP_STOP_HANC_POS_FLD1_POS_Y_MASK 0x00000FFF
    #define DISP_HD_COMP_STOP_HANC_POS_FLD1_POS_Y_SHIFT 0
    #define DISP_HD_COMP_STOP_HANC_POS_FLD2_POS_Y_MASK 0x00FFF000
    #define DISP_HD_COMP_STOP_HANC_POS_FLD2_POS_Y_SHIFT 12
#define  DISP_HD_COMP_STOP_VBI_POS 0xD9C8
    #define DISP_HD_COMP_STOP_VBI_POS_FLD1_POS_Y_MASK 0x00000FFF
    #define DISP_HD_COMP_STOP_VBI_POS_FLD1_POS_Y_SHIFT 0
    #define DISP_HD_COMP_STOP_VBI_POS_FLD2_POS_Y_MASK 0x00FFF000
    #define DISP_HD_COMP_STOP_VBI_POS_FLD2_POS_Y_SHIFT 12
#define  DISP_HD_COMP_VID0_POS 0xD9A0
    #define DISP_HD_COMP_VID0_POS_POS_X_MASK 0x00000FFF
    #define DISP_HD_COMP_VID0_POS_POS_X_SHIFT 0
    #define DISP_HD_COMP_VID0_POS_POS_Y_MASK 0x00FFF000
    #define DISP_HD_COMP_VID0_POS_POS_Y_SHIFT 12
#define  DISP_HD_COMP_VID1_POS 0xD9A4
    #define DISP_HD_COMP_VID1_POS_POS_X_MASK 0x00000FFF
    #define DISP_HD_COMP_VID1_POS_POS_X_SHIFT 0
    #define DISP_HD_COMP_VID1_POS_POS_Y_MASK 0x00FFF000
    #define DISP_HD_COMP_VID1_POS_POS_Y_SHIFT 12
#define  DISP_HD_CURR_CMD0 0xD80C
    #define HD_VBI0_BOT_IDX_CURR_MASK 0x0000003F
    #define HD_VBI0_BOT_IDX_CURR_SHIFT 0
    #define HD_VBI0_TOP_IDX_CURR_MASK 0x00000FC0
    #define HD_VBI0_TOP_IDX_CURR_SHIFT 6
    #define HD_VBI0_FLD_SEL_CURR_MASK 0x00003000
    #define HD_VBI0_FLD_SEL_CURR_SHIFT 12
    #define HD_VID0_BOT_IDX_CURR_MASK 0x000FC000
    #define HD_VID0_BOT_IDX_CURR_SHIFT 14
    #define HD_VID0_TOP_IDX_CURR_MASK 0x03F00000
    #define HD_VID0_TOP_IDX_CURR_SHIFT 20
    #define HD_VID0_FLD_SEL_CURR_MASK 0x1C000000
    #define HD_VID0_FLD_SEL_CURR_SHIFT 26
    #define HD_UPDATE_CMD_CURR_MASK 0x80000000
    #define HD_UPDATE_CMD_CURR_SHIFT 31
#define  DISP_HD_CURR_CMD1 0xD810
    #define HD_ANC0_BOT_IDX_CURR_MASK 0x0000003F
    #define HD_ANC0_BOT_IDX_CURR_SHIFT 0
    #define HD_ANC0_TOP_IDX_CURR_MASK 0x00000FC0
    #define HD_ANC0_TOP_IDX_CURR_SHIFT 6
    #define HD_ANC0_FLD_SEL_CURR_MASK 0x00003000
    #define HD_ANC0_FLD_SEL_CURR_SHIFT 12
    #define HD_VID1_BOT_IDX_CURR_MASK 0x000FC000
    #define HD_VID1_BOT_IDX_CURR_SHIFT 14
    #define HD_VID1_TOP_IDX_CURR_MASK 0x03F00000
    #define HD_VID1_TOP_IDX_CURR_SHIFT 20
    #define HD_VID1_FLD_SEL_CURR_MASK 0x1C000000
    #define HD_VID1_FLD_SEL_CURR_SHIFT 26
#define  DISP_HD_CURR_CMD2 0xD814
    #define HD_GRA0_IDX_CURR_MASK 0x0000003F
    #define HD_GRA0_IDX_CURR_SHIFT 0
    #define HD_GRA1_IDX_CURR_MASK 0x00000FC0
    #define HD_GRA1_IDX_CURR_SHIFT 6
#define  DISP_HD_FIFO_STATUS 0xD830
    #define DISP_HD_FIFO_STATUS_FREE_ENTRIES_MASK 0x0000001F
    #define DISP_HD_FIFO_STATUS_FREE_ENTRIES_SHIFT 0
    #define DISP_HD_FIFO_STATUS_CURR_IDX_MASK 0x00000F00
    #define DISP_HD_FIFO_STATUS_CURR_IDX_SHIFT 8
    #define DISP_HD_FIFO_STATUS_FRM_CNT_MASK 0x000FF000
    #define DISP_HD_FIFO_STATUS_FRM_CNT_SHIFT 12
#define  DISP_HD_GENLOCK_DEN 0xDB58
    #define DISP_HD_GENLOCK_DEN_DEN_MASK 0xFFFFFFFF
    #define DISP_HD_GENLOCK_DEN_DEN_SHIFT 0
#define  DISP_HD_GENLOCK_LOWER 0xDB50
    #define DISP_HD_GENLOCK_LOWER_L_MASK 0xFFFFFFFF
    #define DISP_HD_GENLOCK_LOWER_L_SHIFT 0
#define  DISP_HD_GENLOCK_NUM 0xDB54
    #define DISP_HD_GENLOCK_NUM_NUM_MASK 0xFFFFFFFF
    #define DISP_HD_GENLOCK_NUM_NUM_SHIFT 0
#define  DISP_HD_GENLOCK_PCR 0xDB40
    #define DISP_HD_GENLOCK_PCR_NUM_MASK 0x0000FFFF
    #define DISP_HD_GENLOCK_PCR_NUM_SHIFT 0
    #define DISP_HD_GENLOCK_PCR_DEN_MASK 0xFFFF0000
    #define DISP_HD_GENLOCK_PCR_DEN_SHIFT 16
#define  DISP_HD_GENLOCK_PCR_LOWER 0xDB48
    #define DISP_HD_GENLOCK_PCR_LOWER_L_MASK 0xFFFFFFFF
    #define DISP_HD_GENLOCK_PCR_LOWER_L_SHIFT 0
#define  DISP_HD_GENLOCK_PCR_UPPER 0xDB44
    #define DISP_HD_GENLOCK_PCR_UPPER_U_MASK 0x000003FF
    #define DISP_HD_GENLOCK_PCR_UPPER_U_SHIFT 0
#define  DISP_HD_GENLOCK_UPPER 0xDB4C
    #define DISP_HD_GENLOCK_UPPER_U_MASK 0x000003FF
    #define DISP_HD_GENLOCK_UPPER_U_SHIFT 0
#define  DISP_HD_GRA0_ADR 0xD904
    #define DISP_HD_GRA0_ADR_BASE_MASK 0xFFFFFFF0
    #define DISP_HD_GRA0_ADR_BASE_SHIFT 4
#define  DISP_HD_GRA0_BUF 0xD908
    #define DISP_HD_GRA0_BUF_PITCH_MASK 0x0000FFF0
    #define DISP_HD_GRA0_BUF_PITCH_SHIFT 4
    #define DISP_HD_GRA0_BUF_SIZE_MASK 0xFFFF0000
    #define DISP_HD_GRA0_BUF_SIZE_SHIFT 16
#define  DISP_HD_GRA0_CLUT_DATA 0xD930
    #define GRA0_CLUT_DATA_MASK 0xFFFFFFFF
    #define GRA0_CLUT_DATA_SHIFT 0
#define  DISP_HD_GRA0_CLUT_INDEX 0xD92C
    #define GRA0_CLUT_INDEX_MASK 0x000000FF
    #define GRA0_CLUT_INDEX_SHIFT 0
#define  DISP_HD_GRA0_FORMAT 0xD90C
    #define DISP_HD_GRA0_FORMAT_MEM_FORMAT_MASK 0x0000000F
    #define DISP_HD_GRA0_FORMAT_MEM_FORMAT_SHIFT 0
    #define DISP_HD_GRA0_FORMAT_TRANS_MASK 0x00000080
    #define DISP_HD_GRA0_FORMAT_TRANS_SHIFT 7
    #define DISP_HD_GRA0_FORMAT_DITHER_MASK 0x00000300
    #define DISP_HD_GRA0_FORMAT_DITHER_SHIFT 8
    #define DISP_HD_GRA0_FORMAT_TAG_MASK 0x0001F000
    #define DISP_HD_GRA0_FORMAT_TAG_SHIFT 12
    #define DISP_HD_GRA0_FORMAT_CLK_GATE_ENABLE_MASK 0x00020000
    #define DISP_HD_GRA0_FORMAT_CLK_GATE_ENABLE_SHIFT 17
    #define DISP_HD_GRA0_FORMAT_MEM_RCLI_SAFE_OFF_MASK 0x00040000
    #define DISP_HD_GRA0_FORMAT_MEM_RCLI_SAFE_OFF_SHIFT 18
    #define DISP_HD_GRA0_FORMAT_UNDERFLOW_RESET_OFF_MASK 0x00080000
    #define DISP_HD_GRA0_FORMAT_UNDERFLOW_RESET_OFF_SHIFT 19
    #define DISP_HD_GRA0_FORMAT_MAX_REQ_SIZE_MASK 0x0FF00000
    #define DISP_HD_GRA0_FORMAT_MAX_REQ_SIZE_SHIFT 20
    #define DISP_HD_GRA0_FORMAT_PIPE_DISABLE_MASK 0x80000000
    #define DISP_HD_GRA0_FORMAT_PIPE_DISABLE_SHIFT 31
#define  DISP_HD_GRA0_FORMAT1 0xD910
    #define DISP_HD_GRA0_FORMAT1_PEL_POSITION_A_MASK 0x00000003
    #define DISP_HD_GRA0_FORMAT1_PEL_POSITION_A_SHIFT 0
    #define DISP_HD_GRA0_FORMAT1_PEL_POSITION_R_MASK 0x0000000C
    #define DISP_HD_GRA0_FORMAT1_PEL_POSITION_R_SHIFT 2
    #define DISP_HD_GRA0_FORMAT1_PEL_POSITION_G_MASK 0x00000030
    #define DISP_HD_GRA0_FORMAT1_PEL_POSITION_G_SHIFT 4
    #define DISP_HD_GRA0_FORMAT1_PEL_POSITION_B_MASK 0x000000C0
    #define DISP_HD_GRA0_FORMAT1_PEL_POSITION_B_SHIFT 6
    #define DISP_HD_GRA0_FORMAT1_CLUT_OFFSET_MASK 0x0000FF00
    #define DISP_HD_GRA0_FORMAT1_CLUT_OFFSET_SHIFT 8
    #define DISP_HD_GRA0_FORMAT1_CLUT_PAGE_MASK 0x00010000
    #define DISP_HD_GRA0_FORMAT1_CLUT_PAGE_SHIFT 16
    #define DISP_HD_GRA0_FORMAT1_URGENT_REQ_FLAG_MASK 0xFFF00000
    #define DISP_HD_GRA0_FORMAT1_URGENT_REQ_FLAG_SHIFT 20
#define  DISP_HD_GRA0_HSCA_INV_RATIO 0xD928
    #define DISP_HD_GRA0_HSCA_INV_RATIO_HSCA_INV_RATIO_MASK 0xFFFFFFFF
    #define DISP_HD_GRA0_HSCA_INV_RATIO_HSCA_INV_RATIO_SHIFT 0
#define  DISP_HD_GRA0_SAMPLES 0xD914
    #define DISP_HD_GRA0_SAMPLES_WIDTH_MASK 0x0000FFFF
    #define DISP_HD_GRA0_SAMPLES_WIDTH_SHIFT 0
#define  DISP_HD_GRA0_SCALED_SIZE 0xD91C
    #define DISP_HD_GRA0_SCALED_SIZE_H_SCALED_SIZE_MASK 0x00000FFF
    #define DISP_HD_GRA0_SCALED_SIZE_H_SCALED_SIZE_SHIFT 0
    #define DISP_HD_GRA0_SCALED_SIZE_V_SCALED_SIZE_MASK 0x00FFF000
    #define DISP_HD_GRA0_SCALED_SIZE_V_SCALED_SIZE_SHIFT 12
#define  DISP_HD_GRA0_SIZE 0xD900
    #define DISP_HD_GRA0_SIZE_H_SIZE_MASK 0x00000FFF
    #define DISP_HD_GRA0_SIZE_H_SIZE_SHIFT 0
    #define DISP_HD_GRA0_SIZE_V_SIZE_MASK 0x00FFF000
    #define DISP_HD_GRA0_SIZE_V_SIZE_SHIFT 12
#define  DISP_HD_GRA0_VSCA_INIT 0xD924
    #define DISP_HD_GRA0_VSCA_INIT_POSREG_INIT0_MASK 0x000000FF
    #define DISP_HD_GRA0_VSCA_INIT_POSREG_INIT0_SHIFT 0
    #define DISP_HD_GRA0_VSCA_INIT_POSREG_INIT1_MASK 0x00FF0000
    #define DISP_HD_GRA0_VSCA_INIT_POSREG_INIT1_SHIFT 16
#define  DISP_HD_GRA0_VSCA_INV_RATIO 0xD918
    #define DISP_HD_GRA0_VSCA_INV_RATIO_VSCA_INV_RATIO_MASK 0xFFFFFFFF
    #define DISP_HD_GRA0_VSCA_INV_RATIO_VSCA_INV_RATIO_SHIFT 0
#define  DISP_HD_GRA0_VSCA_START 0xD920
    #define DISP_HD_GRA0_VSCA_START_START_POS0_MASK 0x0000000F
    #define DISP_HD_GRA0_VSCA_START_START_POS0_SHIFT 0
    #define DISP_HD_GRA0_VSCA_START_START_POS1_MASK 0x000F0000
    #define DISP_HD_GRA0_VSCA_START_START_POS1_SHIFT 16
#define  DISP_HD_GRA1_ADR 0xD938
    #define DISP_HD_GRA1_ADR_BASE_MASK 0xFFFFFFF0
    #define DISP_HD_GRA1_ADR_BASE_SHIFT 4
#define  DISP_HD_GRA1_BUF 0xD93C
    #define DISP_HD_GRA1_BUF_PITCH_MASK 0x0000FFF0
    #define DISP_HD_GRA1_BUF_PITCH_SHIFT 4
    #define DISP_HD_GRA1_BUF_SIZE_MASK 0xFFFF0000
    #define DISP_HD_GRA1_BUF_SIZE_SHIFT 16
#define  DISP_HD_GRA1_CLUT_DATA 0xD964
    #define GRA1_CLUT_DATA_MASK 0xFFFFFFFF
    #define GRA1_CLUT_DATA_SHIFT 0
#define  DISP_HD_GRA1_CLUT_INDEX 0xD960
    #define GRA1_CLUT_INDEX_MASK 0x000000FF
    #define GRA1_CLUT_INDEX_SHIFT 0
#define  DISP_HD_GRA1_FORMAT 0xD940
    #define DISP_HD_GRA1_FORMAT_MEM_FORMAT_MASK 0x0000000F
    #define DISP_HD_GRA1_FORMAT_MEM_FORMAT_SHIFT 0
    #define DISP_HD_GRA1_FORMAT_TRANS_MASK 0x00000080
    #define DISP_HD_GRA1_FORMAT_TRANS_SHIFT 7
    #define DISP_HD_GRA1_FORMAT_DITHER_MASK 0x00000300
    #define DISP_HD_GRA1_FORMAT_DITHER_SHIFT 8
    #define DISP_HD_GRA1_FORMAT_TAG_MASK 0x0001F000
    #define DISP_HD_GRA1_FORMAT_TAG_SHIFT 12
    #define DISP_HD_GRA1_FORMAT_CLK_GATE_ENABLE_MASK 0x00020000
    #define DISP_HD_GRA1_FORMAT_CLK_GATE_ENABLE_SHIFT 17
    #define DISP_HD_GRA1_FORMAT_MEM_RCLI_SAFE_OFF_MASK 0x00040000
    #define DISP_HD_GRA1_FORMAT_MEM_RCLI_SAFE_OFF_SHIFT 18
    #define DISP_HD_GRA1_FORMAT_UNDERFLOW_RESET_OFF_MASK 0x00080000
    #define DISP_HD_GRA1_FORMAT_UNDERFLOW_RESET_OFF_SHIFT 19
    #define DISP_HD_GRA1_FORMAT_MAX_REQ_SIZE_MASK 0x0FF00000
    #define DISP_HD_GRA1_FORMAT_MAX_REQ_SIZE_SHIFT 20
    #define DISP_HD_GRA1_FORMAT_PIPE_DISABLE_MASK 0x80000000
    #define DISP_HD_GRA1_FORMAT_PIPE_DISABLE_SHIFT 31
#define  DISP_HD_GRA1_FORMAT1 0xD944
    #define DISP_HD_GRA1_FORMAT1_PEL_POSITION_A_MASK 0x00000003
    #define DISP_HD_GRA1_FORMAT1_PEL_POSITION_A_SHIFT 0
    #define DISP_HD_GRA1_FORMAT1_PEL_POSITION_R_MASK 0x0000000C
    #define DISP_HD_GRA1_FORMAT1_PEL_POSITION_R_SHIFT 2
    #define DISP_HD_GRA1_FORMAT1_PEL_POSITION_G_MASK 0x00000030
    #define DISP_HD_GRA1_FORMAT1_PEL_POSITION_G_SHIFT 4
    #define DISP_HD_GRA1_FORMAT1_PEL_POSITION_B_MASK 0x000000C0
    #define DISP_HD_GRA1_FORMAT1_PEL_POSITION_B_SHIFT 6
    #define DISP_HD_GRA1_FORMAT1_CLUT_OFFSET_MASK 0x0000FF00
    #define DISP_HD_GRA1_FORMAT1_CLUT_OFFSET_SHIFT 8
    #define DISP_HD_GRA1_FORMAT1_CLUT_PAGE_MASK 0x00010000
    #define DISP_HD_GRA1_FORMAT1_CLUT_PAGE_SHIFT 16
    #define DISP_HD_GRA1_FORMAT1_URGENT_REQ_FLAG_MASK 0xFFF00000
    #define DISP_HD_GRA1_FORMAT1_URGENT_REQ_FLAG_SHIFT 20
#define  DISP_HD_GRA1_HSCA_INV_RATIO 0xD954
    #define DISP_HD_GRA1_HSCA_INV_RATIO_HSCA_INV_RATIO_MASK 0xFFFFFFFF
    #define DISP_HD_GRA1_HSCA_INV_RATIO_HSCA_INV_RATIO_SHIFT 0
#define  DISP_HD_GRA1_SAMPLES 0xD948
    #define DISP_HD_GRA1_SAMPLES_WIDTH_MASK 0x0000FFFF
    #define DISP_HD_GRA1_SAMPLES_WIDTH_SHIFT 0
#define  DISP_HD_GRA1_SCALED_SIZE 0xD950
    #define DISP_HD_GRA1_SCALED_SIZE_H_SCALED_SIZE_MASK 0x00000FFF
    #define DISP_HD_GRA1_SCALED_SIZE_H_SCALED_SIZE_SHIFT 0
    #define DISP_HD_GRA1_SCALED_SIZE_V_SCALED_SIZE_MASK 0x00FFF000
    #define DISP_HD_GRA1_SCALED_SIZE_V_SCALED_SIZE_SHIFT 12
#define  DISP_HD_GRA1_SIZE 0xD934
    #define DISP_HD_GRA1_SIZE_H_SIZE_MASK 0x00000FFF
    #define DISP_HD_GRA1_SIZE_H_SIZE_SHIFT 0
    #define DISP_HD_GRA1_SIZE_V_SIZE_MASK 0x00FFF000
    #define DISP_HD_GRA1_SIZE_V_SIZE_SHIFT 12
#define  DISP_HD_GRA1_VSCA_INIT 0xD95C
    #define DISP_HD_GRA1_VSCA_INIT_POSREG_INIT0_MASK 0x000000FF
    #define DISP_HD_GRA1_VSCA_INIT_POSREG_INIT0_SHIFT 0
    #define DISP_HD_GRA1_VSCA_INIT_POSREG_INIT1_MASK 0x00FF0000
    #define DISP_HD_GRA1_VSCA_INIT_POSREG_INIT1_SHIFT 16
#define  DISP_HD_GRA1_VSCA_INV_RATIO 0xD94C
    #define DISP_HD_GRA1_VSCA_INV_RATIO_VSCA_INV_RATIO_MASK 0xFFFFFFFF
    #define DISP_HD_GRA1_VSCA_INV_RATIO_VSCA_INV_RATIO_SHIFT 0
#define  DISP_HD_GRA1_VSCA_START 0xD958
    #define DISP_HD_GRA1_VSCA_START_START_POS0_MASK 0x0000000F
    #define DISP_HD_GRA1_VSCA_START_START_POS0_SHIFT 0
    #define DISP_HD_GRA1_VSCA_START_START_POS1_MASK 0x000F0000
    #define DISP_HD_GRA1_VSCA_START_START_POS1_SHIFT 16
#define  DISP_HD_HANC0_ADR 0xD978
    #define DISP_HD_HANC0_ADR_BASE_MASK 0xFFFFFFF0
    #define DISP_HD_HANC0_ADR_BASE_SHIFT 4
#define  DISP_HD_HANC0_BUF 0xD97C
    #define DISP_HD_HANC0_BUF_PITCH_MASK 0x0000FFF0
    #define DISP_HD_HANC0_BUF_PITCH_SHIFT 4
    #define DISP_HD_HANC0_BUF_SIZE_MASK 0xFFFF0000
    #define DISP_HD_HANC0_BUF_SIZE_SHIFT 16
#define  DISP_HD_HANC0_SAMPLES 0xD984
    #define DISP_HD_HANC0_SAMPLES_WIDTH_MASK 0x0000FFFF
    #define DISP_HD_HANC0_SAMPLES_WIDTH_SHIFT 0
#define  DISP_HD_LINE_INTERRUPT 0xD9E8
    #define DISP_HD_LINE_INTERRUPT_A_MASK 0x00000FFF
    #define DISP_HD_LINE_INTERRUPT_A_SHIFT 0
    #define DISP_HD_LINE_INTERRUPT_B_MASK 0x0FFF0000
    #define DISP_HD_LINE_INTERRUPT_B_SHIFT 16
#define  DISP_HD_OCC_C11 0xD9D0
    #define DISP_HD_OCC_C11_C11_MASK 0x0000FFFF
    #define DISP_HD_OCC_C11_C11_SHIFT 0
    #define DISP_HD_OCC_C11_C12_MASK 0xFFFF0000
    #define DISP_HD_OCC_C11_C12_SHIFT 16
#define  DISP_HD_OCC_C13 0xD9D4
    #define DISP_HD_OCC_C13_C13_MASK 0x0000FFFF
    #define DISP_HD_OCC_C13_C13_SHIFT 0
    #define DISP_HD_OCC_C13_K1_MASK 0xFFFF0000
    #define DISP_HD_OCC_C13_K1_SHIFT 16
#define  DISP_HD_OCC_C21 0xD9D8
    #define DISP_HD_OCC_C21_C21_MASK 0x0000FFFF
    #define DISP_HD_OCC_C21_C21_SHIFT 0
    #define DISP_HD_OCC_C21_C22_MASK 0xFFFF0000
    #define DISP_HD_OCC_C21_C22_SHIFT 16
#define  DISP_HD_OCC_C23 0xD9DC
    #define DISP_HD_OCC_C23_C23_MASK 0x0000FFFF
    #define DISP_HD_OCC_C23_C23_SHIFT 0
    #define DISP_HD_OCC_C23_K2_MASK 0xFFFF0000
    #define DISP_HD_OCC_C23_K2_SHIFT 16
#define  DISP_HD_OCC_C31 0xD9E0
    #define DISP_HD_OCC_C31_C31_MASK 0x0000FFFF
    #define DISP_HD_OCC_C31_C31_SHIFT 0
    #define DISP_HD_OCC_C31_C32_MASK 0xFFFF0000
    #define DISP_HD_OCC_C31_C32_SHIFT 16
#define  DISP_HD_OCC_C33 0xD9E4
    #define DISP_HD_OCC_C33_C33_MASK 0x0000FFFF
    #define DISP_HD_OCC_C33_C33_SHIFT 0
    #define DISP_HD_OCC_C33_K3_MASK 0xFFFF0000
    #define DISP_HD_OCC_C33_K3_SHIFT 16
#define  DISP_HD_OUTPUT_LIMIT 0xD834
    #define DISP_HD_OUTPUT_LIMIT_Y_LIMIT_PLUS_MASK 0x000000FF
    #define DISP_HD_OUTPUT_LIMIT_Y_LIMIT_PLUS_SHIFT 0
    #define DISP_HD_OUTPUT_LIMIT_Y_LIMIT_MINUS_MASK 0x0000FF00
    #define DISP_HD_OUTPUT_LIMIT_Y_LIMIT_MINUS_SHIFT 8
    #define DISP_HD_OUTPUT_LIMIT_CBCR_LIMIT_PLUS_MASK 0x00FF0000
    #define DISP_HD_OUTPUT_LIMIT_CBCR_LIMIT_PLUS_SHIFT 16
    #define DISP_HD_OUTPUT_LIMIT_CBCR_LIMIT_MINUS_MASK 0xFF000000
    #define DISP_HD_OUTPUT_LIMIT_CBCR_LIMIT_MINUS_SHIFT 24
#define  DISP_HD_RAM_ADDR 0xD82C
    #define DISP_HD_RAM_ADDR_ADDR_MASK 0x0000FFFF
    #define DISP_HD_RAM_ADDR_ADDR_SHIFT 0
    #define DISP_BLOCK_SEL_MASK 0x00FF0000
    #define DISP_BLOCK_SEL_SHIFT 16
    #define DISP_CLOCK_SEL_MASK 0x07000000
    #define DISP_CLOCK_SEL_SHIFT 24
#define  DISP_HD_RAM_STATUS 0xD828
    #define DISP_STATUS_MASK 0x00000001
    #define DISP_STATUS_SHIFT 0
#define  DISP_HD_RAM_WDATA 0xD818
    #define DISP_HD_RAM_WDATA_DATA_MASK 0xFFFFFFFF
    #define DISP_HD_RAM_WDATA_DATA_SHIFT 0
#define  DISP_HD_RAM_WDATA1 0xD81C
    #define DISP_HD_RAM_WDATA1_DATA_MASK 0xFFFFFFFF
    #define DISP_HD_RAM_WDATA1_DATA_SHIFT 0
#define  DISP_HD_RAM_WDATA2 0xD820
    #define DISP_HD_RAM_WDATA2_DATA_MASK 0xFFFFFFFF
    #define DISP_HD_RAM_WDATA2_DATA_SHIFT 0
#define  DISP_HD_RAM_WDATA3 0xD824
    #define DISP_HD_RAM_WDATA3_DATA_MASK 0xFFFFFFFF
    #define DISP_HD_RAM_WDATA3_DATA_SHIFT 0
#define  DISP_HD_VBI0_ADR 0xD96C
    #define DISP_HD_VBI0_ADR_BASE_MASK 0xFFFFFFF0
    #define DISP_HD_VBI0_ADR_BASE_SHIFT 4
#define  DISP_HD_VBI0_BUF 0xD970
    #define DISP_HD_VBI0_BUF_PITCH_MASK 0x0000FFF0
    #define DISP_HD_VBI0_BUF_PITCH_SHIFT 4
    #define DISP_HD_VBI0_BUF_SIZE_MASK 0xFFFF0000
    #define DISP_HD_VBI0_BUF_SIZE_SHIFT 16
#define  DISP_HD_VBI0_HANC0_FORMAT 0xD980
    #define DISP_HD_VBI0_HANC0_FORMAT_HANC_INPUT_10BIT_MASK 0x00000001
    #define DISP_HD_VBI0_HANC0_FORMAT_HANC_INPUT_10BIT_SHIFT 0
    #define DISP_HD_VBI0_HANC0_FORMAT_HANC_MEM_FORMAT_MASK 0x00000002
    #define DISP_HD_VBI0_HANC0_FORMAT_HANC_MEM_FORMAT_SHIFT 1
    #define DISP_HD_VBI0_HANC0_FORMAT_HANC_MAX_REQ_SIZE_MASK 0x00000FF0
    #define DISP_HD_VBI0_HANC0_FORMAT_HANC_MAX_REQ_SIZE_SHIFT 4
    #define DISP_HD_VBI0_HANC0_FORMAT_HANC_MEM_RCLI_SAFE_OFF_MASK 0x00002000
    #define DISP_HD_VBI0_HANC0_FORMAT_HANC_MEM_RCLI_SAFE_OFF_SHIFT 13
    #define DISP_HD_VBI0_HANC0_FORMAT_HANC_PIPE_DISABLE_MASK 0x00008000
    #define DISP_HD_VBI0_HANC0_FORMAT_HANC_PIPE_DISABLE_SHIFT 15
    #define DISP_HD_VBI0_HANC0_FORMAT_VBI_MEM_FORMAT_MASK 0x00010000
    #define DISP_HD_VBI0_HANC0_FORMAT_VBI_MEM_FORMAT_SHIFT 16
    #define DISP_HD_VBI0_HANC0_FORMAT_VBI_MAX_REQ_SIZE_MASK 0x0FF00000
    #define DISP_HD_VBI0_HANC0_FORMAT_VBI_MAX_REQ_SIZE_SHIFT 20
    #define DISP_HD_VBI0_HANC0_FORMAT_VBI_MEM_RCLI_SAFE_OFF_MASK 0x20000000
    #define DISP_HD_VBI0_HANC0_FORMAT_VBI_MEM_RCLI_SAFE_OFF_SHIFT 29
    #define DISP_HD_VBI0_HANC0_FORMAT_VBI_PIPE_DISABLE_MASK 0x80000000
    #define DISP_HD_VBI0_HANC0_FORMAT_VBI_PIPE_DISABLE_SHIFT 31
#define  DISP_HD_VBI0_HANC0_SIZE 0xD968
    #define DISP_HD_VBI0_HANC0_SIZE_VBI_SIZE_MASK 0x00000FFF
    #define DISP_HD_VBI0_HANC0_SIZE_VBI_SIZE_SHIFT 0
    #define DISP_HD_VBI0_HANC0_SIZE_HANC_SIZE_MASK 0x00FFF000
    #define DISP_HD_VBI0_HANC0_SIZE_HANC_SIZE_SHIFT 12
#define  DISP_HD_VBI0_SAMPLES 0xD974
    #define DISP_HD_VBI0_SAMPLES_WIDTH_MASK 0x0000FFFF
    #define DISP_HD_VBI0_SAMPLES_WIDTH_SHIFT 0
#define  DISP_HD_VENC0_BLACK 0xDA04
    #define DISP_HD_VENC0_BLACK_BLACK_MASK 0x000003FF
    #define DISP_HD_VENC0_BLACK_BLACK_SHIFT 0
#define  DISP_HD_VENC0_BLANK 0xDA08
    #define DISP_HD_VENC0_BLANK_BLANK_MASK 0x000003FF
    #define DISP_HD_VENC0_BLANK_BLANK_SHIFT 0
    #define DISP_HD_VENC0_BLANK_SYNC_STEP_MASK 0x03FF0000
    #define DISP_HD_VENC0_BLANK_SYNC_STEP_SHIFT 16
#define  DISP_HD_VENC0_CB2GAIN 0xDA18
    #define DISP_HD_VENC0_CB2GAIN_CB2PBGAIN_MASK 0x000000FF
    #define DISP_HD_VENC0_CB2GAIN_CB2PBGAIN_SHIFT 0
    #define DISP_HD_VENC0_CB2GAIN_CB2PRGAIN_MASK 0x00FF0000
    #define DISP_HD_VENC0_CB2GAIN_CB2PRGAIN_SHIFT 16
    #define DISP_HD_VENC0_CB2GAIN_SOFT_CLIP_MASK 0x80000000
    #define DISP_HD_VENC0_CB2GAIN_SOFT_CLIP_SHIFT 31
#define  DISP_HD_VENC0_CB_FREQ 0xD9F8
    #define DISP_HD_VENC0_CB_FREQ_CB_FREQ_MASK 0xFFFFFFFF
    #define DISP_HD_VENC0_CB_FREQ_CB_FREQ_SHIFT 0
#define  DISP_HD_VENC0_CB_PHASE 0xD9FC
    #define DISP_HD_VENC0_CB_PHASE_CB_PHASE_MASK 0x000000FF
    #define DISP_HD_VENC0_CB_PHASE_CB_PHASE_SHIFT 0
#define  DISP_HD_VENC0_CLRSPC 0xDA68
    #define DISP_HD_VENC0_CLRSPC_ACTIVE_MASK 0x00000001
    #define DISP_HD_VENC0_CLRSPC_ACTIVE_SHIFT 0
    #define DISP_HD_VENC0_CLRSPC_REDADDBLANK_MASK 0x00000002
    #define DISP_HD_VENC0_CLRSPC_REDADDBLANK_SHIFT 1
    #define DISP_HD_VENC0_CLRSPC_REDADDSYNC_MASK 0x00000004
    #define DISP_HD_VENC0_CLRSPC_REDADDSYNC_SHIFT 2
    #define DISP_HD_VENC0_CLRSPC_GRNADDBLANK_MASK 0x00000008
    #define DISP_HD_VENC0_CLRSPC_GRNADDBLANK_SHIFT 3
    #define DISP_HD_VENC0_CLRSPC_GRNADDSYNC_MASK 0x00000010
    #define DISP_HD_VENC0_CLRSPC_GRNADDSYNC_SHIFT 4
    #define DISP_HD_VENC0_CLRSPC_BLUADDBLANK_MASK 0x00000020
    #define DISP_HD_VENC0_CLRSPC_BLUADDBLANK_SHIFT 5
    #define DISP_HD_VENC0_CLRSPC_BLUADDSYNC_MASK 0x00000040
    #define DISP_HD_VENC0_CLRSPC_BLUADDSYNC_SHIFT 6
    #define DISP_HD_VENC0_CLRSPC_SCALE_MASK 0x00000080
    #define DISP_HD_VENC0_CLRSPC_SCALE_SHIFT 7
#define  DISP_HD_VENC0_CLRSPCPB 0xDA60
    #define DISP_HD_VENC0_CLRSPCPB_PB2R_MASK 0x000003FF
    #define DISP_HD_VENC0_CLRSPCPB_PB2R_SHIFT 0
    #define DISP_HD_VENC0_CLRSPCPB_PB2G_MASK 0x000FFC00
    #define DISP_HD_VENC0_CLRSPCPB_PB2G_SHIFT 10
    #define DISP_HD_VENC0_CLRSPCPB_PB2B_MASK 0x3FF00000
    #define DISP_HD_VENC0_CLRSPCPB_PB2B_SHIFT 20
#define  DISP_HD_VENC0_CLRSPCPR 0xDA64
    #define DISP_HD_VENC0_CLRSPCPR_PR2R_MASK 0x000003FF
    #define DISP_HD_VENC0_CLRSPCPR_PR2R_SHIFT 0
    #define DISP_HD_VENC0_CLRSPCPR_PR2G_MASK 0x000FFC00
    #define DISP_HD_VENC0_CLRSPCPR_PR2G_SHIFT 10
    #define DISP_HD_VENC0_CLRSPCPR_PR2B_MASK 0x3FF00000
    #define DISP_HD_VENC0_CLRSPCPR_PR2B_SHIFT 20
#define  DISP_HD_VENC0_CLRSPCY 0xDA5C
    #define DISP_HD_VENC0_CLRSPCY_Y2R_MASK 0x000003FF
    #define DISP_HD_VENC0_CLRSPCY_Y2R_SHIFT 0
    #define DISP_HD_VENC0_CLRSPCY_Y2G_MASK 0x000FFC00
    #define DISP_HD_VENC0_CLRSPCY_Y2G_SHIFT 10
    #define DISP_HD_VENC0_CLRSPCY_Y2B_MASK 0x3FF00000
    #define DISP_HD_VENC0_CLRSPCY_Y2B_SHIFT 20
    #define DISP_HD_VENC0_CLRSPCY_CSC_CNTL_MASK 0xC0000000
    #define DISP_HD_VENC0_CLRSPCY_CSC_CNTL_SHIFT 30
#define  DISP_HD_VENC0_CMPST_GAIN 0xDA00
    #define DISP_HD_VENC0_CMPST_GAIN_CMPST_Y_GAIN_MASK 0x000000FF
    #define DISP_HD_VENC0_CMPST_GAIN_CMPST_Y_GAIN_SHIFT 0
    #define DISP_HD_VENC0_CMPST_GAIN_CMPST_V_GAIN_MASK 0x0000FF00
    #define DISP_HD_VENC0_CMPST_GAIN_CMPST_V_GAIN_SHIFT 8
    #define DISP_HD_VENC0_CMPST_GAIN_CMPST_U_GAIN_MASK 0x00FF0000
    #define DISP_HD_VENC0_CMPST_GAIN_CMPST_U_GAIN_SHIFT 16
    #define DISP_HD_VENC0_CMPST_GAIN_CMPST_CB_GAIN_MASK 0xFF000000
    #define DISP_HD_VENC0_CMPST_GAIN_CMPST_CB_GAIN_SHIFT 24
#define  DISP_HD_VENC0_COEF_FUVCMPS0 0xDA30
    #define DISP_HD_VENC0_COEF_FUVCMPS0_COEF0_FUVCMPS_MASK 0x000000FF
    #define DISP_HD_VENC0_COEF_FUVCMPS0_COEF0_FUVCMPS_SHIFT 0
    #define DISP_HD_VENC0_COEF_FUVCMPS0_COEF1_FUVCMPS_MASK 0x0000FF00
    #define DISP_HD_VENC0_COEF_FUVCMPS0_COEF1_FUVCMPS_SHIFT 8
    #define DISP_HD_VENC0_COEF_FUVCMPS0_COEF2_FUVCMPS_MASK 0x00FF0000
    #define DISP_HD_VENC0_COEF_FUVCMPS0_COEF2_FUVCMPS_SHIFT 16
    #define DISP_HD_VENC0_COEF_FUVCMPS0_COEF3_FUVCMPS_MASK 0xFF000000
    #define DISP_HD_VENC0_COEF_FUVCMPS0_COEF3_FUVCMPS_SHIFT 24
#define  DISP_HD_VENC0_COEF_FUVCMPS1 0xDA34
    #define DISP_HD_VENC0_COEF_FUVCMPS1_COEF4_FUVCMPS_MASK 0x000000FF
    #define DISP_HD_VENC0_COEF_FUVCMPS1_COEF4_FUVCMPS_SHIFT 0
    #define DISP_HD_VENC0_COEF_FUVCMPS1_COEF5_FUVCMPS_MASK 0x0000FF00
    #define DISP_HD_VENC0_COEF_FUVCMPS1_COEF5_FUVCMPS_SHIFT 8
    #define DISP_HD_VENC0_COEF_FUVCMPS1_COEF6_FUVCMPS_MASK 0x00FF0000
    #define DISP_HD_VENC0_COEF_FUVCMPS1_COEF6_FUVCMPS_SHIFT 16
    #define DISP_HD_VENC0_COEF_FUVCMPS1_COEF7_FUVCMPS_MASK 0xFF000000
    #define DISP_HD_VENC0_COEF_FUVCMPS1_COEF7_FUVCMPS_SHIFT 24
#define  DISP_HD_VENC0_COEF_FUVCMPS2 0xDA38
    #define DISP_HD_VENC0_COEF_FUVCMPS2_COEF8_FUVCMPS_MASK 0x000000FF
    #define DISP_HD_VENC0_COEF_FUVCMPS2_COEF8_FUVCMPS_SHIFT 0
    #define DISP_HD_VENC0_COEF_FUVCMPS2_COEF9_FUVCMPS_MASK 0x0000FF00
    #define DISP_HD_VENC0_COEF_FUVCMPS2_COEF9_FUVCMPS_SHIFT 8
    #define DISP_HD_VENC0_COEF_FUVCMPS2_COEF10_FUVCMPS_MASK 0x00FF0000
    #define DISP_HD_VENC0_COEF_FUVCMPS2_COEF10_FUVCMPS_SHIFT 16
    #define DISP_HD_VENC0_COEF_FUVCMPS2_COEF11_FUVCMPS_MASK 0xFF000000
    #define DISP_HD_VENC0_COEF_FUVCMPS2_COEF11_FUVCMPS_SHIFT 24
#define  DISP_HD_VENC0_COEF_FUVCMPS3 0xDA3C
    #define DISP_HD_VENC0_COEF_FUVCMPS3_COEF12_FUVCMPS_MASK 0x000000FF
    #define DISP_HD_VENC0_COEF_FUVCMPS3_COEF12_FUVCMPS_SHIFT 0
#define  DISP_HD_VENC0_COEF_FYCMPS0 0xDA20
    #define DISP_HD_VENC0_COEF_FYCMPS0_COEF0_FYCMPS_MASK 0x000000FF
    #define DISP_HD_VENC0_COEF_FYCMPS0_COEF0_FYCMPS_SHIFT 0
    #define DISP_HD_VENC0_COEF_FYCMPS0_COEF1_FYCMPS_MASK 0x0000FF00
    #define DISP_HD_VENC0_COEF_FYCMPS0_COEF1_FYCMPS_SHIFT 8
    #define DISP_HD_VENC0_COEF_FYCMPS0_COEF2_FYCMPS_MASK 0x00FF0000
    #define DISP_HD_VENC0_COEF_FYCMPS0_COEF2_FYCMPS_SHIFT 16
    #define DISP_HD_VENC0_COEF_FYCMPS0_COEF3_FYCMPS_MASK 0xFF000000
    #define DISP_HD_VENC0_COEF_FYCMPS0_COEF3_FYCMPS_SHIFT 24
#define  DISP_HD_VENC0_COEF_FYCMPS1 0xDA24
    #define DISP_HD_VENC0_COEF_FYCMPS1_COEF4_FYCMPS_MASK 0x000000FF
    #define DISP_HD_VENC0_COEF_FYCMPS1_COEF4_FYCMPS_SHIFT 0
    #define DISP_HD_VENC0_COEF_FYCMPS1_COEF5_FYCMPS_MASK 0x0000FF00
    #define DISP_HD_VENC0_COEF_FYCMPS1_COEF5_FYCMPS_SHIFT 8
    #define DISP_HD_VENC0_COEF_FYCMPS1_COEF6_FYCMPS_MASK 0x00FF0000
    #define DISP_HD_VENC0_COEF_FYCMPS1_COEF6_FYCMPS_SHIFT 16
    #define DISP_HD_VENC0_COEF_FYCMPS1_COEF7_FYCMPS_MASK 0xFF000000
    #define DISP_HD_VENC0_COEF_FYCMPS1_COEF7_FYCMPS_SHIFT 24
#define  DISP_HD_VENC0_COEF_FYCMPS2 0xDA28
    #define DISP_HD_VENC0_COEF_FYCMPS2_COEF8_FYCMPS_MASK 0x000000FF
    #define DISP_HD_VENC0_COEF_FYCMPS2_COEF8_FYCMPS_SHIFT 0
    #define DISP_HD_VENC0_COEF_FYCMPS2_COEF9_FYCMPS_MASK 0x0000FF00
    #define DISP_HD_VENC0_COEF_FYCMPS2_COEF9_FYCMPS_SHIFT 8
    #define DISP_HD_VENC0_COEF_FYCMPS2_COEF10_FYCMPS_MASK 0x00FF0000
    #define DISP_HD_VENC0_COEF_FYCMPS2_COEF10_FYCMPS_SHIFT 16
    #define DISP_HD_VENC0_COEF_FYCMPS2_COEF11_FYCMPS_MASK 0xFF000000
    #define DISP_HD_VENC0_COEF_FYCMPS2_COEF11_FYCMPS_SHIFT 24
#define  DISP_HD_VENC0_COEF_FYCMPS3 0xDA2C
    #define DISP_HD_VENC0_COEF_FYCMPS3_COEF12_FYCMPS_MASK 0x000000FF
    #define DISP_HD_VENC0_COEF_FYCMPS3_COEF12_FYCMPS_SHIFT 0
#define  DISP_HD_VENC0_COMPDEG 0xDA6C
    #define DISP_HD_VENC0_COMPDEG_COMPDEG_CS_MASK 0x000000FF
    #define DISP_HD_VENC0_COMPDEG_COMPDEG_CS_SHIFT 0
#define  DISP_HD_VENC0_CONT_STATUS 0xD9F4
    #define DISP_HD_VENC0_CONT_STATUS_CONT_STATUS_MASK 0xFFFFFFFF
    #define DISP_HD_VENC0_CONT_STATUS_CONT_STATUS_SHIFT 0
#define  DISP_HD_VENC0_DCS_CMPNT 0xDA98
    #define DISP_HD_VENC0_DCS_CMPNT_SYNC_MASK 0x00000FFF
    #define DISP_HD_VENC0_DCS_CMPNT_SYNC_SHIFT 0
    #define DISP_HD_VENC0_DCS_CMPNT_BLANK_MASK 0x0FFF0000
    #define DISP_HD_VENC0_DCS_CMPNT_BLANK_SHIFT 16
#define  DISP_HD_VENC0_DCS_CMPNT_AGC 0xDAA8
    #define DISP_HD_VENC0_DCS_CMPNT_AGC_AGC1_A_MASK 0x00000FFF
    #define DISP_HD_VENC0_DCS_CMPNT_AGC_AGC1_A_SHIFT 0
    #define DISP_HD_VENC0_DCS_CMPNT_AGC_AGC1_B_MASK 0x0FFF0000
    #define DISP_HD_VENC0_DCS_CMPNT_AGC_AGC1_B_SHIFT 16
#define  DISP_HD_VENC0_DCS_CMPNT_GO 0xDA9C
    #define DISP_HD_VENC0_DCS_CMPNT_GO_GAIN_MASK 0x00000FFF
    #define DISP_HD_VENC0_DCS_CMPNT_GO_GAIN_SHIFT 0
    #define DISP_HD_VENC0_DCS_CMPNT_GO_OFFSET_MASK 0x0FFF0000
    #define DISP_HD_VENC0_DCS_CMPNT_GO_OFFSET_SHIFT 16
#define  DISP_HD_VENC0_DCS_CMPNT_ICLK227K 0xDAA4
    #define DISP_HD_VENC0_DCS_CMPNT_ICLK227K_ICLK227K_1_MASK 0x00000FFF
    #define DISP_HD_VENC0_DCS_CMPNT_ICLK227K_ICLK227K_1_SHIFT 0
    #define DISP_HD_VENC0_DCS_CMPNT_ICLK227K_ICLK227K_2_MASK 0x0FFF0000
    #define DISP_HD_VENC0_DCS_CMPNT_ICLK227K_ICLK227K_2_SHIFT 16
#define  DISP_HD_VENC0_DCS_CMPNT_ICLK397K 0xDAA0
    #define DISP_HD_VENC0_DCS_CMPNT_ICLK397K_ICLK397K_MASK 0x00000FFF
    #define DISP_HD_VENC0_DCS_CMPNT_ICLK397K_ICLK397K_SHIFT 0
    #define DISP_HD_VENC0_DCS_CMPNT_ICLK397K_ICLK397K_C_MASK 0x0FFF0000
    #define DISP_HD_VENC0_DCS_CMPNT_ICLK397K_ICLK397K_C_SHIFT 16
#define  DISP_HD_VENC0_DCS_CONFIG 0xDA94
    #define DISP_HD_VENC0_DCS_CONFIG_FIELDRATE50_MASK 0x00000001
    #define DISP_HD_VENC0_DCS_CONFIG_FIELDRATE50_SHIFT 0
    #define DISP_HD_VENC0_DCS_CONFIG_SD_COMPOSITE_MASK 0x00000002
    #define DISP_HD_VENC0_DCS_CONFIG_SD_COMPOSITE_SHIFT 1
    #define DISP_HD_VENC0_DCS_CONFIG_SD_COMPONENT_I_MASK 0x00000004
    #define DISP_HD_VENC0_DCS_CONFIG_SD_COMPONENT_I_SHIFT 2
    #define DISP_HD_VENC0_DCS_CONFIG_SD_COMPONENT_P_MASK 0x00000008
    #define DISP_HD_VENC0_DCS_CONFIG_SD_COMPONENT_P_SHIFT 3
    #define DISP_HD_VENC0_DCS_CONFIG_HD_720P_MASK 0x00000010
    #define DISP_HD_VENC0_DCS_CONFIG_HD_720P_SHIFT 4
    #define DISP_HD_VENC0_DCS_CONFIG_HD_1080I_MASK 0x00000020
    #define DISP_HD_VENC0_DCS_CONFIG_HD_1080I_SHIFT 5
    #define DISP_HD_VENC0_DCS_CONFIG_HD_1080P_MASK 0x00000040
    #define DISP_HD_VENC0_DCS_CONFIG_HD_1080P_SHIFT 6
    #define DISP_HD_VENC0_DCS_CONFIG_HD_1080P_SLOW_MASK 0x00000080
    #define DISP_HD_VENC0_DCS_CONFIG_HD_1080P_SLOW_SHIFT 7
    #define DISP_HD_VENC0_DCS_CONFIG_DCS_ENABLE_MASK 0x00000100
    #define DISP_HD_VENC0_DCS_CONFIG_DCS_ENABLE_SHIFT 8
    #define DISP_HD_VENC0_DCS_CONFIG_DCS_CLOCK2X_MASK 0x00000200
    #define DISP_HD_VENC0_DCS_CONFIG_DCS_CLOCK2X_SHIFT 9
    #define DISP_HD_VENC0_DCS_CONFIG_DCS_SYNC_OFFSET_MASK 0x1FFF0000
    #define DISP_HD_VENC0_DCS_CONFIG_DCS_SYNC_OFFSET_SHIFT 16
    #define DISP_HD_VENC0_DCS_CONFIG_DCS_RST_MASK 0x80000000
    #define DISP_HD_VENC0_DCS_CONFIG_DCS_RST_SHIFT 31
#define  DISP_HD_VENC0_DCS_FAKE_FRAME_START 0xDAB0
    #define DISP_HD_VENC0_DCS_FAKE_FRAME_START_DUMMY_BIT_MASK 0x00000001
    #define DISP_HD_VENC0_DCS_FAKE_FRAME_START_DUMMY_BIT_SHIFT 0
#define  DISP_HD_VENC0_DCS_KEY_HIGH 0xDA8C
    #define DISP_HD_VENC0_DCS_KEY_HIGH_DATA_MASK 0xFFFFFFFF
    #define DISP_HD_VENC0_DCS_KEY_HIGH_DATA_SHIFT 0
#define  DISP_HD_VENC0_DCS_KEY_LOW 0xDA90
    #define DISP_HD_VENC0_DCS_KEY_LOW_DATA_MASK 0xFFFFFFFF
    #define DISP_HD_VENC0_DCS_KEY_LOW_DATA_SHIFT 0
#define  DISP_HD_VENC0_DCS_START_LINE 0xDAAC
    #define DISP_HD_VENC0_DCS_START_LINE_MASK 0x00000FFF
    #define DISP_HD_VENC0_DCS_START_LINE_SHIFT 0
#define  DISP_HD_VENC0_DCS_STATUS 0xDAB4
    #define DISP_HD_VENC0_DCS_STATUS_BUSY_N_MASK 0x00000001
    #define DISP_HD_VENC0_DCS_STATUS_BUSY_N_SHIFT 0
    #define DISP_HD_VENC0_DCS_STATUS_LOCKED_MASK 0x00000002
    #define DISP_HD_VENC0_DCS_STATUS_LOCKED_SHIFT 1
    #define DISP_HD_VENC0_DCS_STATUS_ACTIVE_MASK 0x00000004
    #define DISP_HD_VENC0_DCS_STATUS_ACTIVE_SHIFT 2
    #define DISP_HD_VENC0_DCS_STATUS_CPREGLOW_MASK 0xFFFFFF00
    #define DISP_HD_VENC0_DCS_STATUS_CPREGLOW_SHIFT 8
#define  DISP_HD_VENC0_DVE_CNTRL 0xDA7C
    #define DISP_HD_VENC0_DVE_CNTRL_CLKDIV_MASK 0x00000001
    #define DISP_HD_VENC0_DVE_CNTRL_CLKDIV_SHIFT 0
    #define DISP_HD_VENC0_DVE_CNTRL_BUSTYPE_MASK 0x00000006
    #define DISP_HD_VENC0_DVE_CNTRL_BUSTYPE_SHIFT 1
    #define DISP_HD_VENC0_DVE_CNTRL_BUSWIDTH_MASK 0x00000018
    #define DISP_HD_VENC0_DVE_CNTRL_BUSWIDTH_SHIFT 3
    #define DISP_HD_VENC0_DVE_CNTRL_CLKSAMPONRISING_MASK 0x00000020
    #define DISP_HD_VENC0_DVE_CNTRL_CLKSAMPONRISING_SHIFT 5
    #define DISP_HD_VENC0_DVE_CNTRL_OUTPUT_ORDER_MASK 0x000003C0
    #define DISP_HD_VENC0_DVE_CNTRL_OUTPUT_ORDER_SHIFT 6
    #define DISP_HD_VENC0_DVE_CNTRL_BLANK_ON_EOFN_MASK 0x00010000
    #define DISP_HD_VENC0_DVE_CNTRL_BLANK_ON_EOFN_SHIFT 16
#define  DISP_HD_VENC0_DVE_FIELD_BNDRY 0xDA70
    #define DISP_HD_VENC0_DVE_FIELD_BNDRY_DVE_FIELD_BNDRY_1_MASK 0x00000FFF
    #define DISP_HD_VENC0_DVE_FIELD_BNDRY_DVE_FIELD_BNDRY_1_SHIFT 0
    #define DISP_HD_VENC0_DVE_FIELD_BNDRY_DVE_FIELD_BNDRY_2_MASK 0x0FFF0000
    #define DISP_HD_VENC0_DVE_FIELD_BNDRY_DVE_FIELD_BNDRY_2_SHIFT 16
#define  DISP_HD_VENC0_DVE_HSYNC 0xDA88
    #define DISP_HD_VENC0_DVE_HSYNC_START_MASK 0x00001FFF
    #define DISP_HD_VENC0_DVE_HSYNC_START_SHIFT 0
    #define DISP_HD_VENC0_DVE_HSYNC_END_MASK 0x1FFF0000
    #define DISP_HD_VENC0_DVE_HSYNC_END_SHIFT 16
#define  DISP_HD_VENC0_DVE_VBLANK_END_BNDRY 0xDA78
    #define DISP_HD_VENC0_DVE_VBLANK_END_BNDRY_DVE_VBLANK_END_BNDRY_1_MASK 0x00000FFF
    #define DISP_HD_VENC0_DVE_VBLANK_END_BNDRY_DVE_VBLANK_END_BNDRY_1_SHIFT 0
    #define DISP_HD_VENC0_DVE_VBLANK_END_BNDRY_DVE_VBLANK_END_BNDRY_2_MASK 0x0FFF0000
    #define DISP_HD_VENC0_DVE_VBLANK_END_BNDRY_DVE_VBLANK_END_BNDRY_2_SHIFT 16
#define  DISP_HD_VENC0_DVE_VBLANK_START_BNDRY 0xDA74
    #define DISP_HD_VENC0_DVE_VBLANK_START_BNDRY_DVE_VBLANK_START_BNDRY_1_MASK 0x00000FFF
    #define DISP_HD_VENC0_DVE_VBLANK_START_BNDRY_DVE_VBLANK_START_BNDRY_1_SHIFT 0
    #define DISP_HD_VENC0_DVE_VBLANK_START_BNDRY_DVE_VBLANK_START_BNDRY_2_MASK 0x0FFF0000
    #define DISP_HD_VENC0_DVE_VBLANK_START_BNDRY_DVE_VBLANK_START_BNDRY_2_SHIFT 16
#define  DISP_HD_VENC0_DVE_VSYNC_END 0xDA84
    #define DISP_HD_VENC0_DVE_VSYNC_END_FRAME_1_MASK 0x00000FFF
    #define DISP_HD_VENC0_DVE_VSYNC_END_FRAME_1_SHIFT 0
    #define DISP_HD_VENC0_DVE_VSYNC_END_FRAME_2_MASK 0x00FFF000
    #define DISP_HD_VENC0_DVE_VSYNC_END_FRAME_2_SHIFT 12
    #define F2OFFHIGH_MASK 0x1F000000
    #define F2OFFHIGH_SHIFT 24
#define  DISP_HD_VENC0_DVE_VSYNC_START 0xDA80
    #define DISP_HD_VENC0_DVE_VSYNC_START_FRAME_1_MASK 0x00000FFF
    #define DISP_HD_VENC0_DVE_VSYNC_START_FRAME_1_SHIFT 0
    #define DISP_HD_VENC0_DVE_VSYNC_START_FRAME_2_MASK 0x00FFF000
    #define DISP_HD_VENC0_DVE_VSYNC_START_FRAME_2_SHIFT 12
    #define F2OFFLOW_MASK 0xFF000000
    #define F2OFFLOW_SHIFT 24
#define  DISP_HD_VENC0_FIELDBNDRY 0xDA1C
    #define DISP_HD_VENC0_FIELDBNDRY_FIELDBNDRY_MASK 0x00000FFF
    #define DISP_HD_VENC0_FIELDBNDRY_FIELDBNDRY_SHIFT 0
#define  DISP_HD_VENC0_MACROV_CS_PARAM 0xDA58
    #define DISP_HD_VENC0_MACROV_CS_PARAM_MACROV_CS_INC_MASK 0x00000FFF
    #define DISP_HD_VENC0_MACROV_CS_PARAM_MACROV_CS_INC_SHIFT 0
    #define DISP_HD_VENC0_MACROV_CS_PARAM_MACROV_CS_NUM_LINES_MASK 0x000F0000
    #define DISP_HD_VENC0_MACROV_CS_PARAM_MACROV_CS_NUM_LINES_SHIFT 16
#define  DISP_HD_VENC0_MACROV_CS_STRTF 0xDA54
    #define DISP_HD_VENC0_MACROV_CS_STRTF_MACROV_CS_STRTF1_MASK 0x00000FFF
    #define DISP_HD_VENC0_MACROV_CS_STRTF_MACROV_CS_STRTF1_SHIFT 0
    #define DISP_HD_VENC0_MACROV_CS_STRTF_MACROV_CS_STRTF2_MASK 0x0FFF0000
    #define DISP_HD_VENC0_MACROV_CS_STRTF_MACROV_CS_STRTF2_SHIFT 16
    #define DISP_HD_VENC0_MACROV_CS_STRTF_MACROV_CS_EN_MASK 0x80000000
    #define DISP_HD_VENC0_MACROV_CS_STRTF_MACROV_CS_EN_SHIFT 31
#define  DISP_HD_VENC0_MACROV_LVL 0xDA50
    #define DISP_HD_VENC0_MACROV_LVL_MACROV_LVL_MASK 0xFFFFFFFF
    #define DISP_HD_VENC0_MACROV_LVL_MACROV_LVL_SHIFT 0
#define  DISP_HD_VENC0_MACROV_T1_EVEN 0xDA40
    #define DISP_HD_VENC0_MACROV_T1_EVEN_MACROV_T1_EVEN_MASK 0xFFFFFFFF
    #define DISP_HD_VENC0_MACROV_T1_EVEN_MACROV_T1_EVEN_SHIFT 0
#define  DISP_HD_VENC0_MACROV_T1_ODD 0xDA48
    #define DISP_HD_VENC0_MACROV_T1_ODD_MACROV_T1_ODD_MASK 0xFFFFFFFF
    #define DISP_HD_VENC0_MACROV_T1_ODD_MACROV_T1_ODD_SHIFT 0
#define  DISP_HD_VENC0_MACROV_T2_EVEN 0xDA44
    #define DISP_HD_VENC0_MACROV_T2_EVEN_MACROV_T2_EVEN_MASK 0xFFFFFFFF
    #define DISP_HD_VENC0_MACROV_T2_EVEN_MACROV_T2_EVEN_SHIFT 0
#define  DISP_HD_VENC0_MACROV_T2_ODD 0xDA4C
    #define DISP_HD_VENC0_MACROV_T2_ODD_MACROV_T2_ODD_MASK 0xFFFFFFFF
    #define DISP_HD_VENC0_MACROV_T2_ODD_MACROV_T2_ODD_SHIFT 0
#define  DISP_HD_VENC0_SYNC1 0xDA0C
    #define DISP_HD_VENC0_SYNC1_SYNC1_MASK 0x000003FF
    #define DISP_HD_VENC0_SYNC1_SYNC1_SHIFT 0
    #define DISP_HD_VENC0_SYNC1_CNST1_MASK 0x03FF0000
    #define DISP_HD_VENC0_SYNC1_CNST1_SHIFT 16
#define  DISP_HD_VENC0_SYNC2 0xDA10
    #define DISP_HD_VENC0_SYNC2_SYNC2_MASK 0x000003FF
    #define DISP_HD_VENC0_SYNC2_SYNC2_SHIFT 0
    #define DISP_HD_VENC0_SYNC2_CNST2_MASK 0x03FF0000
    #define DISP_HD_VENC0_SYNC2_CNST2_SHIFT 16
#define  DISP_HD_VENC0_WRADDR 0xD9EC
    #define DISP_HD_VENC0_WRADDR_WRADDR_MASK 0xFFFFFFFF
    #define DISP_HD_VENC0_WRADDR_WRADDR_SHIFT 0
#define  DISP_HD_VENC0_WRDATA 0xD9F0
    #define DISP_HD_VENC0_WRDATA_WRDATA_MASK 0xFFFFFFFF
    #define DISP_HD_VENC0_WRDATA_WRDATA_SHIFT 0
#define  DISP_HD_VENC0_YCMPN 0xDA14
    #define DISP_HD_VENC0_YCMPN_YCMPNGAIN_MASK 0x000000FF
    #define DISP_HD_VENC0_YCMPN_YCMPNGAIN_SHIFT 0
    #define DISP_HD_VENC0_YCMPN_YCMPNOFF_MASK 0x03FF0000
    #define DISP_HD_VENC0_YCMPN_YCMPNOFF_SHIFT 16
#define  DISP_HD_VID0_BUF_PITCH 0xD840
    #define DISP_HD_VID0_BUF_PITCH_Y_MASK 0x00001FF0
    #define DISP_HD_VID0_BUF_PITCH_Y_SHIFT 4
    #define DISP_HD_VID0_BUF_PITCH_C_MASK 0x1FF00000
    #define DISP_HD_VID0_BUF_PITCH_C_SHIFT 20
#define  DISP_HD_VID0_BUF_SIZE 0xD844
    #define DISP_HD_VID0_BUF_SIZE_Y_MASK 0x00007FFF
    #define DISP_HD_VID0_BUF_SIZE_Y_SHIFT 0
    #define DISP_HD_VID0_BUF_SIZE_C_MASK 0xFFFF0000
    #define DISP_HD_VID0_BUF_SIZE_C_SHIFT 16
#define  DISP_HD_VID0_CB_ADR 0xD850
    #define DISP_HD_VID0_CB_ADR_BASE_MASK 0xFFFFFFF0
    #define DISP_HD_VID0_CB_ADR_BASE_SHIFT 4
#define  DISP_HD_VID0_CR_ADR 0xD854
    #define DISP_HD_VID0_CR_ADR_BASE_MASK 0xFFFFFFF0
    #define DISP_HD_VID0_CR_ADR_BASE_SHIFT 4
#define  DISP_HD_VID0_DEINT0 0xD89C
    #define DEINT_HYBRID_TYPE_MASK 0x00000007
    #define DEINT_HYBRID_TYPE_SHIFT 0
    #define MAX_OTHER_NEG_ONLY2_MASK 0x00000010
    #define MAX_OTHER_NEG_ONLY2_SHIFT 4
    #define MAX_OTHER_NEG_ONLY4_MASK 0x00000020
    #define MAX_OTHER_NEG_ONLY4_SHIFT 5
    #define MAX_OTHER_NEG_ONLY6_MASK 0x00000040
    #define MAX_OTHER_NEG_ONLY6_SHIFT 6
    #define MAX_OTHER_NEG_ONLY8_MASK 0x00000080
    #define MAX_OTHER_NEG_ONLY8_SHIFT 7
    #define PROTECTION_COEF0_MASK 0x00000F00
    #define PROTECTION_COEF0_SHIFT 8
    #define PROTECTION_COEF1_MASK 0x0000F000
    #define PROTECTION_COEF1_SHIFT 12
    #define FORCE90_LEFT_MASK 0x000F0000
    #define FORCE90_LEFT_SHIFT 16
    #define FORCE90_RIGHT_MASK 0x7FF00000
    #define FORCE90_RIGHT_SHIFT 20
#define  DISP_HD_VID0_DEINT1 0xD8A0
    #define THRESHOLD2_MASK 0x0000FFFF
    #define THRESHOLD2_SHIFT 0
    #define THRESHOLD4_MASK 0xFFFF0000
    #define THRESHOLD4_SHIFT 16
#define  DISP_HD_VID0_DEINT2 0xD8A4
    #define THRESHOLD6_MASK 0x0000FFFF
    #define THRESHOLD6_SHIFT 0
    #define THRESHOLD8_MASK 0xFFFF0000
    #define THRESHOLD8_SHIFT 16
#define  DISP_HD_VID0_FORMAT 0xD838
    #define DISP_HD_VID0_FORMAT_INPUT_10BIT_MASK 0x00000001
    #define DISP_HD_VID0_FORMAT_INPUT_10BIT_SHIFT 0
    #define DISP_HD_VID0_FORMAT_INPUT_422_MASK 0x00000002
    #define DISP_HD_VID0_FORMAT_INPUT_422_SHIFT 1
    #define DISP_HD_VID0_FORMAT_DITHER_MASK 0x0000000C
    #define DISP_HD_VID0_FORMAT_DITHER_SHIFT 2
    #define DISP_HD_VID0_FORMAT_BANK_ACTIVE_MASK 0x00000010
    #define DISP_HD_VID0_FORMAT_BANK_ACTIVE_SHIFT 4
    #define DISP_HD_VID0_FORMAT_DEINT_EN_MASK 0x00000300
    #define DISP_HD_VID0_FORMAT_DEINT_EN_SHIFT 8
    #define DISP_HD_VID0_FORMAT_DEINT_CBCR_MASK 0x00000400
    #define DISP_HD_VID0_FORMAT_DEINT_CBCR_SHIFT 10
    #define DIAGONAL_MASK 0x00000800
    #define DIAGONAL_SHIFT 11
    #define DISP_HD_VID0_FORMAT_VID_FORMAT_MASK 0x00010000
    #define DISP_HD_VID0_FORMAT_VID_FORMAT_SHIFT 16
    #define DISP_HD_VID0_FORMAT_CLK_GATE_ENABLE_MASK 0x00020000
    #define DISP_HD_VID0_FORMAT_CLK_GATE_ENABLE_SHIFT 17
    #define DISP_HD_VID0_FORMAT_MEM_RCLI_SAFE_OFF_MASK 0x00040000
    #define DISP_HD_VID0_FORMAT_MEM_RCLI_SAFE_OFF_SHIFT 18
    #define DISP_HD_VID0_FORMAT_UNDERFLOW_RESET_OFF_MASK 0x00080000
    #define DISP_HD_VID0_FORMAT_UNDERFLOW_RESET_OFF_SHIFT 19
    #define DISP_HD_VID0_FORMAT_URGENT_REQ_FLAG_MASK 0x0FF00000
    #define DISP_HD_VID0_FORMAT_URGENT_REQ_FLAG_SHIFT 20
    #define DISP_HD_VID0_FORMAT_MAX_LINE_REQ_MASK 0x70000000
    #define DISP_HD_VID0_FORMAT_MAX_LINE_REQ_SHIFT 28
    #define DISP_HD_VID0_FORMAT_PIPE_DISABLE_MASK 0x80000000
    #define DISP_HD_VID0_FORMAT_PIPE_DISABLE_SHIFT 31
#define  DISP_HD_VID0_HSBC0 0xD858
    #define DISP_HD_VID0_HSBC0_SCALE_Y_MASK 0x000000FF
    #define DISP_HD_VID0_HSBC0_SCALE_Y_SHIFT 0
    #define DISP_HD_VID0_HSBC0_BRIGHT_MASK 0x0003FF00
    #define DISP_HD_VID0_HSBC0_BRIGHT_SHIFT 8
    #define DISP_HD_VID0_HSBC0_CONTRAST_MASK 0xFF000000
    #define DISP_HD_VID0_HSBC0_CONTRAST_SHIFT 24
#define  DISP_HD_VID0_HSBC1 0xD85C
    #define DISP_HD_VID0_HSBC1_HUE_COS_MASK 0x0000FFFF
    #define DISP_HD_VID0_HSBC1_HUE_COS_SHIFT 0
    #define DISP_HD_VID0_HSBC1_HUE_SIN_MASK 0xFFFF0000
    #define DISP_HD_VID0_HSBC1_HUE_SIN_SHIFT 16
#define  DISP_HD_VID0_HSBC2 0xD860
    #define DISP_HD_VID0_HSBC2_SCALE_CBCR_MASK 0x000000FF
    #define DISP_HD_VID0_HSBC2_SCALE_CBCR_SHIFT 0
    #define DISP_HD_VID0_HSBC2_SAT_MASK 0xFF000000
    #define DISP_HD_VID0_HSBC2_SAT_SHIFT 24
#define  DISP_HD_VID0_HSCA_INIT 0xD884
    #define DISP_HD_VID0_HSCA_INIT_POSREG_INIT_Y_MASK 0x0000FFFF
    #define DISP_HD_VID0_HSCA_INIT_POSREG_INIT_Y_SHIFT 0
    #define DISP_HD_VID0_HSCA_INIT_POSREG_INIT_CBCR_MASK 0xFFFF0000
    #define DISP_HD_VID0_HSCA_INIT_POSREG_INIT_CBCR_SHIFT 16
#define  DISP_HD_VID0_HSCA_INV_RATIO 0xD87C
    #define DISP_HD_VID0_HSCA_INV_RATIO_HSCA_INV_RATIO_MASK 0xFFFFFFFF
    #define DISP_HD_VID0_HSCA_INV_RATIO_HSCA_INV_RATIO_SHIFT 0
#define  DISP_HD_VID0_HSCA_NONLINEAR 0xD880
    #define DISP_HD_VID0_HSCA_NONLINEAR_SIZE_MASK 0x000003FF
    #define DISP_HD_VID0_HSCA_NONLINEAR_SIZE_SHIFT 0
#define  DISP_HD_VID0_HSCA_START 0xD888
    #define DISP_HD_VID0_HSCA_START_START_POS_MASK 0x0000003F
    #define DISP_HD_VID0_HSCA_START_START_POS_SHIFT 0
    #define DISP_HD_VID0_HSCA_START_START_CBCR_POS_MASK 0x00003F00
    #define DISP_HD_VID0_HSCA_START_START_CBCR_POS_SHIFT 8
#define  DISP_HD_VID0_HSHARP0 0xD88C
    #define H0_MASK 0x000000FF
    #define H0_SHIFT 0
    #define H1_MASK 0x0000FF00
    #define H1_SHIFT 8
    #define H2_MASK 0x00FF0000
    #define H2_SHIFT 16
    #define H3_MASK 0xFF000000
    #define H3_SHIFT 24
#define  DISP_HD_VID0_HSHARP1 0xD890
    #define H4_MASK 0x000000FF
    #define H4_SHIFT 0
    #define G0_MASK 0x0000FF00
    #define G0_SHIFT 8
    #define N0_MASK 0x00FF0000
    #define N0_SHIFT 16
    #define DISP_HD_VID0_HSHARP1_ENABLE_MASK 0x80000000
    #define DISP_HD_VID0_HSHARP1_ENABLE_SHIFT 31
#define  DISP_HD_VID0_INPUT_CBCR_LIMIT 0xD898
    #define DISP_HD_VID0_INPUT_CBCR_LIMIT_CBCR_LIMIT_PLUS_MASK 0x000000FF
    #define DISP_HD_VID0_INPUT_CBCR_LIMIT_CBCR_LIMIT_PLUS_SHIFT 0
    #define DISP_HD_VID0_INPUT_CBCR_LIMIT_CBCR_LIMIT_MINUS_MASK 0x0000FF00
    #define DISP_HD_VID0_INPUT_CBCR_LIMIT_CBCR_LIMIT_MINUS_SHIFT 8
#define  DISP_HD_VID0_INPUT_Y_LIMIT 0xD894
    #define DISP_HD_VID0_INPUT_Y_LIMIT_Y_LIMIT_PLUS_MASK 0x000000FF
    #define DISP_HD_VID0_INPUT_Y_LIMIT_Y_LIMIT_PLUS_SHIFT 0
    #define DISP_HD_VID0_INPUT_Y_LIMIT_Y_LIMIT_MINUS_MASK 0x0000FF00
    #define DISP_HD_VID0_INPUT_Y_LIMIT_Y_LIMIT_MINUS_SHIFT 8
    #define DISP_HD_VID0_INPUT_Y_LIMIT_Y_ZERO_MASK 0x00FF0000
    #define DISP_HD_VID0_INPUT_Y_LIMIT_Y_ZERO_SHIFT 16
    #define DISP_HD_VID0_INPUT_Y_LIMIT_Y_CENTER_MASK 0xFF000000
    #define DISP_HD_VID0_INPUT_Y_LIMIT_Y_CENTER_SHIFT 24
#define  DISP_HD_VID0_MEM_RCLI_CTRL 0xD83C
    #define DISP_HD_VID0_MEM_RCLI_CTRL_Y_TAG_MASK 0x0000001F
    #define DISP_HD_VID0_MEM_RCLI_CTRL_Y_TAG_SHIFT 0
    #define DISP_HD_VID0_MEM_RCLI_CTRL_CB_TAG_MASK 0x000003E0
    #define DISP_HD_VID0_MEM_RCLI_CTRL_CB_TAG_SHIFT 5
    #define DISP_HD_VID0_MEM_RCLI_CTRL_CR_TAG_MASK 0x00007C00
    #define DISP_HD_VID0_MEM_RCLI_CTRL_CR_TAG_SHIFT 10
    #define DISP_HD_VID0_MEM_RCLI_CTRL_MAX_REQ_SIZE_Y_MASK 0x00FF0000
    #define DISP_HD_VID0_MEM_RCLI_CTRL_MAX_REQ_SIZE_Y_SHIFT 16
    #define DISP_HD_VID0_MEM_RCLI_CTRL_MAX_REQ_SIZE_C_MASK 0xFF000000
    #define DISP_HD_VID0_MEM_RCLI_CTRL_MAX_REQ_SIZE_C_SHIFT 24
#define  DISP_HD_VID0_SAMPLES 0xD848
    #define DISP_HD_VID0_SAMPLES_WIDTH_MASK 0x00000FFF
    #define DISP_HD_VID0_SAMPLES_WIDTH_SHIFT 0
#define  DISP_HD_VID0_SCALED_SIZE 0xD86C
    #define DISP_HD_VID0_SCALED_SIZE_H_SCALED_SIZE_MASK 0x00000FFF
    #define DISP_HD_VID0_SCALED_SIZE_H_SCALED_SIZE_SHIFT 0
    #define DISP_HD_VID0_SCALED_SIZE_V_SCALED_SIZE_MASK 0x00FFF000
    #define DISP_HD_VID0_SCALED_SIZE_V_SCALED_SIZE_SHIFT 12
#define  DISP_HD_VID0_SIZE 0xD868
    #define DISP_HD_VID0_SIZE_H_SIZE_MASK 0x00000FFF
    #define DISP_HD_VID0_SIZE_H_SIZE_SHIFT 0
    #define DISP_HD_VID0_SIZE_V_SIZE_MASK 0x00FFF000
    #define DISP_HD_VID0_SIZE_V_SIZE_SHIFT 12
    #define DISP_HD_VID0_SIZE_H_SIZE16_MASK 0xFF000000
    #define DISP_HD_VID0_SIZE_H_SIZE16_SHIFT 24
#define  DISP_HD_VID0_VSCA_INIT0 0xD870
    #define DISP_HD_VID0_VSCA_INIT0_POSREG_INIT_Y00_MASK 0x000000FF
    #define DISP_HD_VID0_VSCA_INIT0_POSREG_INIT_Y00_SHIFT 0
    #define DISP_HD_VID0_VSCA_INIT0_POSREG_INIT_CBCR00_MASK 0x0000FF00
    #define DISP_HD_VID0_VSCA_INIT0_POSREG_INIT_CBCR00_SHIFT 8
    #define DISP_HD_VID0_VSCA_INIT0_POSREG_INIT_Y01_MASK 0x00FF0000
    #define DISP_HD_VID0_VSCA_INIT0_POSREG_INIT_Y01_SHIFT 16
    #define DISP_HD_VID0_VSCA_INIT0_POSREG_INIT_CBCR01_MASK 0xFF000000
    #define DISP_HD_VID0_VSCA_INIT0_POSREG_INIT_CBCR01_SHIFT 24
#define  DISP_HD_VID0_VSCA_INIT1 0xD874
    #define DISP_HD_VID0_VSCA_INIT1_POSREG_INIT_Y10_MASK 0x000000FF
    #define DISP_HD_VID0_VSCA_INIT1_POSREG_INIT_Y10_SHIFT 0
    #define DISP_HD_VID0_VSCA_INIT1_POSREG_INIT_CBCR10_MASK 0x0000FF00
    #define DISP_HD_VID0_VSCA_INIT1_POSREG_INIT_CBCR10_SHIFT 8
    #define DISP_HD_VID0_VSCA_INIT1_POSREG_INIT_Y11_MASK 0x00FF0000
    #define DISP_HD_VID0_VSCA_INIT1_POSREG_INIT_Y11_SHIFT 16
    #define DISP_HD_VID0_VSCA_INIT1_POSREG_INIT_CBCR11_MASK 0xFF000000
    #define DISP_HD_VID0_VSCA_INIT1_POSREG_INIT_CBCR11_SHIFT 24
#define  DISP_HD_VID0_VSCA_INV_RATIO 0xD864
    #define DISP_HD_VID0_VSCA_INV_RATIO_VSCA_INV_RATIO_MASK 0xFFFFFFFF
    #define DISP_HD_VID0_VSCA_INV_RATIO_VSCA_INV_RATIO_SHIFT 0
#define  DISP_HD_VID0_VSCA_START 0xD878
    #define DISP_HD_VID0_VSCA_START_START_POS00_MASK 0x0000000F
    #define DISP_HD_VID0_VSCA_START_START_POS00_SHIFT 0
    #define DISP_HD_VID0_VSCA_START_START_POS10_MASK 0x000000F0
    #define DISP_HD_VID0_VSCA_START_START_POS10_SHIFT 4
    #define DISP_HD_VID0_VSCA_START_START_CBCR_POS00_MASK 0x00000F00
    #define DISP_HD_VID0_VSCA_START_START_CBCR_POS00_SHIFT 8
    #define DISP_HD_VID0_VSCA_START_START_CBCR_POS10_MASK 0x0000F000
    #define DISP_HD_VID0_VSCA_START_START_CBCR_POS10_SHIFT 12
    #define DISP_HD_VID0_VSCA_START_START_POS01_MASK 0x000F0000
    #define DISP_HD_VID0_VSCA_START_START_POS01_SHIFT 16
    #define DISP_HD_VID0_VSCA_START_START_POS11_MASK 0x00F00000
    #define DISP_HD_VID0_VSCA_START_START_POS11_SHIFT 20
    #define DISP_HD_VID0_VSCA_START_START_CBCR_POS01_MASK 0x0F000000
    #define DISP_HD_VID0_VSCA_START_START_CBCR_POS01_SHIFT 24
    #define DISP_HD_VID0_VSCA_START_START_CBCR_POS11_MASK 0xF0000000
    #define DISP_HD_VID0_VSCA_START_START_CBCR_POS11_SHIFT 28
#define  DISP_HD_VID0_Y_ADR 0xD84C
    #define DISP_HD_VID0_Y_ADR_BASE_MASK 0xFFFFFFF0
    #define DISP_HD_VID0_Y_ADR_BASE_SHIFT 4
#define  DISP_HD_VID1_BUF_PITCH 0xD8B0
    #define DISP_HD_VID1_BUF_PITCH_Y_MASK 0x00001FF0
    #define DISP_HD_VID1_BUF_PITCH_Y_SHIFT 4
    #define DISP_HD_VID1_BUF_PITCH_C_MASK 0x1FF00000
    #define DISP_HD_VID1_BUF_PITCH_C_SHIFT 20
#define  DISP_HD_VID1_BUF_SIZE 0xD8B4
    #define DISP_HD_VID1_BUF_SIZE_Y_MASK 0x00007FFF
    #define DISP_HD_VID1_BUF_SIZE_Y_SHIFT 0
    #define DISP_HD_VID1_BUF_SIZE_C_MASK 0xFFFF0000
    #define DISP_HD_VID1_BUF_SIZE_C_SHIFT 16
#define  DISP_HD_VID1_CB_ADR 0xD8C0
    #define DISP_HD_VID1_CB_ADR_BASE_MASK 0xFFFFFFF0
    #define DISP_HD_VID1_CB_ADR_BASE_SHIFT 4
#define  DISP_HD_VID1_CR_ADR 0xD8C4
    #define DISP_HD_VID1_CR_ADR_BASE_MASK 0xFFFFFFF0
    #define DISP_HD_VID1_CR_ADR_BASE_SHIFT 4
#define  DISP_HD_VID1_FORMAT 0xD8A8
    #define DISP_HD_VID1_FORMAT_INPUT_10BIT_MASK 0x00000001
    #define DISP_HD_VID1_FORMAT_INPUT_10BIT_SHIFT 0
    #define DISP_HD_VID1_FORMAT_INPUT_422_MASK 0x00000002
    #define DISP_HD_VID1_FORMAT_INPUT_422_SHIFT 1
    #define DISP_HD_VID1_FORMAT_DITHER_MASK 0x0000000C
    #define DISP_HD_VID1_FORMAT_DITHER_SHIFT 2
    #define DISP_HD_VID1_FORMAT_BANK_ACTIVE_MASK 0x00000010
    #define DISP_HD_VID1_FORMAT_BANK_ACTIVE_SHIFT 4
    #define DISP_HD_VID1_FORMAT_DEINT_EN_MASK 0x00000300
    #define DISP_HD_VID1_FORMAT_DEINT_EN_SHIFT 8
    #define DISP_HD_VID1_FORMAT_DEINT_CBCR_MASK 0x00000400
    #define DISP_HD_VID1_FORMAT_DEINT_CBCR_SHIFT 10
    #define DISP_HD_VID1_FORMAT_VID_FORMAT_MASK 0x00010000
    #define DISP_HD_VID1_FORMAT_VID_FORMAT_SHIFT 16
    #define DISP_HD_VID1_FORMAT_CLK_GATE_ENABLE_MASK 0x00020000
    #define DISP_HD_VID1_FORMAT_CLK_GATE_ENABLE_SHIFT 17
    #define DISP_HD_VID1_FORMAT_MEM_RCLI_SAFE_OFF_MASK 0x00040000
    #define DISP_HD_VID1_FORMAT_MEM_RCLI_SAFE_OFF_SHIFT 18
    #define DISP_HD_VID1_FORMAT_UNDERFLOW_RESET_OFF_MASK 0x00080000
    #define DISP_HD_VID1_FORMAT_UNDERFLOW_RESET_OFF_SHIFT 19
    #define DISP_HD_VID1_FORMAT_URGENT_REQ_FLAG_MASK 0x0FF00000
    #define DISP_HD_VID1_FORMAT_URGENT_REQ_FLAG_SHIFT 20
    #define DISP_HD_VID1_FORMAT_MAX_LINE_REQ_MASK 0x70000000
    #define DISP_HD_VID1_FORMAT_MAX_LINE_REQ_SHIFT 28
    #define DISP_HD_VID1_FORMAT_PIPE_DISABLE_MASK 0x80000000
    #define DISP_HD_VID1_FORMAT_PIPE_DISABLE_SHIFT 31
#define  DISP_HD_VID1_HSBC0 0xD8C8
    #define DISP_HD_VID1_HSBC0_SCALE_Y_MASK 0x000000FF
    #define DISP_HD_VID1_HSBC0_SCALE_Y_SHIFT 0
    #define DISP_HD_VID1_HSBC0_BRIGHT_MASK 0x0003FF00
    #define DISP_HD_VID1_HSBC0_BRIGHT_SHIFT 8
    #define DISP_HD_VID1_HSBC0_CONTRAST_MASK 0xFF000000
    #define DISP_HD_VID1_HSBC0_CONTRAST_SHIFT 24
#define  DISP_HD_VID1_HSBC1 0xD8CC
    #define DISP_HD_VID1_HSBC1_HUE_COS_MASK 0x0000FFFF
    #define DISP_HD_VID1_HSBC1_HUE_COS_SHIFT 0
    #define DISP_HD_VID1_HSBC1_HUE_SIN_MASK 0xFFFF0000
    #define DISP_HD_VID1_HSBC1_HUE_SIN_SHIFT 16
#define  DISP_HD_VID1_HSBC2 0xD8D0
    #define DISP_HD_VID1_HSBC2_SCALE_CBCR_MASK 0x000000FF
    #define DISP_HD_VID1_HSBC2_SCALE_CBCR_SHIFT 0
    #define DISP_HD_VID1_HSBC2_SAT_MASK 0xFF000000
    #define DISP_HD_VID1_HSBC2_SAT_SHIFT 24
#define  DISP_HD_VID1_HSCA_INIT 0xD8F0
    #define DISP_HD_VID1_HSCA_INIT_POSREG_INIT_Y_MASK 0x0000FFFF
    #define DISP_HD_VID1_HSCA_INIT_POSREG_INIT_Y_SHIFT 0
    #define DISP_HD_VID1_HSCA_INIT_POSREG_INIT_CBCR_MASK 0xFFFF0000
    #define DISP_HD_VID1_HSCA_INIT_POSREG_INIT_CBCR_SHIFT 16
#define  DISP_HD_VID1_HSCA_INV_RATIO 0xD8EC
    #define DISP_HD_VID1_HSCA_INV_RATIO_HSCA_INV_RATIO_MASK 0xFFFFFFFF
    #define DISP_HD_VID1_HSCA_INV_RATIO_HSCA_INV_RATIO_SHIFT 0
#define  DISP_HD_VID1_HSCA_START 0xD8F4
    #define DISP_HD_VID1_HSCA_START_START_POS_MASK 0x0000003F
    #define DISP_HD_VID1_HSCA_START_START_POS_SHIFT 0
    #define DISP_HD_VID1_HSCA_START_START_CBCR_POS_MASK 0x00003F00
    #define DISP_HD_VID1_HSCA_START_START_CBCR_POS_SHIFT 8
#define  DISP_HD_VID1_INPUT_CBCR_LIMIT 0xD8FC
    #define DISP_HD_VID1_INPUT_CBCR_LIMIT_CBCR_LIMIT_PLUS_MASK 0x000000FF
    #define DISP_HD_VID1_INPUT_CBCR_LIMIT_CBCR_LIMIT_PLUS_SHIFT 0
    #define DISP_HD_VID1_INPUT_CBCR_LIMIT_CBCR_LIMIT_MINUS_MASK 0x0000FF00
    #define DISP_HD_VID1_INPUT_CBCR_LIMIT_CBCR_LIMIT_MINUS_SHIFT 8
#define  DISP_HD_VID1_INPUT_Y_LIMIT 0xD8F8
    #define DISP_HD_VID1_INPUT_Y_LIMIT_Y_LIMIT_PLUS_MASK 0x000000FF
    #define DISP_HD_VID1_INPUT_Y_LIMIT_Y_LIMIT_PLUS_SHIFT 0
    #define DISP_HD_VID1_INPUT_Y_LIMIT_Y_LIMIT_MINUS_MASK 0x0000FF00
    #define DISP_HD_VID1_INPUT_Y_LIMIT_Y_LIMIT_MINUS_SHIFT 8
    #define DISP_HD_VID1_INPUT_Y_LIMIT_Y_ZERO_MASK 0x00FF0000
    #define DISP_HD_VID1_INPUT_Y_LIMIT_Y_ZERO_SHIFT 16
    #define DISP_HD_VID1_INPUT_Y_LIMIT_Y_CENTER_MASK 0xFF000000
    #define DISP_HD_VID1_INPUT_Y_LIMIT_Y_CENTER_SHIFT 24
#define  DISP_HD_VID1_MEM_RCLI_CTRL 0xD8AC
    #define DISP_HD_VID1_MEM_RCLI_CTRL_Y_TAG_MASK 0x0000001F
    #define DISP_HD_VID1_MEM_RCLI_CTRL_Y_TAG_SHIFT 0
    #define DISP_HD_VID1_MEM_RCLI_CTRL_CB_TAG_MASK 0x000003E0
    #define DISP_HD_VID1_MEM_RCLI_CTRL_CB_TAG_SHIFT 5
    #define DISP_HD_VID1_MEM_RCLI_CTRL_CR_TAG_MASK 0x00007C00
    #define DISP_HD_VID1_MEM_RCLI_CTRL_CR_TAG_SHIFT 10
    #define DISP_HD_VID1_MEM_RCLI_CTRL_MAX_REQ_SIZE_Y_MASK 0x00FF0000
    #define DISP_HD_VID1_MEM_RCLI_CTRL_MAX_REQ_SIZE_Y_SHIFT 16
    #define DISP_HD_VID1_MEM_RCLI_CTRL_MAX_REQ_SIZE_C_MASK 0xFF000000
    #define DISP_HD_VID1_MEM_RCLI_CTRL_MAX_REQ_SIZE_C_SHIFT 24
#define  DISP_HD_VID1_SAMPLES 0xD8B8
    #define DISP_HD_VID1_SAMPLES_WIDTH_MASK 0x00000FFF
    #define DISP_HD_VID1_SAMPLES_WIDTH_SHIFT 0
#define  DISP_HD_VID1_SCALED_SIZE 0xD8DC
    #define DISP_HD_VID1_SCALED_SIZE_H_SCALED_SIZE_MASK 0x00000FFF
    #define DISP_HD_VID1_SCALED_SIZE_H_SCALED_SIZE_SHIFT 0
    #define DISP_HD_VID1_SCALED_SIZE_V_SCALED_SIZE_MASK 0x00FFF000
    #define DISP_HD_VID1_SCALED_SIZE_V_SCALED_SIZE_SHIFT 12
#define  DISP_HD_VID1_SIZE 0xD8D8
    #define DISP_HD_VID1_SIZE_H_SIZE_MASK 0x00000FFF
    #define DISP_HD_VID1_SIZE_H_SIZE_SHIFT 0
    #define DISP_HD_VID1_SIZE_V_SIZE_MASK 0x00FFF000
    #define DISP_HD_VID1_SIZE_V_SIZE_SHIFT 12
    #define DISP_HD_VID1_SIZE_H_SIZE16_MASK 0xFF000000
    #define DISP_HD_VID1_SIZE_H_SIZE16_SHIFT 24
#define  DISP_HD_VID1_VSCA_INIT0 0xD8E0
    #define DISP_HD_VID1_VSCA_INIT0_POSREG_INIT_Y00_MASK 0x000000FF
    #define DISP_HD_VID1_VSCA_INIT0_POSREG_INIT_Y00_SHIFT 0
    #define DISP_HD_VID1_VSCA_INIT0_POSREG_INIT_CBCR00_MASK 0x0000FF00
    #define DISP_HD_VID1_VSCA_INIT0_POSREG_INIT_CBCR00_SHIFT 8
    #define DISP_HD_VID1_VSCA_INIT0_POSREG_INIT_Y01_MASK 0x00FF0000
    #define DISP_HD_VID1_VSCA_INIT0_POSREG_INIT_Y01_SHIFT 16
    #define DISP_HD_VID1_VSCA_INIT0_POSREG_INIT_CBCR01_MASK 0xFF000000
    #define DISP_HD_VID1_VSCA_INIT0_POSREG_INIT_CBCR01_SHIFT 24
#define  DISP_HD_VID1_VSCA_INIT1 0xD8E4
    #define DISP_HD_VID1_VSCA_INIT1_POSREG_INIT_Y10_MASK 0x000000FF
    #define DISP_HD_VID1_VSCA_INIT1_POSREG_INIT_Y10_SHIFT 0
    #define DISP_HD_VID1_VSCA_INIT1_POSREG_INIT_CBCR10_MASK 0x0000FF00
    #define DISP_HD_VID1_VSCA_INIT1_POSREG_INIT_CBCR10_SHIFT 8
    #define DISP_HD_VID1_VSCA_INIT1_POSREG_INIT_Y11_MASK 0x00FF0000
    #define DISP_HD_VID1_VSCA_INIT1_POSREG_INIT_Y11_SHIFT 16
    #define DISP_HD_VID1_VSCA_INIT1_POSREG_INIT_CBCR11_MASK 0xFF000000
    #define DISP_HD_VID1_VSCA_INIT1_POSREG_INIT_CBCR11_SHIFT 24
#define  DISP_HD_VID1_VSCA_INV_RATIO 0xD8D4
    #define DISP_HD_VID1_VSCA_INV_RATIO_VSCA_INV_RATIO_MASK 0xFFFFFFFF
    #define DISP_HD_VID1_VSCA_INV_RATIO_VSCA_INV_RATIO_SHIFT 0
#define  DISP_HD_VID1_VSCA_START 0xD8E8
    #define DISP_HD_VID1_VSCA_START_START_POS00_MASK 0x0000000F
    #define DISP_HD_VID1_VSCA_START_START_POS00_SHIFT 0
    #define DISP_HD_VID1_VSCA_START_START_POS10_MASK 0x000000F0
    #define DISP_HD_VID1_VSCA_START_START_POS10_SHIFT 4
    #define DISP_HD_VID1_VSCA_START_START_CBCR_POS00_MASK 0x00000F00
    #define DISP_HD_VID1_VSCA_START_START_CBCR_POS00_SHIFT 8
    #define DISP_HD_VID1_VSCA_START_START_CBCR_POS10_MASK 0x0000F000
    #define DISP_HD_VID1_VSCA_START_START_CBCR_POS10_SHIFT 12
    #define DISP_HD_VID1_VSCA_START_START_POS01_MASK 0x000F0000
    #define DISP_HD_VID1_VSCA_START_START_POS01_SHIFT 16
    #define DISP_HD_VID1_VSCA_START_START_POS11_MASK 0x00F00000
    #define DISP_HD_VID1_VSCA_START_START_POS11_SHIFT 20
    #define DISP_HD_VID1_VSCA_START_START_CBCR_POS01_MASK 0x0F000000
    #define DISP_HD_VID1_VSCA_START_START_CBCR_POS01_SHIFT 24
    #define DISP_HD_VID1_VSCA_START_START_CBCR_POS11_MASK 0xF0000000
    #define DISP_HD_VID1_VSCA_START_START_CBCR_POS11_SHIFT 28
#define  DISP_HD_VID1_Y_ADR 0xD8BC
    #define DISP_HD_VID1_Y_ADR_BASE_MASK 0xFFFFFFF0
    #define DISP_HD_VID1_Y_ADR_BASE_SHIFT 4
#define  DISP_INT_MASK 0xDB08
    #define HD_CMD_FIFO_EMPTY_INT_MASK_MASK 0x00000001
    #define HD_CMD_FIFO_EMPTY_INT_MASK_SHIFT 0
    #define HD_LINE_A_INT_MASK_MASK 0x00000002
    #define HD_LINE_A_INT_MASK_SHIFT 1
    #define HD_LINE_B_INT_MASK_MASK 0x00000004
    #define HD_LINE_B_INT_MASK_SHIFT 2
    #define HD_EOFIELD_INT_MASK_MASK 0x00000008
    #define HD_EOFIELD_INT_MASK_SHIFT 3
    #define HD_EOFRAME_INT_MASK_MASK 0x00000010
    #define HD_EOFRAME_INT_MASK_SHIFT 4
    #define SD_CMD_FIFO_EMPTY_INT_MASK_MASK 0x00000100
    #define SD_CMD_FIFO_EMPTY_INT_MASK_SHIFT 8
    #define SD_LINE_A_INT_MASK_MASK 0x00000200
    #define SD_LINE_A_INT_MASK_SHIFT 9
    #define SD_LINE_B_INT_MASK_MASK 0x00000400
    #define SD_LINE_B_INT_MASK_SHIFT 10
    #define SD_EOFIELD_INT_MASK_MASK 0x00000800
    #define SD_EOFIELD_INT_MASK_SHIFT 11
    #define SD_EOFRAME_INT_MASK_MASK 0x00001000
    #define SD_EOFRAME_INT_MASK_SHIFT 12
    #define HDMI_INT_MASK_MASK 0x08000000
    #define HDMI_INT_MASK_SHIFT 27
    #define GLOBAL_UNDERFLOW_INT_MASK_MASK 0x10000000
    #define GLOBAL_UNDERFLOW_INT_MASK_SHIFT 28
    #define GLOBAL_OVERFLOW_INT_MASK_MASK 0x20000000
    #define GLOBAL_OVERFLOW_INT_MASK_SHIFT 29
#define  DISP_INT_STATUS 0xDB04
    #define HD_CMD_FIFO_EMPTY_INT_MASK 0x00000001
    #define HD_CMD_FIFO_EMPTY_INT_SHIFT 0
    #define HD_LINE_A_INT_MASK 0x00000002
    #define HD_LINE_A_INT_SHIFT 1
    #define HD_LINE_B_INT_MASK 0x00000004
    #define HD_LINE_B_INT_SHIFT 2
    #define HD_EOFIELD_INT_MASK 0x00000008
    #define HD_EOFIELD_INT_SHIFT 3
    #define HD_EOFRAME_INT_MASK 0x00000010
    #define HD_EOFRAME_INT_SHIFT 4
    #define SD_CMD_FIFO_EMPTY_INT_MASK 0x00000100
    #define SD_CMD_FIFO_EMPTY_INT_SHIFT 8
    #define SD_LINE_A_INT_MASK 0x00000200
    #define SD_LINE_A_INT_SHIFT 9
    #define SD_LINE_B_INT_MASK 0x00000400
    #define SD_LINE_B_INT_SHIFT 10
    #define SD_EOFIELD_INT_MASK 0x00000800
    #define SD_EOFIELD_INT_SHIFT 11
    #define SD_EOFRAME_INT_MASK 0x00001000
    #define SD_EOFRAME_INT_SHIFT 12
    #define HDMI_INT_MASK 0x08000000
    #define HDMI_INT_SHIFT 27
    #define GLOBAL_UNDERFLOW_INT_MASK 0x10000000
    #define GLOBAL_UNDERFLOW_INT_SHIFT 28
    #define GLOBAL_OVERFLOW_INT_MASK 0x20000000
    #define GLOBAL_OVERFLOW_INT_SHIFT 29
#define  DISP_OUTPUT_MUX 0xDAD8
    #define OVS_RATIOGRP1_MASK 0x00000003
    #define OVS_RATIOGRP1_SHIFT 0
    #define OVS_RATIOGRP2_MASK 0x0000000C
    #define OVS_RATIOGRP2_SHIFT 2
    #define SEL_VENC1_CMPNT_MASK 0x00000010
    #define SEL_VENC1_CMPNT_SHIFT 4
    #define SEL_VENC2_CMPNT_MASK 0x00000020
    #define SEL_VENC2_CMPNT_SHIFT 5
    #define SEL_RGB_VENC1_MASK 0x00000100
    #define SEL_RGB_VENC1_SHIFT 8
    #define SEL_RGB_VENC2_MASK 0x00000200
    #define SEL_RGB_VENC2_SHIFT 9
    #define SWIZZLE_DAC0_MASK 0x00000400
    #define SWIZZLE_DAC0_SHIFT 10
    #define SWIZZLE_DAC1_MASK 0x00000800
    #define SWIZZLE_DAC1_SHIFT 11
    #define SWIZZLE_DAC2_MASK 0x00001000
    #define SWIZZLE_DAC2_SHIFT 12
    #define SWIZZLE_DAC3_MASK 0x00002000
    #define SWIZZLE_DAC3_SHIFT 13
    #define SWIZZLE_DAC4_MASK 0x00004000
    #define SWIZZLE_DAC4_SHIFT 14
    #define SWIZZLE_DAC5_MASK 0x00008000
    #define SWIZZLE_DAC5_SHIFT 15
    #define DAC_TEST_MASK 0x00010000
    #define DAC_TEST_SHIFT 16
    #define DAC_TEST_DUAL_TONE_MASK 0x00020000
    #define DAC_TEST_DUAL_TONE_SHIFT 17
    #define DAC_TONE_EN0_MASK 0x00040000
    #define DAC_TONE_EN0_SHIFT 18
    #define DAC_TONE_EN1_MASK 0x00080000
    #define DAC_TONE_EN1_SHIFT 19
    #define DAC_TONE_EN2_MASK 0x00100000
    #define DAC_TONE_EN2_SHIFT 20
    #define DAC_TONE_EN3_MASK 0x00200000
    #define DAC_TONE_EN3_SHIFT 21
    #define DAC_TONE_EN4_MASK 0x00400000
    #define DAC_TONE_EN4_SHIFT 22
    #define DAC_TONE_EN5_MASK 0x00800000
    #define DAC_TONE_EN5_SHIFT 23
    #define DAC_TONE_FREQ_MASK 0x0F000000
    #define DAC_TONE_FREQ_SHIFT 24
    #define DAC_TONE_AMPL_MASK 0x30000000
    #define DAC_TONE_AMPL_SHIFT 28
    #define O656_SD_MASK 0x80000000
    #define O656_SD_SHIFT 31
#define  DISP_OUTPUT_TEST_OFF 0xDADC
    #define DAC_TEST_OFFSET_MASK 0x000003FF
    #define DAC_TEST_OFFSET_SHIFT 0
#define  DISP_SD_CC 0xDC60
    #define DISP_SD_CC_GRA0_MODE_MASK 0x0000000F
    #define DISP_SD_CC_GRA0_MODE_SHIFT 0
#define  DISP_SD_CMD0_FIFO 0xDC00
    #define SD_VBI0_BOT_IDX_MASK 0x0000003F
    #define SD_VBI0_BOT_IDX_SHIFT 0
    #define SD_VBI0_TOP_IDX_MASK 0x00000FC0
    #define SD_VBI0_TOP_IDX_SHIFT 6
    #define SD_VBI0_FLD_SEL_MASK 0x00003000
    #define SD_VBI0_FLD_SEL_SHIFT 12
    #define DISP_SD_CMD0_FIFO_CMD0_FIFO_WE_MASK 0x40000000
    #define DISP_SD_CMD0_FIFO_CMD0_FIFO_WE_SHIFT 30
    #define DISP_SD_CMD0_FIFO_SD_UPDATE_CMD_MASK 0x80000000
    #define DISP_SD_CMD0_FIFO_SD_UPDATE_CMD_SHIFT 31
#define  DISP_SD_CMD1_FIFO 0xDC04
    #define SD_ANC0_BOT_IDX_MASK 0x0000003F
    #define SD_ANC0_BOT_IDX_SHIFT 0
    #define SD_ANC0_TOP_IDX_MASK 0x00000FC0
    #define SD_ANC0_TOP_IDX_SHIFT 6
    #define SD_ANC0_FLD_SEL_MASK 0x00003000
    #define SD_ANC0_FLD_SEL_SHIFT 12
    #define SD_GRA0_IDX_MASK 0x000FC000
    #define SD_GRA0_IDX_SHIFT 14
    #define DISP_SD_CMD1_FIFO_CMD1_FIFO_WE_MASK 0x40000000
    #define DISP_SD_CMD1_FIFO_CMD1_FIFO_WE_SHIFT 30
    #define DISP_SD_CMD1_FIFO_SD_UPDATE_CMD_MASK 0x80000000
    #define DISP_SD_CMD1_FIFO_SD_UPDATE_CMD_SHIFT 31
#define  DISP_SD_COMP_ALPHA_MODE 0xDC64
    #define DISP_SD_COMP_ALPHA_MODE_PREMULT_DISABLE_G0_MASK 0x00000004
    #define DISP_SD_COMP_ALPHA_MODE_PREMULT_DISABLE_G0_SHIFT 2
    #define DISP_SD_COMP_ALPHA_MODE_BACKGROUND_Y_MASK 0x0000FF00
    #define DISP_SD_COMP_ALPHA_MODE_BACKGROUND_Y_SHIFT 8
    #define DISP_SD_COMP_ALPHA_MODE_BACKGROUND_CB_MASK 0x00FF0000
    #define DISP_SD_COMP_ALPHA_MODE_BACKGROUND_CB_SHIFT 16
    #define DISP_SD_COMP_ALPHA_MODE_BACKGROUND_CR_MASK 0xFF000000
    #define DISP_SD_COMP_ALPHA_MODE_BACKGROUND_CR_SHIFT 24
#define  DISP_SD_COMP_CTRL 0xDC58
    #define DISP_SD_COMP_CTRL_GAMMA_EN_MASK 0x00010000
    #define DISP_SD_COMP_CTRL_GAMMA_EN_SHIFT 16
    #define DISP_SD_COMP_CTRL_DISABLE_SHADOW_MASK 0x00020000
    #define DISP_SD_COMP_CTRL_DISABLE_SHADOW_SHIFT 17
    #define DISP_SD_COMP_CTRL_DAC_ACTIVE_MASK 0x10000000
    #define DISP_SD_COMP_CTRL_DAC_ACTIVE_SHIFT 28
    #define DISP_SD_COMP_CTRL_COMP_MODE_MASK 0x60000000
    #define DISP_SD_COMP_CTRL_COMP_MODE_SHIFT 29
    #define DISP_SD_COMP_CTRL_COMP_EN_MASK 0x80000000
    #define DISP_SD_COMP_CTRL_COMP_EN_SHIFT 31
#define  DISP_SD_COMP_GLOBAL_SIZE 0xDC6C
    #define DISP_SD_COMP_GLOBAL_SIZE_SIZE_X_MASK 0x00000FFF
    #define DISP_SD_COMP_GLOBAL_SIZE_SIZE_X_SHIFT 0
    #define DISP_SD_COMP_GLOBAL_SIZE_SIZE_Y_MASK 0x00FFF000
    #define DISP_SD_COMP_GLOBAL_SIZE_SIZE_Y_SHIFT 12
#define  DISP_SD_COMP_GRA0_POS 0xDC68
    #define DISP_SD_COMP_GRA0_POS_POS_X_MASK 0x00000FFF
    #define DISP_SD_COMP_GRA0_POS_POS_X_SHIFT 0
    #define DISP_SD_COMP_GRA0_POS_POS_Y_MASK 0x00FFF000
    #define DISP_SD_COMP_GRA0_POS_POS_Y_SHIFT 12
#define  DISP_SD_COMP_SIZE 0xDC5C
    #define DISP_SD_COMP_SIZE_SIZE_X_MASK 0x00000FFF
    #define DISP_SD_COMP_SIZE_SIZE_X_SHIFT 0
    #define DISP_SD_COMP_SIZE_SIZE_Y_MASK 0x00FFF000
    #define DISP_SD_COMP_SIZE_SIZE_Y_SHIFT 12
    #define DISP_SD_COMP_SIZE_OSR_MASK 0x01000000
    #define DISP_SD_COMP_SIZE_OSR_SHIFT 24
    #define DISP_SD_COMP_SIZE_INTERLACED_MASK 0x80000000
    #define DISP_SD_COMP_SIZE_INTERLACED_SHIFT 31
#define  DISP_SD_COMP_START_FLD_POS 0xDC74
    #define DISP_SD_COMP_START_FLD_POS_FLD1_POS_Y_MASK 0x00000FFF
    #define DISP_SD_COMP_START_FLD_POS_FLD1_POS_Y_SHIFT 0
    #define DISP_SD_COMP_START_FLD_POS_FLD2_POS_Y_MASK 0x00FFF000
    #define DISP_SD_COMP_START_FLD_POS_FLD2_POS_Y_SHIFT 12
#define  DISP_SD_COMP_START_HANC_POS 0xDC78
    #define DISP_SD_COMP_START_HANC_POS_FLD1_POS_Y_MASK 0x00000FFF
    #define DISP_SD_COMP_START_HANC_POS_FLD1_POS_Y_SHIFT 0
    #define DISP_SD_COMP_START_HANC_POS_FLD2_POS_Y_MASK 0x00FFF000
    #define DISP_SD_COMP_START_HANC_POS_FLD2_POS_Y_SHIFT 12
#define  DISP_SD_COMP_START_PIX_POS 0xDC70
    #define DISP_SD_COMP_START_PIX_POS_POS_X_MASK 0x00000FFF
    #define DISP_SD_COMP_START_PIX_POS_POS_X_SHIFT 0
#define  DISP_SD_COMP_START_VBI_POS 0xDC80
    #define DISP_SD_COMP_START_VBI_POS_FLD1_POS_Y_MASK 0x00000FFF
    #define DISP_SD_COMP_START_VBI_POS_FLD1_POS_Y_SHIFT 0
    #define DISP_SD_COMP_START_VBI_POS_FLD2_POS_Y_MASK 0x00FFF000
    #define DISP_SD_COMP_START_VBI_POS_FLD2_POS_Y_SHIFT 12
#define  DISP_SD_COMP_STOP_HANC_POS 0xDC7C
    #define DISP_SD_COMP_STOP_HANC_POS_FLD1_POS_Y_MASK 0x00000FFF
    #define DISP_SD_COMP_STOP_HANC_POS_FLD1_POS_Y_SHIFT 0
    #define DISP_SD_COMP_STOP_HANC_POS_FLD2_POS_Y_MASK 0x00FFF000
    #define DISP_SD_COMP_STOP_HANC_POS_FLD2_POS_Y_SHIFT 12
#define  DISP_SD_COMP_STOP_VBI_POS 0xDC84
    #define DISP_SD_COMP_STOP_VBI_POS_FLD1_POS_Y_MASK 0x00000FFF
    #define DISP_SD_COMP_STOP_VBI_POS_FLD1_POS_Y_SHIFT 0
    #define DISP_SD_COMP_STOP_VBI_POS_FLD2_POS_Y_MASK 0x00FFF000
    #define DISP_SD_COMP_STOP_VBI_POS_FLD2_POS_Y_SHIFT 12
#define  DISP_SD_CURR_CMD0 0xDC08
    #define SD_VBI0_BOT_IDX_CURR_MASK 0x0000003F
    #define SD_VBI0_BOT_IDX_CURR_SHIFT 0
    #define SD_VBI0_TOP_IDX_CURR_MASK 0x00000FC0
    #define SD_VBI0_TOP_IDX_CURR_SHIFT 6
    #define SD_VBI0_FLD_SEL_CURR_MASK 0x00003000
    #define SD_VBI0_FLD_SEL_CURR_SHIFT 12
    #define SD_UPDATE_CMD_CURR_MASK 0x80000000
    #define SD_UPDATE_CMD_CURR_SHIFT 31
#define  DISP_SD_CURR_CMD1 0xDC0C
    #define SD_ANC0_BOT_IDX_CURR_MASK 0x0000003F
    #define SD_ANC0_BOT_IDX_CURR_SHIFT 0
    #define SD_ANC0_TOP_IDX_CURR_MASK 0x00000FC0
    #define SD_ANC0_TOP_IDX_CURR_SHIFT 6
    #define SD_ANC0_FLD_SEL_CURR_MASK 0x00003000
    #define SD_ANC0_FLD_SEL_CURR_SHIFT 12
    #define SD_GRA0_IDX_CURR_MASK 0x000FC000
    #define SD_GRA0_IDX_CURR_SHIFT 14
#define  DISP_SD_FIFO_STATUS 0xDC10
    #define DISP_SD_FIFO_STATUS_FREE_ENTRIES_MASK 0x0000001F
    #define DISP_SD_FIFO_STATUS_FREE_ENTRIES_SHIFT 0
    #define DISP_SD_FIFO_STATUS_CURR_IDX_MASK 0x00000F00
    #define DISP_SD_FIFO_STATUS_CURR_IDX_SHIFT 8
    #define DISP_SD_FIFO_STATUS_FRM_CNT_MASK 0x000FF000
    #define DISP_SD_FIFO_STATUS_FRM_CNT_SHIFT 12
#define  DISP_SD_GENLOCK_DEN 0xDD7C
    #define DISP_SD_GENLOCK_DEN_DEN_MASK 0xFFFFFFFF
    #define DISP_SD_GENLOCK_DEN_DEN_SHIFT 0
#define  DISP_SD_GENLOCK_LOWER 0xDD74
    #define DISP_SD_GENLOCK_LOWER_L_MASK 0xFFFFFFFF
    #define DISP_SD_GENLOCK_LOWER_L_SHIFT 0
#define  DISP_SD_GENLOCK_NUM 0xDD78
    #define DISP_SD_GENLOCK_NUM_NUM_MASK 0xFFFFFFFF
    #define DISP_SD_GENLOCK_NUM_NUM_SHIFT 0
#define  DISP_SD_GENLOCK_PCR 0xDD64
    #define DISP_SD_GENLOCK_PCR_NUM_MASK 0x0000FFFF
    #define DISP_SD_GENLOCK_PCR_NUM_SHIFT 0
    #define DISP_SD_GENLOCK_PCR_DEN_MASK 0xFFFF0000
    #define DISP_SD_GENLOCK_PCR_DEN_SHIFT 16
#define  DISP_SD_GENLOCK_PCR_LOWER 0xDD6C
    #define DISP_SD_GENLOCK_PCR_LOWER_L_MASK 0xFFFFFFFF
    #define DISP_SD_GENLOCK_PCR_LOWER_L_SHIFT 0
#define  DISP_SD_GENLOCK_PCR_UPPER 0xDD68
    #define DISP_SD_GENLOCK_PCR_UPPER_U_MASK 0x000003FF
    #define DISP_SD_GENLOCK_PCR_UPPER_U_SHIFT 0
#define  DISP_SD_GENLOCK_UPPER 0xDD70
    #define DISP_SD_GENLOCK_UPPER_U_MASK 0x000003FF
    #define DISP_SD_GENLOCK_UPPER_U_SHIFT 0
#define  DISP_SD_GRA0_ADR 0xDC1C
    #define DISP_SD_GRA0_ADR_BASE_MASK 0xFFFFFFF0
    #define DISP_SD_GRA0_ADR_BASE_SHIFT 4
#define  DISP_SD_GRA0_BUF 0xDC20
    #define DISP_SD_GRA0_BUF_PITCH_MASK 0x0000FFF0
    #define DISP_SD_GRA0_BUF_PITCH_SHIFT 4
    #define DISP_SD_GRA0_BUF_SIZE_MASK 0xFFFF0000
    #define DISP_SD_GRA0_BUF_SIZE_SHIFT 16
#define  DISP_SD_GRA0_FORMAT 0xDC24
    #define DISP_SD_GRA0_FORMAT_MEM_FORMAT_MASK 0x0000000F
    #define DISP_SD_GRA0_FORMAT_MEM_FORMAT_SHIFT 0
    #define DISP_SD_GRA0_FORMAT_TRANS_MASK 0x00000080
    #define DISP_SD_GRA0_FORMAT_TRANS_SHIFT 7
    #define DISP_SD_GRA0_FORMAT_DITHER_MASK 0x00000300
    #define DISP_SD_GRA0_FORMAT_DITHER_SHIFT 8
    #define DISP_SD_GRA0_FORMAT_TAG_MASK 0x0001F000
    #define DISP_SD_GRA0_FORMAT_TAG_SHIFT 12
    #define DISP_SD_GRA0_FORMAT_CLK_GATE_ENABLE_MASK 0x00020000
    #define DISP_SD_GRA0_FORMAT_CLK_GATE_ENABLE_SHIFT 17
    #define DISP_SD_GRA0_FORMAT_MEM_RCLI_SAFE_OFF_MASK 0x00040000
    #define DISP_SD_GRA0_FORMAT_MEM_RCLI_SAFE_OFF_SHIFT 18
    #define DISP_SD_GRA0_FORMAT_UNDERFLOW_RESET_OFF_MASK 0x00080000
    #define DISP_SD_GRA0_FORMAT_UNDERFLOW_RESET_OFF_SHIFT 19
    #define DISP_SD_GRA0_FORMAT_MAX_REQ_SIZE_MASK 0x0FF00000
    #define DISP_SD_GRA0_FORMAT_MAX_REQ_SIZE_SHIFT 20
    #define DISP_SD_GRA0_FORMAT_PIPE_DISABLE_MASK 0x80000000
    #define DISP_SD_GRA0_FORMAT_PIPE_DISABLE_SHIFT 31
#define  DISP_SD_GRA0_FORMAT1 0xDC28
    #define DISP_SD_GRA0_FORMAT1_PEL_POSITION_A_MASK 0x00000003
    #define DISP_SD_GRA0_FORMAT1_PEL_POSITION_A_SHIFT 0
    #define DISP_SD_GRA0_FORMAT1_PEL_POSITION_R_MASK 0x0000000C
    #define DISP_SD_GRA0_FORMAT1_PEL_POSITION_R_SHIFT 2
    #define DISP_SD_GRA0_FORMAT1_PEL_POSITION_G_MASK 0x00000030
    #define DISP_SD_GRA0_FORMAT1_PEL_POSITION_G_SHIFT 4
    #define DISP_SD_GRA0_FORMAT1_PEL_POSITION_B_MASK 0x000000C0
    #define DISP_SD_GRA0_FORMAT1_PEL_POSITION_B_SHIFT 6
    #define DISP_SD_GRA0_FORMAT1_CLUT_OFFSET_MASK 0x0000FF00
    #define DISP_SD_GRA0_FORMAT1_CLUT_OFFSET_SHIFT 8
    #define DISP_SD_GRA0_FORMAT1_URGENT_REQ_FLAG_MASK 0xFFF00000
    #define DISP_SD_GRA0_FORMAT1_URGENT_REQ_FLAG_SHIFT 20
#define  DISP_SD_GRA0_HSCA_INV_RATIO 0xDC34
    #define DISP_SD_GRA0_HSCA_INV_RATIO_HSCA_INV_RATIO_MASK 0xFFFFFFFF
    #define DISP_SD_GRA0_HSCA_INV_RATIO_HSCA_INV_RATIO_SHIFT 0
#define  DISP_SD_GRA0_SAMPLES 0xDC2C
    #define DISP_SD_GRA0_SAMPLES_WIDTH_MASK 0x0000FFFF
    #define DISP_SD_GRA0_SAMPLES_WIDTH_SHIFT 0
#define  DISP_SD_GRA0_SCALED_SIZE 0xDC30
    #define DISP_SD_GRA0_SCALED_SIZE_H_SCALED_SIZE_MASK 0x00000FFF
    #define DISP_SD_GRA0_SCALED_SIZE_H_SCALED_SIZE_SHIFT 0
    #define DISP_SD_GRA0_SCALED_SIZE_V_SCALED_SIZE_MASK 0x00FFF000
    #define DISP_SD_GRA0_SCALED_SIZE_V_SCALED_SIZE_SHIFT 12
#define  DISP_SD_GRA0_SIZE 0xDC18
    #define DISP_SD_GRA0_SIZE_H_SIZE_MASK 0x00000FFF
    #define DISP_SD_GRA0_SIZE_H_SIZE_SHIFT 0
    #define DISP_SD_GRA0_SIZE_V_SIZE_MASK 0x00FFF000
    #define DISP_SD_GRA0_SIZE_V_SIZE_SHIFT 12
#define  DISP_SD_HANC0_ADR 0xDC48
    #define DISP_SD_HANC0_ADR_BASE_MASK 0xFFFFFFF0
    #define DISP_SD_HANC0_ADR_BASE_SHIFT 4
#define  DISP_SD_HANC0_BUF 0xDC4C
    #define DISP_SD_HANC0_BUF_PITCH_MASK 0x0000FFF0
    #define DISP_SD_HANC0_BUF_PITCH_SHIFT 4
    #define DISP_SD_HANC0_BUF_SIZE_MASK 0xFFFF0000
    #define DISP_SD_HANC0_BUF_SIZE_SHIFT 16
#define  DISP_SD_HANC0_SAMPLES 0xDC54
    #define DISP_SD_HANC0_SAMPLES_WIDTH_MASK 0x0000FFFF
    #define DISP_SD_HANC0_SAMPLES_WIDTH_SHIFT 0
#define  DISP_SD_LINE_INTERRUPT 0xDCA0
    #define DISP_SD_LINE_INTERRUPT_A_MASK 0x00000FFF
    #define DISP_SD_LINE_INTERRUPT_A_SHIFT 0
    #define DISP_SD_LINE_INTERRUPT_B_MASK 0x0FFF0000
    #define DISP_SD_LINE_INTERRUPT_B_SHIFT 16
#define  DISP_SD_OCC_C11 0xDC88
    #define DISP_SD_OCC_C11_C11_MASK 0x0000FFFF
    #define DISP_SD_OCC_C11_C11_SHIFT 0
    #define DISP_SD_OCC_C11_C12_MASK 0xFFFF0000
    #define DISP_SD_OCC_C11_C12_SHIFT 16
#define  DISP_SD_OCC_C13 0xDC8C
    #define DISP_SD_OCC_C13_C13_MASK 0x0000FFFF
    #define DISP_SD_OCC_C13_C13_SHIFT 0
    #define DISP_SD_OCC_C13_K1_MASK 0xFFFF0000
    #define DISP_SD_OCC_C13_K1_SHIFT 16
#define  DISP_SD_OCC_C21 0xDC90
    #define DISP_SD_OCC_C21_C21_MASK 0x0000FFFF
    #define DISP_SD_OCC_C21_C21_SHIFT 0
    #define DISP_SD_OCC_C21_C22_MASK 0xFFFF0000
    #define DISP_SD_OCC_C21_C22_SHIFT 16
#define  DISP_SD_OCC_C23 0xDC94
    #define DISP_SD_OCC_C23_C23_MASK 0x0000FFFF
    #define DISP_SD_OCC_C23_C23_SHIFT 0
    #define DISP_SD_OCC_C23_K2_MASK 0xFFFF0000
    #define DISP_SD_OCC_C23_K2_SHIFT 16
#define  DISP_SD_OCC_C31 0xDC98
    #define DISP_SD_OCC_C31_C31_MASK 0x0000FFFF
    #define DISP_SD_OCC_C31_C31_SHIFT 0
    #define DISP_SD_OCC_C31_C32_MASK 0xFFFF0000
    #define DISP_SD_OCC_C31_C32_SHIFT 16
#define  DISP_SD_OCC_C33 0xDC9C
    #define DISP_SD_OCC_C33_C33_MASK 0x0000FFFF
    #define DISP_SD_OCC_C33_C33_SHIFT 0
    #define DISP_SD_OCC_C33_K3_MASK 0xFFFF0000
    #define DISP_SD_OCC_C33_K3_SHIFT 16
#define  DISP_SD_OUTPUT_LIMIT 0xDC14
    #define DISP_SD_OUTPUT_LIMIT_Y_LIMIT_PLUS_MASK 0x000000FF
    #define DISP_SD_OUTPUT_LIMIT_Y_LIMIT_PLUS_SHIFT 0
    #define DISP_SD_OUTPUT_LIMIT_Y_LIMIT_MINUS_MASK 0x0000FF00
    #define DISP_SD_OUTPUT_LIMIT_Y_LIMIT_MINUS_SHIFT 8
    #define DISP_SD_OUTPUT_LIMIT_CBCR_LIMIT_PLUS_MASK 0x00FF0000
    #define DISP_SD_OUTPUT_LIMIT_CBCR_LIMIT_PLUS_SHIFT 16
    #define DISP_SD_OUTPUT_LIMIT_CBCR_LIMIT_MINUS_MASK 0xFF000000
    #define DISP_SD_OUTPUT_LIMIT_CBCR_LIMIT_MINUS_SHIFT 24
#define  DISP_SD_VBI0_ADR 0xDC3C
    #define DISP_SD_VBI0_ADR_BASE_MASK 0xFFFFFFF0
    #define DISP_SD_VBI0_ADR_BASE_SHIFT 4
#define  DISP_SD_VBI0_BUF 0xDC40
    #define DISP_SD_VBI0_BUF_PITCH_MASK 0x0000FFF0
    #define DISP_SD_VBI0_BUF_PITCH_SHIFT 4
    #define DISP_SD_VBI0_BUF_SIZE_MASK 0xFFFF0000
    #define DISP_SD_VBI0_BUF_SIZE_SHIFT 16
#define  DISP_SD_VBI0_HANC0_FORMAT 0xDC50
    #define DISP_SD_VBI0_HANC0_FORMAT_HANC_INPUT_10BIT_MASK 0x00000001
    #define DISP_SD_VBI0_HANC0_FORMAT_HANC_INPUT_10BIT_SHIFT 0
    #define DISP_SD_VBI0_HANC0_FORMAT_HANC_MEM_FORMAT_MASK 0x00000002
    #define DISP_SD_VBI0_HANC0_FORMAT_HANC_MEM_FORMAT_SHIFT 1
    #define DISP_SD_VBI0_HANC0_FORMAT_HANC_MAX_REQ_SIZE_MASK 0x00000FF0
    #define DISP_SD_VBI0_HANC0_FORMAT_HANC_MAX_REQ_SIZE_SHIFT 4
    #define DISP_SD_VBI0_HANC0_FORMAT_HANC_MEM_RCLI_SAFE_OFF_MASK 0x00002000
    #define DISP_SD_VBI0_HANC0_FORMAT_HANC_MEM_RCLI_SAFE_OFF_SHIFT 13
    #define DISP_SD_VBI0_HANC0_FORMAT_HANC_PIPE_DISABLE_MASK 0x00008000
    #define DISP_SD_VBI0_HANC0_FORMAT_HANC_PIPE_DISABLE_SHIFT 15
    #define DISP_SD_VBI0_HANC0_FORMAT_VBI_MEM_FORMAT_MASK 0x00010000
    #define DISP_SD_VBI0_HANC0_FORMAT_VBI_MEM_FORMAT_SHIFT 16
    #define DISP_SD_VBI0_HANC0_FORMAT_VBI_MAX_REQ_SIZE_MASK 0x0FF00000
    #define DISP_SD_VBI0_HANC0_FORMAT_VBI_MAX_REQ_SIZE_SHIFT 20
    #define DISP_SD_VBI0_HANC0_FORMAT_VBI_MEM_RCLI_SAFE_OFF_MASK 0x20000000
    #define DISP_SD_VBI0_HANC0_FORMAT_VBI_MEM_RCLI_SAFE_OFF_SHIFT 29
    #define DISP_SD_VBI0_HANC0_FORMAT_VBI_PIPE_DISABLE_MASK 0x80000000
    #define DISP_SD_VBI0_HANC0_FORMAT_VBI_PIPE_DISABLE_SHIFT 31
#define  DISP_SD_VBI0_HANC0_SIZE 0xDC38
    #define DISP_SD_VBI0_HANC0_SIZE_VBI_SIZE_MASK 0x00000FFF
    #define DISP_SD_VBI0_HANC0_SIZE_VBI_SIZE_SHIFT 0
    #define DISP_SD_VBI0_HANC0_SIZE_HANC_SIZE_MASK 0x00FFF000
    #define DISP_SD_VBI0_HANC0_SIZE_HANC_SIZE_SHIFT 12
#define  DISP_SD_VBI0_SAMPLES 0xDC44
    #define DISP_SD_VBI0_SAMPLES_WIDTH_MASK 0x0000FFFF
    #define DISP_SD_VBI0_SAMPLES_WIDTH_SHIFT 0
#define  DISP_SD_VENC0_BLACK 0xDCBC
    #define DISP_SD_VENC0_BLACK_BLACK_MASK 0x000003FF
    #define DISP_SD_VENC0_BLACK_BLACK_SHIFT 0
#define  DISP_SD_VENC0_BLANK 0xDCC0
    #define DISP_SD_VENC0_BLANK_BLANK_MASK 0x000003FF
    #define DISP_SD_VENC0_BLANK_BLANK_SHIFT 0
    #define DISP_SD_VENC0_BLANK_SYNC_STEP_MASK 0x03FF0000
    #define DISP_SD_VENC0_BLANK_SYNC_STEP_SHIFT 16
#define  DISP_SD_VENC0_CB2GAIN 0xDCD0
    #define DISP_SD_VENC0_CB2GAIN_CB2PBGAIN_MASK 0x000000FF
    #define DISP_SD_VENC0_CB2GAIN_CB2PBGAIN_SHIFT 0
    #define DISP_SD_VENC0_CB2GAIN_CB2PRGAIN_MASK 0x00FF0000
    #define DISP_SD_VENC0_CB2GAIN_CB2PRGAIN_SHIFT 16
    #define DISP_SD_VENC0_CB2GAIN_SOFT_CLIP_MASK 0x80000000
    #define DISP_SD_VENC0_CB2GAIN_SOFT_CLIP_SHIFT 31
#define  DISP_SD_VENC0_CB_FREQ 0xDCB0
    #define DISP_SD_VENC0_CB_FREQ_CB_FREQ_MASK 0xFFFFFFFF
    #define DISP_SD_VENC0_CB_FREQ_CB_FREQ_SHIFT 0
#define  DISP_SD_VENC0_CB_PHASE 0xDCB4
    #define DISP_SD_VENC0_CB_PHASE_CB_PHASE_MASK 0x000000FF
    #define DISP_SD_VENC0_CB_PHASE_CB_PHASE_SHIFT 0
#define  DISP_SD_VENC0_CLRSPC 0xDD20
    #define DISP_SD_VENC0_CLRSPC_ACTIVE_MASK 0x00000001
    #define DISP_SD_VENC0_CLRSPC_ACTIVE_SHIFT 0
    #define DISP_SD_VENC0_CLRSPC_REDADDBLANK_MASK 0x00000002
    #define DISP_SD_VENC0_CLRSPC_REDADDBLANK_SHIFT 1
    #define DISP_SD_VENC0_CLRSPC_REDADDSYNC_MASK 0x00000004
    #define DISP_SD_VENC0_CLRSPC_REDADDSYNC_SHIFT 2
    #define DISP_SD_VENC0_CLRSPC_GRNADDBLANK_MASK 0x00000008
    #define DISP_SD_VENC0_CLRSPC_GRNADDBLANK_SHIFT 3
    #define DISP_SD_VENC0_CLRSPC_GRNADDSYNC_MASK 0x00000010
    #define DISP_SD_VENC0_CLRSPC_GRNADDSYNC_SHIFT 4
    #define DISP_SD_VENC0_CLRSPC_BLUADDBLANK_MASK 0x00000020
    #define DISP_SD_VENC0_CLRSPC_BLUADDBLANK_SHIFT 5
    #define DISP_SD_VENC0_CLRSPC_BLUADDSYNC_MASK 0x00000040
    #define DISP_SD_VENC0_CLRSPC_BLUADDSYNC_SHIFT 6
    #define DISP_SD_VENC0_CLRSPC_SCALE_MASK 0x00000080
    #define DISP_SD_VENC0_CLRSPC_SCALE_SHIFT 7
#define  DISP_SD_VENC0_CLRSPCPB 0xDD18
    #define DISP_SD_VENC0_CLRSPCPB_PB2R_MASK 0x000003FF
    #define DISP_SD_VENC0_CLRSPCPB_PB2R_SHIFT 0
    #define DISP_SD_VENC0_CLRSPCPB_PB2G_MASK 0x000FFC00
    #define DISP_SD_VENC0_CLRSPCPB_PB2G_SHIFT 10
    #define DISP_SD_VENC0_CLRSPCPB_PB2B_MASK 0x3FF00000
    #define DISP_SD_VENC0_CLRSPCPB_PB2B_SHIFT 20
#define  DISP_SD_VENC0_CLRSPCPR 0xDD1C
    #define DISP_SD_VENC0_CLRSPCPR_PR2R_MASK 0x000003FF
    #define DISP_SD_VENC0_CLRSPCPR_PR2R_SHIFT 0
    #define DISP_SD_VENC0_CLRSPCPR_PR2G_MASK 0x000FFC00
    #define DISP_SD_VENC0_CLRSPCPR_PR2G_SHIFT 10
    #define DISP_SD_VENC0_CLRSPCPR_PR2B_MASK 0x3FF00000
    #define DISP_SD_VENC0_CLRSPCPR_PR2B_SHIFT 20
#define  DISP_SD_VENC0_CLRSPCY 0xDD14
    #define DISP_SD_VENC0_CLRSPCY_Y2R_MASK 0x000003FF
    #define DISP_SD_VENC0_CLRSPCY_Y2R_SHIFT 0
    #define DISP_SD_VENC0_CLRSPCY_Y2G_MASK 0x000FFC00
    #define DISP_SD_VENC0_CLRSPCY_Y2G_SHIFT 10
    #define DISP_SD_VENC0_CLRSPCY_Y2B_MASK 0x3FF00000
    #define DISP_SD_VENC0_CLRSPCY_Y2B_SHIFT 20
    #define DISP_SD_VENC0_CLRSPCY_CSC_CNTL_MASK 0xC0000000
    #define DISP_SD_VENC0_CLRSPCY_CSC_CNTL_SHIFT 30
#define  DISP_SD_VENC0_CMPST_GAIN 0xDCB8
    #define DISP_SD_VENC0_CMPST_GAIN_CMPST_Y_GAIN_MASK 0x000000FF
    #define DISP_SD_VENC0_CMPST_GAIN_CMPST_Y_GAIN_SHIFT 0
    #define DISP_SD_VENC0_CMPST_GAIN_CMPST_V_GAIN_MASK 0x0000FF00
    #define DISP_SD_VENC0_CMPST_GAIN_CMPST_V_GAIN_SHIFT 8
    #define DISP_SD_VENC0_CMPST_GAIN_CMPST_U_GAIN_MASK 0x00FF0000
    #define DISP_SD_VENC0_CMPST_GAIN_CMPST_U_GAIN_SHIFT 16
    #define DISP_SD_VENC0_CMPST_GAIN_CMPST_CB_GAIN_MASK 0xFF000000
    #define DISP_SD_VENC0_CMPST_GAIN_CMPST_CB_GAIN_SHIFT 24
#define  DISP_SD_VENC0_COEF_FUVCMPS0 0xDCE8
    #define DISP_SD_VENC0_COEF_FUVCMPS0_COEF0_FUVCMPS_MASK 0x000000FF
    #define DISP_SD_VENC0_COEF_FUVCMPS0_COEF0_FUVCMPS_SHIFT 0
    #define DISP_SD_VENC0_COEF_FUVCMPS0_COEF1_FUVCMPS_MASK 0x0000FF00
    #define DISP_SD_VENC0_COEF_FUVCMPS0_COEF1_FUVCMPS_SHIFT 8
    #define DISP_SD_VENC0_COEF_FUVCMPS0_COEF2_FUVCMPS_MASK 0x00FF0000
    #define DISP_SD_VENC0_COEF_FUVCMPS0_COEF2_FUVCMPS_SHIFT 16
    #define DISP_SD_VENC0_COEF_FUVCMPS0_COEF3_FUVCMPS_MASK 0xFF000000
    #define DISP_SD_VENC0_COEF_FUVCMPS0_COEF3_FUVCMPS_SHIFT 24
#define  DISP_SD_VENC0_COEF_FUVCMPS1 0xDCEC
    #define DISP_SD_VENC0_COEF_FUVCMPS1_COEF4_FUVCMPS_MASK 0x000000FF
    #define DISP_SD_VENC0_COEF_FUVCMPS1_COEF4_FUVCMPS_SHIFT 0
    #define DISP_SD_VENC0_COEF_FUVCMPS1_COEF5_FUVCMPS_MASK 0x0000FF00
    #define DISP_SD_VENC0_COEF_FUVCMPS1_COEF5_FUVCMPS_SHIFT 8
    #define DISP_SD_VENC0_COEF_FUVCMPS1_COEF6_FUVCMPS_MASK 0x00FF0000
    #define DISP_SD_VENC0_COEF_FUVCMPS1_COEF6_FUVCMPS_SHIFT 16
    #define DISP_SD_VENC0_COEF_FUVCMPS1_COEF7_FUVCMPS_MASK 0xFF000000
    #define DISP_SD_VENC0_COEF_FUVCMPS1_COEF7_FUVCMPS_SHIFT 24
#define  DISP_SD_VENC0_COEF_FUVCMPS2 0xDCF0
    #define DISP_SD_VENC0_COEF_FUVCMPS2_COEF8_FUVCMPS_MASK 0x000000FF
    #define DISP_SD_VENC0_COEF_FUVCMPS2_COEF8_FUVCMPS_SHIFT 0
    #define DISP_SD_VENC0_COEF_FUVCMPS2_COEF9_FUVCMPS_MASK 0x0000FF00
    #define DISP_SD_VENC0_COEF_FUVCMPS2_COEF9_FUVCMPS_SHIFT 8
    #define DISP_SD_VENC0_COEF_FUVCMPS2_COEF10_FUVCMPS_MASK 0x00FF0000
    #define DISP_SD_VENC0_COEF_FUVCMPS2_COEF10_FUVCMPS_SHIFT 16
    #define DISP_SD_VENC0_COEF_FUVCMPS2_COEF11_FUVCMPS_MASK 0xFF000000
    #define DISP_SD_VENC0_COEF_FUVCMPS2_COEF11_FUVCMPS_SHIFT 24
#define  DISP_SD_VENC0_COEF_FUVCMPS3 0xDCF4
    #define DISP_SD_VENC0_COEF_FUVCMPS3_COEF12_FUVCMPS_MASK 0x000000FF
    #define DISP_SD_VENC0_COEF_FUVCMPS3_COEF12_FUVCMPS_SHIFT 0
#define  DISP_SD_VENC0_COEF_FYCMPS0 0xDCD8
    #define DISP_SD_VENC0_COEF_FYCMPS0_COEF0_FYCMPS_MASK 0x000000FF
    #define DISP_SD_VENC0_COEF_FYCMPS0_COEF0_FYCMPS_SHIFT 0
    #define DISP_SD_VENC0_COEF_FYCMPS0_COEF1_FYCMPS_MASK 0x0000FF00
    #define DISP_SD_VENC0_COEF_FYCMPS0_COEF1_FYCMPS_SHIFT 8
    #define DISP_SD_VENC0_COEF_FYCMPS0_COEF2_FYCMPS_MASK 0x00FF0000
    #define DISP_SD_VENC0_COEF_FYCMPS0_COEF2_FYCMPS_SHIFT 16
    #define DISP_SD_VENC0_COEF_FYCMPS0_COEF3_FYCMPS_MASK 0xFF000000
    #define DISP_SD_VENC0_COEF_FYCMPS0_COEF3_FYCMPS_SHIFT 24
#define  DISP_SD_VENC0_COEF_FYCMPS1 0xDCDC
    #define DISP_SD_VENC0_COEF_FYCMPS1_COEF4_FYCMPS_MASK 0x000000FF
    #define DISP_SD_VENC0_COEF_FYCMPS1_COEF4_FYCMPS_SHIFT 0
    #define DISP_SD_VENC0_COEF_FYCMPS1_COEF5_FYCMPS_MASK 0x0000FF00
    #define DISP_SD_VENC0_COEF_FYCMPS1_COEF5_FYCMPS_SHIFT 8
    #define DISP_SD_VENC0_COEF_FYCMPS1_COEF6_FYCMPS_MASK 0x00FF0000
    #define DISP_SD_VENC0_COEF_FYCMPS1_COEF6_FYCMPS_SHIFT 16
    #define DISP_SD_VENC0_COEF_FYCMPS1_COEF7_FYCMPS_MASK 0xFF000000
    #define DISP_SD_VENC0_COEF_FYCMPS1_COEF7_FYCMPS_SHIFT 24
#define  DISP_SD_VENC0_COEF_FYCMPS2 0xDCE0
    #define DISP_SD_VENC0_COEF_FYCMPS2_COEF8_FYCMPS_MASK 0x000000FF
    #define DISP_SD_VENC0_COEF_FYCMPS2_COEF8_FYCMPS_SHIFT 0
    #define DISP_SD_VENC0_COEF_FYCMPS2_COEF9_FYCMPS_MASK 0x0000FF00
    #define DISP_SD_VENC0_COEF_FYCMPS2_COEF9_FYCMPS_SHIFT 8
    #define DISP_SD_VENC0_COEF_FYCMPS2_COEF10_FYCMPS_MASK 0x00FF0000
    #define DISP_SD_VENC0_COEF_FYCMPS2_COEF10_FYCMPS_SHIFT 16
    #define DISP_SD_VENC0_COEF_FYCMPS2_COEF11_FYCMPS_MASK 0xFF000000
    #define DISP_SD_VENC0_COEF_FYCMPS2_COEF11_FYCMPS_SHIFT 24
#define  DISP_SD_VENC0_COEF_FYCMPS3 0xDCE4
    #define DISP_SD_VENC0_COEF_FYCMPS3_COEF12_FYCMPS_MASK 0x000000FF
    #define DISP_SD_VENC0_COEF_FYCMPS3_COEF12_FYCMPS_SHIFT 0
#define  DISP_SD_VENC0_COMPDEG 0xDD24
    #define DISP_SD_VENC0_COMPDEG_COMPDEG_CS_MASK 0x000000FF
    #define DISP_SD_VENC0_COMPDEG_COMPDEG_CS_SHIFT 0
#define  DISP_SD_VENC0_CONT_STATUS 0xDCAC
    #define DISP_SD_VENC0_CONT_STATUS_CONT_STATUS_MASK 0xFFFFFFFF
    #define DISP_SD_VENC0_CONT_STATUS_CONT_STATUS_SHIFT 0
#define  DISP_SD_VENC0_DCS_CMPNT 0xDD44
    #define DISP_SD_VENC0_DCS_CMPNT_SYNC_MASK 0x00000FFF
    #define DISP_SD_VENC0_DCS_CMPNT_SYNC_SHIFT 0
    #define DISP_SD_VENC0_DCS_CMPNT_BLANK_MASK 0x0FFF0000
    #define DISP_SD_VENC0_DCS_CMPNT_BLANK_SHIFT 16
#define  DISP_SD_VENC0_DCS_CMPNT_AGC 0xDD54
    #define DISP_SD_VENC0_DCS_CMPNT_AGC_AGC1_A_MASK 0x00000FFF
    #define DISP_SD_VENC0_DCS_CMPNT_AGC_AGC1_A_SHIFT 0
    #define DISP_SD_VENC0_DCS_CMPNT_AGC_AGC1_B_MASK 0x0FFF0000
    #define DISP_SD_VENC0_DCS_CMPNT_AGC_AGC1_B_SHIFT 16
#define  DISP_SD_VENC0_DCS_CMPNT_GO 0xDD48
    #define DISP_SD_VENC0_DCS_CMPNT_GO_GAIN_MASK 0x00000FFF
    #define DISP_SD_VENC0_DCS_CMPNT_GO_GAIN_SHIFT 0
    #define DISP_SD_VENC0_DCS_CMPNT_GO_OFFSET_MASK 0x0FFF0000
    #define DISP_SD_VENC0_DCS_CMPNT_GO_OFFSET_SHIFT 16
#define  DISP_SD_VENC0_DCS_CMPNT_ICLK227K 0xDD50
    #define DISP_SD_VENC0_DCS_CMPNT_ICLK227K_ICLK227K_1_MASK 0x00000FFF
    #define DISP_SD_VENC0_DCS_CMPNT_ICLK227K_ICLK227K_1_SHIFT 0
    #define DISP_SD_VENC0_DCS_CMPNT_ICLK227K_ICLK227K_2_MASK 0x0FFF0000
    #define DISP_SD_VENC0_DCS_CMPNT_ICLK227K_ICLK227K_2_SHIFT 16
#define  DISP_SD_VENC0_DCS_CMPNT_ICLK397K 0xDD4C
    #define DISP_SD_VENC0_DCS_CMPNT_ICLK397K_ICLK397K_MASK 0x00000FFF
    #define DISP_SD_VENC0_DCS_CMPNT_ICLK397K_ICLK397K_SHIFT 0
    #define DISP_SD_VENC0_DCS_CMPNT_ICLK397K_ICLK397K_C_MASK 0x0FFF0000
    #define DISP_SD_VENC0_DCS_CMPNT_ICLK397K_ICLK397K_C_SHIFT 16
#define  DISP_SD_VENC0_DCS_CONFIG 0xDD40
    #define DISP_SD_VENC0_DCS_CONFIG_FIELDRATE50_MASK 0x00000001
    #define DISP_SD_VENC0_DCS_CONFIG_FIELDRATE50_SHIFT 0
    #define DISP_SD_VENC0_DCS_CONFIG_SD_COMPOSITE_MASK 0x00000002
    #define DISP_SD_VENC0_DCS_CONFIG_SD_COMPOSITE_SHIFT 1
    #define DISP_SD_VENC0_DCS_CONFIG_SD_COMPONENT_I_MASK 0x00000004
    #define DISP_SD_VENC0_DCS_CONFIG_SD_COMPONENT_I_SHIFT 2
    #define DISP_SD_VENC0_DCS_CONFIG_SD_COMPONENT_P_MASK 0x00000008
    #define DISP_SD_VENC0_DCS_CONFIG_SD_COMPONENT_P_SHIFT 3
    #define DISP_SD_VENC0_DCS_CONFIG_HD_720P_MASK 0x00000010
    #define DISP_SD_VENC0_DCS_CONFIG_HD_720P_SHIFT 4
    #define DISP_SD_VENC0_DCS_CONFIG_HD_1080I_MASK 0x00000020
    #define DISP_SD_VENC0_DCS_CONFIG_HD_1080I_SHIFT 5
    #define DISP_SD_VENC0_DCS_CONFIG_HD_1080P_MASK 0x00000040
    #define DISP_SD_VENC0_DCS_CONFIG_HD_1080P_SHIFT 6
    #define DISP_SD_VENC0_DCS_CONFIG_HD_1080P_SLOW_MASK 0x00000080
    #define DISP_SD_VENC0_DCS_CONFIG_HD_1080P_SLOW_SHIFT 7
    #define DISP_SD_VENC0_DCS_CONFIG_DCS_ENABLE_MASK 0x00000100
    #define DISP_SD_VENC0_DCS_CONFIG_DCS_ENABLE_SHIFT 8
    #define DISP_SD_VENC0_DCS_CONFIG_DCS_CLOCK2X_MASK 0x00000200
    #define DISP_SD_VENC0_DCS_CONFIG_DCS_CLOCK2X_SHIFT 9
    #define DISP_SD_VENC0_DCS_CONFIG_DCS_SYNC_OFFSET_MASK 0x1FFF0000
    #define DISP_SD_VENC0_DCS_CONFIG_DCS_SYNC_OFFSET_SHIFT 16
    #define DISP_SD_VENC0_DCS_CONFIG_DCS_RST_MASK 0x80000000
    #define DISP_SD_VENC0_DCS_CONFIG_DCS_RST_SHIFT 31
#define  DISP_SD_VENC0_DCS_FAKE_FRAME_START 0xDD5C
    #define DISP_SD_VENC0_DCS_FAKE_FRAME_START_DUMMY_BIT_MASK 0x00000001
    #define DISP_SD_VENC0_DCS_FAKE_FRAME_START_DUMMY_BIT_SHIFT 0
#define  DISP_SD_VENC0_DCS_KEY_HIGH 0xDD38
    #define DISP_SD_VENC0_DCS_KEY_HIGH_DATA_MASK 0xFFFFFFFF
    #define DISP_SD_VENC0_DCS_KEY_HIGH_DATA_SHIFT 0
#define  DISP_SD_VENC0_DCS_KEY_LOW 0xDD3C
    #define DISP_SD_VENC0_DCS_KEY_LOW_DATA_MASK 0xFFFFFFFF
    #define DISP_SD_VENC0_DCS_KEY_LOW_DATA_SHIFT 0
#define  DISP_SD_VENC0_DCS_START_LINE 0xDD58
    #define DISP_SD_VENC0_DCS_START_LINE_MASK 0x00000FFF
    #define DISP_SD_VENC0_DCS_START_LINE_SHIFT 0
#define  DISP_SD_VENC0_DCS_STATUS 0xDD60
    #define DISP_SD_VENC0_DCS_STATUS_BUSY_N_MASK 0x00000001
    #define DISP_SD_VENC0_DCS_STATUS_BUSY_N_SHIFT 0
    #define DISP_SD_VENC0_DCS_STATUS_LOCKED_MASK 0x00000002
    #define DISP_SD_VENC0_DCS_STATUS_LOCKED_SHIFT 1
    #define DISP_SD_VENC0_DCS_STATUS_ACTIVE_MASK 0x00000004
    #define DISP_SD_VENC0_DCS_STATUS_ACTIVE_SHIFT 2
    #define DISP_SD_VENC0_DCS_STATUS_CPREGLOW_MASK 0xFFFFFF00
    #define DISP_SD_VENC0_DCS_STATUS_CPREGLOW_SHIFT 8
#define  DISP_SD_VENC0_DVE_CNTRL 0xDD34
    #define DISP_SD_VENC0_DVE_CNTRL_CLKDIV_MASK 0x00000001
    #define DISP_SD_VENC0_DVE_CNTRL_CLKDIV_SHIFT 0
    #define DISP_SD_VENC0_DVE_CNTRL_BUSTYPE_MASK 0x00000006
    #define DISP_SD_VENC0_DVE_CNTRL_BUSTYPE_SHIFT 1
    #define DISP_SD_VENC0_DVE_CNTRL_BUSWIDTH_MASK 0x00000018
    #define DISP_SD_VENC0_DVE_CNTRL_BUSWIDTH_SHIFT 3
    #define DISP_SD_VENC0_DVE_CNTRL_CLKSAMPONRISING_MASK 0x00000020
    #define DISP_SD_VENC0_DVE_CNTRL_CLKSAMPONRISING_SHIFT 5
    #define DISP_SD_VENC0_DVE_CNTRL_OUTPUT_ORDER_MASK 0x000003C0
    #define DISP_SD_VENC0_DVE_CNTRL_OUTPUT_ORDER_SHIFT 6
    #define DISP_SD_VENC0_DVE_CNTRL_BLANK_ON_EOFN_MASK 0x00010000
    #define DISP_SD_VENC0_DVE_CNTRL_BLANK_ON_EOFN_SHIFT 16
#define  DISP_SD_VENC0_DVE_FIELD_BNDRY 0xDD28
    #define DISP_SD_VENC0_DVE_FIELD_BNDRY_DVE_FIELD_BNDRY_1_MASK 0x00000FFF
    #define DISP_SD_VENC0_DVE_FIELD_BNDRY_DVE_FIELD_BNDRY_1_SHIFT 0
    #define DISP_SD_VENC0_DVE_FIELD_BNDRY_DVE_FIELD_BNDRY_2_MASK 0x0FFF0000
    #define DISP_SD_VENC0_DVE_FIELD_BNDRY_DVE_FIELD_BNDRY_2_SHIFT 16
#define  DISP_SD_VENC0_DVE_VBLANK_END_BNDRY 0xDD30
    #define DISP_SD_VENC0_DVE_VBLANK_END_BNDRY_DVE_VBLANK_END_BNDRY_1_MASK 0x00000FFF
    #define DISP_SD_VENC0_DVE_VBLANK_END_BNDRY_DVE_VBLANK_END_BNDRY_1_SHIFT 0
    #define DISP_SD_VENC0_DVE_VBLANK_END_BNDRY_DVE_VBLANK_END_BNDRY_2_MASK 0x0FFF0000
    #define DISP_SD_VENC0_DVE_VBLANK_END_BNDRY_DVE_VBLANK_END_BNDRY_2_SHIFT 16
#define  DISP_SD_VENC0_DVE_VBLANK_START_BNDRY 0xDD2C
    #define DISP_SD_VENC0_DVE_VBLANK_START_BNDRY_DVE_VBLANK_START_BNDRY_1_MASK 0x00000FFF
    #define DISP_SD_VENC0_DVE_VBLANK_START_BNDRY_DVE_VBLANK_START_BNDRY_1_SHIFT 0
    #define DISP_SD_VENC0_DVE_VBLANK_START_BNDRY_DVE_VBLANK_START_BNDRY_2_MASK 0x0FFF0000
    #define DISP_SD_VENC0_DVE_VBLANK_START_BNDRY_DVE_VBLANK_START_BNDRY_2_SHIFT 16
#define  DISP_SD_VENC0_FIELDBNDRY 0xDCD4
    #define DISP_SD_VENC0_FIELDBNDRY_FIELDBNDRY_MASK 0x00000FFF
    #define DISP_SD_VENC0_FIELDBNDRY_FIELDBNDRY_SHIFT 0
#define  DISP_SD_VENC0_MACROV_CS_PARAM 0xDD10
    #define DISP_SD_VENC0_MACROV_CS_PARAM_MACROV_CS_INC_MASK 0x00000FFF
    #define DISP_SD_VENC0_MACROV_CS_PARAM_MACROV_CS_INC_SHIFT 0
    #define DISP_SD_VENC0_MACROV_CS_PARAM_MACROV_CS_NUM_LINES_MASK 0x000F0000
    #define DISP_SD_VENC0_MACROV_CS_PARAM_MACROV_CS_NUM_LINES_SHIFT 16
#define  DISP_SD_VENC0_MACROV_CS_STRTF 0xDD0C
    #define DISP_SD_VENC0_MACROV_CS_STRTF_MACROV_CS_STRTF1_MASK 0x00000FFF
    #define DISP_SD_VENC0_MACROV_CS_STRTF_MACROV_CS_STRTF1_SHIFT 0
    #define DISP_SD_VENC0_MACROV_CS_STRTF_MACROV_CS_STRTF2_MASK 0x0FFF0000
    #define DISP_SD_VENC0_MACROV_CS_STRTF_MACROV_CS_STRTF2_SHIFT 16
    #define DISP_SD_VENC0_MACROV_CS_STRTF_MACROV_CS_EN_MASK 0x80000000
    #define DISP_SD_VENC0_MACROV_CS_STRTF_MACROV_CS_EN_SHIFT 31
#define  DISP_SD_VENC0_MACROV_LVL 0xDD08
    #define DISP_SD_VENC0_MACROV_LVL_MACROV_LVL_MASK 0xFFFFFFFF
    #define DISP_SD_VENC0_MACROV_LVL_MACROV_LVL_SHIFT 0
#define  DISP_SD_VENC0_MACROV_T1_EVEN 0xDCF8
    #define DISP_SD_VENC0_MACROV_T1_EVEN_MACROV_T1_EVEN_MASK 0xFFFFFFFF
    #define DISP_SD_VENC0_MACROV_T1_EVEN_MACROV_T1_EVEN_SHIFT 0
#define  DISP_SD_VENC0_MACROV_T1_ODD 0xDD00
    #define DISP_SD_VENC0_MACROV_T1_ODD_MACROV_T1_ODD_MASK 0xFFFFFFFF
    #define DISP_SD_VENC0_MACROV_T1_ODD_MACROV_T1_ODD_SHIFT 0
#define  DISP_SD_VENC0_MACROV_T2_EVEN 0xDCFC
    #define DISP_SD_VENC0_MACROV_T2_EVEN_MACROV_T2_EVEN_MASK 0xFFFFFFFF
    #define DISP_SD_VENC0_MACROV_T2_EVEN_MACROV_T2_EVEN_SHIFT 0
#define  DISP_SD_VENC0_MACROV_T2_ODD 0xDD04
    #define DISP_SD_VENC0_MACROV_T2_ODD_MACROV_T2_ODD_MASK 0xFFFFFFFF
    #define DISP_SD_VENC0_MACROV_T2_ODD_MACROV_T2_ODD_SHIFT 0
#define  DISP_SD_VENC0_SYNC1 0xDCC4
    #define DISP_SD_VENC0_SYNC1_SYNC1_MASK 0x000003FF
    #define DISP_SD_VENC0_SYNC1_SYNC1_SHIFT 0
    #define DISP_SD_VENC0_SYNC1_CNST1_MASK 0x03FF0000
    #define DISP_SD_VENC0_SYNC1_CNST1_SHIFT 16
#define  DISP_SD_VENC0_SYNC2 0xDCC8
    #define DISP_SD_VENC0_SYNC2_SYNC2_MASK 0x000003FF
    #define DISP_SD_VENC0_SYNC2_SYNC2_SHIFT 0
    #define DISP_SD_VENC0_SYNC2_CNST2_MASK 0x03FF0000
    #define DISP_SD_VENC0_SYNC2_CNST2_SHIFT 16
#define  DISP_SD_VENC0_WRADDR 0xDCA4
    #define DISP_SD_VENC0_WRADDR_WRADDR_MASK 0xFFFFFFFF
    #define DISP_SD_VENC0_WRADDR_WRADDR_SHIFT 0
#define  DISP_SD_VENC0_WRDATA 0xDCA8
    #define DISP_SD_VENC0_WRDATA_WRDATA_MASK 0xFFFFFFFF
    #define DISP_SD_VENC0_WRDATA_WRDATA_SHIFT 0
#define  DISP_SD_VENC0_YCMPN 0xDCCC
    #define DISP_SD_VENC0_YCMPN_YCMPNGAIN_MASK 0x000000FF
    #define DISP_SD_VENC0_YCMPN_YCMPNGAIN_SHIFT 0
    #define DISP_SD_VENC0_YCMPN_YCMPNOFF_MASK 0x03FF0000
    #define DISP_SD_VENC0_YCMPN_YCMPNOFF_SHIFT 16
#define  DISP_SFT_RESET 0xDB14
    #define GLOBAL_SFT_RSTN_MASK 0x00000001
    #define GLOBAL_SFT_RSTN_SHIFT 0
    #define MEM_RCLI_SFT_RSTN_MASK 0x00000002
    #define MEM_RCLI_SFT_RSTN_SHIFT 1
    #define HDMI_SFT_RSTN_MASK 0x00000004
    #define HDMI_SFT_RSTN_SHIFT 2
    #define OUTPUT_MUX_SFT_RSTN_MASK 0x00000008
    #define OUTPUT_MUX_SFT_RSTN_SHIFT 3
    #define HD_PATH_SFT_RSTN_MASK 0x00000010
    #define HD_PATH_SFT_RSTN_SHIFT 4
    #define HD_CMD_FIFO_SFT_RSTN_MASK 0x00000020
    #define HD_CMD_FIFO_SFT_RSTN_SHIFT 5
    #define HD_SHDW_SFT_RSTN_MASK 0x00000040
    #define HD_SHDW_SFT_RSTN_SHIFT 6
    #define HD_VENC_SFT_RSTN_MASK 0x00000080
    #define HD_VENC_SFT_RSTN_SHIFT 7
    #define HD_COMP_SFT_RSTN_MASK 0x00000100
    #define HD_COMP_SFT_RSTN_SHIFT 8
    #define SD_PATH_SFT_RSTN_MASK 0x00000200
    #define SD_PATH_SFT_RSTN_SHIFT 9
    #define SD_CMD_FIFO_SFT_RSTN_MASK 0x00000400
    #define SD_CMD_FIFO_SFT_RSTN_SHIFT 10
    #define SD_SHDW_SFT_RSTN_MASK 0x00000800
    #define SD_SHDW_SFT_RSTN_SHIFT 11
    #define SD_VENC_SFT_RSTN_MASK 0x00001000
    #define SD_VENC_SFT_RSTN_SHIFT 12
    #define SD_COMP_SFT_RSTN_MASK 0x00002000
    #define SD_COMP_SFT_RSTN_SHIFT 13
    #define HD_GSCALER0_CLOCK_STOP_MASK 0x00010000
    #define HD_GSCALER0_CLOCK_STOP_SHIFT 16
    #define HD_GSCALER1_CLOCK_STOP_MASK 0x00020000
    #define HD_GSCALER1_CLOCK_STOP_SHIFT 17
    #define HD_VSCALER0_CLOCK_STOP_MASK 0x00040000
    #define HD_VSCALER0_CLOCK_STOP_SHIFT 18
    #define HD_VSCALER1_CLOCK_STOP_MASK 0x00080000
    #define HD_VSCALER1_CLOCK_STOP_SHIFT 19
    #define HD_CLOCK_STOP_MASK 0x00100000
    #define HD_CLOCK_STOP_SHIFT 20
    #define SD_GSCALER0_CLOCK_STOP_MASK 0x00200000
    #define SD_GSCALER0_CLOCK_STOP_SHIFT 21
    #define SD_CLOCK_STOP_MASK 0x00400000
    #define SD_CLOCK_STOP_SHIFT 22
    #define DISP_CLOCK_STOP_MASK 0x80000000
    #define DISP_CLOCK_STOP_SHIFT 31
#define  DISP_SIMULATION 0xDB10
    #define FID_COMP_OUT_MASK 0x0000000F
    #define FID_COMP_OUT_SHIFT 0
    #define FID_VID0_OUT_MASK 0x000000F0
    #define FID_VID0_OUT_SHIFT 4
    #define FID_VID0_IN_MASK 0x00000F00
    #define FID_VID0_IN_SHIFT 8
    #define FID_VID1_OUT_MASK 0x0000F000
    #define FID_VID1_OUT_SHIFT 12
    #define FID_VID1_IN_MASK 0x000F0000
    #define FID_VID1_IN_SHIFT 16
    #define FID_GRA0_IN_MASK 0x00F00000
    #define FID_GRA0_IN_SHIFT 20
    #define FID_GRA1_IN_MASK 0x0F000000
    #define FID_GRA1_IN_SHIFT 24
    #define COEF_AUTO_GENERATE_MASK 0x80000000
    #define COEF_AUTO_GENERATE_SHIFT 31
#define  DISP_VDAC01_CNTL 0xDB1C
    #define DISP_VDAC01_CNTL_MASK 0xFFFFFFFF
    #define DISP_VDAC01_CNTL_SHIFT 0
#define  DISP_VDAC23_CNTL 0xDB20
    #define DISP_VDAC23_CNTL_MASK 0xFFFFFFFF
    #define DISP_VDAC23_CNTL_SHIFT 0
#define  DISP_VDAC45_CNTL 0xDB24
    #define DISP_VDAC45_CNTL_MASK 0xFFFFFFFF
    #define DISP_VDAC45_CNTL_SHIFT 0
#define  DISP_VDAC_BIAS_CNTL 0xDB34
    #define DISP_VDAC_BIAS_CNTL_MASK 0x0000FFFF
    #define DISP_VDAC_BIAS_CNTL_SHIFT 0
#define  DISP_VDAC_CABLE_CONNECT 0xDB30
    #define DISP_VDAC_CABLE_CONNECT_MASK 0xFFFFFFFF
    #define DISP_VDAC_CABLE_CONNECT_SHIFT 0
#define  DISP_VDAC_CABLE_DETECT 0xDB38
    #define DISP_VDAC_CABLE_DETECT_MASK 0x0000003F
    #define DISP_VDAC_CABLE_DETECT_SHIFT 0
#define  DISP_VDAC_SET0_CNTL 0xDB28
    #define DISP_VDAC_SET0_CNTL_MASK 0xFFFFFFFF
    #define DISP_VDAC_SET0_CNTL_SHIFT 0
#define  DISP_VDAC_SET1_CNTL 0xDB2C
    #define DISP_VDAC_SET1_CNTL_MASK 0xFFFFFFFF
    #define DISP_VDAC_SET1_CNTL_SHIFT 0
#define  DMA_ACTIVE_CMD 0x0C30
    #define DMA_ACTIVE_CMD_BYTECNT_MASK 0x0000FFFF
    #define DMA_ACTIVE_CMD_BYTECNT_SHIFT 0
    #define DMA_ACTIVE_CMD_ENCRYPT_TYPE_SEL_MASK 0x00070000
    #define DMA_ACTIVE_CMD_ENCRYPT_TYPE_SEL_SHIFT 16
    #define EXTENDED_MASK 0x00080000
    #define EXTENDED_SHIFT 19
    #define DMA_ACTIVE_CMD_ENCRYPT_EN_MASK 0x00300000
    #define DMA_ACTIVE_CMD_ENCRYPT_EN_SHIFT 20
    #define DMA_ACTIVE_CMD_STREAMCIPHER_START_MASK 0x00400000
    #define DMA_ACTIVE_CMD_STREAMCIPHER_START_SHIFT 22
    #define DMA_ACTIVE_CMD_FILL_MODE_MASK 0x00800000
    #define DMA_ACTIVE_CMD_FILL_MODE_SHIFT 23
    #define DMA_ACTIVE_CMD_SRCSPACE_MASK 0x01000000
    #define DMA_ACTIVE_CMD_SRCSPACE_SHIFT 24
    #define DMA_ACTIVE_CMD_DSTSPACE_MASK 0x02000000
    #define DMA_ACTIVE_CMD_DSTSPACE_SHIFT 25
    #define DMA_ACTIVE_CMD_SWAP_MASK 0x0C000000
    #define DMA_ACTIVE_CMD_SWAP_SHIFT 26
    #define DMA_ACTIVE_CMD_INTHOST_MASK 0x10000000
    #define DMA_ACTIVE_CMD_INTHOST_SHIFT 28
    #define DMA_ACTIVE_CMD_INTMIPS_MASK 0x20000000
    #define DMA_ACTIVE_CMD_INTMIPS_SHIFT 29
    #define PREEMPTED_MASK 0x40000000
    #define PREEMPTED_SHIFT 30
    #define EOL_MASK 0x80000000
    #define EOL_SHIFT 31
#define  DMA_ACTIVE_DESCRIPTOR 0x0C38
    #define DMA_ACTIVE_DESCRIPTOR_BASE_MASK 0x0FFFFFF8
    #define DMA_ACTIVE_DESCRIPTOR_BASE_SHIFT 3
    #define READING_MASK 0x10000000
    #define READING_SHIFT 28
    #define UPPER_BASE_MASK 0xE0000000
    #define UPPER_BASE_SHIFT 29
#define  DMA_C2_CTRL 0x0CF8
    #define SC_SELECT_MASK 0x00000001
    #define SC_SELECT_SHIFT 0
#define  DMA_CLI_PIPELINE_CTRL 0x0CC8
    #define DMA_CLI_PIPELINE_CTRL_ENABLE_MASK 0x00000001
    #define DMA_CLI_PIPELINE_CTRL_ENABLE_SHIFT 0
#define  DMA_CLI_PIPELINE_STATUS 0x0CC4
    #define CLI0_ACTIVE_MASK 0x0000000F
    #define CLI0_ACTIVE_SHIFT 0
    #define CLI1_ACTIVE_MASK 0x000000F0
    #define CLI1_ACTIVE_SHIFT 4
    #define CLI2_ACTIVE_MASK 0x00000F00
    #define CLI2_ACTIVE_SHIFT 8
    #define CLI3_ACTIVE_MASK 0x0000F000
    #define CLI3_ACTIVE_SHIFT 12
    #define CLI4_ACTIVE_MASK 0x000F0000
    #define CLI4_ACTIVE_SHIFT 16
    #define CLI5_ACTIVE_MASK 0x00F00000
    #define CLI5_ACTIVE_SHIFT 20
    #define CLI6_ACTIVE_MASK 0x0F000000
    #define CLI6_ACTIVE_SHIFT 24
    #define CLI7_ACTIVE_MASK 0xF0000000
    #define CLI7_ACTIVE_SHIFT 28
#define  DMA_CRC_STATUS 0x0CC0
    #define CRC_VALUE_MASK 0xFFFFFFFF
    #define CRC_VALUE_SHIFT 0
#define  DMA_DAT_CNT_STATUS 0x0CE0
    #define DATIN_BYTECNT_MASK 0x0000FFFF
    #define DATIN_BYTECNT_SHIFT 0
    #define DATOUT_BYTECNT_MASK 0xFFFF0000
    #define DATOUT_BYTECNT_SHIFT 16
#define  DMA_DEBUG 0x0CE8
    #define DEBUG_INFO_MASK 0x000FFFFF
    #define DEBUG_INFO_SHIFT 0
#define  DMA_DEBUG_CTRL 0x0CE4
    #define DEBUG_CTRL_MASK 0x0000000F
    #define DEBUG_CTRL_SHIFT 0
#define  DMA_DIRECT_CRYPT_INDICES_A 0x0CD0
    #define DMA_DIRECT_CRYPT_INDICES_A_IV_SRC_INDEX_MASK 0x000000FF
    #define DMA_DIRECT_CRYPT_INDICES_A_IV_SRC_INDEX_SHIFT 0
    #define DMA_DIRECT_CRYPT_INDICES_A_IV_DST_INDEX_MASK 0x0000FF00
    #define DMA_DIRECT_CRYPT_INDICES_A_IV_DST_INDEX_SHIFT 8
    #define DMA_DIRECT_CRYPT_INDICES_A_CW_SRC_INDEX_MASK 0x00FF0000
    #define DMA_DIRECT_CRYPT_INDICES_A_CW_SRC_INDEX_SHIFT 16
    #define DMA_DIRECT_CRYPT_INDICES_A_CW_SRC_INDEX_ODD_MASK 0xFF000000
    #define DMA_DIRECT_CRYPT_INDICES_A_CW_SRC_INDEX_ODD_SHIFT 24
#define  DMA_DIRECT_CRYPT_INDICES_B 0x0CD4
    #define DMA_DIRECT_CRYPT_INDICES_B_IV_SRC_INDEX_MASK 0x000000FF
    #define DMA_DIRECT_CRYPT_INDICES_B_IV_SRC_INDEX_SHIFT 0
    #define DMA_DIRECT_CRYPT_INDICES_B_IV_DST_INDEX_MASK 0x0000FF00
    #define DMA_DIRECT_CRYPT_INDICES_B_IV_DST_INDEX_SHIFT 8
    #define DMA_DIRECT_CRYPT_INDICES_B_CW_SRC_INDEX_MASK 0x00FF0000
    #define DMA_DIRECT_CRYPT_INDICES_B_CW_SRC_INDEX_SHIFT 16
    #define DMA_DIRECT_CRYPT_INDICES_B_CW_SRC_INDEX_ODD_MASK 0xFF000000
    #define DMA_DIRECT_CRYPT_INDICES_B_CW_SRC_INDEX_ODD_SHIFT 24
#define  DMA_DIRECT_DMACMD_A 0x0C90
    #define DMA_DIRECT_DMACMD_A_BYTECNT_MASK 0x0000FFFF
    #define DMA_DIRECT_DMACMD_A_BYTECNT_SHIFT 0
    #define DMA_DIRECT_DMACMD_A_ENCRYPT_TYPE_SEL_MASK 0x00070000
    #define DMA_DIRECT_DMACMD_A_ENCRYPT_TYPE_SEL_SHIFT 16
    #define DMA_DIRECT_DMACMD_A_ENCRYPT_EN_MASK 0x00300000
    #define DMA_DIRECT_DMACMD_A_ENCRYPT_EN_SHIFT 20
    #define DMA_DIRECT_DMACMD_A_STREAMCIPHER_START_MASK 0x00400000
    #define DMA_DIRECT_DMACMD_A_STREAMCIPHER_START_SHIFT 22
    #define DMA_DIRECT_DMACMD_A_FILL_MODE_MASK 0x00800000
    #define DMA_DIRECT_DMACMD_A_FILL_MODE_SHIFT 23
    #define DMA_DIRECT_DMACMD_A_SRCSPACE_MASK 0x01000000
    #define DMA_DIRECT_DMACMD_A_SRCSPACE_SHIFT 24
    #define DMA_DIRECT_DMACMD_A_DSTSPACE_MASK 0x02000000
    #define DMA_DIRECT_DMACMD_A_DSTSPACE_SHIFT 25
    #define DMA_DIRECT_DMACMD_A_SWAP_MASK 0x0C000000
    #define DMA_DIRECT_DMACMD_A_SWAP_SHIFT 26
    #define DMA_DIRECT_DMACMD_A_INTHOST_MASK 0x10000000
    #define DMA_DIRECT_DMACMD_A_INTHOST_SHIFT 28
    #define DMA_DIRECT_DMACMD_A_INTMIPS_MASK 0x20000000
    #define DMA_DIRECT_DMACMD_A_INTMIPS_SHIFT 29
    #define DMA_DIRECT_DMACMD_A_URGENT_MASK 0x40000000
    #define DMA_DIRECT_DMACMD_A_URGENT_SHIFT 30
#define  DMA_DIRECT_DMACMD_B 0x0CB0
    #define DMA_DIRECT_DMACMD_B_BYTECNT_MASK 0x0000FFFF
    #define DMA_DIRECT_DMACMD_B_BYTECNT_SHIFT 0
    #define DMA_DIRECT_DMACMD_B_ENCRYPT_TYPE_SEL_MASK 0x00070000
    #define DMA_DIRECT_DMACMD_B_ENCRYPT_TYPE_SEL_SHIFT 16
    #define DMA_DIRECT_DMACMD_B_ENCRYPT_EN_MASK 0x00300000
    #define DMA_DIRECT_DMACMD_B_ENCRYPT_EN_SHIFT 20
    #define DMA_DIRECT_DMACMD_B_STREAMCIPHER_START_MASK 0x00400000
    #define DMA_DIRECT_DMACMD_B_STREAMCIPHER_START_SHIFT 22
    #define DMA_DIRECT_DMACMD_B_FILL_MODE_MASK 0x00800000
    #define DMA_DIRECT_DMACMD_B_FILL_MODE_SHIFT 23
    #define DMA_DIRECT_DMACMD_B_SRCSPACE_MASK 0x01000000
    #define DMA_DIRECT_DMACMD_B_SRCSPACE_SHIFT 24
    #define DMA_DIRECT_DMACMD_B_DSTSPACE_MASK 0x02000000
    #define DMA_DIRECT_DMACMD_B_DSTSPACE_SHIFT 25
    #define DMA_DIRECT_DMACMD_B_SWAP_MASK 0x0C000000
    #define DMA_DIRECT_DMACMD_B_SWAP_SHIFT 26
    #define DMA_DIRECT_DMACMD_B_INTHOST_MASK 0x10000000
    #define DMA_DIRECT_DMACMD_B_INTHOST_SHIFT 28
    #define DMA_DIRECT_DMACMD_B_INTMIPS_MASK 0x20000000
    #define DMA_DIRECT_DMACMD_B_INTMIPS_SHIFT 29
    #define DMA_DIRECT_DMACMD_B_URGENT_MASK 0x40000000
    #define DMA_DIRECT_DMACMD_B_URGENT_SHIFT 30
#define  DMA_DIRECT_DMACW_A 0x0C94
    #define DMA_DIRECT_DMACW_A_DES_S0_CTRL_MASK 0x00000040
    #define DMA_DIRECT_DMACW_A_DES_S0_CTRL_SHIFT 6
    #define DMA_DIRECT_DMACW_A_DES_S0_MODE_MASK 0x00000080
    #define DMA_DIRECT_DMACW_A_DES_S0_MODE_SHIFT 7
    #define DMA_DIRECT_DMACW_A_DES_S1_CTRL_MASK 0x00000100
    #define DMA_DIRECT_DMACW_A_DES_S1_CTRL_SHIFT 8
    #define DMA_DIRECT_DMACW_A_DES_S1_MODE_MASK 0x00000200
    #define DMA_DIRECT_DMACW_A_DES_S1_MODE_SHIFT 9
    #define DMA_DIRECT_DMACW_A_DES_S2_CTRL_MASK 0x00000400
    #define DMA_DIRECT_DMACW_A_DES_S2_CTRL_SHIFT 10
    #define DMA_DIRECT_DMACW_A_DES_S2_MODE_MASK 0x00000800
    #define DMA_DIRECT_DMACW_A_DES_S2_MODE_SHIFT 11
    #define DMA_DIRECT_DMACW_A_AES_CFB_MASK 0x00001000
    #define DMA_DIRECT_DMACW_A_AES_CFB_SHIFT 12
    #define DMA_DIRECT_DMACW_A_AES_OFB_MASK 0x00002000
    #define DMA_DIRECT_DMACW_A_AES_OFB_SHIFT 13
    #define DMA_DIRECT_DMACW_A_AES_NEW_CW_MASK 0x00004000
    #define DMA_DIRECT_DMACW_A_AES_NEW_CW_SHIFT 14
    #define DMA_DIRECT_DMACW_A_INPUT_DWORD_SWAP_MASK 0x00400000
    #define DMA_DIRECT_DMACW_A_INPUT_DWORD_SWAP_SHIFT 22
    #define DMA_DIRECT_DMACW_A_OUTPUT_DWORD_SWAP_MASK 0x00800000
    #define DMA_DIRECT_DMACW_A_OUTPUT_DWORD_SWAP_SHIFT 23
    #define DMA_DIRECT_DMACW_A_KEYSTORE_SRC_MASK 0x20000000
    #define DMA_DIRECT_DMACW_A_KEYSTORE_SRC_SHIFT 29
    #define DMA_DIRECT_DMACW_A_KEYSTORE_DST_MASK 0x40000000
    #define DMA_DIRECT_DMACW_A_KEYSTORE_DST_SHIFT 30
    #define DMA_DIRECT_DMACW_A_DEBUG_MODE_MASK 0x80000000
    #define DMA_DIRECT_DMACW_A_DEBUG_MODE_SHIFT 31
#define  DMA_DIRECT_DMACW_B 0x0CB4
    #define DMA_DIRECT_DMACW_B_DES_S0_CTRL_MASK 0x00000040
    #define DMA_DIRECT_DMACW_B_DES_S0_CTRL_SHIFT 6
    #define DMA_DIRECT_DMACW_B_DES_S0_MODE_MASK 0x00000080
    #define DMA_DIRECT_DMACW_B_DES_S0_MODE_SHIFT 7
    #define DMA_DIRECT_DMACW_B_DES_S1_CTRL_MASK 0x00000100
    #define DMA_DIRECT_DMACW_B_DES_S1_CTRL_SHIFT 8
    #define DMA_DIRECT_DMACW_B_DES_S1_MODE_MASK 0x00000200
    #define DMA_DIRECT_DMACW_B_DES_S1_MODE_SHIFT 9
    #define DMA_DIRECT_DMACW_B_DES_S2_CTRL_MASK 0x00000400
    #define DMA_DIRECT_DMACW_B_DES_S2_CTRL_SHIFT 10
    #define DMA_DIRECT_DMACW_B_DES_S2_MODE_MASK 0x00000800
    #define DMA_DIRECT_DMACW_B_DES_S2_MODE_SHIFT 11
    #define DMA_DIRECT_DMACW_B_AES_CFB_MASK 0x00001000
    #define DMA_DIRECT_DMACW_B_AES_CFB_SHIFT 12
    #define DMA_DIRECT_DMACW_B_AES_OFB_MASK 0x00002000
    #define DMA_DIRECT_DMACW_B_AES_OFB_SHIFT 13
    #define DMA_DIRECT_DMACW_B_AES_NEW_CW_MASK 0x00004000
    #define DMA_DIRECT_DMACW_B_AES_NEW_CW_SHIFT 14
    #define DMA_DIRECT_DMACW_B_INPUT_DWORD_SWAP_MASK 0x00400000
    #define DMA_DIRECT_DMACW_B_INPUT_DWORD_SWAP_SHIFT 22
    #define DMA_DIRECT_DMACW_B_OUTPUT_DWORD_SWAP_MASK 0x00800000
    #define DMA_DIRECT_DMACW_B_OUTPUT_DWORD_SWAP_SHIFT 23
    #define DMA_DIRECT_DMACW_B_KEYSTORE_SRC_MASK 0x20000000
    #define DMA_DIRECT_DMACW_B_KEYSTORE_SRC_SHIFT 29
    #define DMA_DIRECT_DMACW_B_KEYSTORE_DST_MASK 0x40000000
    #define DMA_DIRECT_DMACW_B_KEYSTORE_DST_SHIFT 30
    #define DMA_DIRECT_DMACW_B_DEBUG_MODE_MASK 0x80000000
    #define DMA_DIRECT_DMACW_B_DEBUG_MODE_SHIFT 31
#define  DMA_DIRECT_LDST_A 0x0C88
    #define DMA_DIRECT_LDST_A_BASE_MASK 0xFFFFFFFF
    #define DMA_DIRECT_LDST_A_BASE_SHIFT 0
#define  DMA_DIRECT_LDST_B 0x0CA8
    #define DMA_DIRECT_LDST_B_BASE_MASK 0xFFFFFFFF
    #define DMA_DIRECT_LDST_B_BASE_SHIFT 0
#define  DMA_DIRECT_LSRC_A 0x0C80
    #define DMA_DIRECT_LSRC_A_BASE_MASK 0xFFFFFFFF
    #define DMA_DIRECT_LSRC_A_BASE_SHIFT 0
#define  DMA_DIRECT_LSRC_B 0x0CA0
    #define DMA_DIRECT_LSRC_B_BASE_MASK 0xFFFFFFFF
    #define DMA_DIRECT_LSRC_B_BASE_SHIFT 0
#define  DMA_DIRECT_UDST_A 0x0C8C
    #define DMA_DIRECT_UDST_A_BASE_MASK 0xFFFFFFFF
    #define DMA_DIRECT_UDST_A_BASE_SHIFT 0
#define  DMA_DIRECT_UDST_B 0x0CAC
    #define DMA_DIRECT_UDST_B_BASE_MASK 0xFFFFFFFF
    #define DMA_DIRECT_UDST_B_BASE_SHIFT 0
#define  DMA_DIRECT_USRC_A 0x0C84
    #define DMA_DIRECT_USRC_A_BASE_MASK 0xFFFFFFFF
    #define DMA_DIRECT_USRC_A_BASE_SHIFT 0
#define  DMA_DIRECT_USRC_B 0x0CA4
    #define DMA_DIRECT_USRC_B_BASE_MASK 0xFFFFFFFF
    #define DMA_DIRECT_USRC_B_BASE_SHIFT 0
#define  DMA_DQ_PTR0 0x0C00
    #define DMA_DQ_PTR0_ID_MASK 0x00000007
    #define DMA_DQ_PTR0_ID_SHIFT 0
    #define DMA_DQ_PTR0_BASE_MASK 0x7FFFFFF0
    #define DMA_DQ_PTR0_BASE_SHIFT 4
#define  DMA_DQ_PTR1 0x0C04
    #define DMA_DQ_PTR1_ID_MASK 0x00000007
    #define DMA_DQ_PTR1_ID_SHIFT 0
    #define DMA_DQ_PTR1_BASE_MASK 0x7FFFFFF0
    #define DMA_DQ_PTR1_BASE_SHIFT 4
#define  DMA_DUMMY_REG 0x0C7C
    #define DMA_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define DMA_DUMMY_REG_DATA_SHIFT 0
#define  DMA_HOST_INT_MASK 0x0C54
    #define DMA_HOST_INT_MASK_INT_EN_XFER_DONE0_MASK 0x00000001
    #define DMA_HOST_INT_MASK_INT_EN_XFER_DONE0_SHIFT 0
    #define DMA_HOST_INT_MASK_INT_EN_XFER_DONE1_MASK 0x00000002
    #define DMA_HOST_INT_MASK_INT_EN_XFER_DONE1_SHIFT 1
    #define DMA_HOST_INT_MASK_INT_EN_XFER_DONEA_MASK 0x00000004
    #define DMA_HOST_INT_MASK_INT_EN_XFER_DONEA_SHIFT 2
    #define DMA_HOST_INT_MASK_INT_EN_XFER_DONEB_MASK 0x00000008
    #define DMA_HOST_INT_MASK_INT_EN_XFER_DONEB_SHIFT 3
#define  DMA_HOST_INT_STATUS 0x0C50
    #define DMA_HOST_INT_STATUS_XFER_DONE0_MASK 0x00000001
    #define DMA_HOST_INT_STATUS_XFER_DONE0_SHIFT 0
    #define DMA_HOST_INT_STATUS_XFER_DONE1_MASK 0x00000002
    #define DMA_HOST_INT_STATUS_XFER_DONE1_SHIFT 1
    #define DMA_HOST_INT_STATUS_XFER_DONEA_MASK 0x00000004
    #define DMA_HOST_INT_STATUS_XFER_DONEA_SHIFT 2
    #define DMA_HOST_INT_STATUS_XFER_DONEB_MASK 0x00000008
    #define DMA_HOST_INT_STATUS_XFER_DONEB_SHIFT 3
#define  DMA_MIPS_INT_MASK 0x0C5C
    #define DMA_MIPS_INT_MASK_INT_EN_XFER_DONE0_MASK 0x00000001
    #define DMA_MIPS_INT_MASK_INT_EN_XFER_DONE0_SHIFT 0
    #define DMA_MIPS_INT_MASK_INT_EN_XFER_DONE1_MASK 0x00000002
    #define DMA_MIPS_INT_MASK_INT_EN_XFER_DONE1_SHIFT 1
    #define DMA_MIPS_INT_MASK_INT_EN_XFER_DONEA_MASK 0x00000004
    #define DMA_MIPS_INT_MASK_INT_EN_XFER_DONEA_SHIFT 2
    #define DMA_MIPS_INT_MASK_INT_EN_XFER_DONEB_MASK 0x00000008
    #define DMA_MIPS_INT_MASK_INT_EN_XFER_DONEB_SHIFT 3
#define  DMA_MIPS_INT_STATUS 0x0C58
    #define DMA_MIPS_INT_STATUS_XFER_DONE0_MASK 0x00000001
    #define DMA_MIPS_INT_STATUS_XFER_DONE0_SHIFT 0
    #define DMA_MIPS_INT_STATUS_XFER_DONE1_MASK 0x00000002
    #define DMA_MIPS_INT_STATUS_XFER_DONE1_SHIFT 1
    #define DMA_MIPS_INT_STATUS_XFER_DONEA_MASK 0x00000004
    #define DMA_MIPS_INT_STATUS_XFER_DONEA_SHIFT 2
    #define DMA_MIPS_INT_STATUS_XFER_DONEB_MASK 0x00000008
    #define DMA_MIPS_INT_STATUS_XFER_DONEB_SHIFT 3
#define  DMA_STATUS 0x0C34
    #define INDIRECT0_MASK 0x00000001
    #define INDIRECT0_SHIFT 0
    #define INDIRECT1_MASK 0x00000002
    #define INDIRECT1_SHIFT 1
    #define DIRECT_A_MASK 0x00000004
    #define DIRECT_A_SHIFT 2
    #define DIRECT_B_MASK 0x00000008
    #define DIRECT_B_SHIFT 3
    #define ERR_INDIRECT0_MASK 0x00000010
    #define ERR_INDIRECT0_SHIFT 4
    #define ERR_INDIRECT1_MASK 0x00000020
    #define ERR_INDIRECT1_SHIFT 5
    #define ERR_DIRECT_A_MASK 0x00000040
    #define ERR_DIRECT_A_SHIFT 6
    #define ERR_DIRECT_B_MASK 0x00000080
    #define ERR_DIRECT_B_SHIFT 7
    #define INDIRECT0_CURRENT_MASK 0x00000100
    #define INDIRECT0_CURRENT_SHIFT 8
    #define INDIRECT1_CURRENT_MASK 0x00000200
    #define INDIRECT1_CURRENT_SHIFT 9
    #define DIRECT_A_CURRENT_MASK 0x00000400
    #define DIRECT_A_CURRENT_SHIFT 10
    #define DIRECT_B_CURRENT_MASK 0x00000800
    #define DIRECT_B_CURRENT_SHIFT 11
#define  DMA_SYS_ACCESS 0x0CEC
    #define SYS_ADR_LOCKOUT_MASK 0x00000001
    #define SYS_ADR_LOCKOUT_SHIFT 0
#define  DMA_TS_HANDLING_A 0x0CF0
    #define DMA_TS_HANDLING_A_INSTRIDE_MASK 0x00000001
    #define DMA_TS_HANDLING_A_INSTRIDE_SHIFT 0
    #define DMA_TS_HANDLING_A_E_O_MASK 0x00000002
    #define DMA_TS_HANDLING_A_E_O_SHIFT 1
    #define DMA_TS_HANDLING_A_RESIDUAL_HANDLING_MASK 0x0000003C
    #define DMA_TS_HANDLING_A_RESIDUAL_HANDLING_SHIFT 2
    #define DMA_TS_HANDLING_A_AES_VAR_MASK 0x000000C0
    #define DMA_TS_HANDLING_A_AES_VAR_SHIFT 6
    #define DMA_TS_HANDLING_A_MSC_LENGTH_MASK 0x0000FF00
    #define DMA_TS_HANDLING_A_MSC_LENGTH_SHIFT 8
    #define DMA_TS_HANDLING_A_NSA_DATAMODE_MASK 0x00010000
    #define DMA_TS_HANDLING_A_NSA_DATAMODE_SHIFT 16
    #define DMA_TS_HANDLING_A_TRANSPORT_STREAM_MASK 0x80000000
    #define DMA_TS_HANDLING_A_TRANSPORT_STREAM_SHIFT 31
#define  DMA_TS_HANDLING_B 0x0CF4
    #define DMA_TS_HANDLING_B_INSTRIDE_MASK 0x00000001
    #define DMA_TS_HANDLING_B_INSTRIDE_SHIFT 0
    #define DMA_TS_HANDLING_B_E_O_MASK 0x00000002
    #define DMA_TS_HANDLING_B_E_O_SHIFT 1
    #define DMA_TS_HANDLING_B_RESIDUAL_HANDLING_MASK 0x0000003C
    #define DMA_TS_HANDLING_B_RESIDUAL_HANDLING_SHIFT 2
    #define DMA_TS_HANDLING_B_AES_VAR_MASK 0x000000C0
    #define DMA_TS_HANDLING_B_AES_VAR_SHIFT 6
    #define DMA_TS_HANDLING_B_MSC_LENGTH_MASK 0x0000FF00
    #define DMA_TS_HANDLING_B_MSC_LENGTH_SHIFT 8
    #define DMA_TS_HANDLING_B_NSA_DATAMODE_MASK 0x00010000
    #define DMA_TS_HANDLING_B_NSA_DATAMODE_SHIFT 16
    #define DMA_TS_HANDLING_B_TRANSPORT_STREAM_MASK 0x80000000
    #define DMA_TS_HANDLING_B_TRANSPORT_STREAM_SHIFT 31
#define  DQS_CLK_CTRL 0x74CC
    #define DQS_ECLK_GATE_EN_MASK 0x00000001
    #define DQS_ECLK_GATE_EN_SHIFT 0
    #define DQS_MCLK_GATE_EN_MASK 0x00000002
    #define DQS_MCLK_GATE_EN_SHIFT 1
    #define RFM_ECLK_GATE_EN_MASK 0x00000004
    #define RFM_ECLK_GATE_EN_SHIFT 2
    #define RFM_MCLK_GATE_EN_MASK 0x00000008
    #define RFM_MCLK_GATE_EN_SHIFT 3
    #define DQS_PASS_GATE_EN_MASK 0x00000010
    #define DQS_PASS_GATE_EN_SHIFT 4
    #define RCB_ECLK_GATE_EN_MASK 0x00000020
    #define RCB_ECLK_GATE_EN_SHIFT 5
    #define OSF_MAIN_GATE_EN_MASK 0x00000040
    #define OSF_MAIN_GATE_EN_SHIFT 6
    #define OSF_MPG4_GATE_EN_MASK 0x00000080
    #define OSF_MPG4_GATE_EN_SHIFT 7
#define  DQS_DUMMY_REG 0x72E0
    #define DQS_DUMMY_REG_DUMMY_MASK 0xFFFFFFFF
    #define DQS_DUMMY_REG_DUMMY_SHIFT 0
#define  DQS_STAT_MUX 0x7298
    #define DQS_STAT_MUX_STAT_MUX_MASK 0x0000001F
    #define DQS_STAT_MUX_STAT_MUX_SHIFT 0
#define  DQS_STAT_MUX_RB 0x7294
    #define DQS_STAT_MUX_RB_STAT_RB_MASK 0xFFFFFFFF
    #define DQS_STAT_MUX_RB_STAT_RB_SHIFT 0
#define  DSCL_BOT_CR_WR_ADR 0x5C48
    #define DSCL_BOT_CR_WR_ADR_BASE_MASK 0x7FFFE000
    #define DSCL_BOT_CR_WR_ADR_BASE_SHIFT 13
#define  DSCL_BOT_C_WR_ADR 0x5C44
    #define DSCL_BOT_C_WR_ADR_BASE_MASK 0x7FFFE000
    #define DSCL_BOT_C_WR_ADR_BASE_SHIFT 13
#define  DSCL_BOT_Y_WR_ADR 0x5C40
    #define DSCL_BOT_Y_WR_ADR_BASE_MASK 0x7FFFE000
    #define DSCL_BOT_Y_WR_ADR_BASE_SHIFT 13
#define  DSCL_CR_RD_ADR 0x5C3C
    #define DSCL_CR_RD_ADR_BASE_MASK 0x7FFFE000
    #define DSCL_CR_RD_ADR_BASE_SHIFT 13
#define  DSCL_CR_WR_ADR 0x5C38
    #define DSCL_CR_WR_ADR_BASE_MASK 0x7FFFE000
    #define DSCL_CR_WR_ADR_BASE_SHIFT 13
#define  DSCL_C_RD_ADR 0x5C34
    #define DSCL_C_RD_ADR_BASE_MASK 0x7FFFE000
    #define DSCL_C_RD_ADR_BASE_SHIFT 13
#define  DSCL_C_WR_ADR 0x5C2C
    #define DSCL_C_WR_ADR_BASE_MASK 0x7FFFE000
    #define DSCL_C_WR_ADR_BASE_SHIFT 13
#define  DSCL_DUMMY_REG 0x5CF0
    #define DSCL_DUMMY_REG_DUMMY_MASK 0x00000001
    #define DSCL_DUMMY_REG_DUMMY_SHIFT 0
#define  DSCL_HORI_CTRL 0x5C20
    #define DSCL_HORI_CTRL_SCALE_EN_MASK 0x00000001
    #define DSCL_HORI_CTRL_SCALE_EN_SHIFT 0
    #define DSCL_HORI_CTRL_UCODE_VCNT_MASK 0x0000007E
    #define DSCL_HORI_CTRL_UCODE_VCNT_SHIFT 1
    #define DSCL_HORI_CTRL_INV_DIV_MASK 0xFFFF0000
    #define DSCL_HORI_CTRL_INV_DIV_SHIFT 16
#define  DSCL_HORI_UCODE 0x5C04
    #define DSCL_HORI_UCODE_HORI0_UCODE_MASK 0x000000FF
    #define DSCL_HORI_UCODE_HORI0_UCODE_SHIFT 0
    #define DSCL_HORI_UCODE_HORI1_UCODE_MASK 0x0000FF00
    #define DSCL_HORI_UCODE_HORI1_UCODE_SHIFT 8
    #define DSCL_HORI_UCODE_HORI2_UCODE_MASK 0x00FF0000
    #define DSCL_HORI_UCODE_HORI2_UCODE_SHIFT 16
    #define DSCL_HORI_UCODE_HORI3_UCODE_MASK 0xFF000000
    #define DSCL_HORI_UCODE_HORI3_UCODE_SHIFT 24
#define  DSCL_INT 0x5C54
    #define DSCL_INTERRUPT_MASK 0x00000001
    #define DSCL_INTERRUPT_SHIFT 0
#define  DSCL_INT_CTRL 0x5C58
    #define DSCL_INT_MIPS_EN_MASK 0x00000001
    #define DSCL_INT_MIPS_EN_SHIFT 0
    #define DSCL_INT_HOST_EN_MASK 0x00000002
    #define DSCL_INT_HOST_EN_SHIFT 1
#define  DSCL_MARB_CTRL 0x5C64
    #define DSCL_MARB_CTRL_MEM_CNT_RESET_MASK 0x00000001
    #define DSCL_MARB_CTRL_MEM_CNT_RESET_SHIFT 0
    #define DSCL_MARB_CTRL_MEM_CNT_EN_MASK 0x00000002
    #define DSCL_MARB_CTRL_MEM_CNT_EN_SHIFT 1
    #define DSCL_MARB_CTRL_MEM_CNT_SEL_MASK 0x00000004
    #define DSCL_MARB_CTRL_MEM_CNT_SEL_SHIFT 2
    #define DSCL_MARB_CTRL_READ_ACCEL_MASK 0x00000100
    #define DSCL_MARB_CTRL_READ_ACCEL_SHIFT 8
    #define DSCL_MARB_CTRL_PF_ARB_MASK 0x00000200
    #define DSCL_MARB_CTRL_PF_ARB_SHIFT 9
    #define DSCL_MARB_CTRL_MEM_DENSITY_MASK 0x00000C00
    #define DSCL_MARB_CTRL_MEM_DENSITY_SHIFT 10
#define  DSCL_MEM_CNT 0x5C68
    #define DSCL_MEM_CNT_MEM_CNT_MASK 0x00FFFFFF
    #define DSCL_MEM_CNT_MEM_CNT_SHIFT 0
#define  DSCL_PICT_RD_SIZE 0x5C14
    #define DSCL_PICT_RD_SIZE_SLICE_RD_SIZE_MASK 0x0000007F
    #define DSCL_PICT_RD_SIZE_SLICE_RD_SIZE_SHIFT 0
    #define DSCL_PICT_RD_SIZE_SLICE_RD_CNT_MASK 0x00007F00
    #define DSCL_PICT_RD_SIZE_SLICE_RD_CNT_SHIFT 8
#define  DSCL_PICT_WR_SIZE 0x5C18
    #define DSCL_PICT_WR_SIZE_SLICE_WR_SIZE_MASK 0x0000007F
    #define DSCL_PICT_WR_SIZE_SLICE_WR_SIZE_SHIFT 0
    #define DSCL_PICT_WR_SIZE_SLICE_WR_CNT_MASK 0x00007F00
    #define DSCL_PICT_WR_SIZE_SLICE_WR_CNT_SHIFT 8
#define  DSCL_SURF_RD_SIZE 0x5C50
    #define DSCL_RD_PITCH_MASK 0x00000FC0
    #define DSCL_RD_PITCH_SHIFT 6
#define  DSCL_SURF_WR_SIZE 0x5C1C
    #define DSCL_WR_PITCH_MASK 0x00000FC0
    #define DSCL_WR_PITCH_SHIFT 6
#define  DSCL_TRIG 0x5C10
    #define DSCL_TRIG_COLBITS_OVERRIDE_MASK 0x00000001
    #define DSCL_TRIG_COLBITS_OVERRIDE_SHIFT 0
    #define DSCL_TRIG_COLBITS_RD_VALUE_MASK 0x000000F0
    #define DSCL_TRIG_COLBITS_RD_VALUE_SHIFT 4
    #define DSCL_TRIG_COLBITS_WR_VALUE_MASK 0x00000F00
    #define DSCL_TRIG_COLBITS_WR_VALUE_SHIFT 8
    #define DSCL_TRIG_FORCE_RD_ONLY_MASK 0x00010000
    #define DSCL_TRIG_FORCE_RD_ONLY_SHIFT 16
    #define DSCL_TRIG_FIELD_SCALE_MASK 0x00100000
    #define DSCL_TRIG_FIELD_SCALE_SHIFT 20
    #define DSCL_TRIG_RD_8X8_MASK 0x00800000
    #define DSCL_TRIG_RD_8X8_SHIFT 23
    #define DSCL_TRIG_RD_LINEAR_MASK 0x01000000
    #define DSCL_TRIG_RD_LINEAR_SHIFT 24
    #define DSCL_TRIG_WR_LINEAR_MASK 0x02000000
    #define DSCL_TRIG_WR_LINEAR_SHIFT 25
    #define DSCL_TRIG_SCL_EN_MASK 0x10000000
    #define DSCL_TRIG_SCL_EN_SHIFT 28
    #define DSCL_TRIG_SKIP_FLD_EN_MASK 0x40000000
    #define DSCL_TRIG_SKIP_FLD_EN_SHIFT 30
    #define DSCL_TRIG_FLD_SEL_MASK 0x80000000
    #define DSCL_TRIG_FLD_SEL_SHIFT 31
#define  DSCL_UCODE_IDX 0x5C00
    #define DSCL_UCODE_IDX_HORI_IDX_MASK 0x0000000F
    #define DSCL_UCODE_IDX_HORI_IDX_SHIFT 0
    #define DSCL_UCODE_IDX_VERT_IDX_MASK 0x000F0000
    #define DSCL_UCODE_IDX_VERT_IDX_SHIFT 16
    #define DSCL_UCODE_IDX_VERT_BOT_IDX_MASK 0x00F00000
    #define DSCL_UCODE_IDX_VERT_BOT_IDX_SHIFT 20
#define  DSCL_VAR_ADR 0x5C60
    #define DSCL_VAR_ADR_BASE_MASK 0x7FFFFFC0
    #define DSCL_VAR_ADR_BASE_SHIFT 6
#define  DSCL_VAR_CTRL 0x5C5C
    #define DSCL_VAR_EN_MASK 0x00000001
    #define DSCL_VAR_EN_SHIFT 0
    #define DSCL_VAR_FLD_DIS_MASK 0x00000002
    #define DSCL_VAR_FLD_DIS_SHIFT 1
#define  DSCL_VERT_BOT_CTRL 0x5C4C
    #define DSCL_VERT_BOT_CTRL_SCALE_EN_MASK 0x00000001
    #define DSCL_VERT_BOT_CTRL_SCALE_EN_SHIFT 0
    #define DSCL_VERT_BOT_CTRL_UCODE_VCNT_MASK 0x0000007E
    #define DSCL_VERT_BOT_CTRL_UCODE_VCNT_SHIFT 1
    #define DSCL_VERT_BOT_CTRL_INV_DIV_MASK 0xFFFF0000
    #define DSCL_VERT_BOT_CTRL_INV_DIV_SHIFT 16
#define  DSCL_VERT_BOT_UCODE 0x5C0C
    #define DSCL_VERT_BOT_UCODE_VERT0_BOT_UCODE_MASK 0x000000FF
    #define DSCL_VERT_BOT_UCODE_VERT0_BOT_UCODE_SHIFT 0
    #define DSCL_VERT_BOT_UCODE_VERT1_BOT_UCODE_MASK 0x0000FF00
    #define DSCL_VERT_BOT_UCODE_VERT1_BOT_UCODE_SHIFT 8
    #define DSCL_VERT_BOT_UCODE_VERT2_BOT_UCODE_MASK 0x00FF0000
    #define DSCL_VERT_BOT_UCODE_VERT2_BOT_UCODE_SHIFT 16
    #define DSCL_VERT_BOT_UCODE_VERT3_BOT_UCODE_MASK 0xFF000000
    #define DSCL_VERT_BOT_UCODE_VERT3_BOT_UCODE_SHIFT 24
#define  DSCL_VERT_CTRL 0x5C24
    #define DSCL_VERT_CTRL_SCALE_EN_MASK 0x00000001
    #define DSCL_VERT_CTRL_SCALE_EN_SHIFT 0
    #define DSCL_VERT_CTRL_UCODE_VCNT_MASK 0x0000007E
    #define DSCL_VERT_CTRL_UCODE_VCNT_SHIFT 1
    #define DSCL_VERT_CTRL_INV_DIV_MASK 0xFFFF0000
    #define DSCL_VERT_CTRL_INV_DIV_SHIFT 16
#define  DSCL_VERT_UCODE 0x5C08
    #define DSCL_VERT_UCODE_VERT0_UCODE_MASK 0x000000FF
    #define DSCL_VERT_UCODE_VERT0_UCODE_SHIFT 0
    #define DSCL_VERT_UCODE_VERT1_UCODE_MASK 0x0000FF00
    #define DSCL_VERT_UCODE_VERT1_UCODE_SHIFT 8
    #define DSCL_VERT_UCODE_VERT2_UCODE_MASK 0x00FF0000
    #define DSCL_VERT_UCODE_VERT2_UCODE_SHIFT 16
    #define DSCL_VERT_UCODE_VERT3_UCODE_MASK 0xFF000000
    #define DSCL_VERT_UCODE_VERT3_UCODE_SHIFT 24
#define  DSCL_Y_RD_ADR 0x5C30
    #define DSCL_Y_RD_ADR_BASE_MASK 0x7FFFE000
    #define DSCL_Y_RD_ADR_BASE_SHIFT 13
#define  DSCL_Y_WR_ADR 0x5C28
    #define DSCL_Y_WR_ADR_BASE_MASK 0x7FFFE000
    #define DSCL_Y_WR_ADR_BASE_SHIFT 13
#define  DVE1_ACTIVE_X 0x4444
    #define DVE1_ACTIVE_X_START_MASK 0x00001FFF
    #define DVE1_ACTIVE_X_START_SHIFT 0
    #define DVE1_ACTIVE_X_END_MASK 0x1FFF0000
    #define DVE1_ACTIVE_X_END_SHIFT 16
#define  DVE1_AV_X 0x4450
    #define DVE1_AV_X_EAV_START_MASK 0x00001FFF
    #define DVE1_AV_X_EAV_START_SHIFT 0
    #define DVE1_AV_X_SAV_START_MASK 0x1FFF0000
    #define DVE1_AV_X_SAV_START_SHIFT 16
#define  DVE1_BOT_ACTIVE_Y 0x4438
    #define DVE1_BOT_ACTIVE_Y_START_MASK 0x00000FFF
    #define DVE1_BOT_ACTIVE_Y_START_SHIFT 0
    #define DVE1_BOT_ACTIVE_Y_END_MASK 0x0FFF0000
    #define DVE1_BOT_ACTIVE_Y_END_SHIFT 16
#define  DVE1_BOT_DE_X 0x447C
    #define DVE1_BOT_DE_X_START_MASK 0x00001FFF
    #define DVE1_BOT_DE_X_START_SHIFT 0
    #define DVE1_BOT_DE_X_END_MASK 0x1FFF0000
    #define DVE1_BOT_DE_X_END_SHIFT 16
#define  DVE1_BOT_DE_Y 0x4474
    #define DVE1_BOT_DE_Y_START_MASK 0x00000FFF
    #define DVE1_BOT_DE_Y_START_SHIFT 0
    #define DVE1_BOT_DE_Y_END_MASK 0x0FFF0000
    #define DVE1_BOT_DE_Y_END_SHIFT 16
#define  DVE1_BOT_VBI_Y 0x4430
    #define DVE1_BOT_VBI_Y_START_MASK 0x00000FFF
    #define DVE1_BOT_VBI_Y_START_SHIFT 0
    #define DVE1_BOT_VBI_Y_END_MASK 0x0FFF0000
    #define DVE1_BOT_VBI_Y_END_SHIFT 16
#define  DVE1_BOT_VIDEO_Y 0x4440
    #define DVE1_BOT_VIDEO_Y_START_MASK 0x00000FFF
    #define DVE1_BOT_VIDEO_Y_START_SHIFT 0
    #define DVE1_BOT_VIDEO_Y_END_MASK 0x0FFF0000
    #define DVE1_BOT_VIDEO_Y_END_SHIFT 16
#define  DVE1_BOT_VSYNC_X 0x4460
    #define DVE1_BOT_VSYNC_X_START_MASK 0x00001FFF
    #define DVE1_BOT_VSYNC_X_START_SHIFT 0
    #define DVE1_BOT_VSYNC_X_END_MASK 0x1FFF0000
    #define DVE1_BOT_VSYNC_X_END_SHIFT 16
#define  DVE1_BOT_VSYNC_Y 0x4458
    #define DVE1_BOT_VSYNC_Y_START_MASK 0x00000FFF
    #define DVE1_BOT_VSYNC_Y_START_SHIFT 0
    #define DVE1_BOT_VSYNC_Y_END_MASK 0x0FFF0000
    #define DVE1_BOT_VSYNC_Y_END_SHIFT 16
#define  DVE1_BUF_STATUS 0x4504
    #define DVE1_BUF_STATUS_CB_FREE_ENTRIES_MASK 0x000000FF
    #define DVE1_BUF_STATUS_CB_FREE_ENTRIES_SHIFT 0
    #define DVE1_BUF_STATUS_CR_FREE_ENTRIES_MASK 0x0000FF00
    #define DVE1_BUF_STATUS_CR_FREE_ENTRIES_SHIFT 8
    #define DVE1_BUF_STATUS_YVBI_FREE_ENTRIES_MASK 0x01FF0000
    #define DVE1_BUF_STATUS_YVBI_FREE_ENTRIES_SHIFT 16
#define  DVE1_CB_ADR 0x44BC
    #define DVE1_CB_ADR_BASE_MASK 0x0FFFFFC0
    #define DVE1_CB_ADR_BASE_SHIFT 6
#define  DVE1_CHROMA_LIMIT 0x44EC
    #define DVE1_CHROMA_LIMIT_UPPER_THRES_MASK 0x000003FF
    #define DVE1_CHROMA_LIMIT_UPPER_THRES_SHIFT 0
    #define DVE1_CHROMA_LIMIT_LOWER_THRES_MASK 0x03FF0000
    #define DVE1_CHROMA_LIMIT_LOWER_THRES_SHIFT 16
#define  DVE1_CMD_FIFO 0x4418
    #define DVE1_CMD_FIFO_TOP_IDX_MASK 0x0000003F
    #define DVE1_CMD_FIFO_TOP_IDX_SHIFT 0
    #define DVE1_CMD_FIFO_FLD_SEL_MASK 0x000000C0
    #define DVE1_CMD_FIFO_FLD_SEL_SHIFT 6
    #define DVE1_CMD_FIFO_BOT_IDX_MASK 0x00003F00
    #define DVE1_CMD_FIFO_BOT_IDX_SHIFT 8
    #define DVE1_CMD_FIFO_VBI_FLD_SEL_MASK 0x0000C000
    #define DVE1_CMD_FIFO_VBI_FLD_SEL_SHIFT 14
    #define DVE1_CMD_FIFO_VBI_TOP_IDX_MASK 0x007F0000
    #define DVE1_CMD_FIFO_VBI_TOP_IDX_SHIFT 16
    #define DVE1_CMD_FIFO_BLEND_MASK 0x00800000
    #define DVE1_CMD_FIFO_BLEND_SHIFT 23
    #define DVE1_CMD_FIFO_VBI_BOT_IDX_MASK 0x7F000000
    #define DVE1_CMD_FIFO_VBI_BOT_IDX_SHIFT 24
    #define DVE1_CMD_FIFO_UPDATE_MASK 0x80000000
    #define DVE1_CMD_FIFO_UPDATE_SHIFT 31
#define  DVE1_CR_ADR 0x44C0
    #define DVE1_CR_ADR_BASE_MASK 0x0FFFFFC0
    #define DVE1_CR_ADR_BASE_SHIFT 6
#define  DVE1_CTRL 0x4410
    #define DVE1_CTRL_INPUT_BIT_SIZE_MASK 0x00000001
    #define DVE1_CTRL_INPUT_BIT_SIZE_SHIFT 0
    #define DVE1_CTRL_INPUT_422_MASK 0x00000002
    #define DVE1_CTRL_INPUT_422_SHIFT 1
    #define DVE1_CTRL_MEM_FORMAT_MASK 0x0000000C
    #define DVE1_CTRL_MEM_FORMAT_SHIFT 2
    #define DVE1_CTRL_EXTEND_8BIT_MASK 0x00000010
    #define DVE1_CTRL_EXTEND_8BIT_SHIFT 4
    #define DVE1_CTRL_OUTPUT_BIT_SIZE_MASK 0x00000020
    #define DVE1_CTRL_OUTPUT_BIT_SIZE_SHIFT 5
    #define DVE1_CTRL_OUT_CLK_EDGE_MASK 0x00000040
    #define DVE1_CTRL_OUT_CLK_EDGE_SHIFT 6
    #define DVE1_CTRL_DUPLICATE_CODE_MASK 0x00000080
    #define DVE1_CTRL_DUPLICATE_CODE_SHIFT 7
    #define DVE1_CTRL_OUTPUT_TYPE_MASK 0x00000300
    #define DVE1_CTRL_OUTPUT_TYPE_SHIFT 8
    #define DVE1_CTRL_EMPTY_FIFO_MODE_MASK 0x00000C00
    #define DVE1_CTRL_EMPTY_FIFO_MODE_SHIFT 10
    #define DVE1_CTRL_FIELD_POLARITY_MASK 0x00001000
    #define DVE1_CTRL_FIELD_POLARITY_SHIFT 12
    #define DVE1_CTRL_VSYNC_POLARITY_MASK 0x00002000
    #define DVE1_CTRL_VSYNC_POLARITY_SHIFT 13
    #define DVE1_CTRL_HSYNC_POLARITY_MASK 0x00004000
    #define DVE1_CTRL_HSYNC_POLARITY_SHIFT 14
    #define DVE1_CTRL_DE_POLARITY_MASK 0x00008000
    #define DVE1_CTRL_DE_POLARITY_SHIFT 15
    #define DVE1_CTRL_HS_BANK_MASK 0x00010000
    #define DVE1_CTRL_HS_BANK_SHIFT 16
    #define DVE1_CTRL_COL_CONV_EN_MASK 0x00020000
    #define DVE1_CTRL_COL_CONV_EN_SHIFT 17
    #define DVE1_CTRL_COL_CONV_SEL_MASK 0x000C0000
    #define DVE1_CTRL_COL_CONV_SEL_SHIFT 18
    #define DVE1_CTRL_EXT_SYNC_MODE_MASK 0x00100000
    #define DVE1_CTRL_EXT_SYNC_MODE_SHIFT 20
    #define DVE1_CTRL_AV_VSYNC_POLARITY_MASK 0x01000000
    #define DVE1_CTRL_AV_VSYNC_POLARITY_SHIFT 24
    #define DVE1_CTRL_AV_FIELD_POLARITY_MASK 0x02000000
    #define DVE1_CTRL_AV_FIELD_POLARITY_SHIFT 25
    #define DVE1_CTRL_PROG_TO_INTLCD_MODE_MASK 0x04000000
    #define DVE1_CTRL_PROG_TO_INTLCD_MODE_SHIFT 26
    #define DVE1_CTRL_MEM_PACKED_MASK 0x10000000
    #define DVE1_CTRL_MEM_PACKED_SHIFT 28
#define  DVE1_CURR_CMD 0x4424
    #define DVE1_CURR_CMD_TOP_IDX_MASK 0x0000003F
    #define DVE1_CURR_CMD_TOP_IDX_SHIFT 0
    #define DVE1_CURR_CMD_FLD_SEL_MASK 0x000000C0
    #define DVE1_CURR_CMD_FLD_SEL_SHIFT 6
    #define DVE1_CURR_CMD_BOT_IDX_MASK 0x00003F00
    #define DVE1_CURR_CMD_BOT_IDX_SHIFT 8
    #define DVE1_CURR_CMD_VBI_FLD_SEL_MASK 0x0000C000
    #define DVE1_CURR_CMD_VBI_FLD_SEL_SHIFT 14
    #define DVE1_CURR_CMD_VBI_TOP_IDX_MASK 0x007F0000
    #define DVE1_CURR_CMD_VBI_TOP_IDX_SHIFT 16
    #define DVE1_CURR_CMD_BLEND_MASK 0x00800000
    #define DVE1_CURR_CMD_BLEND_SHIFT 23
    #define DVE1_CURR_CMD_VBI_BOT_IDX_MASK 0x7F000000
    #define DVE1_CURR_CMD_VBI_BOT_IDX_SHIFT 24
    #define DVE1_CURR_CMD_UPDATE_MASK 0x80000000
    #define DVE1_CURR_CMD_UPDATE_SHIFT 31
#define  DVE1_C_ADR 0x44AC
    #define DVE1_C_ADR_BASE_MASK 0x0FFFFFC0
    #define DVE1_C_ADR_BASE_SHIFT 6
#define  DVE1_DEFAULT_CHROMA 0x4494
    #define DVE1_DEFAULT_CHROMA_CB_VAL_MASK 0x000003FF
    #define DVE1_DEFAULT_CHROMA_CB_VAL_SHIFT 0
    #define DVE1_DEFAULT_CHROMA_CR_VAL_MASK 0x03FF0000
    #define DVE1_DEFAULT_CHROMA_CR_VAL_SHIFT 16
#define  DVE1_DEFAULT_LUMA 0x4490
    #define DVE1_DEFAULT_LUMA_Y_VAL_MASK 0x000003FF
    #define DVE1_DEFAULT_LUMA_Y_VAL_SHIFT 0
#define  DVE1_DEN 0x4524
    #define DVE1_DEN_DEN_MASK 0xFFFFFFFF
    #define DVE1_DEN_DEN_SHIFT 0
#define  DVE1_DUMMY_REG 0x4500
    #define DVE1_DUMMY_REG_DUMMY_BITS_MASK 0xFFFFFFFF
    #define DVE1_DUMMY_REG_DUMMY_BITS_SHIFT 0
#define  DVE1_FIELD_X 0x446C
    #define DVE1_FIELD_X_FO_START_MASK 0x00001FFF
    #define DVE1_FIELD_X_FO_START_SHIFT 0
    #define DVE1_FIELD_X_FE_START_MASK 0x1FFF0000
    #define DVE1_FIELD_X_FE_START_SHIFT 16
#define  DVE1_FIELD_Y 0x4468
    #define DVE1_FIELD_Y_FO_START_MASK 0x00000FFF
    #define DVE1_FIELD_Y_FO_START_SHIFT 0
    #define DVE1_FIELD_Y_FE_START_MASK 0x0FFF0000
    #define DVE1_FIELD_Y_FE_START_SHIFT 16
#define  DVE1_FIFO_STATUS 0x441C
    #define DVE1_FIFO_STATUS_FREE_ENTRIES_MASK 0x0000001F
    #define DVE1_FIFO_STATUS_FREE_ENTRIES_SHIFT 0
    #define DVE1_FIFO_STATUS_CURR_IDX_MASK 0x00000F00
    #define DVE1_FIFO_STATUS_CURR_IDX_SHIFT 8
    #define DVE1_FIFO_STATUS_FRM_CNT_MASK 0x000FF000
    #define DVE1_FIFO_STATUS_FRM_CNT_SHIFT 12
#define  DVE1_FRAME_SIZE 0x4428
    #define DVE1_FRAME_SIZE_H_TOTAL_MASK 0x00001FFF
    #define DVE1_FRAME_SIZE_H_TOTAL_SHIFT 0
    #define DVE1_FRAME_SIZE_V_TOTAL_MASK 0x0FFF0000
    #define DVE1_FRAME_SIZE_V_TOTAL_SHIFT 16
#define  DVE1_GENLOCK_LOWER 0x452C
    #define DVE1_GENLOCK_LOWER_GENLOCK_L_MASK 0xFFFFFFFF
    #define DVE1_GENLOCK_LOWER_GENLOCK_L_SHIFT 0
#define  DVE1_GENLOCK_PCR_LOWER 0x44FC
    #define DVE1_GENLOCK_PCR_LOWER_GENLOCK_PCR_L_MASK 0xFFFFFFFF
    #define DVE1_GENLOCK_PCR_LOWER_GENLOCK_PCR_L_SHIFT 0
#define  DVE1_GENLOCK_PCR_UPPER 0x44F8
    #define DVE1_GENLOCK_PCR_UPPER_GENLOCK_PCR_U_MASK 0x000003FF
    #define DVE1_GENLOCK_PCR_UPPER_GENLOCK_PCR_U_SHIFT 0
#define  DVE1_GENLOCK_UPPER 0x4528
    #define DVE1_GENLOCK_UPPER_GENLOCK_U_MASK 0x000003FF
    #define DVE1_GENLOCK_UPPER_GENLOCK_U_SHIFT 0
#define  DVE1_HBLANK_CHROMA 0x4484
    #define DVE1_HBLANK_CHROMA_CB_VAL_MASK 0x000003FF
    #define DVE1_HBLANK_CHROMA_CB_VAL_SHIFT 0
    #define DVE1_HBLANK_CHROMA_CR_VAL_MASK 0x03FF0000
    #define DVE1_HBLANK_CHROMA_CR_VAL_SHIFT 16
#define  DVE1_HBLANK_LUMA 0x4480
    #define DVE1_HBLANK_LUMA_Y_VAL_MASK 0x000003FF
    #define DVE1_HBLANK_LUMA_Y_VAL_SHIFT 0
#define  DVE1_HOST_INT_MASK 0x4408
    #define DVE1_HOST_INT_MASK_MASK 0x00000001
    #define DVE1_HOST_INT_MASK_SHIFT 0
#define  DVE1_HSCAL_CHROMA_CTRL 0x44DC
    #define DVE1_HSCAL_CHROMA_CTRL_PHASES_MASK 0x0000001F
    #define DVE1_HSCAL_CHROMA_CTRL_PHASES_SHIFT 0
    #define DVE1_HSCAL_CHROMA_CTRL_SRC_RES_MASK 0x00007F00
    #define DVE1_HSCAL_CHROMA_CTRL_SRC_RES_SHIFT 8
    #define DVE1_HSCAL_CHROMA_CTRL_DST_RES_MASK 0x007F0000
    #define DVE1_HSCAL_CHROMA_CTRL_DST_RES_SHIFT 16
    #define DVE1_HSCAL_CHROMA_CTRL_IDX_SHIFT_MASK 0x03000000
    #define DVE1_HSCAL_CHROMA_CTRL_IDX_SHIFT_SHIFT 24
#define  DVE1_HSCAL_CHROMA_DATA 0x44E4
    #define DVE1_HSCAL_CHROMA_DATA_COEF_MASK 0xFFFFFFFF
    #define DVE1_HSCAL_CHROMA_DATA_COEF_SHIFT 0
#define  DVE1_HSCAL_CHROMA_IDX 0x44E0
    #define DVE1_HSCAL_CHROMA_IDX_FLD_MASK 0x00000003
    #define DVE1_HSCAL_CHROMA_IDX_FLD_SHIFT 0
    #define DVE1_HSCAL_CHROMA_IDX_ADR_MASK 0x000000F0
    #define DVE1_HSCAL_CHROMA_IDX_ADR_SHIFT 4
    #define DVE1_HSCAL_CHROMA_IDX_BANK_MASK 0x00000100
    #define DVE1_HSCAL_CHROMA_IDX_BANK_SHIFT 8
#define  DVE1_HSCAL_LUMA_CTRL 0x44D0
    #define DVE1_HSCAL_LUMA_CTRL_PHASES_MASK 0x0000001F
    #define DVE1_HSCAL_LUMA_CTRL_PHASES_SHIFT 0
    #define DVE1_HSCAL_LUMA_CTRL_SRC_RES_MASK 0x00007F00
    #define DVE1_HSCAL_LUMA_CTRL_SRC_RES_SHIFT 8
    #define DVE1_HSCAL_LUMA_CTRL_DST_RES_MASK 0x007F0000
    #define DVE1_HSCAL_LUMA_CTRL_DST_RES_SHIFT 16
    #define DVE1_HSCAL_LUMA_CTRL_IDX_SHIFT_MASK 0x03000000
    #define DVE1_HSCAL_LUMA_CTRL_IDX_SHIFT_SHIFT 24
#define  DVE1_HSCAL_LUMA_DATA 0x44D8
    #define DVE1_HSCAL_LUMA_DATA_COEF_MASK 0xFFFFFFFF
    #define DVE1_HSCAL_LUMA_DATA_COEF_SHIFT 0
#define  DVE1_HSCAL_LUMA_IDX 0x44D4
    #define DVE1_HSCAL_LUMA_IDX_FLD_MASK 0x00000003
    #define DVE1_HSCAL_LUMA_IDX_FLD_SHIFT 0
    #define DVE1_HSCAL_LUMA_IDX_ADR_MASK 0x000000F0
    #define DVE1_HSCAL_LUMA_IDX_ADR_SHIFT 4
    #define DVE1_HSCAL_LUMA_IDX_BANK_MASK 0x00000100
    #define DVE1_HSCAL_LUMA_IDX_BANK_SHIFT 8
#define  DVE1_HSYNC_X 0x4464
    #define DVE1_HSYNC_X_START_MASK 0x00001FFF
    #define DVE1_HSYNC_X_START_SHIFT 0
    #define DVE1_HSYNC_X_END_MASK 0x1FFF0000
    #define DVE1_HSYNC_X_END_SHIFT 16
#define  DVE1_INT_CTRL 0x4400
    #define DVE1_INT_EN_MASK 0x000000FF
    #define DVE1_INT_EN_SHIFT 0
#define  DVE1_INT_STATUS 0x4404
    #define DVE1_INT_MASK 0x00000001
    #define DVE1_INT_SHIFT 0
    #define DVE1_INT_STATUS_FRM_CNT_RST_MASK 0x00000010
    #define DVE1_INT_STATUS_FRM_CNT_RST_SHIFT 4
#define  DVE1_LUMA_LIMIT 0x44E8
    #define DVE1_LUMA_LIMIT_UPPER_THRES_MASK 0x000003FF
    #define DVE1_LUMA_LIMIT_UPPER_THRES_SHIFT 0
    #define DVE1_LUMA_LIMIT_LOWER_THRES_MASK 0x03FF0000
    #define DVE1_LUMA_LIMIT_LOWER_THRES_SHIFT 16
#define  DVE1_MC_ARB 0x4544
    #define DVE1_MC_ARB_REQ_CNT_LIMIT_MASK 0x0000000F
    #define DVE1_MC_ARB_REQ_CNT_LIMIT_SHIFT 0
#define  DVE1_MIPS_INT_MASK 0x440C
    #define DVE1_MIPS_INT_MASK_MASK 0x00000001
    #define DVE1_MIPS_INT_MASK_SHIFT 0
#define  DVE1_NUM 0x4520
    #define DVE1_NUM_NUM_MASK 0xFFFFFFFF
    #define DVE1_NUM_NUM_SHIFT 0
#define  DVE1_OUTPUT_CLK_CTRL 0x4530
    #define DVE1_OUTPUT_CLK_CTRL_DDR_MODE_MASK 0x00000001
    #define DVE1_OUTPUT_CLK_CTRL_DDR_MODE_SHIFT 0
    #define DVE1_OUTPUT_CLK_CTRL_DDR_CLK_POLARITY_MASK 0x00000010
    #define DVE1_OUTPUT_CLK_CTRL_DDR_CLK_POLARITY_SHIFT 4
    #define DVE1_OUTPUT_CLK_CTRL_STOP_OUT_CLK_MASK 0x80000000
    #define DVE1_OUTPUT_CLK_CTRL_STOP_OUT_CLK_SHIFT 31
#define  DVE1_OUTPUT_SEL 0x4540
    #define DVE1_OUTPUT_SEL_VODATA_9_0_SEL_MASK 0x00000003
    #define DVE1_OUTPUT_SEL_VODATA_9_0_SEL_SHIFT 0
    #define DVE1_OUTPUT_SEL_VODATA_19_10_SEL_MASK 0x00000300
    #define DVE1_OUTPUT_SEL_VODATA_19_10_SEL_SHIFT 8
    #define DVE1_OUTPUT_SEL_VODATA_29_20_SEL_MASK 0x00030000
    #define DVE1_OUTPUT_SEL_VODATA_29_20_SEL_SHIFT 16
#define  DVE1_OUT_STATUS 0x4420
    #define DVE1_OUT_STATUS_X_COORD_MASK 0x00001FFF
    #define DVE1_OUT_STATUS_X_COORD_SHIFT 0
    #define DVE1_OUT_STATUS_Y_COORD_MASK 0x01FFE000
    #define DVE1_OUT_STATUS_Y_COORD_SHIFT 13
    #define DVE1_OUT_STATUS_FRM_STATE_MASK 0xFE000000
    #define DVE1_OUT_STATUS_FRM_STATE_SHIFT 25
#define  DVE1_PACKED_ORDER 0x4414
    #define DVE1_PACKED_ORDER_Y_BYTE_SEL_MASK 0x00000003
    #define DVE1_PACKED_ORDER_Y_BYTE_SEL_SHIFT 0
    #define DVE1_PACKED_ORDER_CB_BYTE_SEL_MASK 0x00000030
    #define DVE1_PACKED_ORDER_CB_BYTE_SEL_SHIFT 4
    #define DVE1_PACKED_ORDER_CR_BYTE_SEL_MASK 0x00000300
    #define DVE1_PACKED_ORDER_CR_BYTE_SEL_SHIFT 8
    #define AL_BYTE_SEL_MASK 0x00003000
    #define AL_BYTE_SEL_SHIFT 12
#define  DVE1_PCR_DEN 0x44F4
    #define DVE1_PCR_DEN_DEN_MASK 0x0000FFFF
    #define DVE1_PCR_DEN_DEN_SHIFT 0
#define  DVE1_PCR_NUM 0x44F0
    #define DVE1_PCR_NUM_NUM_MASK 0x0000FFFF
    #define DVE1_PCR_NUM_NUM_SHIFT 0
#define  DVE1_PLANAR_BUF 0x4498
    #define DVE1_PLANAR_BUF_PITCH_MASK 0x00001FE0
    #define DVE1_PLANAR_BUF_PITCH_SHIFT 5
    #define DVE1_PLANAR_BUF_SIZE_MASK 0x7FFF0000
    #define DVE1_PLANAR_BUF_SIZE_SHIFT 16
#define  DVE1_PLANAR_SAMPLES 0x449C
    #define DVE1_PLANAR_SAMPLES_WIDTH_MASK 0x00000FFF
    #define DVE1_PLANAR_SAMPLES_WIDTH_SHIFT 0
#define  DVE1_REQ_STATUS 0x4508
    #define DVE1_REQ_STATUS_C_REQ_WAIT_MASK 0x00000001
    #define DVE1_REQ_STATUS_C_REQ_WAIT_SHIFT 0
    #define DVE1_REQ_STATUS_Y_REQ_WAIT_MASK 0x00000010
    #define DVE1_REQ_STATUS_Y_REQ_WAIT_SHIFT 4
    #define DVE1_REQ_STATUS_VBI_REQ_WAIT_MASK 0x00000100
    #define DVE1_REQ_STATUS_VBI_REQ_WAIT_SHIFT 8
    #define DVE1_REQ_STATUS_MEM_RCLI_RDY_MASK 0x00001000
    #define DVE1_REQ_STATUS_MEM_RCLI_RDY_SHIFT 12
#define  DVE1_TILED_BUF 0x44A0
    #define DVE1_TILED_BUF_PITCH_MASK 0x00000FF0
    #define DVE1_TILED_BUF_PITCH_SHIFT 4
    #define DVE1_TILED_BUF_SIZE_Y_MASK 0x001FF000
    #define DVE1_TILED_BUF_SIZE_Y_SHIFT 12
    #define DVE1_TILED_BUF_SIZE_C_MASK 0xFF000000
    #define DVE1_TILED_BUF_SIZE_C_SHIFT 24
#define  DVE1_TILED_SAMPLES 0x44A4
    #define DVE1_TILED_SAMPLES_WIDTH_MASK 0x00000FFF
    #define DVE1_TILED_SAMPLES_WIDTH_SHIFT 0
#define  DVE1_TOP_ACTIVE_Y 0x4434
    #define DVE1_TOP_ACTIVE_Y_START_MASK 0x00000FFF
    #define DVE1_TOP_ACTIVE_Y_START_SHIFT 0
    #define DVE1_TOP_ACTIVE_Y_END_MASK 0x0FFF0000
    #define DVE1_TOP_ACTIVE_Y_END_SHIFT 16
#define  DVE1_TOP_DE_X 0x4478
    #define DVE1_TOP_DE_X_START_MASK 0x00001FFF
    #define DVE1_TOP_DE_X_START_SHIFT 0
    #define DVE1_TOP_DE_X_END_MASK 0x1FFF0000
    #define DVE1_TOP_DE_X_END_SHIFT 16
#define  DVE1_TOP_DE_Y 0x4470
    #define DVE1_TOP_DE_Y_START_MASK 0x00000FFF
    #define DVE1_TOP_DE_Y_START_SHIFT 0
    #define DVE1_TOP_DE_Y_END_MASK 0x0FFF0000
    #define DVE1_TOP_DE_Y_END_SHIFT 16
#define  DVE1_TOP_VBI_Y 0x442C
    #define DVE1_TOP_VBI_Y_START_MASK 0x00000FFF
    #define DVE1_TOP_VBI_Y_START_SHIFT 0
    #define DVE1_TOP_VBI_Y_END_MASK 0x0FFF0000
    #define DVE1_TOP_VBI_Y_END_SHIFT 16
#define  DVE1_TOP_VIDEO_Y 0x443C
    #define DVE1_TOP_VIDEO_Y_START_MASK 0x00000FFF
    #define DVE1_TOP_VIDEO_Y_START_SHIFT 0
    #define DVE1_TOP_VIDEO_Y_END_MASK 0x0FFF0000
    #define DVE1_TOP_VIDEO_Y_END_SHIFT 16
#define  DVE1_TOP_VSYNC_X 0x445C
    #define DVE1_TOP_VSYNC_X_START_MASK 0x00001FFF
    #define DVE1_TOP_VSYNC_X_START_SHIFT 0
    #define DVE1_TOP_VSYNC_X_END_MASK 0x1FFF0000
    #define DVE1_TOP_VSYNC_X_END_SHIFT 16
#define  DVE1_TOP_VSYNC_Y 0x4454
    #define DVE1_TOP_VSYNC_Y_START_MASK 0x00000FFF
    #define DVE1_TOP_VSYNC_Y_START_SHIFT 0
    #define DVE1_TOP_VSYNC_Y_END_MASK 0x0FFF0000
    #define DVE1_TOP_VSYNC_Y_END_SHIFT 16
#define  DVE1_VBI_ADR 0x44B8
    #define DVE1_VBI_ADR_BASE_MASK 0x0FFFFFC0
    #define DVE1_VBI_ADR_BASE_SHIFT 6
#define  DVE1_VBI_BUF 0x44B0
    #define DVE1_VBI_BUF_PITCH_MASK 0x00000FE0
    #define DVE1_VBI_BUF_PITCH_SHIFT 5
    #define DVE1_VBI_BUF_SIZE_MASK 0x0FFF0000
    #define DVE1_VBI_BUF_SIZE_SHIFT 16
#define  DVE1_VBI_SAMPLES 0x44B4
    #define DVE1_VBI_SAMPLES_WIDTH_MASK 0x00000FFF
    #define DVE1_VBI_SAMPLES_WIDTH_SHIFT 0
#define  DVE1_VBI_X 0x444C
    #define DVE1_VBI_X_START_MASK 0x00001FFF
    #define DVE1_VBI_X_START_SHIFT 0
    #define DVE1_VBI_X_END_MASK 0x1FFF0000
    #define DVE1_VBI_X_END_SHIFT 16
#define  DVE1_VFILT_BOT0 0x4518
    #define DVE1_VFILT_BOT0_COEF_MASK 0x7FFFFFFF
    #define DVE1_VFILT_BOT0_COEF_SHIFT 0
#define  DVE1_VFILT_BOT1 0x451C
    #define DVE1_VFILT_BOT1_COEF_MASK 0x7FFFFFFF
    #define DVE1_VFILT_BOT1_COEF_SHIFT 0
#define  DVE1_VFILT_CTRL 0x450C
    #define DVE1_VFILT_CTRL_VCNT_INIT_FRAC_MASK 0x00000001
    #define DVE1_VFILT_CTRL_VCNT_INIT_FRAC_SHIFT 0
    #define DVE1_VFILT_CTRL_VCNT_INIT_MASK 0x00003FFE
    #define DVE1_VFILT_CTRL_VCNT_INIT_SHIFT 1
    #define DVE1_VFILT_CTRL_VCNT_INCR_FRAC_MASK 0x00010000
    #define DVE1_VFILT_CTRL_VCNT_INCR_FRAC_SHIFT 16
    #define DVE1_VFILT_CTRL_VCNT_INCR_MASK 0x00020000
    #define DVE1_VFILT_CTRL_VCNT_INCR_SHIFT 17
#define  DVE1_VFILT_TOP0 0x4510
    #define DVE1_VFILT_TOP0_COEF_MASK 0x7FFFFFFF
    #define DVE1_VFILT_TOP0_COEF_SHIFT 0
#define  DVE1_VFILT_TOP1 0x4514
    #define DVE1_VFILT_TOP1_COEF_MASK 0x7FFFFFFF
    #define DVE1_VFILT_TOP1_COEF_SHIFT 0
#define  DVE1_VIDEO_BORDER_CHROMA 0x448C
    #define DVE1_VIDEO_BORDER_CHROMA_CB_VAL_MASK 0x000003FF
    #define DVE1_VIDEO_BORDER_CHROMA_CB_VAL_SHIFT 0
    #define DVE1_VIDEO_BORDER_CHROMA_CR_VAL_MASK 0x03FF0000
    #define DVE1_VIDEO_BORDER_CHROMA_CR_VAL_SHIFT 16
#define  DVE1_VIDEO_BORDER_LUMA 0x4488
    #define DVE1_VIDEO_BORDER_LUMA_Y_VAL_MASK 0x000003FF
    #define DVE1_VIDEO_BORDER_LUMA_Y_VAL_SHIFT 0
#define  DVE1_VIDEO_X 0x4448
    #define DVE1_VIDEO_X_START_MASK 0x00001FFF
    #define DVE1_VIDEO_X_START_SHIFT 0
    #define DVE1_VIDEO_X_END_MASK 0x1FFF0000
    #define DVE1_VIDEO_X_END_SHIFT 16
#define  DVE1_Y_ADR 0x44A8
    #define DVE1_Y_ADR_BASE_MASK 0x0FFFFFC0
    #define DVE1_Y_ADR_BASE_SHIFT 6
#define  DVE_ACTIVE_X 0x4044
    #define DVE_ACTIVE_X_START_MASK 0x00001FFF
    #define DVE_ACTIVE_X_START_SHIFT 0
    #define DVE_ACTIVE_X_END_MASK 0x1FFF0000
    #define DVE_ACTIVE_X_END_SHIFT 16
#define  DVE_AV_X 0x4050
    #define DVE_AV_X_EAV_START_MASK 0x00001FFF
    #define DVE_AV_X_EAV_START_SHIFT 0
    #define DVE_AV_X_SAV_START_MASK 0x1FFF0000
    #define DVE_AV_X_SAV_START_SHIFT 16
#define  DVE_BOT_ACTIVE_Y 0x4038
    #define DVE_BOT_ACTIVE_Y_START_MASK 0x00000FFF
    #define DVE_BOT_ACTIVE_Y_START_SHIFT 0
    #define DVE_BOT_ACTIVE_Y_END_MASK 0x0FFF0000
    #define DVE_BOT_ACTIVE_Y_END_SHIFT 16
#define  DVE_BOT_DE_X 0x407C
    #define DVE_BOT_DE_X_START_MASK 0x00001FFF
    #define DVE_BOT_DE_X_START_SHIFT 0
    #define DVE_BOT_DE_X_END_MASK 0x1FFF0000
    #define DVE_BOT_DE_X_END_SHIFT 16
#define  DVE_BOT_DE_Y 0x4074
    #define DVE_BOT_DE_Y_START_MASK 0x00000FFF
    #define DVE_BOT_DE_Y_START_SHIFT 0
    #define DVE_BOT_DE_Y_END_MASK 0x0FFF0000
    #define DVE_BOT_DE_Y_END_SHIFT 16
#define  DVE_BOT_VBI_Y 0x4030
    #define DVE_BOT_VBI_Y_START_MASK 0x00000FFF
    #define DVE_BOT_VBI_Y_START_SHIFT 0
    #define DVE_BOT_VBI_Y_END_MASK 0x0FFF0000
    #define DVE_BOT_VBI_Y_END_SHIFT 16
#define  DVE_BOT_VIDEO_Y 0x4040
    #define DVE_BOT_VIDEO_Y_START_MASK 0x00000FFF
    #define DVE_BOT_VIDEO_Y_START_SHIFT 0
    #define DVE_BOT_VIDEO_Y_END_MASK 0x0FFF0000
    #define DVE_BOT_VIDEO_Y_END_SHIFT 16
#define  DVE_BOT_VSYNC_X 0x4060
    #define DVE_BOT_VSYNC_X_START_MASK 0x00001FFF
    #define DVE_BOT_VSYNC_X_START_SHIFT 0
    #define DVE_BOT_VSYNC_X_END_MASK 0x1FFF0000
    #define DVE_BOT_VSYNC_X_END_SHIFT 16
#define  DVE_BOT_VSYNC_Y 0x4058
    #define DVE_BOT_VSYNC_Y_START_MASK 0x00000FFF
    #define DVE_BOT_VSYNC_Y_START_SHIFT 0
    #define DVE_BOT_VSYNC_Y_END_MASK 0x0FFF0000
    #define DVE_BOT_VSYNC_Y_END_SHIFT 16
#define  DVE_BUF_STATUS 0x4104
    #define DVE_BUF_STATUS_CB_FREE_ENTRIES_MASK 0x000000FF
    #define DVE_BUF_STATUS_CB_FREE_ENTRIES_SHIFT 0
    #define DVE_BUF_STATUS_CR_FREE_ENTRIES_MASK 0x0000FF00
    #define DVE_BUF_STATUS_CR_FREE_ENTRIES_SHIFT 8
    #define DVE_BUF_STATUS_YVBI_FREE_ENTRIES_MASK 0x01FF0000
    #define DVE_BUF_STATUS_YVBI_FREE_ENTRIES_SHIFT 16
#define  DVE_CB_ADR 0x40BC
    #define DVE_CB_ADR_BASE_MASK 0x0FFFFFC0
    #define DVE_CB_ADR_BASE_SHIFT 6
#define  DVE_CHROMA_LIMIT 0x40EC
    #define DVE_CHROMA_LIMIT_UPPER_THRES_MASK 0x000003FF
    #define DVE_CHROMA_LIMIT_UPPER_THRES_SHIFT 0
    #define DVE_CHROMA_LIMIT_LOWER_THRES_MASK 0x03FF0000
    #define DVE_CHROMA_LIMIT_LOWER_THRES_SHIFT 16
#define  DVE_CMD_FIFO 0x4018
    #define DVE_CMD_FIFO_TOP_IDX_MASK 0x0000003F
    #define DVE_CMD_FIFO_TOP_IDX_SHIFT 0
    #define DVE_CMD_FIFO_FLD_SEL_MASK 0x000000C0
    #define DVE_CMD_FIFO_FLD_SEL_SHIFT 6
    #define DVE_CMD_FIFO_BOT_IDX_MASK 0x00003F00
    #define DVE_CMD_FIFO_BOT_IDX_SHIFT 8
    #define DVE_CMD_FIFO_VBI_FLD_SEL_MASK 0x0000C000
    #define DVE_CMD_FIFO_VBI_FLD_SEL_SHIFT 14
    #define DVE_CMD_FIFO_VBI_TOP_IDX_MASK 0x007F0000
    #define DVE_CMD_FIFO_VBI_TOP_IDX_SHIFT 16
    #define DVE_CMD_FIFO_BLEND_MASK 0x00800000
    #define DVE_CMD_FIFO_BLEND_SHIFT 23
    #define DVE_CMD_FIFO_VBI_BOT_IDX_MASK 0x7F000000
    #define DVE_CMD_FIFO_VBI_BOT_IDX_SHIFT 24
    #define DVE_CMD_FIFO_UPDATE_MASK 0x80000000
    #define DVE_CMD_FIFO_UPDATE_SHIFT 31
#define  DVE_CR_ADR 0x40C0
    #define DVE_CR_ADR_BASE_MASK 0x0FFFFFC0
    #define DVE_CR_ADR_BASE_SHIFT 6
#define  DVE_CTRL 0x4010
    #define DVE_CTRL_INPUT_BIT_SIZE_MASK 0x00000001
    #define DVE_CTRL_INPUT_BIT_SIZE_SHIFT 0
    #define DVE_CTRL_INPUT_422_MASK 0x00000002
    #define DVE_CTRL_INPUT_422_SHIFT 1
    #define DVE_CTRL_MEM_FORMAT_MASK 0x0000000C
    #define DVE_CTRL_MEM_FORMAT_SHIFT 2
    #define DVE_CTRL_EXTEND_8BIT_MASK 0x00000010
    #define DVE_CTRL_EXTEND_8BIT_SHIFT 4
    #define DVE_CTRL_OUTPUT_BIT_SIZE_MASK 0x00000020
    #define DVE_CTRL_OUTPUT_BIT_SIZE_SHIFT 5
    #define DVE_CTRL_OUT_CLK_EDGE_MASK 0x00000040
    #define DVE_CTRL_OUT_CLK_EDGE_SHIFT 6
    #define DVE_CTRL_DUPLICATE_CODE_MASK 0x00000080
    #define DVE_CTRL_DUPLICATE_CODE_SHIFT 7
    #define DVE_CTRL_OUTPUT_TYPE_MASK 0x00000300
    #define DVE_CTRL_OUTPUT_TYPE_SHIFT 8
    #define DVE_CTRL_EMPTY_FIFO_MODE_MASK 0x00000C00
    #define DVE_CTRL_EMPTY_FIFO_MODE_SHIFT 10
    #define DVE_CTRL_FIELD_POLARITY_MASK 0x00001000
    #define DVE_CTRL_FIELD_POLARITY_SHIFT 12
    #define DVE_CTRL_VSYNC_POLARITY_MASK 0x00002000
    #define DVE_CTRL_VSYNC_POLARITY_SHIFT 13
    #define DVE_CTRL_HSYNC_POLARITY_MASK 0x00004000
    #define DVE_CTRL_HSYNC_POLARITY_SHIFT 14
    #define DVE_CTRL_DE_POLARITY_MASK 0x00008000
    #define DVE_CTRL_DE_POLARITY_SHIFT 15
    #define DVE_CTRL_HS_BANK_MASK 0x00010000
    #define DVE_CTRL_HS_BANK_SHIFT 16
    #define DVE_CTRL_COL_CONV_EN_MASK 0x00020000
    #define DVE_CTRL_COL_CONV_EN_SHIFT 17
    #define DVE_CTRL_COL_CONV_SEL_MASK 0x000C0000
    #define DVE_CTRL_COL_CONV_SEL_SHIFT 18
    #define DVE_CTRL_EXT_SYNC_MODE_MASK 0x00100000
    #define DVE_CTRL_EXT_SYNC_MODE_SHIFT 20
    #define DVE_CTRL_AV_VSYNC_POLARITY_MASK 0x01000000
    #define DVE_CTRL_AV_VSYNC_POLARITY_SHIFT 24
    #define DVE_CTRL_AV_FIELD_POLARITY_MASK 0x02000000
    #define DVE_CTRL_AV_FIELD_POLARITY_SHIFT 25
    #define DVE_CTRL_PROG_TO_INTLCD_MODE_MASK 0x04000000
    #define DVE_CTRL_PROG_TO_INTLCD_MODE_SHIFT 26
    #define DVE_CTRL_MEM_PACKED_MASK 0x10000000
    #define DVE_CTRL_MEM_PACKED_SHIFT 28
    #define ALPHA_BLD_MASK 0x20000000
    #define ALPHA_BLD_SHIFT 29
    #define BLD_AVG_MASK 0x40000000
    #define BLD_AVG_SHIFT 30
#define  DVE_CURR_CMD 0x4024
    #define DVE_CURR_CMD_TOP_IDX_MASK 0x0000003F
    #define DVE_CURR_CMD_TOP_IDX_SHIFT 0
    #define DVE_CURR_CMD_FLD_SEL_MASK 0x000000C0
    #define DVE_CURR_CMD_FLD_SEL_SHIFT 6
    #define DVE_CURR_CMD_BOT_IDX_MASK 0x00003F00
    #define DVE_CURR_CMD_BOT_IDX_SHIFT 8
    #define DVE_CURR_CMD_VBI_FLD_SEL_MASK 0x0000C000
    #define DVE_CURR_CMD_VBI_FLD_SEL_SHIFT 14
    #define DVE_CURR_CMD_VBI_TOP_IDX_MASK 0x007F0000
    #define DVE_CURR_CMD_VBI_TOP_IDX_SHIFT 16
    #define DVE_CURR_CMD_BLEND_MASK 0x00800000
    #define DVE_CURR_CMD_BLEND_SHIFT 23
    #define DVE_CURR_CMD_VBI_BOT_IDX_MASK 0x7F000000
    #define DVE_CURR_CMD_VBI_BOT_IDX_SHIFT 24
    #define DVE_CURR_CMD_UPDATE_MASK 0x80000000
    #define DVE_CURR_CMD_UPDATE_SHIFT 31
#define  DVE_C_ADR 0x40AC
    #define DVE_C_ADR_BASE_MASK 0x0FFFFFC0
    #define DVE_C_ADR_BASE_SHIFT 6
#define  DVE_DEFAULT_CHROMA 0x4094
    #define DVE_DEFAULT_CHROMA_CB_VAL_MASK 0x000003FF
    #define DVE_DEFAULT_CHROMA_CB_VAL_SHIFT 0
    #define DVE_DEFAULT_CHROMA_CR_VAL_MASK 0x03FF0000
    #define DVE_DEFAULT_CHROMA_CR_VAL_SHIFT 16
#define  DVE_DEFAULT_LUMA 0x4090
    #define DVE_DEFAULT_LUMA_Y_VAL_MASK 0x000003FF
    #define DVE_DEFAULT_LUMA_Y_VAL_SHIFT 0
#define  DVE_DEN 0x4124
    #define DVE_DEN_DEN_MASK 0xFFFFFFFF
    #define DVE_DEN_DEN_SHIFT 0
#define  DVE_DUMMY_REG 0x4100
    #define DVE_DUMMY_REG_DUMMY_BITS_MASK 0xFFFFFFFF
    #define DVE_DUMMY_REG_DUMMY_BITS_SHIFT 0
#define  DVE_FIELD_X 0x406C
    #define DVE_FIELD_X_FO_START_MASK 0x00001FFF
    #define DVE_FIELD_X_FO_START_SHIFT 0
    #define DVE_FIELD_X_FE_START_MASK 0x1FFF0000
    #define DVE_FIELD_X_FE_START_SHIFT 16
#define  DVE_FIELD_Y 0x4068
    #define DVE_FIELD_Y_FO_START_MASK 0x00000FFF
    #define DVE_FIELD_Y_FO_START_SHIFT 0
    #define DVE_FIELD_Y_FE_START_MASK 0x0FFF0000
    #define DVE_FIELD_Y_FE_START_SHIFT 16
#define  DVE_FIFO_STATUS 0x401C
    #define DVE_FIFO_STATUS_FREE_ENTRIES_MASK 0x0000001F
    #define DVE_FIFO_STATUS_FREE_ENTRIES_SHIFT 0
    #define DVE_FIFO_STATUS_CURR_IDX_MASK 0x00000F00
    #define DVE_FIFO_STATUS_CURR_IDX_SHIFT 8
    #define DVE_FIFO_STATUS_FRM_CNT_MASK 0x000FF000
    #define DVE_FIFO_STATUS_FRM_CNT_SHIFT 12
#define  DVE_FRAME_SIZE 0x4028
    #define DVE_FRAME_SIZE_H_TOTAL_MASK 0x00001FFF
    #define DVE_FRAME_SIZE_H_TOTAL_SHIFT 0
    #define DVE_FRAME_SIZE_V_TOTAL_MASK 0x0FFF0000
    #define DVE_FRAME_SIZE_V_TOTAL_SHIFT 16
#define  DVE_GENLOCK_LOWER 0x412C
    #define DVE_GENLOCK_LOWER_GENLOCK_L_MASK 0xFFFFFFFF
    #define DVE_GENLOCK_LOWER_GENLOCK_L_SHIFT 0
#define  DVE_GENLOCK_PCR_LOWER 0x40FC
    #define DVE_GENLOCK_PCR_LOWER_GENLOCK_PCR_L_MASK 0xFFFFFFFF
    #define DVE_GENLOCK_PCR_LOWER_GENLOCK_PCR_L_SHIFT 0
#define  DVE_GENLOCK_PCR_UPPER 0x40F8
    #define DVE_GENLOCK_PCR_UPPER_GENLOCK_PCR_U_MASK 0x000003FF
    #define DVE_GENLOCK_PCR_UPPER_GENLOCK_PCR_U_SHIFT 0
#define  DVE_GENLOCK_UPPER 0x4128
    #define DVE_GENLOCK_UPPER_GENLOCK_U_MASK 0x000003FF
    #define DVE_GENLOCK_UPPER_GENLOCK_U_SHIFT 0
#define  DVE_HBLANK_CHROMA 0x4084
    #define DVE_HBLANK_CHROMA_CB_VAL_MASK 0x000003FF
    #define DVE_HBLANK_CHROMA_CB_VAL_SHIFT 0
    #define DVE_HBLANK_CHROMA_CR_VAL_MASK 0x03FF0000
    #define DVE_HBLANK_CHROMA_CR_VAL_SHIFT 16
#define  DVE_HBLANK_LUMA 0x4080
    #define DVE_HBLANK_LUMA_Y_VAL_MASK 0x000003FF
    #define DVE_HBLANK_LUMA_Y_VAL_SHIFT 0
#define  DVE_HOST_INT_MASK 0x4008
    #define DVE_HOST_INT_MASK_MASK 0x00000001
    #define DVE_HOST_INT_MASK_SHIFT 0
#define  DVE_HSCAL_CHROMA_CTRL 0x40DC
    #define DVE_HSCAL_CHROMA_CTRL_PHASES_MASK 0x0000001F
    #define DVE_HSCAL_CHROMA_CTRL_PHASES_SHIFT 0
    #define DVE_HSCAL_CHROMA_CTRL_SRC_RES_MASK 0x00007F00
    #define DVE_HSCAL_CHROMA_CTRL_SRC_RES_SHIFT 8
    #define DVE_HSCAL_CHROMA_CTRL_DST_RES_MASK 0x007F0000
    #define DVE_HSCAL_CHROMA_CTRL_DST_RES_SHIFT 16
    #define DVE_HSCAL_CHROMA_CTRL_IDX_SHIFT_MASK 0x03000000
    #define DVE_HSCAL_CHROMA_CTRL_IDX_SHIFT_SHIFT 24
#define  DVE_HSCAL_CHROMA_DATA 0x40E4
    #define DVE_HSCAL_CHROMA_DATA_COEF_MASK 0xFFFFFFFF
    #define DVE_HSCAL_CHROMA_DATA_COEF_SHIFT 0
#define  DVE_HSCAL_CHROMA_IDX 0x40E0
    #define DVE_HSCAL_CHROMA_IDX_FLD_MASK 0x00000003
    #define DVE_HSCAL_CHROMA_IDX_FLD_SHIFT 0
    #define DVE_HSCAL_CHROMA_IDX_ADR_MASK 0x000000F0
    #define DVE_HSCAL_CHROMA_IDX_ADR_SHIFT 4
    #define DVE_HSCAL_CHROMA_IDX_BANK_MASK 0x00000100
    #define DVE_HSCAL_CHROMA_IDX_BANK_SHIFT 8
#define  DVE_HSCAL_LUMA_CTRL 0x40D0
    #define DVE_HSCAL_LUMA_CTRL_PHASES_MASK 0x0000001F
    #define DVE_HSCAL_LUMA_CTRL_PHASES_SHIFT 0
    #define DVE_HSCAL_LUMA_CTRL_SRC_RES_MASK 0x00007F00
    #define DVE_HSCAL_LUMA_CTRL_SRC_RES_SHIFT 8
    #define DVE_HSCAL_LUMA_CTRL_DST_RES_MASK 0x007F0000
    #define DVE_HSCAL_LUMA_CTRL_DST_RES_SHIFT 16
    #define DVE_HSCAL_LUMA_CTRL_IDX_SHIFT_MASK 0x03000000
    #define DVE_HSCAL_LUMA_CTRL_IDX_SHIFT_SHIFT 24
#define  DVE_HSCAL_LUMA_DATA 0x40D8
    #define DVE_HSCAL_LUMA_DATA_COEF_MASK 0xFFFFFFFF
    #define DVE_HSCAL_LUMA_DATA_COEF_SHIFT 0
#define  DVE_HSCAL_LUMA_IDX 0x40D4
    #define DVE_HSCAL_LUMA_IDX_FLD_MASK 0x00000003
    #define DVE_HSCAL_LUMA_IDX_FLD_SHIFT 0
    #define DVE_HSCAL_LUMA_IDX_ADR_MASK 0x000000F0
    #define DVE_HSCAL_LUMA_IDX_ADR_SHIFT 4
    #define DVE_HSCAL_LUMA_IDX_BANK_MASK 0x00000100
    #define DVE_HSCAL_LUMA_IDX_BANK_SHIFT 8
#define  DVE_HSYNC_X 0x4064
    #define DVE_HSYNC_X_START_MASK 0x00001FFF
    #define DVE_HSYNC_X_START_SHIFT 0
    #define DVE_HSYNC_X_END_MASK 0x1FFF0000
    #define DVE_HSYNC_X_END_SHIFT 16
#define  DVE_INT_CTRL 0x4000
    #define DVE_INT_EN_MASK 0x000000FF
    #define DVE_INT_EN_SHIFT 0
#define  DVE_INT_STATUS 0x4004
    #define DVE_INT_STATUS_DVE_INT_MASK 0x00000001
    #define DVE_INT_STATUS_DVE_INT_SHIFT 0
    #define DVE_INT_STATUS_FRM_CNT_RST_MASK 0x00000010
    #define DVE_INT_STATUS_FRM_CNT_RST_SHIFT 4
#define  DVE_LUMA_LIMIT 0x40E8
    #define DVE_LUMA_LIMIT_UPPER_THRES_MASK 0x000003FF
    #define DVE_LUMA_LIMIT_UPPER_THRES_SHIFT 0
    #define DVE_LUMA_LIMIT_LOWER_THRES_MASK 0x03FF0000
    #define DVE_LUMA_LIMIT_LOWER_THRES_SHIFT 16
#define  DVE_MC_ARB 0x4144
    #define DVE_MC_ARB_REQ_CNT_LIMIT_MASK 0x0000000F
    #define DVE_MC_ARB_REQ_CNT_LIMIT_SHIFT 0
#define  DVE_MIPS_INT_MASK 0x400C
    #define DVE_MIPS_INT_MASK_MASK 0x00000001
    #define DVE_MIPS_INT_MASK_SHIFT 0
#define  DVE_NUM 0x4120
    #define DVE_NUM_NUM_MASK 0xFFFFFFFF
    #define DVE_NUM_NUM_SHIFT 0
#define  DVE_OUTPUT_CLK_CTRL 0x4130
    #define DVE_OUTPUT_CLK_CTRL_DDR_MODE_MASK 0x00000001
    #define DVE_OUTPUT_CLK_CTRL_DDR_MODE_SHIFT 0
    #define DVE_OUTPUT_CLK_CTRL_DDR_CLK_POLARITY_MASK 0x00000010
    #define DVE_OUTPUT_CLK_CTRL_DDR_CLK_POLARITY_SHIFT 4
    #define DVE_OUTPUT_CLK_CTRL_STOP_OUT_CLK_MASK 0x80000000
    #define DVE_OUTPUT_CLK_CTRL_STOP_OUT_CLK_SHIFT 31
#define  DVE_OUTPUT_SEL 0x4140
    #define DVE_OUTPUT_SEL_VODATA_9_0_SEL_MASK 0x00000003
    #define DVE_OUTPUT_SEL_VODATA_9_0_SEL_SHIFT 0
    #define DVE_OUTPUT_SEL_VODATA_19_10_SEL_MASK 0x00000300
    #define DVE_OUTPUT_SEL_VODATA_19_10_SEL_SHIFT 8
    #define DVE_OUTPUT_SEL_VODATA_29_20_SEL_MASK 0x00030000
    #define DVE_OUTPUT_SEL_VODATA_29_20_SEL_SHIFT 16
#define  DVE_OUT_STATUS 0x4020
    #define DVE_OUT_STATUS_X_COORD_MASK 0x00001FFF
    #define DVE_OUT_STATUS_X_COORD_SHIFT 0
    #define DVE_OUT_STATUS_Y_COORD_MASK 0x01FFE000
    #define DVE_OUT_STATUS_Y_COORD_SHIFT 13
    #define DVE_OUT_STATUS_FRM_STATE_MASK 0xFE000000
    #define DVE_OUT_STATUS_FRM_STATE_SHIFT 25
#define  DVE_PACKED_ORDER 0x4014
    #define DVE_PACKED_ORDER_Y_BYTE_SEL_MASK 0x00000003
    #define DVE_PACKED_ORDER_Y_BYTE_SEL_SHIFT 0
    #define DVE_PACKED_ORDER_CB_BYTE_SEL_MASK 0x00000030
    #define DVE_PACKED_ORDER_CB_BYTE_SEL_SHIFT 4
    #define DVE_PACKED_ORDER_CR_BYTE_SEL_MASK 0x00000300
    #define DVE_PACKED_ORDER_CR_BYTE_SEL_SHIFT 8
#define  DVE_PCR_DEN 0x40F4
    #define DVE_PCR_DEN_DEN_MASK 0x0000FFFF
    #define DVE_PCR_DEN_DEN_SHIFT 0
#define  DVE_PCR_NUM 0x40F0
    #define DVE_PCR_NUM_NUM_MASK 0x0000FFFF
    #define DVE_PCR_NUM_NUM_SHIFT 0
#define  DVE_PLANAR_BUF 0x4098
    #define DVE_PLANAR_BUF_PITCH_MASK 0x00001FE0
    #define DVE_PLANAR_BUF_PITCH_SHIFT 5
    #define DVE_PLANAR_BUF_SIZE_MASK 0x7FFF0000
    #define DVE_PLANAR_BUF_SIZE_SHIFT 16
#define  DVE_PLANAR_SAMPLES 0x409C
    #define DVE_PLANAR_SAMPLES_WIDTH_MASK 0x00000FFF
    #define DVE_PLANAR_SAMPLES_WIDTH_SHIFT 0
#define  DVE_REQ_STATUS 0x4108
    #define DVE_REQ_STATUS_C_REQ_WAIT_MASK 0x00000001
    #define DVE_REQ_STATUS_C_REQ_WAIT_SHIFT 0
    #define DVE_REQ_STATUS_Y_REQ_WAIT_MASK 0x00000010
    #define DVE_REQ_STATUS_Y_REQ_WAIT_SHIFT 4
    #define DVE_REQ_STATUS_VBI_REQ_WAIT_MASK 0x00000100
    #define DVE_REQ_STATUS_VBI_REQ_WAIT_SHIFT 8
    #define DVE_REQ_STATUS_MEM_RCLI_RDY_MASK 0x00001000
    #define DVE_REQ_STATUS_MEM_RCLI_RDY_SHIFT 12
#define  DVE_TILED_BUF 0x40A0
    #define DVE_TILED_BUF_PITCH_MASK 0x00000FF0
    #define DVE_TILED_BUF_PITCH_SHIFT 4
    #define DVE_TILED_BUF_SIZE_Y_MASK 0x001FF000
    #define DVE_TILED_BUF_SIZE_Y_SHIFT 12
    #define DVE_TILED_BUF_SIZE_C_MASK 0xFF000000
    #define DVE_TILED_BUF_SIZE_C_SHIFT 24
#define  DVE_TILED_SAMPLES 0x40A4
    #define DVE_TILED_SAMPLES_WIDTH_MASK 0x00000FFF
    #define DVE_TILED_SAMPLES_WIDTH_SHIFT 0
#define  DVE_TOP_ACTIVE_Y 0x4034
    #define DVE_TOP_ACTIVE_Y_START_MASK 0x00000FFF
    #define DVE_TOP_ACTIVE_Y_START_SHIFT 0
    #define DVE_TOP_ACTIVE_Y_END_MASK 0x0FFF0000
    #define DVE_TOP_ACTIVE_Y_END_SHIFT 16
#define  DVE_TOP_DE_X 0x4078
    #define DVE_TOP_DE_X_START_MASK 0x00001FFF
    #define DVE_TOP_DE_X_START_SHIFT 0
    #define DVE_TOP_DE_X_END_MASK 0x1FFF0000
    #define DVE_TOP_DE_X_END_SHIFT 16
#define  DVE_TOP_DE_Y 0x4070
    #define DVE_TOP_DE_Y_START_MASK 0x00000FFF
    #define DVE_TOP_DE_Y_START_SHIFT 0
    #define DVE_TOP_DE_Y_END_MASK 0x0FFF0000
    #define DVE_TOP_DE_Y_END_SHIFT 16
#define  DVE_TOP_VBI_Y 0x402C
    #define DVE_TOP_VBI_Y_START_MASK 0x00000FFF
    #define DVE_TOP_VBI_Y_START_SHIFT 0
    #define DVE_TOP_VBI_Y_END_MASK 0x0FFF0000
    #define DVE_TOP_VBI_Y_END_SHIFT 16
#define  DVE_TOP_VIDEO_Y 0x403C
    #define DVE_TOP_VIDEO_Y_START_MASK 0x00000FFF
    #define DVE_TOP_VIDEO_Y_START_SHIFT 0
    #define DVE_TOP_VIDEO_Y_END_MASK 0x0FFF0000
    #define DVE_TOP_VIDEO_Y_END_SHIFT 16
#define  DVE_TOP_VSYNC_X 0x405C
    #define DVE_TOP_VSYNC_X_START_MASK 0x00001FFF
    #define DVE_TOP_VSYNC_X_START_SHIFT 0
    #define DVE_TOP_VSYNC_X_END_MASK 0x1FFF0000
    #define DVE_TOP_VSYNC_X_END_SHIFT 16
#define  DVE_TOP_VSYNC_Y 0x4054
    #define DVE_TOP_VSYNC_Y_START_MASK 0x00000FFF
    #define DVE_TOP_VSYNC_Y_START_SHIFT 0
    #define DVE_TOP_VSYNC_Y_END_MASK 0x0FFF0000
    #define DVE_TOP_VSYNC_Y_END_SHIFT 16
#define  DVE_VBI_ADR 0x40B8
    #define DVE_VBI_ADR_BASE_MASK 0x0FFFFFC0
    #define DVE_VBI_ADR_BASE_SHIFT 6
#define  DVE_VBI_BUF 0x40B0
    #define DVE_VBI_BUF_PITCH_MASK 0x00000FE0
    #define DVE_VBI_BUF_PITCH_SHIFT 5
    #define DVE_VBI_BUF_SIZE_MASK 0x0FFF0000
    #define DVE_VBI_BUF_SIZE_SHIFT 16
#define  DVE_VBI_SAMPLES 0x40B4
    #define DVE_VBI_SAMPLES_WIDTH_MASK 0x00000FFF
    #define DVE_VBI_SAMPLES_WIDTH_SHIFT 0
#define  DVE_VBI_X 0x404C
    #define DVE_VBI_X_START_MASK 0x00001FFF
    #define DVE_VBI_X_START_SHIFT 0
    #define DVE_VBI_X_END_MASK 0x1FFF0000
    #define DVE_VBI_X_END_SHIFT 16
#define  DVE_VFILT_BOT0 0x4118
    #define DVE_VFILT_BOT0_COEF_MASK 0x7FFFFFFF
    #define DVE_VFILT_BOT0_COEF_SHIFT 0
#define  DVE_VFILT_BOT1 0x411C
    #define DVE_VFILT_BOT1_COEF_MASK 0x7FFFFFFF
    #define DVE_VFILT_BOT1_COEF_SHIFT 0
#define  DVE_VFILT_CTRL 0x410C
    #define DVE_VFILT_CTRL_VCNT_INIT_FRAC_MASK 0x00000001
    #define DVE_VFILT_CTRL_VCNT_INIT_FRAC_SHIFT 0
    #define DVE_VFILT_CTRL_VCNT_INIT_MASK 0x00003FFE
    #define DVE_VFILT_CTRL_VCNT_INIT_SHIFT 1
    #define DVE_VFILT_CTRL_VCNT_INCR_FRAC_MASK 0x00010000
    #define DVE_VFILT_CTRL_VCNT_INCR_FRAC_SHIFT 16
    #define DVE_VFILT_CTRL_VCNT_INCR_MASK 0x00020000
    #define DVE_VFILT_CTRL_VCNT_INCR_SHIFT 17
#define  DVE_VFILT_TOP0 0x4110
    #define DVE_VFILT_TOP0_COEF_MASK 0x7FFFFFFF
    #define DVE_VFILT_TOP0_COEF_SHIFT 0
#define  DVE_VFILT_TOP1 0x4114
    #define DVE_VFILT_TOP1_COEF_MASK 0x7FFFFFFF
    #define DVE_VFILT_TOP1_COEF_SHIFT 0
#define  DVE_VIDEO_BORDER_CHROMA 0x408C
    #define DVE_VIDEO_BORDER_CHROMA_CB_VAL_MASK 0x000003FF
    #define DVE_VIDEO_BORDER_CHROMA_CB_VAL_SHIFT 0
    #define DVE_VIDEO_BORDER_CHROMA_CR_VAL_MASK 0x03FF0000
    #define DVE_VIDEO_BORDER_CHROMA_CR_VAL_SHIFT 16
#define  DVE_VIDEO_BORDER_LUMA 0x4088
    #define DVE_VIDEO_BORDER_LUMA_Y_VAL_MASK 0x000003FF
    #define DVE_VIDEO_BORDER_LUMA_Y_VAL_SHIFT 0
#define  DVE_VIDEO_X 0x4048
    #define DVE_VIDEO_X_START_MASK 0x00001FFF
    #define DVE_VIDEO_X_START_SHIFT 0
    #define DVE_VIDEO_X_END_MASK 0x1FFF0000
    #define DVE_VIDEO_X_END_SHIFT 16
#define  DVE_Y_ADR 0x40A8
    #define DVE_Y_ADR_BASE_MASK 0x0FFFFFC0
    #define DVE_Y_ADR_BASE_SHIFT 6
#define  DVO1_CTRL 0x62B8
    #define DVO1_CTRL_PARTIAL_TSO_MASK 0x00000002
    #define DVO1_CTRL_PARTIAL_TSO_SHIFT 1
    #define DVO1_CTRL_CLK_INV_MASK 0x00000004
    #define DVO1_CTRL_CLK_INV_SHIFT 2
    #define DVO1_CTRL_CLK_STOP_MASK 0x00000008
    #define DVO1_CTRL_CLK_STOP_SHIFT 3
    #define DVO1_CTRL_PS_MODE_MASK 0x00000020
    #define DVO1_CTRL_PS_MODE_SHIFT 5
    #define DVO1_CTRL_DVO_VALID_HIGH_MASK 0x00000040
    #define DVO1_CTRL_DVO_VALID_HIGH_SHIFT 6
    #define DVO1_CTRL_CLK_MASK 0x00000380
    #define DVO1_CTRL_CLK_SHIFT 7
    #define DVO1_CTRL_NULL_STUFF_MASK 0x00001000
    #define DVO1_CTRL_NULL_STUFF_SHIFT 12
    #define DVO1_CTRL_DROP_HEADER_MASK 0x00004000
    #define DVO1_CTRL_DROP_HEADER_SHIFT 14
    #define DVO1_CTRL_SYNC_DUR_MASK 0x00008000
    #define DVO1_CTRL_SYNC_DUR_SHIFT 15
    #define DVO1_CTRL_PAR_RATE_MASK 0x07FF0000
    #define DVO1_CTRL_PAR_RATE_SHIFT 16
    #define DVO1_CTRL_TTS_REF_SEL_MASK 0x38000000
    #define DVO1_CTRL_TTS_REF_SEL_SHIFT 27
    #define DVO1_CTRL_BUF_RDY_THRES_MASK 0xC0000000
    #define DVO1_CTRL_BUF_RDY_THRES_SHIFT 30
#define  DVO1_PARTIAL_RMX 0x60A4
    #define DVO1_PARTIAL_RMX_TTS_EXP_LIMIT_MASK 0xFFFFFFFF
    #define DVO1_PARTIAL_RMX_TTS_EXP_LIMIT_SHIFT 0
#define  DVO_CTRL 0x6090
    #define DVO_CTRL_PARTIAL_TSO_MASK 0x00000002
    #define DVO_CTRL_PARTIAL_TSO_SHIFT 1
    #define DVO_CTRL_CLK_INV_MASK 0x00000004
    #define DVO_CTRL_CLK_INV_SHIFT 2
    #define DVO_CTRL_CLK_STOP_MASK 0x00000008
    #define DVO_CTRL_CLK_STOP_SHIFT 3
    #define INCR_DIS_MASK 0x00000010
    #define INCR_DIS_SHIFT 4
    #define DVO_CTRL_PS_MODE_MASK 0x00000020
    #define DVO_CTRL_PS_MODE_SHIFT 5
    #define DVO_CTRL_DVO_VALID_HIGH_MASK 0x00000040
    #define DVO_CTRL_DVO_VALID_HIGH_SHIFT 6
    #define DVO_CTRL_CLK_MASK 0x00000380
    #define DVO_CTRL_CLK_SHIFT 7
    #define DVO_CTRL_NULL_STUFF_MASK 0x00001000
    #define DVO_CTRL_NULL_STUFF_SHIFT 12
    #define DVO_CTRL_DROP_HEADER_MASK 0x00004000
    #define DVO_CTRL_DROP_HEADER_SHIFT 14
    #define DVO_CTRL_SYNC_DUR_MASK 0x00008000
    #define DVO_CTRL_SYNC_DUR_SHIFT 15
    #define DVO_CTRL_PAR_RATE_MASK 0x07FF0000
    #define DVO_CTRL_PAR_RATE_SHIFT 16
    #define DVO_CTRL_TTS_REF_SEL_MASK 0x38000000
    #define DVO_CTRL_TTS_REF_SEL_SHIFT 27
    #define DVO_CTRL_BUF_RDY_THRES_MASK 0xC0000000
    #define DVO_CTRL_BUF_RDY_THRES_SHIFT 30
#define  DVO_INCR_PCR_CID 0x60A8
    #define DVO_INCR_PCR_CID_PCR_CID0_MASK 0x0000003F
    #define DVO_INCR_PCR_CID_PCR_CID0_SHIFT 0
    #define DVO_INCR_PCR_CID_PCR_CID1_MASK 0x00003F00
    #define DVO_INCR_PCR_CID_PCR_CID1_SHIFT 8
    #define DVO_INCR_PCR_CID_PCR_CID2_MASK 0x003F0000
    #define DVO_INCR_PCR_CID_PCR_CID2_SHIFT 16
    #define DVO_INCR_PCR_CID_PCR_CID3_MASK 0x3F000000
    #define DVO_INCR_PCR_CID_PCR_CID3_SHIFT 24
#define  DVO_INCR_PCR_RTP_CID_ENABLE 0x63B8
    #define PCR_CID0_ENABLE_MASK 0x00000001
    #define PCR_CID0_ENABLE_SHIFT 0
    #define PCR_CID1_ENABLE_MASK 0x00000002
    #define PCR_CID1_ENABLE_SHIFT 1
    #define PCR_CID2_ENABLE_MASK 0x00000004
    #define PCR_CID2_ENABLE_SHIFT 2
    #define PCR_CID3_ENABLE_MASK 0x00000008
    #define PCR_CID3_ENABLE_SHIFT 3
    #define PCR_RTP0_ENABLE_MASK 0x00000100
    #define PCR_RTP0_ENABLE_SHIFT 8
    #define PCR_RTP1_ENABLE_MASK 0x00000200
    #define PCR_RTP1_ENABLE_SHIFT 9
    #define PCR_RTP2_ENABLE_MASK 0x00000400
    #define PCR_RTP2_ENABLE_SHIFT 10
    #define PCR_RTP3_ENABLE_MASK 0x00000800
    #define PCR_RTP3_ENABLE_SHIFT 11
#define  DVO_PARTIAL_RMX 0x60A0
    #define DVO_PARTIAL_RMX_TTS_EXP_LIMIT_MASK 0xFFFFFFFF
    #define DVO_PARTIAL_RMX_TTS_EXP_LIMIT_SHIFT 0
#define  DVO_PCR_INCR_ADR 0x60D0
    #define PCR_INCR_ADR_MASK 0x00000007
    #define PCR_INCR_ADR_SHIFT 0
#define  DVO_PCR_INCR_DATA_L 0x60D4
    #define PCR_INCR_DATA_L_MASK 0xFFFFFFFF
    #define PCR_INCR_DATA_L_SHIFT 0
#define  DVO_PCR_INCR_DATA_U 0x60D8
    #define PCR_INCR_DATA_U_MASK 0x00000001
    #define PCR_INCR_DATA_U_SHIFT 0
    #define PCR_INCR_DATA_RD_VALID_MASK 0x80000000
    #define PCR_INCR_DATA_RD_VALID_SHIFT 31
#define  DVO_PCR_LATCHED_ADR 0x60E0
    #define PCR_LATCHED_ADR_MASK 0x00000007
    #define PCR_LATCHED_ADR_SHIFT 0
#define  DVO_PCR_LATCHED_DATA_L 0x60E4
    #define PCR_LATCHED_DATA_L_MASK 0xFFFFFFFF
    #define PCR_LATCHED_DATA_L_SHIFT 0
#define  DVO_PCR_LATCHED_DATA_U 0x60E8
    #define PCR_LATCHED_DATA_U_MASK 0x00000001
    #define PCR_LATCHED_DATA_U_SHIFT 0
    #define PCR_LATCHED_DATA_RD_VALID_MASK 0x80000000
    #define PCR_LATCHED_DATA_RD_VALID_SHIFT 31
#define  DVO_PCR_PID0_1 0x6094
    #define PCR_PID0_MASK 0x00001FFF
    #define PCR_PID0_SHIFT 0
    #define PCR_STR0_MASK 0x00006000
    #define PCR_STR0_SHIFT 13
    #define PCR_PID1_MASK 0x1FFF0000
    #define PCR_PID1_SHIFT 16
    #define PCR_STR1_MASK 0x60000000
    #define PCR_STR1_SHIFT 29
#define  DVO_PCR_PID2_3 0x6098
    #define PCR_PID2_MASK 0x00001FFF
    #define PCR_PID2_SHIFT 0
    #define PCR_STR2_MASK 0x00006000
    #define PCR_STR2_SHIFT 13
    #define PCR_PID3_MASK 0x1FFF0000
    #define PCR_PID3_SHIFT 16
    #define PCR_STR3_MASK 0x60000000
    #define PCR_STR3_SHIFT 29
#define  DVO_RING_SEL_0 0x6378
    #define RID0_MASK 0x00000003
    #define RID0_SHIFT 0
    #define RID1_MASK 0x0000000C
    #define RID1_SHIFT 2
    #define RID2_MASK 0x00000030
    #define RID2_SHIFT 4
    #define RID3_MASK 0x000000C0
    #define RID3_SHIFT 6
    #define RID4_MASK 0x00000300
    #define RID4_SHIFT 8
    #define RID5_MASK 0x00000C00
    #define RID5_SHIFT 10
    #define RID6_MASK 0x00003000
    #define RID6_SHIFT 12
    #define RID7_MASK 0x0000C000
    #define RID7_SHIFT 14
    #define RID8_MASK 0x00030000
    #define RID8_SHIFT 16
    #define RID9_MASK 0x000C0000
    #define RID9_SHIFT 18
    #define RID10_MASK 0x00300000
    #define RID10_SHIFT 20
    #define RID11_MASK 0x00C00000
    #define RID11_SHIFT 22
    #define RID12_MASK 0x03000000
    #define RID12_SHIFT 24
    #define RID13_MASK 0x0C000000
    #define RID13_SHIFT 26
    #define RID14_MASK 0x30000000
    #define RID14_SHIFT 28
    #define RID15_MASK 0xC0000000
    #define RID15_SHIFT 30
#define  DVO_RING_SEL_1 0x637C
    #define RID16_MASK 0x00000003
    #define RID16_SHIFT 0
    #define RID17_MASK 0x0000000C
    #define RID17_SHIFT 2
    #define RID18_MASK 0x00000030
    #define RID18_SHIFT 4
    #define RID19_MASK 0x000000C0
    #define RID19_SHIFT 6
    #define RID20_MASK 0x00000300
    #define RID20_SHIFT 8
    #define RID21_MASK 0x00000C00
    #define RID21_SHIFT 10
    #define RID22_MASK 0x00003000
    #define RID22_SHIFT 12
    #define RID23_MASK 0x0000C000
    #define RID23_SHIFT 14
    #define RID24_MASK 0x00030000
    #define RID24_SHIFT 16
    #define RID25_MASK 0x000C0000
    #define RID25_SHIFT 18
    #define RID26_MASK 0x00300000
    #define RID26_SHIFT 20
    #define RID27_MASK 0x00C00000
    #define RID27_SHIFT 22
    #define RID28_MASK 0x03000000
    #define RID28_SHIFT 24
    #define RID29_MASK 0x0C000000
    #define RID29_SHIFT 26
    #define RID30_MASK 0x30000000
    #define RID30_SHIFT 28
    #define RID31_MASK 0xC0000000
    #define RID31_SHIFT 30
#define  DVO_RING_SEL_2 0x6380
    #define RID32_MASK 0x00000003
    #define RID32_SHIFT 0
    #define RID33_MASK 0x0000000C
    #define RID33_SHIFT 2
    #define RID34_MASK 0x00000030
    #define RID34_SHIFT 4
    #define RID35_MASK 0x000000C0
    #define RID35_SHIFT 6
    #define RID36_MASK 0x00000300
    #define RID36_SHIFT 8
    #define RID37_MASK 0x00000C00
    #define RID37_SHIFT 10
    #define RID38_MASK 0x00003000
    #define RID38_SHIFT 12
    #define RID39_MASK 0x0000C000
    #define RID39_SHIFT 14
    #define RID40_MASK 0x00030000
    #define RID40_SHIFT 16
    #define RID41_MASK 0x000C0000
    #define RID41_SHIFT 18
    #define RID42_MASK 0x00300000
    #define RID42_SHIFT 20
    #define RID43_MASK 0x00C00000
    #define RID43_SHIFT 22
    #define RID44_MASK 0x03000000
    #define RID44_SHIFT 24
    #define RID45_MASK 0x0C000000
    #define RID45_SHIFT 26
    #define RID46_MASK 0x30000000
    #define RID46_SHIFT 28
    #define RID47_MASK 0xC0000000
    #define RID47_SHIFT 30
#define  DVO_RING_SEL_3 0x6384
    #define RID48_MASK 0x00000003
    #define RID48_SHIFT 0
    #define RID49_MASK 0x0000000C
    #define RID49_SHIFT 2
    #define RID50_MASK 0x00000030
    #define RID50_SHIFT 4
    #define RID51_MASK 0x000000C0
    #define RID51_SHIFT 6
    #define RID52_MASK 0x00000300
    #define RID52_SHIFT 8
    #define RID53_MASK 0x00000C00
    #define RID53_SHIFT 10
    #define RID54_MASK 0x00003000
    #define RID54_SHIFT 12
    #define RID55_MASK 0x0000C000
    #define RID55_SHIFT 14
    #define RID56_MASK 0x00030000
    #define RID56_SHIFT 16
    #define RID57_MASK 0x000C0000
    #define RID57_SHIFT 18
    #define RID58_MASK 0x00300000
    #define RID58_SHIFT 20
    #define RID59_MASK 0x00C00000
    #define RID59_SHIFT 22
    #define RID60_MASK 0x03000000
    #define RID60_SHIFT 24
    #define RID61_MASK 0x0C000000
    #define RID61_SHIFT 26
    #define RID62_MASK 0x30000000
    #define RID62_SHIFT 28
    #define RID63_MASK 0xC0000000
    #define RID63_SHIFT 30
#define  DVO_RTP_PCR_CID 0x60AC
    #define DVO_RTP_PCR_CID_PCR_CID0_MASK 0x0000003F
    #define DVO_RTP_PCR_CID_PCR_CID0_SHIFT 0
    #define DVO_RTP_PCR_CID_PCR_CID1_MASK 0x00003F00
    #define DVO_RTP_PCR_CID_PCR_CID1_SHIFT 8
    #define DVO_RTP_PCR_CID_PCR_CID2_MASK 0x003F0000
    #define DVO_RTP_PCR_CID_PCR_CID2_SHIFT 16
    #define DVO_RTP_PCR_CID_PCR_CID3_MASK 0x3F000000
    #define DVO_RTP_PCR_CID_PCR_CID3_SHIFT 24
#define  ENC_BWD_C_ADR 0x7410
    #define ENC_BWD_C_ADR_BASE_MASK 0x7FFFE000
    #define ENC_BWD_C_ADR_BASE_SHIFT 13
#define  ENC_BWD_Y_ADR 0x740C
    #define ENC_BWD_Y_ADR_BASE_MASK 0x7FFFE000
    #define ENC_BWD_Y_ADR_BASE_SHIFT 13
#define  ENC_CANDIDATE_COUNT 0x72C0
    #define ENC_CANDIDATE_COUNT_VALUE_MASK 0x0001FFFF
    #define ENC_CANDIDATE_COUNT_VALUE_SHIFT 0
#define  ENC_CTRL 0x73F0
    #define ENC_CTRL_MISMATCH_MASK 0x00000001
    #define ENC_CTRL_MISMATCH_SHIFT 0
    #define ENC_CTRL_SCAN_ORDER_MASK 0x0000000C
    #define ENC_CTRL_SCAN_ORDER_SHIFT 2
    #define ENC_CTRL_DC_SCALE_MASK 0x00000030
    #define ENC_CTRL_DC_SCALE_SHIFT 4
    #define ENC_CTRL_QSCALE_METHOD_MASK 0x00000040
    #define ENC_CTRL_QSCALE_METHOD_SHIFT 6
    #define ENC_CTRL_QSCALE_TYPE_MASK 0x00000080
    #define ENC_CTRL_QSCALE_TYPE_SHIFT 7
    #define ENC_CTRL_SATURATE_MASK 0x00000F00
    #define ENC_CTRL_SATURATE_SHIFT 8
    #define RFM_DIS_MASK 0x00010000
    #define RFM_DIS_SHIFT 16
#define  ENC_CUR_CR_ADR 0x7424
    #define ENC_CUR_CR_ADR_BASE_MASK 0x7FFFE000
    #define ENC_CUR_CR_ADR_BASE_SHIFT 13
#define  ENC_CUR_CR_BOT_ADR 0x7428
    #define ENC_CUR_CR_BOT_ADR_BASE_MASK 0x7FFFE000
    #define ENC_CUR_CR_BOT_ADR_BASE_SHIFT 13
#define  ENC_CUR_C_ADR 0x7400
    #define ENC_CUR_C_ADR_BASE_MASK 0x7FFFE000
    #define ENC_CUR_C_ADR_BASE_SHIFT 13
#define  ENC_CUR_C_BOT_ADR 0x7420
    #define ENC_CUR_C_BOT_ADR_BASE_MASK 0x7FFFE000
    #define ENC_CUR_C_BOT_ADR_BASE_SHIFT 13
#define  ENC_CUR_Y_ADR 0x73FC
    #define ENC_CUR_Y_ADR_BASE_MASK 0x7FFFE000
    #define ENC_CUR_Y_ADR_BASE_SHIFT 13
#define  ENC_CUR_Y_BOT_ADR 0x741C
    #define ENC_CUR_Y_BOT_ADR_BASE_MASK 0x7FFFE000
    #define ENC_CUR_Y_BOT_ADR_BASE_SHIFT 13
#define  ENC_FULL_COUNT 0x72C8
    #define ENC_FULL_COUNT_VALUE_MASK 0x00003FFF
    #define ENC_FULL_COUNT_VALUE_SHIFT 0
#define  ENC_FWD_C_ADR 0x7408
    #define ENC_FWD_C_ADR_BASE_MASK 0x7FFFE000
    #define ENC_FWD_C_ADR_BASE_SHIFT 13
#define  ENC_FWD_Y_ADR 0x7404
    #define ENC_FWD_Y_ADR_BASE_MASK 0x7FFFE000
    #define ENC_FWD_Y_ADR_BASE_SHIFT 13
#define  ENC_INT 0x74D4
    #define ENC_INTERRUPT_MASK 0x00000001
    #define ENC_INTERRUPT_SHIFT 0
#define  ENC_INTRA_COUNT 0x72B8
    #define ENC_INTRA_COUNT_VALUE_MASK 0x00003FFF
    #define ENC_INTRA_COUNT_VALUE_SHIFT 0
#define  ENC_INT_CTRL 0x74D8
    #define ENC_INT_MIPS_EN_MASK 0x00000001
    #define ENC_INT_MIPS_EN_SHIFT 0
    #define ENC_INT_HOST_EN_MASK 0x00000002
    #define ENC_INT_HOST_EN_SHIFT 1
#define  ENC_MVA_ADR 0x7414
    #define ENC_MVA_ADR_BASE_MASK 0x7FFFFC00
    #define ENC_MVA_ADR_BASE_SHIFT 10
#define  ENC_MVA_IDX_ADR 0x7418
    #define ENC_MVA_IDX_ADR_BASE_MASK 0x7FFFFC00
    #define ENC_MVA_IDX_ADR_BASE_SHIFT 10
#define  ENC_MV_SCALE 0x73EC
    #define ENC_MV_SCALE_MV_SCL_X_MASK 0x0000FFFF
    #define ENC_MV_SCALE_MV_SCL_X_SHIFT 0
    #define ENC_MV_SCALE_MV_SCL_Y_MASK 0xFFFF0000
    #define ENC_MV_SCALE_MV_SCL_Y_SHIFT 16
#define  ENC_PART_COUNT 0x72C4
    #define ENC_PART_COUNT_VALUE_MASK 0x00003FFF
    #define ENC_PART_COUNT_VALUE_SHIFT 0
#define  ENC_PICT_INFO 0x73E0
    #define ENC_PICT_INFO_PICT_TYPE_MASK 0x00000003
    #define ENC_PICT_INFO_PICT_TYPE_SHIFT 0
    #define ENC_PICT_INFO_PICT_STRUCT_MASK 0x0000000C
    #define ENC_PICT_INFO_PICT_STRUCT_SHIFT 2
    #define ENC_PICT_INFO_MPEG_FRMT_MASK 0x00000030
    #define ENC_PICT_INFO_MPEG_FRMT_SHIFT 4
    #define CHROMA_ROUNDING_MASK 0x00000040
    #define CHROMA_ROUNDING_SHIFT 6
    #define ENC_PICT_INFO_SECOND_FLD_MASK 0x80000000
    #define ENC_PICT_INFO_SECOND_FLD_SHIFT 31
#define  ENC_PICT_SIZE 0x73E4
    #define ENC_PICT_SIZE_SLICE_SIZE_MASK 0x0000007F
    #define ENC_PICT_SIZE_SLICE_SIZE_SHIFT 0
    #define ENC_PICT_SIZE_SLICE_CNT_MASK 0x00007F00
    #define ENC_PICT_SIZE_SLICE_CNT_SHIFT 8
#define  ENC_QMATRIX_0_3_INTRA 0x7180
    #define ENC_QM0_INT_MASK 0x000000FF
    #define ENC_QM0_INT_SHIFT 0
    #define ENC_QM1_INT_MASK 0x0000FF00
    #define ENC_QM1_INT_SHIFT 8
    #define ENC_QM2_INT_MASK 0x00FF0000
    #define ENC_QM2_INT_SHIFT 16
    #define ENC_QM3_INT_MASK 0xFF000000
    #define ENC_QM3_INT_SHIFT 24
#define  ENC_QMATRIX_0_3_NONINT 0x71C0
    #define ENC_QM0_NONINT_MASK 0x000000FF
    #define ENC_QM0_NONINT_SHIFT 0
    #define ENC_QM1_NONINT_MASK 0x0000FF00
    #define ENC_QM1_NONINT_SHIFT 8
    #define ENC_QM2_NONINT_MASK 0x00FF0000
    #define ENC_QM2_NONINT_SHIFT 16
    #define ENC_QM3_NONINT_MASK 0xFF000000
    #define ENC_QM3_NONINT_SHIFT 24
#define  ENC_QMATRIX_12_15_INTRA 0x718C
    #define ENC_QM12_INT_MASK 0x000000FF
    #define ENC_QM12_INT_SHIFT 0
    #define ENC_QM13_INT_MASK 0x0000FF00
    #define ENC_QM13_INT_SHIFT 8
    #define ENC_QM14_INT_MASK 0x00FF0000
    #define ENC_QM14_INT_SHIFT 16
    #define ENC_QM15_INT_MASK 0xFF000000
    #define ENC_QM15_INT_SHIFT 24
#define  ENC_QMATRIX_12_15_NONINT 0x71CC
    #define ENC_QM12_NONINT_MASK 0x000000FF
    #define ENC_QM12_NONINT_SHIFT 0
    #define ENC_QM13_NONINT_MASK 0x0000FF00
    #define ENC_QM13_NONINT_SHIFT 8
    #define ENC_QM14_NONINT_MASK 0x00FF0000
    #define ENC_QM14_NONINT_SHIFT 16
    #define ENC_QM15_NONINT_MASK 0xFF000000
    #define ENC_QM15_NONINT_SHIFT 24
#define  ENC_QMATRIX_16_19_INTRA 0x7190
    #define ENC_QM16_INT_MASK 0x000000FF
    #define ENC_QM16_INT_SHIFT 0
    #define ENC_QM17_INT_MASK 0x0000FF00
    #define ENC_QM17_INT_SHIFT 8
    #define ENC_QM18_INT_MASK 0x00FF0000
    #define ENC_QM18_INT_SHIFT 16
    #define ENC_QM19_INT_MASK 0xFF000000
    #define ENC_QM19_INT_SHIFT 24
#define  ENC_QMATRIX_16_19_NONINT 0x71D0
    #define ENC_QM16_NONINT_MASK 0x000000FF
    #define ENC_QM16_NONINT_SHIFT 0
    #define ENC_QM17_NONINT_MASK 0x0000FF00
    #define ENC_QM17_NONINT_SHIFT 8
    #define ENC_QM18_NONINT_MASK 0x00FF0000
    #define ENC_QM18_NONINT_SHIFT 16
    #define ENC_QM19_NONINT_MASK 0xFF000000
    #define ENC_QM19_NONINT_SHIFT 24
#define  ENC_QMATRIX_20_23_INTRA 0x7194
    #define ENC_QM20_INT_MASK 0x000000FF
    #define ENC_QM20_INT_SHIFT 0
    #define ENC_QM21_INT_MASK 0x0000FF00
    #define ENC_QM21_INT_SHIFT 8
    #define ENC_QM22_INT_MASK 0x00FF0000
    #define ENC_QM22_INT_SHIFT 16
    #define ENC_QM23_INT_MASK 0xFF000000
    #define ENC_QM23_INT_SHIFT 24
#define  ENC_QMATRIX_20_23_NONINT 0x71D4
    #define ENC_QM20_NONINT_MASK 0x000000FF
    #define ENC_QM20_NONINT_SHIFT 0
    #define ENC_QM21_NONINT_MASK 0x0000FF00
    #define ENC_QM21_NONINT_SHIFT 8
    #define ENC_QM22_NONINT_MASK 0x00FF0000
    #define ENC_QM22_NONINT_SHIFT 16
    #define ENC_QM23_NONINT_MASK 0xFF000000
    #define ENC_QM23_NONINT_SHIFT 24
#define  ENC_QMATRIX_24_27_INTRA 0x7198
    #define ENC_QM24_INT_MASK 0x000000FF
    #define ENC_QM24_INT_SHIFT 0
    #define ENC_QM25_INT_MASK 0x0000FF00
    #define ENC_QM25_INT_SHIFT 8
    #define ENC_QM26_INT_MASK 0x00FF0000
    #define ENC_QM26_INT_SHIFT 16
    #define ENC_QM27_INT_MASK 0xFF000000
    #define ENC_QM27_INT_SHIFT 24
#define  ENC_QMATRIX_24_27_NONINT 0x71D8
    #define ENC_QM24_NONINT_MASK 0x000000FF
    #define ENC_QM24_NONINT_SHIFT 0
    #define ENC_QM25_NONINT_MASK 0x0000FF00
    #define ENC_QM25_NONINT_SHIFT 8
    #define ENC_QM26_NONINT_MASK 0x00FF0000
    #define ENC_QM26_NONINT_SHIFT 16
    #define ENC_QM27_NONINT_MASK 0xFF000000
    #define ENC_QM27_NONINT_SHIFT 24
#define  ENC_QMATRIX_28_31_INTRA 0x719C
    #define ENC_QM28_INT_MASK 0x000000FF
    #define ENC_QM28_INT_SHIFT 0
    #define ENC_QM29_INT_MASK 0x0000FF00
    #define ENC_QM29_INT_SHIFT 8
    #define ENC_QM30_INT_MASK 0x00FF0000
    #define ENC_QM30_INT_SHIFT 16
    #define ENC_QM31_INT_MASK 0xFF000000
    #define ENC_QM31_INT_SHIFT 24
#define  ENC_QMATRIX_28_31_NONINT 0x71DC
    #define ENC_QM28_NONINT_MASK 0x000000FF
    #define ENC_QM28_NONINT_SHIFT 0
    #define ENC_QM29_NONINT_MASK 0x0000FF00
    #define ENC_QM29_NONINT_SHIFT 8
    #define ENC_QM30_NONINT_MASK 0x00FF0000
    #define ENC_QM30_NONINT_SHIFT 16
    #define ENC_QM31_NONINT_MASK 0xFF000000
    #define ENC_QM31_NONINT_SHIFT 24
#define  ENC_QMATRIX_32_35_INTRA 0x71A0
    #define ENC_QM32_INT_MASK 0x000000FF
    #define ENC_QM32_INT_SHIFT 0
    #define ENC_QM33_INT_MASK 0x0000FF00
    #define ENC_QM33_INT_SHIFT 8
    #define ENC_QM34_INT_MASK 0x00FF0000
    #define ENC_QM34_INT_SHIFT 16
    #define ENC_QM35_INT_MASK 0xFF000000
    #define ENC_QM35_INT_SHIFT 24
#define  ENC_QMATRIX_32_35_NONINT 0x71E0
    #define ENC_QM32_NONINT_MASK 0x000000FF
    #define ENC_QM32_NONINT_SHIFT 0
    #define ENC_QM33_NONINT_MASK 0x0000FF00
    #define ENC_QM33_NONINT_SHIFT 8
    #define ENC_QM34_NONINT_MASK 0x00FF0000
    #define ENC_QM34_NONINT_SHIFT 16
    #define ENC_QM35_NONINT_MASK 0xFF000000
    #define ENC_QM35_NONINT_SHIFT 24
#define  ENC_QMATRIX_36_39_INTRA 0x71A4
    #define ENC_QM36_INT_MASK 0x000000FF
    #define ENC_QM36_INT_SHIFT 0
    #define ENC_QM37_INT_MASK 0x0000FF00
    #define ENC_QM37_INT_SHIFT 8
    #define ENC_QM38_INT_MASK 0x00FF0000
    #define ENC_QM38_INT_SHIFT 16
    #define ENC_QM39_INT_MASK 0xFF000000
    #define ENC_QM39_INT_SHIFT 24
#define  ENC_QMATRIX_36_39_NONINT 0x71E4
    #define ENC_QM36_NONINT_MASK 0x000000FF
    #define ENC_QM36_NONINT_SHIFT 0
    #define ENC_QM37_NONINT_MASK 0x0000FF00
    #define ENC_QM37_NONINT_SHIFT 8
    #define ENC_QM38_NONINT_MASK 0x00FF0000
    #define ENC_QM38_NONINT_SHIFT 16
    #define ENC_QM39_NONINT_MASK 0xFF000000
    #define ENC_QM39_NONINT_SHIFT 24
#define  ENC_QMATRIX_40_43_INTRA 0x71A8
    #define ENC_QM40_INT_MASK 0x000000FF
    #define ENC_QM40_INT_SHIFT 0
    #define ENC_QM41_INT_MASK 0x0000FF00
    #define ENC_QM41_INT_SHIFT 8
    #define ENC_QM42_INT_MASK 0x00FF0000
    #define ENC_QM42_INT_SHIFT 16
    #define ENC_QM43_INT_MASK 0xFF000000
    #define ENC_QM43_INT_SHIFT 24
#define  ENC_QMATRIX_40_43_NONINT 0x71E8
    #define ENC_QM40_NONINT_MASK 0x000000FF
    #define ENC_QM40_NONINT_SHIFT 0
    #define ENC_QM41_NONINT_MASK 0x0000FF00
    #define ENC_QM41_NONINT_SHIFT 8
    #define ENC_QM42_NONINT_MASK 0x00FF0000
    #define ENC_QM42_NONINT_SHIFT 16
    #define ENC_QM43_NONINT_MASK 0xFF000000
    #define ENC_QM43_NONINT_SHIFT 24
#define  ENC_QMATRIX_44_47_INTRA 0x71AC
    #define ENC_QM44_INT_MASK 0x000000FF
    #define ENC_QM44_INT_SHIFT 0
    #define ENC_QM45_INT_MASK 0x0000FF00
    #define ENC_QM45_INT_SHIFT 8
    #define ENC_QM46_INT_MASK 0x00FF0000
    #define ENC_QM46_INT_SHIFT 16
    #define ENC_QM47_INT_MASK 0xFF000000
    #define ENC_QM47_INT_SHIFT 24
#define  ENC_QMATRIX_44_47_NONINT 0x71EC
    #define ENC_QM44_NONINT_MASK 0x000000FF
    #define ENC_QM44_NONINT_SHIFT 0
    #define ENC_QM45_NONINT_MASK 0x0000FF00
    #define ENC_QM45_NONINT_SHIFT 8
    #define ENC_QM46_NONINT_MASK 0x00FF0000
    #define ENC_QM46_NONINT_SHIFT 16
    #define ENC_QM47_NONINT_MASK 0xFF000000
    #define ENC_QM47_NONINT_SHIFT 24
#define  ENC_QMATRIX_48_51_INTRA 0x71B0
    #define ENC_QM48_INT_MASK 0x000000FF
    #define ENC_QM48_INT_SHIFT 0
    #define ENC_QM49_INT_MASK 0x0000FF00
    #define ENC_QM49_INT_SHIFT 8
    #define ENC_QM50_INT_MASK 0x00FF0000
    #define ENC_QM50_INT_SHIFT 16
    #define ENC_QM51_INT_MASK 0xFF000000
    #define ENC_QM51_INT_SHIFT 24
#define  ENC_QMATRIX_48_51_NONINT 0x71F0
    #define ENC_QM48_NONINT_MASK 0x000000FF
    #define ENC_QM48_NONINT_SHIFT 0
    #define ENC_QM49_NONINT_MASK 0x0000FF00
    #define ENC_QM49_NONINT_SHIFT 8
    #define ENC_QM50_NONINT_MASK 0x00FF0000
    #define ENC_QM50_NONINT_SHIFT 16
    #define ENC_QM51_NONINT_MASK 0xFF000000
    #define ENC_QM51_NONINT_SHIFT 24
#define  ENC_QMATRIX_4_7_INTRA 0x7184
    #define ENC_QM4_INT_MASK 0x000000FF
    #define ENC_QM4_INT_SHIFT 0
    #define ENC_QM5_INT_MASK 0x0000FF00
    #define ENC_QM5_INT_SHIFT 8
    #define ENC_QM6_INT_MASK 0x00FF0000
    #define ENC_QM6_INT_SHIFT 16
    #define ENC_QM7_INT_MASK 0xFF000000
    #define ENC_QM7_INT_SHIFT 24
#define  ENC_QMATRIX_4_7_NONINT 0x71C4
    #define ENC_QM4_NONINT_MASK 0x000000FF
    #define ENC_QM4_NONINT_SHIFT 0
    #define ENC_QM5_NONINT_MASK 0x0000FF00
    #define ENC_QM5_NONINT_SHIFT 8
    #define ENC_QM6_NONINT_MASK 0x00FF0000
    #define ENC_QM6_NONINT_SHIFT 16
    #define ENC_QM7_NONINT_MASK 0xFF000000
    #define ENC_QM7_NONINT_SHIFT 24
#define  ENC_QMATRIX_52_55_INTRA 0x71B4
    #define ENC_QM52_INT_MASK 0x000000FF
    #define ENC_QM52_INT_SHIFT 0
    #define ENC_QM53_INT_MASK 0x0000FF00
    #define ENC_QM53_INT_SHIFT 8
    #define ENC_QM54_INT_MASK 0x00FF0000
    #define ENC_QM54_INT_SHIFT 16
    #define ENC_QM55_INT_MASK 0xFF000000
    #define ENC_QM55_INT_SHIFT 24
#define  ENC_QMATRIX_52_55_NONINT 0x71F4
    #define ENC_QM52_NONINT_MASK 0x000000FF
    #define ENC_QM52_NONINT_SHIFT 0
    #define ENC_QM53_NONINT_MASK 0x0000FF00
    #define ENC_QM53_NONINT_SHIFT 8
    #define ENC_QM54_NONINT_MASK 0x00FF0000
    #define ENC_QM54_NONINT_SHIFT 16
    #define ENC_QM55_NONINT_MASK 0xFF000000
    #define ENC_QM55_NONINT_SHIFT 24
#define  ENC_QMATRIX_56_59_INTRA 0x71B8
    #define ENC_QM56_INT_MASK 0x000000FF
    #define ENC_QM56_INT_SHIFT 0
    #define ENC_QM57_INT_MASK 0x0000FF00
    #define ENC_QM57_INT_SHIFT 8
    #define ENC_QM58_INT_MASK 0x00FF0000
    #define ENC_QM58_INT_SHIFT 16
    #define ENC_QM59_INT_MASK 0xFF000000
    #define ENC_QM59_INT_SHIFT 24
#define  ENC_QMATRIX_56_59_NONINT 0x71F8
    #define ENC_QM56_NONINT_MASK 0x000000FF
    #define ENC_QM56_NONINT_SHIFT 0
    #define ENC_QM57_NONINT_MASK 0x0000FF00
    #define ENC_QM57_NONINT_SHIFT 8
    #define ENC_QM58_NONINT_MASK 0x00FF0000
    #define ENC_QM58_NONINT_SHIFT 16
    #define ENC_QM59_NONINT_MASK 0xFF000000
    #define ENC_QM59_NONINT_SHIFT 24
#define  ENC_QMATRIX_60_63_INTRA 0x71BC
    #define ENC_QM60_INT_MASK 0x000000FF
    #define ENC_QM60_INT_SHIFT 0
    #define ENC_QM61_INT_MASK 0x0000FF00
    #define ENC_QM61_INT_SHIFT 8
    #define ENC_QM62_INT_MASK 0x00FF0000
    #define ENC_QM62_INT_SHIFT 16
    #define ENC_QM63_INT_MASK 0xFF000000
    #define ENC_QM63_INT_SHIFT 24
#define  ENC_QMATRIX_60_63_NONINT 0x71FC
    #define ENC_QM60_NONINT_MASK 0x000000FF
    #define ENC_QM60_NONINT_SHIFT 0
    #define ENC_QM61_NONINT_MASK 0x0000FF00
    #define ENC_QM61_NONINT_SHIFT 8
    #define ENC_QM62_NONINT_MASK 0x00FF0000
    #define ENC_QM62_NONINT_SHIFT 16
    #define ENC_QM63_NONINT_MASK 0xFF000000
    #define ENC_QM63_NONINT_SHIFT 24
#define  ENC_QMATRIX_8_11_INTRA 0x7188
    #define ENC_QM8_INT_MASK 0x000000FF
    #define ENC_QM8_INT_SHIFT 0
    #define ENC_QM9_INT_MASK 0x0000FF00
    #define ENC_QM9_INT_SHIFT 8
    #define ENC_QM10_INT_MASK 0x00FF0000
    #define ENC_QM10_INT_SHIFT 16
    #define ENC_QM11_INT_MASK 0xFF000000
    #define ENC_QM11_INT_SHIFT 24
#define  ENC_QMATRIX_8_11_NONINT 0x71C8
    #define ENC_QM8_NONINT_MASK 0x000000FF
    #define ENC_QM8_NONINT_SHIFT 0
    #define ENC_QM9_NONINT_MASK 0x0000FF00
    #define ENC_QM9_NONINT_SHIFT 8
    #define ENC_QM10_NONINT_MASK 0x00FF0000
    #define ENC_QM10_NONINT_SHIFT 16
    #define ENC_QM11_NONINT_MASK 0xFF000000
    #define ENC_QM11_NONINT_SHIFT 24
#define  ENC_RARB_CTRL 0x74B0
    #define RCB_TIMER_MASK 0x0000000F
    #define RCB_TIMER_SHIFT 0
    #define IDX_TIMER_MASK 0x000000F0
    #define IDX_TIMER_SHIFT 4
    #define MVA_TIMER_MASK 0x00000F00
    #define MVA_TIMER_SHIFT 8
    #define CCUR_TIMER_MASK 0x0000F000
    #define CCUR_TIMER_SHIFT 12
    #define YCUR_TIMER_MASK 0x000F0000
    #define YCUR_TIMER_SHIFT 16
    #define CCACHE_TIMER_MASK 0x00F00000
    #define CCACHE_TIMER_SHIFT 20
    #define YCACHE_TIMER_MASK 0x0F000000
    #define YCACHE_TIMER_SHIFT 24
#define  ENC_STATION_COUNT 0x72BC
    #define ENC_STATION_COUNT_VALUE_MASK 0x00003FFF
    #define ENC_STATION_COUNT_VALUE_SHIFT 0
#define  ENC_SURF_SIZE 0x73E8
    #define ENC_SURF_SIZE_PITCH_MASK 0x00000FC0
    #define ENC_SURF_SIZE_PITCH_SHIFT 6
#define  ENC_WARB_CTRL 0x74B4
    #define RFM_TIMER_MASK 0x0000000F
    #define RFM_TIMER_SHIFT 0
    #define OSF_TIMER_MASK 0x000000F0
    #define OSF_TIMER_SHIFT 4
    #define RMV_TIMER_MASK 0x00000F00
    #define RMV_TIMER_SHIFT 8
#define  ENGCTRL_CUR_ADR 0x7094
    #define ENGCTRL_CUR_BASE_MASK 0x00000FFC
    #define ENGCTRL_CUR_BASE_SHIFT 2
#define  ENGCTRL_CUR_DATA 0x7098
    #define ENGCTRL_CUR_DATA_MASK 0xFFFFFFFF
    #define ENGCTRL_CUR_DATA_SHIFT 0
#define  ENGCTRL_REG_CHAIN 0x709C
    #define REGBUS_SETTLE_SEL_MASK 0x00000007
    #define REGBUS_SETTLE_SEL_SHIFT 0
#define  ETH_CSR_CTRL_REG 0x2800
    #define ETH_CSR_CTRL_REG_ADDR_MASK 0x00001FFC
    #define ETH_CSR_CTRL_REG_ADDR_SHIFT 2
    #define ETH_CSR_CTRL_REG_WOP_MASK 0x80000000
    #define ETH_CSR_CTRL_REG_WOP_SHIFT 31
#define  ETH_CTRL_REG 0x2810
    #define ETH_CTRL_REG_RESETN_MASK 0x00000001
    #define ETH_CTRL_REG_RESETN_SHIFT 0
    #define TX_NEGEDGE_MASK 0x00000002
    #define TX_NEGEDGE_SHIFT 1
    #define RX_NEGEDGE_MASK 0x00000004
    #define RX_NEGEDGE_SHIFT 2
    #define SBD_FLOWCTRL_MASK 0x00000008
    #define SBD_FLOWCTRL_SHIFT 3
    #define ETH_CTRL_REG_EXT_MEM_ARB_TIMER_MASK 0x000000F0
    #define ETH_CTRL_REG_EXT_MEM_ARB_TIMER_SHIFT 4
    #define ETH_CTRL_REG_PF_ARB_DIS_MASK 0x00000100
    #define ETH_CTRL_REG_PF_ARB_DIS_SHIFT 8
    #define ETH_CTRL_REG_ABS_PRIORITY_MASK 0x00000200
    #define ETH_CTRL_REG_ABS_PRIORITY_SHIFT 9
#define  ETH_DEBUG_REG 0x2824
    #define ETH_DEBUG_REG_DEBUG_DATA_MASK 0xFFFFFFFF
    #define ETH_DEBUG_REG_DEBUG_DATA_SHIFT 0
#define  ETH_DUMMY_REG 0x2820
    #define ETH_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define ETH_DUMMY_REG_DATA_SHIFT 0
#define  ETH_HOST_INT_MASK_REG 0x2818
    #define ETH_HOST_INT_MASK_REG_PMT_INTR_EN_MASK 0x00000001
    #define ETH_HOST_INT_MASK_REG_PMT_INTR_EN_SHIFT 0
    #define ETH_HOST_INT_MASK_REG_SBD_INTR_EN_MASK 0x00000002
    #define ETH_HOST_INT_MASK_REG_SBD_INTR_EN_SHIFT 1
#define  ETH_INT_STATUS_REG 0x2814
    #define PMT_INTR_STATUS_MASK 0x00000001
    #define PMT_INTR_STATUS_SHIFT 0
    #define SBD_INTR_STATUS_MASK 0x00000002
    #define SBD_INTR_STATUS_SHIFT 1
#define  ETH_MIPS_INT_MASK_REG 0x281C
    #define ETH_MIPS_INT_MASK_REG_PMT_INTR_EN_MASK 0x00000001
    #define ETH_MIPS_INT_MASK_REG_PMT_INTR_EN_SHIFT 0
    #define ETH_MIPS_INT_MASK_REG_SBD_INTR_EN_MASK 0x00000002
    #define ETH_MIPS_INT_MASK_REG_SBD_INTR_EN_SHIFT 1
#define  ETH_RDAT_REG 0x280C
    #define READ_MASK 0xFFFFFFFF
    #define READ_SHIFT 0
#define  ETH_STATUS_REG 0x2804
    #define ETH_STATUS_REG_CSR_BUSY_MASK 0x00000001
    #define ETH_STATUS_REG_CSR_BUSY_SHIFT 0
#define  ETH_WDAT_REG 0x2808
    #define WRITE_MASK 0xFFFFFFFF
    #define WRITE_SHIFT 0
#define  FES0_ALPHA_MODE_SRC1 0xD4E4
    #define FES0_SRC1_ALPHA_MODE_MASK 0x00000003
    #define FES0_SRC1_ALPHA_MODE_SHIFT 0
    #define FES0_SRC1_ALPHA_C_MASK 0x0000FF00
    #define FES0_SRC1_ALPHA_C_SHIFT 8
#define  FES0_CF_MEM0 0xD4DC
    #define FES0_CMD_LIST_BASE_ADR_MASK 0x7FFFFFF0
    #define FES0_CMD_LIST_BASE_ADR_SHIFT 4
#define  FES0_CF_MEM1 0xD4E0
    #define FES0_CMD_LIST_LENGTH_MASK 0x000000FF
    #define FES0_CMD_LIST_LENGTH_SHIFT 0
#define  FES0_CMD_FIFO_0 0xD440
    #define FES0_CMD_DATA_MASK 0xFFFFFFFF
    #define FES0_CMD_DATA_SHIFT 0
#define  FES0_CMD_FIFO_1 0xD444
    #define FES0_CMD_ADR_MASK 0x0000FFFF
    #define FES0_CMD_ADR_SHIFT 0
#define  FES0_CONFIG_CTRL 0xD448
    #define FES0_CSC_EN_MASK 0x00000001
    #define FES0_CSC_EN_SHIFT 0
    #define FES0_ALPHA_PREMUL_EN_MASK 0x00000010
    #define FES0_ALPHA_PREMUL_EN_SHIFT 4
    #define FES0_MLUT_BYPASS_MASK 0x00000100
    #define FES0_MLUT_BYPASS_SHIFT 8
    #define FES0_SRC_MLUT_HZ_PROG_EN_MASK 0x00000C00
    #define FES0_SRC_MLUT_HZ_PROG_EN_SHIFT 10
    #define FES0_SRC_MLUT_VL_PROG_EN_MASK 0x00003000
    #define FES0_SRC_MLUT_VL_PROG_EN_SHIFT 12
    #define FES0_MLUT_ADRMODE_MASK 0x00004000
    #define FES0_MLUT_ADRMODE_SHIFT 14
    #define FES0_CF_FLUSH_MASK 0x00010000
    #define FES0_CF_FLUSH_SHIFT 16
    #define FES0_INT_EN_MASK 0x01000000
    #define FES0_INT_EN_SHIFT 24
    #define FES0_OP_KICKOFF_MASK 0x80000000
    #define FES0_OP_KICKOFF_SHIFT 31
#define  FES0_CSC_PARM0 0xD4B8
    #define FES0_C00_MASK 0x0000FFFF
    #define FES0_C00_SHIFT 0
    #define FES0_C01_MASK 0xFFFF0000
    #define FES0_C01_SHIFT 16
#define  FES0_CSC_PARM1 0xD4BC
    #define FES0_C02_MASK 0x0000FFFF
    #define FES0_C02_SHIFT 0
    #define FES0_C10_MASK 0xFFFF0000
    #define FES0_C10_SHIFT 16
#define  FES0_CSC_PARM2 0xD4C0
    #define FES0_C11_MASK 0x0000FFFF
    #define FES0_C11_SHIFT 0
    #define FES0_C12_MASK 0xFFFF0000
    #define FES0_C12_SHIFT 16
#define  FES0_CSC_PARM3 0xD4C4
    #define FES0_C20_MASK 0x0000FFFF
    #define FES0_C20_SHIFT 0
    #define FES0_C21_MASK 0xFFFF0000
    #define FES0_C21_SHIFT 16
#define  FES0_CSC_PARM4 0xD4C8
    #define FES0_C22_MASK 0x0000FFFF
    #define FES0_C22_SHIFT 0
    #define FES0_OYR_MASK 0x03FF0000
    #define FES0_OYR_SHIFT 16
#define  FES0_CSC_PARM5 0xD4CC
    #define FES0_OUG_MASK 0x000003FF
    #define FES0_OUG_SHIFT 0
    #define FES0_OVB_MASK 0x03FF0000
    #define FES0_OVB_SHIFT 16
#define  FES0_CSC_PARM6 0xD4D0
    #define FES0_RY_MIN_MASK 0x000000FF
    #define FES0_RY_MIN_SHIFT 0
    #define FES0_RY_MAX_MASK 0x0000FF00
    #define FES0_RY_MAX_SHIFT 8
    #define FES0_UG_MIN_MASK 0x00FF0000
    #define FES0_UG_MIN_SHIFT 16
    #define FES0_UG_MAX_MASK 0xFF000000
    #define FES0_UG_MAX_SHIFT 24
#define  FES0_CSC_PARM7 0xD4D4
    #define FES0_VB_MIN_MASK 0x000000FF
    #define FES0_VB_MIN_SHIFT 0
    #define FES0_VB_MAX_MASK 0x0000FF00
    #define FES0_VB_MAX_SHIFT 8
#define  FES0_DST_ADR0 0xD474
    #define FES0_DST_BASE_MASK 0x7FFFFFE0
    #define FES0_DST_BASE_SHIFT 5
#define  FES0_DST_ADR1 0xD478
    #define FES0_DST_U_BASE_MASK 0x7FFFFFE0
    #define FES0_DST_U_BASE_SHIFT 5
#define  FES0_DST_ADR2 0xD47C
    #define FES0_DST_V_BASE_MASK 0x7FFFFFE0
    #define FES0_DST_V_BASE_SHIFT 5
#define  FES0_DST_H_W 0xD488
    #define FES0_DST_W_MASK 0x00007FFF
    #define FES0_DST_W_SHIFT 0
    #define FES0_DST_H_MASK 0x7FFF0000
    #define FES0_DST_H_SHIFT 16
#define  FES0_DST_MODE 0xD480
    #define FES0_DST_FMT_MASK 0x0000000F
    #define FES0_DST_FMT_SHIFT 0
    #define FES0_DST_FLD_SEL_MASK 0x00000040
    #define FES0_DST_FLD_SEL_SHIFT 6
    #define FES0_DST_PLANAR_MODE_MASK 0x000C0000
    #define FES0_DST_PLANAR_MODE_SHIFT 18
    #define FES0_DST_ALPHA_THRES_MASK 0xFF000000
    #define FES0_DST_ALPHA_THRES_SHIFT 24
#define  FES0_DST_PITCH 0xD484
    #define FES0_DST_PITCH_MASK 0x0000FFE0
    #define FES0_DST_PITCH_SHIFT 5
    #define FES0_DST_UV_PITCH_MASK 0xFFE00000
    #define FES0_DST_UV_PITCH_SHIFT 21
#define  FES0_DST_SUBFLD 0xD490
    #define FES0_DST_SUBFLD_W_MASK 0x000007FF
    #define FES0_DST_SUBFLD_W_SHIFT 0
#define  FES0_DST_UV_H_W 0xD48C
    #define FES0_DST_UV_W_MASK 0x00007FFF
    #define FES0_DST_UV_W_SHIFT 0
    #define FES0_DST_UV_H_MASK 0x7FFF0000
    #define FES0_DST_UV_H_SHIFT 16
#define  FES0_DUMMY_REG 0xD4F4
    #define FES0_DUMMY_BITS_MASK 0xFFFFFFFF
    #define FES0_DUMMY_BITS_SHIFT 0
#define  FES0_LUT_ADR 0xD4F0
    #define FES0_LUT_ADR_MASK 0x0000003F
    #define FES0_LUT_ADR_SHIFT 0
#define  FES0_LUT_PROGM 0xD4D8
    #define FES0_LUT_DATA_MASK 0xFFFFFFFF
    #define FES0_LUT_DATA_SHIFT 0
#define  FES0_NUMTAPS_HELD 0xD4B4
    #define FES0_HTAPS_MASK 0x000000FF
    #define FES0_HTAPS_SHIFT 0
    #define FES0_VTAPS_MASK 0x0000FF00
    #define FES0_VTAPS_SHIFT 8
    #define FES0_HTAPS_UV_MASK 0x00FF0000
    #define FES0_HTAPS_UV_SHIFT 16
    #define FES0_VTAPS_UV_MASK 0xFF000000
    #define FES0_VTAPS_UV_SHIFT 24
#define  FES0_POSREG0_INIT 0xD4A4
    #define FES0_POSREG0_INIT_FES0_POSREG_INIT_H_MASK 0x0000FFFF
    #define FES0_POSREG0_INIT_FES0_POSREG_INIT_H_SHIFT 0
    #define FES0_POSREG0_INIT_FES0_POSREG_INIT_V_MASK 0xFFFF0000
    #define FES0_POSREG0_INIT_FES0_POSREG_INIT_V_SHIFT 16
#define  FES0_POSREG0_UV_INIT 0xD4A8
    #define FES0_POSREG0_UV_INIT_FES0_POSREG_INIT_H_MASK 0x0000FFFF
    #define FES0_POSREG0_UV_INIT_FES0_POSREG_INIT_H_SHIFT 0
    #define FES0_POSREG0_UV_INIT_FES0_POSREG_INIT_V_MASK 0xFFFF0000
    #define FES0_POSREG0_UV_INIT_FES0_POSREG_INIT_V_SHIFT 16
#define  FES0_POSREG1_INIT 0xD4AC
    #define FES0_POSREG1_INIT_FES0_POSREG_INIT_H_MASK 0x0000FFFF
    #define FES0_POSREG1_INIT_FES0_POSREG_INIT_H_SHIFT 0
    #define FES0_POSREG1_INIT_FES0_POSREG_INIT_V_MASK 0xFFFF0000
    #define FES0_POSREG1_INIT_FES0_POSREG_INIT_V_SHIFT 16
#define  FES0_POSREG1_UV_INIT 0xD4B0
    #define FES0_POSREG1_UV_INIT_FES0_POSREG_INIT_H_MASK 0x0000FFFF
    #define FES0_POSREG1_UV_INIT_FES0_POSREG_INIT_H_SHIFT 0
    #define FES0_POSREG1_UV_INIT_FES0_POSREG_INIT_V_MASK 0xFFFF0000
    #define FES0_POSREG1_UV_INIT_FES0_POSREG_INIT_V_SHIFT 16
#define  FES0_SRC12_ADR0 0xD458
    #define FES0_SRC12_ADR0_FES0_SRC1_BASE_MASK 0x7FFFFFE0
    #define FES0_SRC12_ADR0_FES0_SRC1_BASE_SHIFT 5
#define  FES0_SRC12_ADR1 0xD45C
    #define FES0_SRC12_ADR1_FES0_SRC1_U_BASE_MASK 0x7FFFFFE0
    #define FES0_SRC12_ADR1_FES0_SRC1_U_BASE_SHIFT 5
#define  FES0_SRC12_ADR2 0xD460
    #define FES0_SRC12_ADR2_FES0_SRC1_V_BASE_MASK 0x7FFFFFE0
    #define FES0_SRC12_ADR2_FES0_SRC1_V_BASE_SHIFT 5
#define  FES0_SRC1_ADR0 0xD44C
    #define FES0_SRC1_ADR0_FES0_SRC1_BASE_MASK 0x7FFFFFE0
    #define FES0_SRC1_ADR0_FES0_SRC1_BASE_SHIFT 5
#define  FES0_SRC1_ADR1 0xD450
    #define FES0_SRC1_ADR1_FES0_SRC1_U_BASE_MASK 0x7FFFFFE0
    #define FES0_SRC1_ADR1_FES0_SRC1_U_BASE_SHIFT 5
#define  FES0_SRC1_ADR2 0xD454
    #define FES0_SRC1_ADR2_FES0_SRC1_V_BASE_MASK 0x7FFFFFE0
    #define FES0_SRC1_ADR2_FES0_SRC1_V_BASE_SHIFT 5
#define  FES0_SRC1_FOLDH_GB_UV 0xD504
    #define FES0_SRC1_FOLDH_GB_UV_FES0_MAX_PHASE_MASK 0x0000007F
    #define FES0_SRC1_FOLDH_GB_UV_FES0_MAX_PHASE_SHIFT 0
    #define FES0_SRC1_FOLDH_GB_UV_FES0_TRIG_PHASE_MASK 0x00007F00
    #define FES0_SRC1_FOLDH_GB_UV_FES0_TRIG_PHASE_SHIFT 8
    #define FES0_SRC1_FOLDH_GB_UV_FES0_ROUND_POSREG_MASK 0x00010000
    #define FES0_SRC1_FOLDH_GB_UV_FES0_ROUND_POSREG_SHIFT 16
#define  FES0_SRC1_FOLDH_R_Y 0xD4FC
    #define FES0_SRC1_FOLDH_R_Y_FES0_MAX_PHASE_MASK 0x0000007F
    #define FES0_SRC1_FOLDH_R_Y_FES0_MAX_PHASE_SHIFT 0
    #define FES0_SRC1_FOLDH_R_Y_FES0_TRIG_PHASE_MASK 0x00007F00
    #define FES0_SRC1_FOLDH_R_Y_FES0_TRIG_PHASE_SHIFT 8
    #define FES0_SRC1_FOLDH_R_Y_FES0_ROUND_POSREG_MASK 0x00010000
    #define FES0_SRC1_FOLDH_R_Y_FES0_ROUND_POSREG_SHIFT 16
#define  FES0_SRC1_FOLDV_GB_UV 0xD500
    #define FES0_SRC1_FOLDV_GB_UV_FES0_MAX_PHASE_MASK 0x0000007F
    #define FES0_SRC1_FOLDV_GB_UV_FES0_MAX_PHASE_SHIFT 0
    #define FES0_SRC1_FOLDV_GB_UV_FES0_TRIG_PHASE_MASK 0x00007F00
    #define FES0_SRC1_FOLDV_GB_UV_FES0_TRIG_PHASE_SHIFT 8
    #define FES0_SRC1_FOLDV_GB_UV_FES0_ROUND_POSREG_MASK 0x00010000
    #define FES0_SRC1_FOLDV_GB_UV_FES0_ROUND_POSREG_SHIFT 16
#define  FES0_SRC1_FOLDV_R_Y 0xD4F8
    #define FES0_SRC1_FOLDV_R_Y_FES0_MAX_PHASE_MASK 0x0000007F
    #define FES0_SRC1_FOLDV_R_Y_FES0_MAX_PHASE_SHIFT 0
    #define FES0_SRC1_FOLDV_R_Y_FES0_TRIG_PHASE_MASK 0x00007F00
    #define FES0_SRC1_FOLDV_R_Y_FES0_TRIG_PHASE_SHIFT 8
    #define FES0_SRC1_FOLDV_R_Y_FES0_ROUND_POSREG_MASK 0x00010000
    #define FES0_SRC1_FOLDV_R_Y_FES0_ROUND_POSREG_SHIFT 16
#define  FES0_SRC1_H_W 0xD46C
    #define FES0_SRC1_W_MASK 0x00007FFF
    #define FES0_SRC1_W_SHIFT 0
    #define FES0_SRC1_H_MASK 0x7FFF0000
    #define FES0_SRC1_H_SHIFT 16
#define  FES0_SRC1_MODE 0xD464
    #define FES0_SRC1_FMT_MASK 0x0000000F
    #define FES0_SRC1_FMT_SHIFT 0
    #define FES0_SRC1_MEM_TILE_MASK 0x00000030
    #define FES0_SRC1_MEM_TILE_SHIFT 4
    #define FES0_SRC1_FLD_SEQ_MASK 0x00000040
    #define FES0_SRC1_FLD_SEQ_SHIFT 6
    #define FES0_SRC1_DEINT_MODE_MASK 0x00000080
    #define FES0_SRC1_DEINT_MODE_SHIFT 7
    #define FES0_SRC1_PIXEL_ENDIAN_MASK 0x00008000
    #define FES0_SRC1_PIXEL_ENDIAN_SHIFT 15
    #define FES0_SRC1_BITEXPD_MODE_MASK 0x00030000
    #define FES0_SRC1_BITEXPD_MODE_SHIFT 16
    #define FES0_SRC1_PLANAR_MODE_MASK 0x000C0000
    #define FES0_SRC1_PLANAR_MODE_SHIFT 18
    #define FES0_SWAP_CTRL_MASK 0x00300000
    #define FES0_SWAP_CTRL_SHIFT 20
    #define FES0_VB_PACK_ORDER_MASK 0x03000000
    #define FES0_VB_PACK_ORDER_SHIFT 24
    #define FES0_UG_PACK_ORDER_MASK 0x0C000000
    #define FES0_UG_PACK_ORDER_SHIFT 26
    #define FES0_YR_PACK_ORDER_MASK 0x30000000
    #define FES0_YR_PACK_ORDER_SHIFT 28
    #define FES0_A_PACK_ORDER_MASK 0xC0000000
    #define FES0_A_PACK_ORDER_SHIFT 30
#define  FES0_SRC1_PITCH 0xD468
    #define FES0_SRC1_PITCH_MASK 0x0000FFE0
    #define FES0_SRC1_PITCH_SHIFT 5
    #define FES0_SRC1_UV_PITCH_MASK 0xFFE00000
    #define FES0_SRC1_UV_PITCH_SHIFT 21
#define  FES0_SRC1_SCLH_GB_UV 0xD4A0
    #define FES0_SRC1_SCLH_GB_UV_FES0_SRC1_SCLH_MASK 0x003FFFFF
    #define FES0_SRC1_SCLH_GB_UV_FES0_SRC1_SCLH_SHIFT 0
#define  FES0_SRC1_SCLH_R_Y 0xD498
    #define FES0_SRC1_SCLH_R_Y_FES0_SRC1_SCLH_MASK 0x003FFFFF
    #define FES0_SRC1_SCLH_R_Y_FES0_SRC1_SCLH_SHIFT 0
#define  FES0_SRC1_SCLV_GB_UV 0xD49C
    #define FES0_SRC1_SCLV_GB_UV_FES0_SRC1_SCLV_MASK 0x003FFFFF
    #define FES0_SRC1_SCLV_GB_UV_FES0_SRC1_SCLV_SHIFT 0
#define  FES0_SRC1_SCLV_R_Y 0xD494
    #define FES0_SRC1_SCLV_R_Y_FES0_SRC1_SCLV_MASK 0x003FFFFF
    #define FES0_SRC1_SCLV_R_Y_FES0_SRC1_SCLV_SHIFT 0
#define  FES0_SRC1_UV_H_W 0xD470
    #define FES0_SRC1_UV_W_MASK 0x00007FFF
    #define FES0_SRC1_UV_W_SHIFT 0
    #define FES0_SRC1_UV_H_MASK 0x7FFF0000
    #define FES0_SRC1_UV_H_SHIFT 16
#define  FES0_SRC1_UV_MINMAX 0xD4EC
    #define FES0_SRC1_UV_MINMAX_MIN_UV_MASK 0x000003FF
    #define FES0_SRC1_UV_MINMAX_MIN_UV_SHIFT 0
    #define FES0_SRC1_UV_MINMAX_MAX_UV_MASK 0x03FF0000
    #define FES0_SRC1_UV_MINMAX_MAX_UV_SHIFT 16
#define  FES0_SRC1_Y_MINMAX 0xD4E8
    #define FES0_SRC1_Y_MINMAX_MIN_Y_MASK 0x000003FF
    #define FES0_SRC1_Y_MINMAX_MIN_Y_SHIFT 0
    #define FES0_SRC1_Y_MINMAX_MAX_Y_MASK 0x03FF0000
    #define FES0_SRC1_Y_MINMAX_MAX_Y_SHIFT 16
#define  FES1_ALPHA_MODE_SRC1 0xD6E4
    #define FES1_SRC1_ALPHA_MODE_MASK 0x00000003
    #define FES1_SRC1_ALPHA_MODE_SHIFT 0
    #define FES1_SRC1_ALPHA_C_MASK 0x0000FF00
    #define FES1_SRC1_ALPHA_C_SHIFT 8
#define  FES1_CF_MEM0 0xD6DC
    #define FES1_CMD_LIST_BASE_ADR_MASK 0x7FFFFFF0
    #define FES1_CMD_LIST_BASE_ADR_SHIFT 4
#define  FES1_CF_MEM1 0xD6E0
    #define FES1_CMD_LIST_LENGTH_MASK 0x000000FF
    #define FES1_CMD_LIST_LENGTH_SHIFT 0
#define  FES1_CMD_FIFO_0 0xD640
    #define FES1_CMD_DATA_MASK 0xFFFFFFFF
    #define FES1_CMD_DATA_SHIFT 0
#define  FES1_CMD_FIFO_1 0xD644
    #define FES1_CMD_ADR_MASK 0x0000FFFF
    #define FES1_CMD_ADR_SHIFT 0
#define  FES1_CONFIG_CTRL 0xD648
    #define FES1_CSC_EN_MASK 0x00000001
    #define FES1_CSC_EN_SHIFT 0
    #define FES1_ALPHA_PREMUL_EN_MASK 0x00000010
    #define FES1_ALPHA_PREMUL_EN_SHIFT 4
    #define FES1_MLUT_BYPASS_MASK 0x00000100
    #define FES1_MLUT_BYPASS_SHIFT 8
    #define FES1_SRC_MLUT_HZ_PROG_EN_MASK 0x00000C00
    #define FES1_SRC_MLUT_HZ_PROG_EN_SHIFT 10
    #define FES1_SRC_MLUT_VL_PROG_EN_MASK 0x00003000
    #define FES1_SRC_MLUT_VL_PROG_EN_SHIFT 12
    #define FES1_MLUT_ADRMODE_MASK 0x00004000
    #define FES1_MLUT_ADRMODE_SHIFT 14
    #define FES1_CF_FLUSH_MASK 0x00010000
    #define FES1_CF_FLUSH_SHIFT 16
    #define FES1_INT_EN_MASK 0x01000000
    #define FES1_INT_EN_SHIFT 24
    #define FES1_OP_KICKOFF_MASK 0x80000000
    #define FES1_OP_KICKOFF_SHIFT 31
#define  FES1_CSC_PARM0 0xD6B8
    #define FES1_C00_MASK 0x0000FFFF
    #define FES1_C00_SHIFT 0
    #define FES1_C01_MASK 0xFFFF0000
    #define FES1_C01_SHIFT 16
#define  FES1_CSC_PARM1 0xD6BC
    #define FES1_C02_MASK 0x0000FFFF
    #define FES1_C02_SHIFT 0
    #define FES1_C10_MASK 0xFFFF0000
    #define FES1_C10_SHIFT 16
#define  FES1_CSC_PARM2 0xD6C0
    #define FES1_C11_MASK 0x0000FFFF
    #define FES1_C11_SHIFT 0
    #define FES1_C12_MASK 0xFFFF0000
    #define FES1_C12_SHIFT 16
#define  FES1_CSC_PARM3 0xD6C4
    #define FES1_C20_MASK 0x0000FFFF
    #define FES1_C20_SHIFT 0
    #define FES1_C21_MASK 0xFFFF0000
    #define FES1_C21_SHIFT 16
#define  FES1_CSC_PARM4 0xD6C8
    #define FES1_C22_MASK 0x0000FFFF
    #define FES1_C22_SHIFT 0
    #define FES1_OYR_MASK 0x03FF0000
    #define FES1_OYR_SHIFT 16
#define  FES1_CSC_PARM5 0xD6CC
    #define FES1_OUG_MASK 0x000003FF
    #define FES1_OUG_SHIFT 0
    #define FES1_OVB_MASK 0x03FF0000
    #define FES1_OVB_SHIFT 16
#define  FES1_CSC_PARM6 0xD6D0
    #define FES1_RY_MIN_MASK 0x000000FF
    #define FES1_RY_MIN_SHIFT 0
    #define FES1_RY_MAX_MASK 0x0000FF00
    #define FES1_RY_MAX_SHIFT 8
    #define FES1_UG_MIN_MASK 0x00FF0000
    #define FES1_UG_MIN_SHIFT 16
    #define FES1_UG_MAX_MASK 0xFF000000
    #define FES1_UG_MAX_SHIFT 24
#define  FES1_CSC_PARM7 0xD6D4
    #define FES1_VB_MIN_MASK 0x000000FF
    #define FES1_VB_MIN_SHIFT 0
    #define FES1_VB_MAX_MASK 0x0000FF00
    #define FES1_VB_MAX_SHIFT 8
#define  FES1_DST_ADR0 0xD674
    #define FES1_DST_BASE_MASK 0x7FFFFFE0
    #define FES1_DST_BASE_SHIFT 5
#define  FES1_DST_ADR1 0xD678
    #define FES1_DST_U_BASE_MASK 0x7FFFFFE0
    #define FES1_DST_U_BASE_SHIFT 5
#define  FES1_DST_ADR2 0xD67C
    #define FES1_DST_V_BASE_MASK 0x7FFFFFE0
    #define FES1_DST_V_BASE_SHIFT 5
#define  FES1_DST_H_W 0xD688
    #define FES1_DST_W_MASK 0x00007FFF
    #define FES1_DST_W_SHIFT 0
    #define FES1_DST_H_MASK 0x7FFF0000
    #define FES1_DST_H_SHIFT 16
#define  FES1_DST_MODE 0xD680
    #define FES1_DST_FMT_MASK 0x0000000F
    #define FES1_DST_FMT_SHIFT 0
    #define FES1_DST_FLD_SEL_MASK 0x00000040
    #define FES1_DST_FLD_SEL_SHIFT 6
    #define FES1_DST_PLANAR_MODE_MASK 0x000C0000
    #define FES1_DST_PLANAR_MODE_SHIFT 18
    #define FES1_DST_ALPHA_THRES_MASK 0xFF000000
    #define FES1_DST_ALPHA_THRES_SHIFT 24
#define  FES1_DST_PITCH 0xD684
    #define FES1_DST_PITCH_MASK 0x0000FFE0
    #define FES1_DST_PITCH_SHIFT 5
    #define FES1_DST_UV_PITCH_MASK 0xFFE00000
    #define FES1_DST_UV_PITCH_SHIFT 21
#define  FES1_DST_SUBFLD 0xD690
    #define FES1_DST_SUBFLD_W_MASK 0x000007FF
    #define FES1_DST_SUBFLD_W_SHIFT 0
#define  FES1_DST_UV_H_W 0xD68C
    #define FES1_DST_UV_W_MASK 0x00007FFF
    #define FES1_DST_UV_W_SHIFT 0
    #define FES1_DST_UV_H_MASK 0x7FFF0000
    #define FES1_DST_UV_H_SHIFT 16
#define  FES1_DUMMY_REG 0xD6F4
    #define FES1_DUMMY_BITS_MASK 0xFFFFFFFF
    #define FES1_DUMMY_BITS_SHIFT 0
#define  FES1_LUT_ADR 0xD6F0
    #define FES1_LUT_ADR_MASK 0x0000003F
    #define FES1_LUT_ADR_SHIFT 0
#define  FES1_LUT_PROGM 0xD6D8
    #define FES1_LUT_DATA_MASK 0xFFFFFFFF
    #define FES1_LUT_DATA_SHIFT 0
#define  FES1_NUMTAPS_HELD 0xD6B4
    #define FES1_HTAPS_MASK 0x000000FF
    #define FES1_HTAPS_SHIFT 0
    #define FES1_VTAPS_MASK 0x0000FF00
    #define FES1_VTAPS_SHIFT 8
    #define FES1_HTAPS_UV_MASK 0x00FF0000
    #define FES1_HTAPS_UV_SHIFT 16
    #define FES1_VTAPS_UV_MASK 0xFF000000
    #define FES1_VTAPS_UV_SHIFT 24
#define  FES1_POSREG0_INIT 0xD6A4
    #define FES1_POSREG0_INIT_FES1_POSREG_INIT_H_MASK 0x0000FFFF
    #define FES1_POSREG0_INIT_FES1_POSREG_INIT_H_SHIFT 0
    #define FES1_POSREG0_INIT_FES1_POSREG_INIT_V_MASK 0xFFFF0000
    #define FES1_POSREG0_INIT_FES1_POSREG_INIT_V_SHIFT 16
#define  FES1_POSREG0_UV_INIT 0xD6A8
    #define FES1_POSREG0_UV_INIT_FES1_POSREG_INIT_H_MASK 0x0000FFFF
    #define FES1_POSREG0_UV_INIT_FES1_POSREG_INIT_H_SHIFT 0
    #define FES1_POSREG0_UV_INIT_FES1_POSREG_INIT_V_MASK 0xFFFF0000
    #define FES1_POSREG0_UV_INIT_FES1_POSREG_INIT_V_SHIFT 16
#define  FES1_POSREG1_INIT 0xD6AC
    #define FES1_POSREG1_INIT_FES1_POSREG_INIT_H_MASK 0x0000FFFF
    #define FES1_POSREG1_INIT_FES1_POSREG_INIT_H_SHIFT 0
    #define FES1_POSREG1_INIT_FES1_POSREG_INIT_V_MASK 0xFFFF0000
    #define FES1_POSREG1_INIT_FES1_POSREG_INIT_V_SHIFT 16
#define  FES1_POSREG1_UV_INIT 0xD6B0
    #define FES1_POSREG1_UV_INIT_FES1_POSREG_INIT_H_MASK 0x0000FFFF
    #define FES1_POSREG1_UV_INIT_FES1_POSREG_INIT_H_SHIFT 0
    #define FES1_POSREG1_UV_INIT_FES1_POSREG_INIT_V_MASK 0xFFFF0000
    #define FES1_POSREG1_UV_INIT_FES1_POSREG_INIT_V_SHIFT 16
#define  FES1_SRC12_ADR0 0xD658
    #define FES1_SRC12_ADR0_FES1_SRC1_BASE_MASK 0x7FFFFFE0
    #define FES1_SRC12_ADR0_FES1_SRC1_BASE_SHIFT 5
#define  FES1_SRC12_ADR1 0xD65C
    #define FES1_SRC12_ADR1_FES1_SRC1_U_BASE_MASK 0x7FFFFFE0
    #define FES1_SRC12_ADR1_FES1_SRC1_U_BASE_SHIFT 5
#define  FES1_SRC12_ADR2 0xD660
    #define FES1_SRC12_ADR2_FES1_SRC1_V_BASE_MASK 0x7FFFFFE0
    #define FES1_SRC12_ADR2_FES1_SRC1_V_BASE_SHIFT 5
#define  FES1_SRC1_ADR0 0xD64C
    #define FES1_SRC1_ADR0_FES1_SRC1_BASE_MASK 0x7FFFFFE0
    #define FES1_SRC1_ADR0_FES1_SRC1_BASE_SHIFT 5
#define  FES1_SRC1_ADR1 0xD650
    #define FES1_SRC1_ADR1_FES1_SRC1_U_BASE_MASK 0x7FFFFFE0
    #define FES1_SRC1_ADR1_FES1_SRC1_U_BASE_SHIFT 5
#define  FES1_SRC1_ADR2 0xD654
    #define FES1_SRC1_ADR2_FES1_SRC1_V_BASE_MASK 0x7FFFFFE0
    #define FES1_SRC1_ADR2_FES1_SRC1_V_BASE_SHIFT 5
#define  FES1_SRC1_FOLDH_GB_UV 0xD704
    #define FES1_SRC1_FOLDH_GB_UV_FES1_MAX_PHASE_MASK 0x0000007F
    #define FES1_SRC1_FOLDH_GB_UV_FES1_MAX_PHASE_SHIFT 0
    #define FES1_SRC1_FOLDH_GB_UV_FES1_TRIG_PHASE_MASK 0x00007F00
    #define FES1_SRC1_FOLDH_GB_UV_FES1_TRIG_PHASE_SHIFT 8
    #define FES1_SRC1_FOLDH_GB_UV_FES1_ROUND_POSREG_MASK 0x00010000
    #define FES1_SRC1_FOLDH_GB_UV_FES1_ROUND_POSREG_SHIFT 16
#define  FES1_SRC1_FOLDH_R_Y 0xD6FC
    #define FES1_SRC1_FOLDH_R_Y_FES1_MAX_PHASE_MASK 0x0000007F
    #define FES1_SRC1_FOLDH_R_Y_FES1_MAX_PHASE_SHIFT 0
    #define FES1_SRC1_FOLDH_R_Y_FES1_TRIG_PHASE_MASK 0x00007F00
    #define FES1_SRC1_FOLDH_R_Y_FES1_TRIG_PHASE_SHIFT 8
    #define FES1_SRC1_FOLDH_R_Y_FES1_ROUND_POSREG_MASK 0x00010000
    #define FES1_SRC1_FOLDH_R_Y_FES1_ROUND_POSREG_SHIFT 16
#define  FES1_SRC1_FOLDV_GB_UV 0xD700
    #define FES1_SRC1_FOLDV_GB_UV_FES1_MAX_PHASE_MASK 0x0000007F
    #define FES1_SRC1_FOLDV_GB_UV_FES1_MAX_PHASE_SHIFT 0
    #define FES1_SRC1_FOLDV_GB_UV_FES1_TRIG_PHASE_MASK 0x00007F00
    #define FES1_SRC1_FOLDV_GB_UV_FES1_TRIG_PHASE_SHIFT 8
    #define FES1_SRC1_FOLDV_GB_UV_FES1_ROUND_POSREG_MASK 0x00010000
    #define FES1_SRC1_FOLDV_GB_UV_FES1_ROUND_POSREG_SHIFT 16
#define  FES1_SRC1_FOLDV_R_Y 0xD6F8
    #define FES1_SRC1_FOLDV_R_Y_FES1_MAX_PHASE_MASK 0x0000007F
    #define FES1_SRC1_FOLDV_R_Y_FES1_MAX_PHASE_SHIFT 0
    #define FES1_SRC1_FOLDV_R_Y_FES1_TRIG_PHASE_MASK 0x00007F00
    #define FES1_SRC1_FOLDV_R_Y_FES1_TRIG_PHASE_SHIFT 8
    #define FES1_SRC1_FOLDV_R_Y_FES1_ROUND_POSREG_MASK 0x00010000
    #define FES1_SRC1_FOLDV_R_Y_FES1_ROUND_POSREG_SHIFT 16
#define  FES1_SRC1_H_W 0xD66C
    #define FES1_SRC1_W_MASK 0x00007FFF
    #define FES1_SRC1_W_SHIFT 0
    #define FES1_SRC1_H_MASK 0x7FFF0000
    #define FES1_SRC1_H_SHIFT 16
#define  FES1_SRC1_MODE 0xD664
    #define FES1_SRC1_FMT_MASK 0x0000000F
    #define FES1_SRC1_FMT_SHIFT 0
    #define FES1_SRC1_MEM_TILE_MASK 0x00000030
    #define FES1_SRC1_MEM_TILE_SHIFT 4
    #define FES1_SRC1_FLD_SEQ_MASK 0x00000040
    #define FES1_SRC1_FLD_SEQ_SHIFT 6
    #define FES1_SRC1_DEINT_MODE_MASK 0x00000080
    #define FES1_SRC1_DEINT_MODE_SHIFT 7
    #define FES1_SRC1_PIXEL_ENDIAN_MASK 0x00008000
    #define FES1_SRC1_PIXEL_ENDIAN_SHIFT 15
    #define FES1_SRC1_BITEXPD_MODE_MASK 0x00030000
    #define FES1_SRC1_BITEXPD_MODE_SHIFT 16
    #define FES1_SRC1_PLANAR_MODE_MASK 0x000C0000
    #define FES1_SRC1_PLANAR_MODE_SHIFT 18
    #define FES1_SWAP_CTRL_MASK 0x00300000
    #define FES1_SWAP_CTRL_SHIFT 20
    #define FES1_VB_PACK_ORDER_MASK 0x03000000
    #define FES1_VB_PACK_ORDER_SHIFT 24
    #define FES1_UG_PACK_ORDER_MASK 0x0C000000
    #define FES1_UG_PACK_ORDER_SHIFT 26
    #define FES1_YR_PACK_ORDER_MASK 0x30000000
    #define FES1_YR_PACK_ORDER_SHIFT 28
    #define FES1_A_PACK_ORDER_MASK 0xC0000000
    #define FES1_A_PACK_ORDER_SHIFT 30
#define  FES1_SRC1_PITCH 0xD668
    #define FES1_SRC1_PITCH_MASK 0x0000FFE0
    #define FES1_SRC1_PITCH_SHIFT 5
    #define FES1_SRC1_UV_PITCH_MASK 0xFFE00000
    #define FES1_SRC1_UV_PITCH_SHIFT 21
#define  FES1_SRC1_SCLH_GB_UV 0xD6A0
    #define FES1_SRC1_SCLH_GB_UV_FES1_SRC1_SCLH_MASK 0x003FFFFF
    #define FES1_SRC1_SCLH_GB_UV_FES1_SRC1_SCLH_SHIFT 0
#define  FES1_SRC1_SCLH_R_Y 0xD698
    #define FES1_SRC1_SCLH_R_Y_FES1_SRC1_SCLH_MASK 0x003FFFFF
    #define FES1_SRC1_SCLH_R_Y_FES1_SRC1_SCLH_SHIFT 0
#define  FES1_SRC1_SCLV_GB_UV 0xD69C
    #define FES1_SRC1_SCLV_GB_UV_FES1_SRC1_SCLV_MASK 0x003FFFFF
    #define FES1_SRC1_SCLV_GB_UV_FES1_SRC1_SCLV_SHIFT 0
#define  FES1_SRC1_SCLV_R_Y 0xD694
    #define FES1_SRC1_SCLV_R_Y_FES1_SRC1_SCLV_MASK 0x003FFFFF
    #define FES1_SRC1_SCLV_R_Y_FES1_SRC1_SCLV_SHIFT 0
#define  FES1_SRC1_UV_H_W 0xD670
    #define FES1_SRC1_UV_W_MASK 0x00007FFF
    #define FES1_SRC1_UV_W_SHIFT 0
    #define FES1_SRC1_UV_H_MASK 0x7FFF0000
    #define FES1_SRC1_UV_H_SHIFT 16
#define  FES1_SRC1_UV_MINMAX 0xD6EC
    #define FES1_SRC1_UV_MINMAX_MIN_UV_MASK 0x000003FF
    #define FES1_SRC1_UV_MINMAX_MIN_UV_SHIFT 0
    #define FES1_SRC1_UV_MINMAX_MAX_UV_MASK 0x03FF0000
    #define FES1_SRC1_UV_MINMAX_MAX_UV_SHIFT 16
#define  FES1_SRC1_Y_MINMAX 0xD6E8
    #define FES1_SRC1_Y_MINMAX_MIN_Y_MASK 0x000003FF
    #define FES1_SRC1_Y_MINMAX_MIN_Y_SHIFT 0
    #define FES1_SRC1_Y_MINMAX_MAX_Y_MASK 0x03FF0000
    #define FES1_SRC1_Y_MINMAX_MAX_Y_SHIFT 16
#define  FES_CFIFO_CTRL 0xD404
    #define CF0_OP_MODE_MASK 0x00000003
    #define CF0_OP_MODE_SHIFT 0
    #define CF1_OP_MODE_MASK 0x0000000C
    #define CF1_OP_MODE_SHIFT 2
    #define FES0_CFARB_TIMER_MASK 0x00000F00
    #define FES0_CFARB_TIMER_SHIFT 8
    #define FES1_CFARB_TIMER_MASK 0x0000F000
    #define FES1_CFARB_TIMER_SHIFT 12
#define  FES_DEBUGBUS_REG 0xD434
    #define FES_DEBUGBUS_MASK 0xFFFFFFFF
    #define FES_DEBUGBUS_SHIFT 0
#define  FES_DUMMY_DIR_REG 0xD430
    #define FES_DUMMY_DIR_REG_DUMMY_BITS_MASK 0xFFFFFFFF
    #define FES_DUMMY_DIR_REG_DUMMY_BITS_SHIFT 0
#define  FES_INT_MASK 0xD40C
    #define INT_HT_MASK_MASK 0x00000001
    #define INT_HT_MASK_SHIFT 0
    #define FES_INT_MASK_LUT_PROG_ERR_INT_MASK 0x00000010
    #define FES_INT_MASK_LUT_PROG_ERR_INT_SHIFT 4
    #define FES_INT_MASK_CF0_FULL_INT_MASK 0x00000100
    #define FES_INT_MASK_CF0_FULL_INT_SHIFT 8
    #define FES_INT_MASK_CF1_FULL_INT_MASK 0x00001000
    #define FES_INT_MASK_CF1_FULL_INT_SHIFT 12
    #define FES_INT_MASK_OUT_FIFO_FULL_INT_MASK 0x00080000
    #define FES_INT_MASK_OUT_FIFO_FULL_INT_SHIFT 19
#define  FES_INT_STATUS 0xD414
    #define FES_INT_STATUS_INT_MASK 0x00000001
    #define FES_INT_STATUS_INT_SHIFT 0
    #define FES_INT_STATUS_LUT_PROG_ERR_INT_MASK 0x00000010
    #define FES_INT_STATUS_LUT_PROG_ERR_INT_SHIFT 4
    #define FES_INT_STATUS_CF0_FULL_INT_MASK 0x00000100
    #define FES_INT_STATUS_CF0_FULL_INT_SHIFT 8
    #define FES_INT_STATUS_CF1_FULL_INT_MASK 0x00001000
    #define FES_INT_STATUS_CF1_FULL_INT_SHIFT 12
    #define FES_INT_STATUS_OUT_FIFO_FULL_INT_MASK 0x00080000
    #define FES_INT_STATUS_OUT_FIFO_FULL_INT_SHIFT 19
#define  FES_MEM_REQ_CTL 0xD408
    #define SRC1_Y_TIMER_MASK 0x0000000F
    #define SRC1_Y_TIMER_SHIFT 0
    #define SRC1_U_TIMER_MASK 0x000000F0
    #define SRC1_U_TIMER_SHIFT 4
    #define SRC1_V_TIMER_MASK 0x00000F00
    #define SRC1_V_TIMER_SHIFT 8
    #define OUTPUT_TIMER_MASK 0x00F00000
    #define OUTPUT_TIMER_SHIFT 20
    #define DEBUG_TIMER_MASK 0x0F000000
    #define DEBUG_TIMER_SHIFT 24
    #define SRC1_LREQ_LIMIT_MASK 0xF0000000
    #define SRC1_LREQ_LIMIT_SHIFT 28
#define  FES_MLUT_RDBCK 0xD438
    #define MLUT_RDBCK_DAT_MASK 0xFFFFFFFF
    #define MLUT_RDBCK_DAT_SHIFT 0
#define  FES_MLUT_RDBCK_ADR 0xD43C
    #define MLUT_RDBCK_ADR_MASK 0x0000003F
    #define MLUT_RDBCK_ADR_SHIFT 0
    #define MLUT_DAT_IDX_MASK 0x000000C0
    #define MLUT_DAT_IDX_SHIFT 6
    #define MLUT_BANK_SEL_MASK 0x00000700
    #define MLUT_BANK_SEL_SHIFT 8
    #define MLUT_RDBCK_EN_MASK 0x00010000
    #define MLUT_RDBCK_EN_SHIFT 16
#define  FES_MLUT_STATUS 0xD428
    #define VL_LUT0_FILL_ADR_MASK 0x0000003F
    #define VL_LUT0_FILL_ADR_SHIFT 0
    #define VL_LUT1_FILL_ADR_MASK 0x00003F00
    #define VL_LUT1_FILL_ADR_SHIFT 8
    #define HZ_LUT0_FILL_ADR_MASK 0x003F0000
    #define HZ_LUT0_FILL_ADR_SHIFT 16
    #define HZ_LUT1_FILL_ADR_MASK 0x3F000000
    #define HZ_LUT1_FILL_ADR_SHIFT 24
#define  FES_PRG_CTRL 0xD400
    #define MLUT_PRG_LOCK_MASK 0x00000001
    #define MLUT_PRG_LOCK_SHIFT 0
    #define SEL_HZ_LUT_MASK 0x00000080
    #define SEL_HZ_LUT_SHIFT 7
    #define S1LB_FREE_SPACE_SEL_MASK 0x00000300
    #define S1LB_FREE_SPACE_SEL_SHIFT 8
    #define FES_PRG_CTRL_RESETN_MASK 0x80000000
    #define FES_PRG_CTRL_RESETN_SHIFT 31
#define  FES_RBM_BRIDGE_CTRL 0xD42C
    #define FES_SETTLE_MASK 0x00000007
    #define FES_SETTLE_SHIFT 0
#define  FES_SRC1FIFO_STATUS1 0xD41C
    #define S1LB0_FREE_SPACE_MASK 0x0000003F
    #define S1LB0_FREE_SPACE_SHIFT 0
    #define S1LB1_FREE_SPACE_MASK 0x00003F00
    #define S1LB1_FREE_SPACE_SHIFT 8
    #define S1LB2_FREE_SPACE_MASK 0x003F0000
    #define S1LB2_FREE_SPACE_SHIFT 16
    #define S1LB3_FREE_SPACE_MASK 0x3F000000
    #define S1LB3_FREE_SPACE_SHIFT 24
#define  FES_SRC1FIFO_STATUS2 0xD420
    #define S1LB0_EMPTY_FLAG_MASK 0x0000003F
    #define S1LB0_EMPTY_FLAG_SHIFT 0
    #define S1LB1_EMPTY_FLAG_MASK 0x00003F00
    #define S1LB1_EMPTY_FLAG_SHIFT 8
    #define S1LB2_EMPTY_FLAG_MASK 0x003F0000
    #define S1LB2_EMPTY_FLAG_SHIFT 16
#define  FES_SRC1OUTFIFO_STATUS 0xD424
    #define OFIFO_LVL_MASK 0x0000007F
    #define OFIFO_LVL_SHIFT 0
    #define S1LB4_FREE_SPACE_MASK 0x003F0000
    #define S1LB4_FREE_SPACE_SHIFT 16
    #define S1LB5_FREE_SPACE_MASK 0x3F000000
    #define S1LB5_FREE_SPACE_SHIFT 24
#define  FES_STATUS 0xD418
    #define FES_BUSY_MASK 0x00000001
    #define FES_BUSY_SHIFT 0
    #define FES0_CF_BUSY_MASK 0x00000002
    #define FES0_CF_BUSY_SHIFT 1
    #define FES1_CF_BUSY_MASK 0x00000004
    #define FES1_CF_BUSY_SHIFT 2
    #define FES0_CF_FREE_ENT_MASK 0x00001FF0
    #define FES0_CF_FREE_ENT_SHIFT 4
    #define FES0_CF_FULL_MASK 0x00002000
    #define FES0_CF_FULL_SHIFT 13
    #define FES0_CF_EMPTY_MASK 0x00004000
    #define FES0_CF_EMPTY_SHIFT 14
    #define FES1_CF_FREE_ENT_MASK 0x01FF0000
    #define FES1_CF_FREE_ENT_SHIFT 16
    #define FES1_CF_FULL_MASK 0x02000000
    #define FES1_CF_FULL_SHIFT 25
    #define FES1_CF_EMPTY_MASK 0x04000000
    #define FES1_CF_EMPTY_SHIFT 26
    #define FES_MLUT_STATE_MASK 0x30000000
    #define FES_MLUT_STATE_SHIFT 28
#define  FMA_CMD 0xFBF8
    #define FMA_CMD_BYTECNT_MASK 0x000FFFF8
    #define FMA_CMD_BYTECNT_SHIFT 3
    #define FMA_CMD_XFER_MODE_MASK 0x10000000
    #define FMA_CMD_XFER_MODE_SHIFT 28
#define  FMA_DST_ADR 0xFBF4
    #define FMA_DST_ADR_DST_ADDRESS_MASK 0x1FFFFFF8
    #define FMA_DST_ADR_DST_ADDRESS_SHIFT 3
#define  FMA_SRC_ADR 0xFBF0
    #define FMA_SRC_ADR_SRC_ADDRESS_MASK 0xFFFFFFFF
    #define FMA_SRC_ADR_SRC_ADDRESS_SHIFT 0
#define  FMA_STATUS 0xFBFC
    #define FMA_STATUS_FIFO_FREE_MASK 0x0000000F
    #define FMA_STATUS_FIFO_FREE_SHIFT 0
    #define FMA_BUSY_MASK 0x00000010
    #define FMA_BUSY_SHIFT 4
#define  G2D_4LUT_2LUT_OFFSET 0x9870
    #define G4LUT_OFFSET_MASK 0x0000000F
    #define G4LUT_OFFSET_SHIFT 0
    #define G2LUT_OFFSET_MASK 0x0000FF00
    #define G2LUT_OFFSET_SHIFT 8
#define  G2D_8LUT_INDEX 0x986C
    #define LUT_INDEX_MASK 0x000000FF
    #define LUT_INDEX_SHIFT 0
    #define LUT_READRAM_MASK 0x00000300
    #define LUT_READRAM_SHIFT 8
#define  G2D_BKGRND_COLOR 0x984C
    #define BKGRND_COLOR_MASK 0xFFFFFFFF
    #define BKGRND_COLOR_SHIFT 0
#define  G2D_BL_GRADIENT_CLR 0x9858
    #define BL_GRADIENT_CLR_MASK 0xFFFFFFFF
    #define BL_GRADIENT_CLR_SHIFT 0
#define  G2D_BR_GRADIENT_CLR 0x985C
    #define BR_GRADIENT_CLR_MASK 0xFFFFFFFF
    #define BR_GRADIENT_CLR_SHIFT 0
#define  G2D_BUFFER_CTRL 0x9B08
    #define G2D_BUFFER_CTRL_OUTPUT_STOP_REQ_MASK 0x00000001
    #define G2D_BUFFER_CTRL_OUTPUT_STOP_REQ_SHIFT 0
    #define G2D_BUFFER_CTRL_OUTPUT_FLUSH_MASK 0x00000002
    #define G2D_BUFFER_CTRL_OUTPUT_FLUSH_SHIFT 1
    #define INPUT_STOP_REQ_MASK 0x00000004
    #define INPUT_STOP_REQ_SHIFT 2
    #define CMDBUFFER_STOP_REQ_MASK 0x00000008
    #define CMDBUFFER_STOP_REQ_SHIFT 3
    #define SRCBUFFER_EMERGENCY_FULL_MASK 0x00000010
    #define SRCBUFFER_EMERGENCY_FULL_SHIFT 4
    #define OUTPUT_CTRL_MUX_MASK 0x000F0000
    #define OUTPUT_CTRL_MUX_SHIFT 16
#define  G2D_BUFFER_STATUS 0x9B0C
    #define G2D_BUFFER_STATUS_OUTPUT_NO_REQUESTS_MASK 0x00000001
    #define G2D_BUFFER_STATUS_OUTPUT_NO_REQUESTS_SHIFT 0
    #define G2D_BUFFER_STATUS_OUTPUT_FLUSHED_MASK 0x00000002
    #define G2D_BUFFER_STATUS_OUTPUT_FLUSHED_SHIFT 1
    #define INPUT_NO_REQUESTS_MASK 0x00000004
    #define INPUT_NO_REQUESTS_SHIFT 2
    #define CMDBUFFER_NO_REQUESTS_MASK 0x00000008
    #define CMDBUFFER_NO_REQUESTS_SHIFT 3
    #define OUTPUT_STATUS_MASK 0xFFFF0000
    #define OUTPUT_STATUS_SHIFT 16
#define  G2D_CLR_CMP_CLR 0x9860
    #define CLR_CMP_CLR_MASK 0xFFFFFFFF
    #define CLR_CMP_CLR_SHIFT 0
#define  G2D_CLR_CMP_FNCT 0x9864
    #define COMPARE_FNCT_MASK 0x0000000F
    #define COMPARE_FNCT_SHIFT 0
    #define COMPARE_INPUT_MASK 0x00000F00
    #define COMPARE_INPUT_SHIFT 8
#define  G2D_CLR_CMP_MASK 0x9868
    #define COMPARE_MASK_MASK 0xFFFFFFFF
    #define COMPARE_MASK_SHIFT 0
#define  G2D_CMDFIFO_WATERMARK 0x9A38
    #define CMDFIFO_WATERMARK_MASK 0x0000007F
    #define CMDFIFO_WATERMARK_SHIFT 0
#define  G2D_CMD_BUFFER_BASE 0x9A20
    #define CMD_BUFFER_BASE_MASK 0x7FFFFFC0
    #define CMD_BUFFER_BASE_SHIFT 6
#define  G2D_CMD_BUFFER_CTRL 0x9A2C
    #define CMD_BUFFER_RUN_MASK 0x00000001
    #define CMD_BUFFER_RUN_SHIFT 0
    #define CMD_BUFFER_BASE_RESET_MASK 0x00000100
    #define CMD_BUFFER_BASE_RESET_SHIFT 8
    #define CMD_BUFFER_ENABLE_MASK 0x00000200
    #define CMD_BUFFER_ENABLE_SHIFT 9
#define  G2D_CMD_BUFFER_RPTR 0x9A28
    #define CMD_BUFFER_RPTR_MASK 0x0000FFFF
    #define CMD_BUFFER_RPTR_SHIFT 0
#define  G2D_CMD_BUFFER_WPTR 0x9A24
    #define CMD_BUFFER_WPTR_MASK 0x0000FFFF
    #define CMD_BUFFER_WPTR_SHIFT 0
#define  G2D_CTRL_BUFFER_OFFSET 0x987C
    #define CTRL_OFFSET_MASK 0xFFFFFFFF
    #define CTRL_OFFSET_SHIFT 0
#define  G2D_CTRL_HEAD_TAIL_REG 0x9880
    #define TAIL_REG_MASK 0x0000FFFF
    #define TAIL_REG_SHIFT 0
    #define HEAD_REG_MASK 0xFFFF0000
    #define HEAD_REG_SHIFT 16
#define  G2D_DEBUG_DATA 0x9B10
    #define G2D_DEBUG_DATA_DEBUG_DATA_MASK 0x000FFFFF
    #define G2D_DEBUG_DATA_DEBUG_DATA_SHIFT 0
#define  G2D_DST_H_W_INIT 0x9808
    #define DST_W_MASK 0x00003FFF
    #define DST_W_SHIFT 0
    #define DST_H_MASK 0x3FFF0000
    #define DST_H_SHIFT 16
#define  G2D_DST_OFFSET 0x9814
    #define DST_OFFSET_BYTE_MASK 0x7FFFFFF0
    #define DST_OFFSET_BYTE_SHIFT 4
#define  G2D_DST_PITCH_FORMAT 0x9818
    #define G2D_DST_PITCH_FORMAT_DST_PITCH_MASK 0x00003FFF
    #define G2D_DST_PITCH_FORMAT_DST_PITCH_SHIFT 0
    #define DST_PIX_FORMAT_MASK 0x000F0000
    #define DST_PIX_FORMAT_SHIFT 16
    #define ROP_ALPHA_FORMAT_MASK 0x00300000
    #define ROP_ALPHA_FORMAT_SHIFT 20
    #define DST_ENDIAN_MASK 0x20000000
    #define DST_ENDIAN_SHIFT 29
    #define DST_DATA_LINEAR_MASK 0x40000000
    #define DST_DATA_LINEAR_SHIFT 30
#define  G2D_DST_Y_X 0x981C
    #define DST_X_MASK 0x00007FFF
    #define DST_X_SHIFT 0
    #define DST_Y_MASK 0x7FFF0000
    #define DST_Y_SHIFT 16
#define  G2D_ERR_CTRL 0x9B18
    #define DISABLE_RLE_ERR1_MASK 0x00004000
    #define DISABLE_RLE_ERR1_SHIFT 14
    #define DISABLE_RLE_ERR2_MASK 0x00008000
    #define DISABLE_RLE_ERR2_SHIFT 15
    #define DISABLE_RLE_ERR3_MASK 0x00010000
    #define DISABLE_RLE_ERR3_SHIFT 16
    #define DISABLE_RLE_ERR4_MASK 0x00020000
    #define DISABLE_RLE_ERR4_SHIFT 17
#define  G2D_ERR_STATUS 0x9B14
    #define SRCBUF_EMERGENCY_MASK 0x00000001
    #define SRCBUF_EMERGENCY_SHIFT 0
    #define DAC_ERR_MASK 0x00000002
    #define DAC_ERR_SHIFT 1
    #define SCALE_BLT_ERR_MASK 0x00000004
    #define SCALE_BLT_ERR_SHIFT 2
    #define BLT_ERR_MASK 0x00000008
    #define BLT_ERR_SHIFT 3
    #define RMF_ERR_MASK 0x00000010
    #define RMF_ERR_SHIFT 4
    #define RFG_ERR_MASK 0x00000020
    #define RFG_ERR_SHIFT 5
    #define RFE_ERR_MASK 0x00000040
    #define RFE_ERR_SHIFT 6
    #define RDE_ERR_MASK 0x00000080
    #define RDE_ERR_SHIFT 7
    #define LDE_ERR_MASK 0x00000100
    #define LDE_ERR_SHIFT 8
    #define OUTPUT_CLIP_OVERFLOW_MASK 0x00000200
    #define OUTPUT_CLIP_OVERFLOW_SHIFT 9
    #define OUTPUT_CLIP_NEGATIVE_MASK 0x00000400
    #define OUTPUT_CLIP_NEGATIVE_SHIFT 10
    #define HOSTPORT_ERR_MASK 0x00000800
    #define HOSTPORT_ERR_SHIFT 11
    #define CTRL_ERR_MASK 0x00001000
    #define CTRL_ERR_SHIFT 12
    #define CMDFIFO_ERR_MASK 0x00002000
    #define CMDFIFO_ERR_SHIFT 13
    #define RLE_ERR1_MASK 0x00004000
    #define RLE_ERR1_SHIFT 14
    #define RLE_ERR2_MASK 0x00008000
    #define RLE_ERR2_SHIFT 15
    #define RLE_ERR3_MASK 0x00010000
    #define RLE_ERR3_SHIFT 16
    #define RLE_ERR4_MASK 0x00020000
    #define RLE_ERR4_SHIFT 17
#define  G2D_FRGND_COLOR 0x9848
    #define FRGND_COLOR_MASK 0xFFFFFFFF
    #define FRGND_COLOR_SHIFT 0
#define  G2D_GUI_CONTROL 0x9800
    #define CTRL_SLOW_TURNAROUND_MASK 0x00000001
    #define CTRL_SLOW_TURNAROUND_SHIFT 0
    #define CTRL_DONTWAIT_FOR_MARB_MASK 0x00000002
    #define CTRL_DONTWAIT_FOR_MARB_SHIFT 1
    #define SINGLE_PIXEL_MODE_DST_MASK 0x00000004
    #define SINGLE_PIXEL_MODE_DST_SHIFT 2
    #define SINGLE_PIXEL_MODE_SRC_MASK 0x00000008
    #define SINGLE_PIXEL_MODE_SRC_SHIFT 3
    #define SRC_DWORD_CTRL_MASK 0x00000010
    #define SRC_DWORD_CTRL_SHIFT 4
    #define SRC_BYTE_CTRL_MASK 0x00000020
    #define SRC_BYTE_CTRL_SHIFT 5
    #define SRC_BIT_CTRL_MASK 0x00000040
    #define SRC_BIT_CTRL_SHIFT 6
    #define OUTPUT_NOWAIT_MASK 0x00000080
    #define OUTPUT_NOWAIT_SHIFT 7
    #define HOSTPORT_NO_CLEAR_MASK 0x00000100
    #define HOSTPORT_NO_CLEAR_SHIFT 8
    #define HOSTPORT_FULL_CLEAR_MASK 0x00000200
    #define HOSTPORT_FULL_CLEAR_SHIFT 9
    #define ALPHAGRAD_DIRECTION_OVERRIDE_MASK 0x00000400
    #define ALPHAGRAD_DIRECTION_OVERRIDE_SHIFT 10
    #define DAC_CHECK_ADR_MASK 0x00000800
    #define DAC_CHECK_ADR_SHIFT 11
    #define SRC_NOWAIT_MASK 0x00001000
    #define SRC_NOWAIT_SHIFT 12
    #define OUTPUT_RESET_MASK 0x00002000
    #define OUTPUT_RESET_SHIFT 13
    #define OUTPUT_CLUTSAFE_MASK 0x00004000
    #define OUTPUT_CLUTSAFE_SHIFT 14
    #define OUTPUT_MEMSAFE_MASK 0x00008000
    #define OUTPUT_MEMSAFE_SHIFT 15
    #define FIFO_SHADOW_DISABLE_MASK 0x04000000
    #define FIFO_SHADOW_DISABLE_SHIFT 26
    #define LB_ENDIAN_MASK 0x08000000
    #define LB_ENDIAN_SHIFT 27
    #define HOSTPORT_RESET_MASK 0x10000000
    #define HOSTPORT_RESET_SHIFT 28
    #define FIFO_RESET_MASK 0x20000000
    #define FIFO_RESET_SHIFT 29
    #define RESET_CONTROLLER_MASK 0x40000000
    #define RESET_CONTROLLER_SHIFT 30
    #define GFX_CONTROL_MASK 0x80000000
    #define GFX_CONTROL_SHIFT 31
#define  G2D_GUI_STAT 0x9B00
    #define STAT_FIFO_MASK 0x0000007F
    #define STAT_FIFO_SHIFT 0
    #define STAT_HOST_MASK 0x00000300
    #define STAT_HOST_SHIFT 8
    #define STAT_CMD_BUFFER_EMPTY_MASK 0x00000400
    #define STAT_CMD_BUFFER_EMPTY_SHIFT 10
    #define STAT_MARB_RBUSY_MASK 0x00010000
    #define STAT_MARB_RBUSY_SHIFT 16
    #define STAT_MARB_WBUSY_MASK 0x00020000
    #define STAT_MARB_WBUSY_SHIFT 17
    #define STAT_OUTPUT_CTRL_BUSY_MASK 0x00040000
    #define STAT_OUTPUT_CTRL_BUSY_SHIFT 18
    #define STAT_DST_READ_DONE_MASK 0x00080000
    #define STAT_DST_READ_DONE_SHIFT 19
    #define STAT_SRC_BUFFER_BUSY_MASK 0x00100000
    #define STAT_SRC_BUFFER_BUSY_SHIFT 20
    #define STAT_CTRL_BUSY_MASK 0x00200000
    #define STAT_CTRL_BUSY_SHIFT 21
    #define STAT_ERR_MASK 0x40000000
    #define STAT_ERR_SHIFT 30
    #define STAT_GFX_BUSY_MASK 0x80000000
    #define STAT_GFX_BUSY_SHIFT 31
#define  G2D_HOST_DATA0 0x9A00
    #define HOST_DATA_MASK 0xFFFFFFFF
    #define HOST_DATA_SHIFT 0
#define  G2D_INT 0x9A34
    #define G2D_INT_INT_FINISHED_MASK 0x00000001
    #define G2D_INT_INT_FINISHED_SHIFT 0
    #define INT_CMD_COMPLETE_MASK 0x00000002
    #define INT_CMD_COMPLETE_SHIFT 1
    #define INT_CMD_COMPLETE_AND_FLUSH_MASK 0x00000004
    #define INT_CMD_COMPLETE_AND_FLUSH_SHIFT 2
    #define INT_CMD_START_MASK 0x00000008
    #define INT_CMD_START_SHIFT 3
    #define INT_CMDFIFO_EMPTY_MASK 0x00000010
    #define INT_CMDFIFO_EMPTY_SHIFT 4
    #define INT_CMDFIFO_WATERMARK_MASK 0x00000020
    #define INT_CMDFIFO_WATERMARK_SHIFT 5
    #define INT_CMDBUFFER_EMPTY_MASK 0x00000040
    #define INT_CMDBUFFER_EMPTY_SHIFT 6
    #define INT_CMDFIFO_BUFFER_EMPTY_MASK 0x00000080
    #define INT_CMDFIFO_BUFFER_EMPTY_SHIFT 7
    #define INT_HOSTPORT_EMPTY_MASK 0x00000100
    #define INT_HOSTPORT_EMPTY_SHIFT 8
    #define INT_HOSTPORT_READY_MASK 0x00000200
    #define INT_HOSTPORT_READY_SHIFT 9
    #define INT_TAG_MASK 0x00000400
    #define INT_TAG_SHIFT 10
    #define INT_ERROR_MASK 0x00000800
    #define INT_ERROR_SHIFT 11
#define  G2D_INT_MASK 0x9A30
    #define G2D_INT_MASK_INT_MASK_FINISHED_MASK 0x00000001
    #define G2D_INT_MASK_INT_MASK_FINISHED_SHIFT 0
    #define INT_MASK_CMD_COMPLETE_MASK 0x00000002
    #define INT_MASK_CMD_COMPLETE_SHIFT 1
    #define INT_MASK_CMD_COMPLETE_AND_FLUSH_MASK 0x00000004
    #define INT_MASK_CMD_COMPLETE_AND_FLUSH_SHIFT 2
    #define INT_MASK_CMD_START_MASK 0x00000008
    #define INT_MASK_CMD_START_SHIFT 3
    #define INT_MASK_CMDFIFO_EMPTY_MASK 0x00000010
    #define INT_MASK_CMDFIFO_EMPTY_SHIFT 4
    #define INT_MASK_CMDFIFO_WATERMARK_MASK 0x00000020
    #define INT_MASK_CMDFIFO_WATERMARK_SHIFT 5
    #define INT_MASK_CMDBUFFER_EMPTY_MASK 0x00000040
    #define INT_MASK_CMDBUFFER_EMPTY_SHIFT 6
    #define INT_MASK_CMDFIFO_BUFFER_EMPTY_MASK 0x00000080
    #define INT_MASK_CMDFIFO_BUFFER_EMPTY_SHIFT 7
    #define INT_MASK_HOSTPORT_EMPTY_MASK 0x00000100
    #define INT_MASK_HOSTPORT_EMPTY_SHIFT 8
    #define INT_MASK_HOSTPORT_READY_MASK 0x00000200
    #define INT_MASK_HOSTPORT_READY_SHIFT 9
    #define INT_MASK_TAG_MASK 0x00000400
    #define INT_MASK_TAG_SHIFT 10
    #define INT_MASK_ERROR_MASK 0x00000800
    #define INT_MASK_ERROR_SHIFT 11
#define  G2D_LINE_DRAW_ENDYX 0x980C
    #define DST_ENDX_MASK 0x00007FFF
    #define DST_ENDX_SHIFT 0
    #define DST_ENDY_MASK 0x7FFF0000
    #define DST_ENDY_SHIFT 16
#define  G2D_LOWER_VALID_MEM 0x9884
    #define LOWVALID_MASK 0x7FFFFF00
    #define LOWVALID_SHIFT 8
#define  G2D_LUT_DATA 0x9874
    #define LUT_DATA_MASK 0xFFFFFFFF
    #define LUT_DATA_SHIFT 0
#define  G2D_MARB_CTRL 0x9A10
    #define G2D_MARB_CTRL_MEM_CNT_RESET_MASK 0x00000001
    #define G2D_MARB_CTRL_MEM_CNT_RESET_SHIFT 0
    #define G2D_MARB_CTRL_MEM_CNT_EN_MASK 0x00000002
    #define G2D_MARB_CTRL_MEM_CNT_EN_SHIFT 1
    #define G2D_MARB_CTRL_MEM_CNT_SEL_MASK 0x00000004
    #define G2D_MARB_CTRL_MEM_CNT_SEL_SHIFT 2
    #define G2D_MARB_CTRL_READ_ACCEL_MASK 0x00000008
    #define G2D_MARB_CTRL_READ_ACCEL_SHIFT 3
    #define G2D_MARB_CTRL_PF_ARB_DIS_MASK 0x00000010
    #define G2D_MARB_CTRL_PF_ARB_DIS_SHIFT 4
    #define G2D_MARB_CTRL_WOP_ARB_DIS_MASK 0x00000020
    #define G2D_MARB_CTRL_WOP_ARB_DIS_SHIFT 5
    #define G2D_MARB_CTRL_MEM_DENSITY_MASK 0x000000C0
    #define G2D_MARB_CTRL_MEM_DENSITY_SHIFT 6
    #define G2D_MARB_CTRL_ABSOLUTE_PRIORITY_MASK 0x0000F000
    #define G2D_MARB_CTRL_ABSOLUTE_PRIORITY_SHIFT 12
    #define G2D_MARB_CTRL_CLI0_REQ_CNT_LIMIT_MASK 0x000F0000
    #define G2D_MARB_CTRL_CLI0_REQ_CNT_LIMIT_SHIFT 16
    #define G2D_MARB_CTRL_CLI1_REQ_CNT_LIMIT_MASK 0x00F00000
    #define G2D_MARB_CTRL_CLI1_REQ_CNT_LIMIT_SHIFT 20
    #define G2D_MARB_CTRL_CLI2_REQ_CNT_LIMIT_MASK 0x0F000000
    #define G2D_MARB_CTRL_CLI2_REQ_CNT_LIMIT_SHIFT 24
    #define G2D_MARB_CTRL_CLI3_REQ_CNT_LIMIT_MASK 0xF0000000
    #define G2D_MARB_CTRL_CLI3_REQ_CNT_LIMIT_SHIFT 28
#define  G2D_MEM_CNT 0x9A1C
    #define G2D_MEM_CNT_MEM_CNT_MASK 0x00FFFFFF
    #define G2D_MEM_CNT_MEM_CNT_SHIFT 0
#define  G2D_OP_CTL 0x9804
    #define SRC_SELECT_MASK 0x000000FF
    #define SRC_SELECT_SHIFT 0
    #define GFX_ROP_MASK 0x00001F00
    #define GFX_ROP_SHIFT 8
    #define BLTDIR_MASK 0x0000E000
    #define BLTDIR_SHIFT 13
    #define GFX_OP_MASK 0x000F0000
    #define GFX_OP_SHIFT 16
    #define FLUSH_HOST_MASK 0x00100000
    #define FLUSH_HOST_SHIFT 20
    #define SCISSOR_DIS_MASK 0x00200000
    #define SCISSOR_DIS_SHIFT 21
    #define COLOR_KEY_MASK 0x00400000
    #define COLOR_KEY_SHIFT 22
    #define SRC_ALPHA_MASK 0x00800000
    #define SRC_ALPHA_SHIFT 23
    #define GFX_ROP_MODE_MASK 0x01000000
    #define GFX_ROP_MODE_SHIFT 24
    #define DEST_BLT_DIR_MASK 0x0E000000
    #define DEST_BLT_DIR_SHIFT 25
    #define GFX_ALPHA_MODE_MASK 0xF0000000
    #define GFX_ALPHA_MODE_SHIFT 28
#define  G2D_PATTERN_DATA0 0x983C
    #define PATTERN_DATA0_MASK 0xFFFFFFFF
    #define PATTERN_DATA0_SHIFT 0
#define  G2D_PATTERN_DATA1 0x9840
    #define PATTERN_DATA1_MASK 0xFFFFFFFF
    #define PATTERN_DATA1_SHIFT 0
#define  G2D_PEN_DATA 0x9844
    #define PEN_DATA_MASK 0xFFFFFFFF
    #define PEN_DATA_SHIFT 0
#define  G2D_RESET 0x9A04
    #define RESET_CTRL_NS_MASK 0x00000001
    #define RESET_CTRL_NS_SHIFT 0
    #define RESET_CMDFIFO_NS_MASK 0x00000002
    #define RESET_CMDFIFO_NS_SHIFT 1
    #define RESET_HOSTPORT_NS_MASK 0x00000004
    #define RESET_HOSTPORT_NS_SHIFT 2
    #define RESET_SRCBUFFER_NS_MASK 0x00000008
    #define RESET_SRCBUFFER_NS_SHIFT 3
    #define RESET_OUTPUT_NS_MASK 0x00000010
    #define RESET_OUTPUT_NS_SHIFT 4
    #define RESET_ENGINES_NS_MASK 0x00000020
    #define RESET_ENGINES_NS_SHIFT 5
    #define RESET_MARB_NS_MASK 0x00000040
    #define RESET_MARB_NS_SHIFT 6
#define  G2D_SCALERYX 0x9878
    #define XSCALER_MASK 0x00007FFF
    #define XSCALER_SHIFT 0
    #define YSCALER_MASK 0x7FFF0000
    #define YSCALER_SHIFT 16
#define  G2D_SC_BOTTOM_RIGHT 0x9838
    #define SC_RIGHT_MASK 0x00007FFF
    #define SC_RIGHT_SHIFT 0
    #define SC_BOTTOM_MASK 0x7FFF0000
    #define SC_BOTTOM_SHIFT 16
#define  G2D_SC_TOP_LEFT 0x9834
    #define SC_LEFT_MASK 0x00007FFF
    #define SC_LEFT_SHIFT 0
    #define SC_TOP_MASK 0x7FFF0000
    #define SC_TOP_SHIFT 16
#define  G2D_SRC_CTRL 0x988C
    #define SRC_CACHE_DISABLE_MASK 0x00000001
    #define SRC_CACHE_DISABLE_SHIFT 0
    #define SRC_CACHE_SAVE_MASK 0x00000002
    #define SRC_CACHE_SAVE_SHIFT 1
    #define SRC_CACHE_INVALIDATE_MASK 0x00000004
    #define SRC_CACHE_INVALIDATE_SHIFT 2
    #define SRC_BUFFER_SLOW_STOP_MASK 0x00000008
    #define SRC_BUFFER_SLOW_STOP_SHIFT 3
    #define SRC_EMERGENCY_FAST_MASK 0x00000010
    #define SRC_EMERGENCY_FAST_SHIFT 4
    #define SRC_PREFETCH_ON_MASK 0x00000020
    #define SRC_PREFETCH_ON_SHIFT 5
    #define SRC_PREFETCH_AUTO_MASK 0x00000040
    #define SRC_PREFETCH_AUTO_SHIFT 6
    #define SRC_BIG_DISABLE_MASK 0x00000080
    #define SRC_BIG_DISABLE_SHIFT 7
    #define SRC_REACT_ONLY_MASK 0x00000100
    #define SRC_REACT_ONLY_SHIFT 8
    #define SRC_DISABLE_VIXS_RTL_MODE_MASK 0x00000200
    #define SRC_DISABLE_VIXS_RTL_MODE_SHIFT 9
    #define SRCBUFFER_REQUEST_LIMIT_MASK 0x0000F000
    #define SRCBUFFER_REQUEST_LIMIT_SHIFT 12
#define  G2D_SRC_H_W 0x982C
    #define SRC_W_MASK 0x00003FFF
    #define SRC_W_SHIFT 0
    #define SRC_H_MASK 0x3FFF0000
    #define SRC_H_SHIFT 16
#define  G2D_SRC_OFFSET 0x9820
    #define SRC_BYTE_OFFSET_MASK 0x7FFFFFF0
    #define SRC_BYTE_OFFSET_SHIFT 4
#define  G2D_SRC_PITCH_FORMAT 0x9824
    #define G2D_SRC_PITCH_FORMAT_SRC_PITCH_MASK 0x00003FFF
    #define G2D_SRC_PITCH_FORMAT_SRC_PITCH_SHIFT 0
    #define SRC_PIX_FORMAT_MASK 0x000F0000
    #define SRC_PIX_FORMAT_SHIFT 16
    #define SRC_SCALE_BLT_ALPHA_PREMULT_MASK 0x04000000
    #define SRC_SCALE_BLT_ALPHA_PREMULT_SHIFT 26
    #define SRC_SCALE_BLT_INIT_MASK 0x08000000
    #define SRC_SCALE_BLT_INIT_SHIFT 27
    #define SRC_RLE_DATA_MASK 0x10000000
    #define SRC_RLE_DATA_SHIFT 28
    #define SRC_ENDIAN_MASK 0x20000000
    #define SRC_ENDIAN_SHIFT 29
    #define SRC_LINEAR_DATA_MASK 0x40000000
    #define SRC_LINEAR_DATA_SHIFT 30
    #define SCALING_TYPE_MASK 0x80000000
    #define SCALING_TYPE_SHIFT 31
#define  G2D_SRC_Y_X 0x9828
    #define SRC_X_MASK 0x00003FFF
    #define SRC_X_SHIFT 0
    #define SRC_Y_MASK 0x3FFF0000
    #define SRC_Y_SHIFT 16
#define  G2D_STATUS2 0x9B04
    #define STAT_CTRL_STATE_MASK 0x0000000F
    #define STAT_CTRL_STATE_SHIFT 0
    #define STAT_OUTPUT_BUSY1_MASK 0x00010000
    #define STAT_OUTPUT_BUSY1_SHIFT 16
    #define STAT_OUTPUT_BUSY2_MASK 0x00020000
    #define STAT_OUTPUT_BUSY2_SHIFT 17
    #define STAT_OUTPUT_BUSY3_MASK 0x00040000
    #define STAT_OUTPUT_BUSY3_SHIFT 18
    #define STAT_OUTPUT_BUSY4_MASK 0x00080000
    #define STAT_OUTPUT_BUSY4_SHIFT 19
    #define STAT_OUTPUT_ST0_MASK 0x00300000
    #define STAT_OUTPUT_ST0_SHIFT 20
    #define STAT_OUTPUT_ST1_MASK 0x00C00000
    #define STAT_OUTPUT_ST1_SHIFT 22
    #define STAT_OUTPUT_MASK 0x0F000000
    #define STAT_OUTPUT_SHIFT 24
#define  G2D_TAG 0x9890
    #define G2D_TAG_TAG_MASK 0x000000FF
    #define G2D_TAG_TAG_SHIFT 0
    #define TAG_INTERRUPT_MASK 0x00000100
    #define TAG_INTERRUPT_SHIFT 8
#define  G2D_TL_GRADIENT_CLR 0x9850
    #define TL_GRADIENT_CLR_MASK 0xFFFFFFFF
    #define TL_GRADIENT_CLR_SHIFT 0
#define  G2D_TOP_VALID_MEM 0x9888
    #define HIGHVALID_MASK 0x7FFFFF00
    #define HIGHVALID_SHIFT 8
#define  G2D_TR_GRADIENT_CLR 0x9854
    #define TR_GRADIENT_CLR_MASK 0xFFFFFFFF
    #define TR_GRADIENT_CLR_SHIFT 0
#define  GFX_ALPHA_GRADIENT 0x9830
    #define GFX_ALPHA_TOPLEFT_MASK 0x000000FF
    #define GFX_ALPHA_TOPLEFT_SHIFT 0
    #define GFX_ALPHA_TOPRIGHT_MASK 0x0000FF00
    #define GFX_ALPHA_TOPRIGHT_SHIFT 8
    #define GFX_ALPHA_BOTLEFT_MASK 0x00FF0000
    #define GFX_ALPHA_BOTLEFT_SHIFT 16
    #define GFX_ALPHA_BOTRIGHT_MASK 0xFF000000
    #define GFX_ALPHA_BOTRIGHT_SHIFT 24
#define  GPIO_B_CTRL 0xFC1C
    #define GPIO_B_CTRL_HOST_INT_MASK_MASK 0x00000001
    #define GPIO_B_CTRL_HOST_INT_MASK_SHIFT 0
    #define GPIO_B_CTRL_MIPS_INT_MASK_MASK 0x00000002
    #define GPIO_B_CTRL_MIPS_INT_MASK_SHIFT 1
    #define GPIO_B_CTRL_GPIO_MODE_SEL_MASK 0x80000000
    #define GPIO_B_CTRL_GPIO_MODE_SEL_SHIFT 31
#define  GPIO_B_IN 0xFC10
    #define GPIO_B_IN_GPIO_IN_MASK 0x00007FFF
    #define GPIO_B_IN_GPIO_IN_SHIFT 0
#define  GPIO_B_OE 0xFC18
    #define GPIO_B_OE_GPIO_OE_MASK 0x00007FFF
    #define GPIO_B_OE_GPIO_OE_SHIFT 0
#define  GPIO_B_OUT 0xFC14
    #define GPIO_B_OUT_GPIO_OUT_MASK 0x00007FFF
    #define GPIO_B_OUT_GPIO_OUT_SHIFT 0
#define  GPIO_C_CTRL 0xFC2C
    #define HOST_INT_MASK0_MASK 0x00000001
    #define HOST_INT_MASK0_SHIFT 0
    #define HOST_INT_MASK1_MASK 0x00000002
    #define HOST_INT_MASK1_SHIFT 1
    #define HOST_INT_MASK2_MASK 0x00000004
    #define HOST_INT_MASK2_SHIFT 2
    #define HOST_INT_MASK3_MASK 0x00000008
    #define HOST_INT_MASK3_SHIFT 3
    #define MIPS_INT_MASK0_MASK 0x00000010
    #define MIPS_INT_MASK0_SHIFT 4
    #define MIPS_INT_MASK1_MASK 0x00000020
    #define MIPS_INT_MASK1_SHIFT 5
    #define MIPS_INT_MASK2_MASK 0x00000040
    #define MIPS_INT_MASK2_SHIFT 6
    #define MIPS_INT_MASK3_MASK 0x00000080
    #define MIPS_INT_MASK3_SHIFT 7
    #define GPIO_MODE_SEL0_MASK 0x10000000
    #define GPIO_MODE_SEL0_SHIFT 28
    #define GPIO_MODE_SEL1_MASK 0x20000000
    #define GPIO_MODE_SEL1_SHIFT 29
    #define GPIO_MODE_SEL2_MASK 0x40000000
    #define GPIO_MODE_SEL2_SHIFT 30
    #define GPIO_MODE_SEL3_MASK 0x80000000
    #define GPIO_MODE_SEL3_SHIFT 31
#define  GPIO_C_IN 0xFC20
    #define GPIO_C_IN_GPIO_IN_MASK 0x1FFFFFFF
    #define GPIO_C_IN_GPIO_IN_SHIFT 0
#define  GPIO_C_OE 0xFC28
    #define GPIO_C_OE_GPIO_OE_MASK 0x1FFFFFFF
    #define GPIO_C_OE_GPIO_OE_SHIFT 0
#define  GPIO_C_OUT 0xFC24
    #define GPIO_C_OUT_GPIO_OUT_MASK 0x1FFFFFFF
    #define GPIO_C_OUT_GPIO_OUT_SHIFT 0
#define  GPIO_DEDICATED_IN 0x1108
    #define GPIO_DEDICATED_IN0_MASK 0x00000001
    #define GPIO_DEDICATED_IN0_SHIFT 0
    #define GPIO_DEDICATED_IN1_MASK 0x00000002
    #define GPIO_DEDICATED_IN1_SHIFT 1
    #define GPIO_DEDICATED_IN2_MASK 0x00000004
    #define GPIO_DEDICATED_IN2_SHIFT 2
    #define GPIO_DEDICATED_IN3_MASK 0x00000008
    #define GPIO_DEDICATED_IN3_SHIFT 3
    #define GPIO_DEDICATED_IN4_MASK 0x00000010
    #define GPIO_DEDICATED_IN4_SHIFT 4
    #define GPIO_DEDICATED_IN5_MASK 0x00000020
    #define GPIO_DEDICATED_IN5_SHIFT 5
    #define GPIO_DEDICATED_IN6_MASK 0x00000040
    #define GPIO_DEDICATED_IN6_SHIFT 6
    #define GPIO_DEDICATED_IN7_MASK 0x00000080
    #define GPIO_DEDICATED_IN7_SHIFT 7
#define  GPIO_DEDICATED_OUT 0x1100
    #define GPIO_DEDICATED_OUT0_MASK 0x00000001
    #define GPIO_DEDICATED_OUT0_SHIFT 0
    #define GPIO_DEDICATED_OUT1_MASK 0x00000002
    #define GPIO_DEDICATED_OUT1_SHIFT 1
    #define GPIO_DEDICATED_OUT2_MASK 0x00000004
    #define GPIO_DEDICATED_OUT2_SHIFT 2
    #define GPIO_DEDICATED_OUT3_MASK 0x00000008
    #define GPIO_DEDICATED_OUT3_SHIFT 3
    #define GPIO_DEDICATED_OUT4_MASK 0x00000010
    #define GPIO_DEDICATED_OUT4_SHIFT 4
    #define GPIO_DEDICATED_OUT5_MASK 0x00000020
    #define GPIO_DEDICATED_OUT5_SHIFT 5
    #define GPIO_DEDICATED_OUT6_MASK 0x00000040
    #define GPIO_DEDICATED_OUT6_SHIFT 6
    #define GPIO_DEDICATED_OUT7_MASK 0x00000080
    #define GPIO_DEDICATED_OUT7_SHIFT 7
#define  GPIO_DEDICATED_OUTEN 0x1104
    #define GPIO_DEDICATED_OUTEN0_MASK 0x00000001
    #define GPIO_DEDICATED_OUTEN0_SHIFT 0
    #define GPIO_DEDICATED_OUTEN1_MASK 0x00000002
    #define GPIO_DEDICATED_OUTEN1_SHIFT 1
    #define GPIO_DEDICATED_OUTEN2_MASK 0x00000004
    #define GPIO_DEDICATED_OUTEN2_SHIFT 2
    #define GPIO_DEDICATED_OUTEN3_MASK 0x00000008
    #define GPIO_DEDICATED_OUTEN3_SHIFT 3
    #define GPIO_DEDICATED_OUTEN4_MASK 0x00000010
    #define GPIO_DEDICATED_OUTEN4_SHIFT 4
    #define GPIO_DEDICATED_OUTEN5_MASK 0x00000020
    #define GPIO_DEDICATED_OUTEN5_SHIFT 5
    #define GPIO_DEDICATED_OUTEN6_MASK 0x00000040
    #define GPIO_DEDICATED_OUTEN6_SHIFT 6
    #define GPIO_DEDICATED_OUTEN7_MASK 0x00000080
    #define GPIO_DEDICATED_OUTEN7_SHIFT 7
    #define GPIO_INT_EDGE_LVL_MASK 0x40000000
    #define GPIO_INT_EDGE_LVL_SHIFT 30
    #define GPIO_INT_POLARITY_MASK 0x80000000
    #define GPIO_INT_POLARITY_SHIFT 31
#define  GPIO_D_CTRL 0xFC3C
    #define GPIO_D_CTRL_HOST_INT_MASK_MASK 0x00000001
    #define GPIO_D_CTRL_HOST_INT_MASK_SHIFT 0
    #define GPIO_D_CTRL_MIPS_INT_MASK_MASK 0x00000002
    #define GPIO_D_CTRL_MIPS_INT_MASK_SHIFT 1
    #define GPIO_D_CTRL_GPIO_MODE_SEL_MASK 0xE0000000
    #define GPIO_D_CTRL_GPIO_MODE_SEL_SHIFT 29
#define  GPIO_D_IN 0xFC30
    #define GPIO_D_IN_GPIO_IN_MASK 0x000003FF
    #define GPIO_D_IN_GPIO_IN_SHIFT 0
#define  GPIO_D_OE 0xFC38
    #define GPIO_D_OE_GPIO_OE_MASK 0x000003FF
    #define GPIO_D_OE_GPIO_OE_SHIFT 0
#define  GPIO_D_OUT 0xFC34
    #define GPIO_D_OUT_GPIO_OUT_MASK 0x000003FF
    #define GPIO_D_OUT_GPIO_OUT_SHIFT 0
#define  GPIO_E_CTRL 0xFC4C
    #define GPIO_E_CTRL_HOST_INT_MASK_MASK 0x00000001
    #define GPIO_E_CTRL_HOST_INT_MASK_SHIFT 0
    #define GPIO_E_CTRL_MIPS_INT_MASK_MASK 0x00000002
    #define GPIO_E_CTRL_MIPS_INT_MASK_SHIFT 1
    #define GPIO_E_CTRL_GPIO_MODE_SEL_MASK 0xC0000000
    #define GPIO_E_CTRL_GPIO_MODE_SEL_SHIFT 30
#define  GPIO_E_IN 0xFC40
    #define GPIO_E_IN_GPIO_IN_MASK 0x0000003F
    #define GPIO_E_IN_GPIO_IN_SHIFT 0
#define  GPIO_E_OE 0xFC48
    #define GPIO_E_OE_GPIO_OE_MASK 0x0000003F
    #define GPIO_E_OE_GPIO_OE_SHIFT 0
#define  GPIO_E_OUT 0xFC44
    #define GPIO_E_OUT_GPIO_OUT_MASK 0x0000003F
    #define GPIO_E_OUT_GPIO_OUT_SHIFT 0
#define  GPIO_F_CTRL 0xFC5C
    #define GPIO_F_CTRL_HOST_INT_MASK_MASK 0x00000001
    #define GPIO_F_CTRL_HOST_INT_MASK_SHIFT 0
    #define GPIO_F_CTRL_MIPS_INT_MASK_MASK 0x00000002
    #define GPIO_F_CTRL_MIPS_INT_MASK_SHIFT 1
    #define GPIO_F_CTRL_GPIO_MODE_SEL_MASK 0x80000000
    #define GPIO_F_CTRL_GPIO_MODE_SEL_SHIFT 31
#define  GPIO_F_IN 0xFC50
    #define GPIO_F_IN_GPIO_IN_MASK 0x000003FF
    #define GPIO_F_IN_GPIO_IN_SHIFT 0
#define  GPIO_F_OE 0xFC58
    #define GPIO_F_OE_GPIO_OE_MASK 0x000003FF
    #define GPIO_F_OE_GPIO_OE_SHIFT 0
#define  GPIO_F_OUT 0xFC54
    #define GPIO_F_OUT_GPIO_OUT_MASK 0x000003FF
    #define GPIO_F_OUT_GPIO_OUT_SHIFT 0
#define  GPIO_G_CTRL 0xFC6C
    #define GPIO_G_CTRL_HOST_INT_MASK_MASK 0x00000001
    #define GPIO_G_CTRL_HOST_INT_MASK_SHIFT 0
    #define GPIO_G_CTRL_MIPS_INT_MASK_MASK 0x00000002
    #define GPIO_G_CTRL_MIPS_INT_MASK_SHIFT 1
    #define GPIO_G_CTRL_GPIO_MODE_SEL_MASK 0x80000000
    #define GPIO_G_CTRL_GPIO_MODE_SEL_SHIFT 31
#define  GPIO_G_IN 0xFC60
    #define GPIO_G_IN_GPIO_IN_MASK 0x000003FF
    #define GPIO_G_IN_GPIO_IN_SHIFT 0
#define  GPIO_G_OE 0xFC68
    #define GPIO_G_OE_GPIO_OE_MASK 0x000003FF
    #define GPIO_G_OE_GPIO_OE_SHIFT 0
    #define DVE_OE_MASK 0x00000400
    #define DVE_OE_SHIFT 10
#define  GPIO_G_OUT 0xFC64
    #define GPIO_G_OUT_GPIO_OUT_MASK 0x000003FF
    #define GPIO_G_OUT_GPIO_OUT_SHIFT 0
#define  GPIO_H_CTRL 0xFC7C
    #define GPIO_H_CTRL_HOST_INT_MASK_MASK 0x00000001
    #define GPIO_H_CTRL_HOST_INT_MASK_SHIFT 0
    #define GPIO_H_CTRL_MIPS_INT_MASK_MASK 0x00000002
    #define GPIO_H_CTRL_MIPS_INT_MASK_SHIFT 1
    #define GPIO_H_CTRL_GPIO_MODE_SEL_MASK 0x80000000
    #define GPIO_H_CTRL_GPIO_MODE_SEL_SHIFT 31
#define  GPIO_H_IN 0xFC70
    #define GPIO_H_IN_GPIO_IN_MASK 0xFFFFFFFF
    #define GPIO_H_IN_GPIO_IN_SHIFT 0
#define  GPIO_H_OE 0xFC78
    #define GPIO_H_OE_GPIO_OE_MASK 0xFFFFFFFF
    #define GPIO_H_OE_GPIO_OE_SHIFT 0
#define  GPIO_H_OUT 0xFC74
    #define GPIO_H_OUT_GPIO_OUT_MASK 0xFFFFFFFF
    #define GPIO_H_OUT_GPIO_OUT_SHIFT 0
#define  GPIO_I_CTRL 0xFC8C
    #define GPIO_I_CTRL_HOST_INT_MASK_MASK 0x00000001
    #define GPIO_I_CTRL_HOST_INT_MASK_SHIFT 0
    #define GPIO_I_CTRL_MIPS_INT_MASK_MASK 0x00000002
    #define GPIO_I_CTRL_MIPS_INT_MASK_SHIFT 1
    #define GPIO_I_CTRL_GPIO_MODE_SEL_MASK 0xFE000000
    #define GPIO_I_CTRL_GPIO_MODE_SEL_SHIFT 25
#define  GPIO_I_IN 0xFC80
    #define GPIO_I_IN_GPIO_IN_MASK 0x0000FFFF
    #define GPIO_I_IN_GPIO_IN_SHIFT 0
#define  GPIO_I_OE 0xFC88
    #define GPIO_I_OE_GPIO_OE_MASK 0x0000FFFF
    #define GPIO_I_OE_GPIO_OE_SHIFT 0
#define  GPIO_I_OUT 0xFC84
    #define GPIO_I_OUT_GPIO_OUT_MASK 0x0000FFFF
    #define GPIO_I_OUT_GPIO_OUT_SHIFT 0
#define  GVD_CMD_FIFO_0 0x8810
    #define GVD_CMD_FIFO_0_DATA_MASK 0xFFFFFFFF
    #define GVD_CMD_FIFO_0_DATA_SHIFT 0
#define  GVD_CMD_FIFO_1 0x8814
    #define GVD_CMD_FIFO_1_VALUE_MASK 0x1FFFFFFF
    #define GVD_CMD_FIFO_1_VALUE_SHIFT 0
    #define GVD_CMD_MASK 0xE0000000
    #define GVD_CMD_SHIFT 29
#define  GVD_CMD_REGISTER 0x881C
    #define GVD_CMD_REGISTER_DATA_MASK 0xFFFFFFFF
    #define GVD_CMD_REGISTER_DATA_SHIFT 0
#define  GVD_CMD_STATUS 0x8818
    #define GVD_CMD_STATUS_FIFO_FREE_MASK 0x0000001F
    #define GVD_CMD_STATUS_FIFO_FREE_SHIFT 0
    #define GVD_DCP_BUSY_MASK 0x80000000
    #define GVD_DCP_BUSY_SHIFT 31
#define  GVD_CTRL 0x883C
    #define GVD_SETTLE_MASK 0x00000007
    #define GVD_SETTLE_SHIFT 0
#define  GVD_DBK_C0_OFFSET 0x894C
    #define GVD_DBK_C0_OFFSET_ALPHA_C0_OFFSET_DIV2_MASK 0x0000000F
    #define GVD_DBK_C0_OFFSET_ALPHA_C0_OFFSET_DIV2_SHIFT 0
    #define GVD_DBK_C0_OFFSET_BETA_C0_OFFSET_DIV2_MASK 0x00000F00
    #define GVD_DBK_C0_OFFSET_BETA_C0_OFFSET_DIV2_SHIFT 8
#define  GVD_DBK_CHROMA_QP_INDEX_OFFSET 0x8950
    #define GVD_DBK_CHROMA_QP_INDEX_OFFSET_CHROMA_QP_INDEX_OFFSET_MASK 0x0000001F
    #define GVD_DBK_CHROMA_QP_INDEX_OFFSET_CHROMA_QP_INDEX_OFFSET_SHIFT 0
    #define SECOND_CHROMA_QP_INDEX_OFFSET_MASK 0x00001F00
    #define SECOND_CHROMA_QP_INDEX_OFFSET_SHIFT 8
#define  GVD_DBK_CTRL 0x8944
    #define GVD_DBK_CTRL_DBK_BYPASS_MASK 0x00000001
    #define GVD_DBK_CTRL_DBK_BYPASS_SHIFT 0
    #define GVD_DBK_CTRL_DBK_DISABLE_MASK 0x00000002
    #define GVD_DBK_CTRL_DBK_DISABLE_SHIFT 1
    #define DBK_TILED_OUT_DIS_MASK 0x00000004
    #define DBK_TILED_OUT_DIS_SHIFT 2
    #define DBK_LINEAR_OUT_DIS_MASK 0x00000008
    #define DBK_LINEAR_OUT_DIS_SHIFT 3
    #define GVD_DBK_CTRL_DBK_REF_INDEX_MASK 0x00001F00
    #define GVD_DBK_CTRL_DBK_REF_INDEX_SHIFT 8
    #define DBK_RANGE_INDEX_MASK 0x001F0000
    #define DBK_RANGE_INDEX_SHIFT 16
#define  GVD_DBK_DBG 0x8960
    #define GVD_DBK_DBG_DATA_MASK 0xFFFFFFFF
    #define GVD_DBK_DBG_DATA_SHIFT 0
#define  GVD_DBK_DBG_CTRL 0x895C
    #define GVD_DBK_DBG_CTRL_SEL_MASK 0x0000003F
    #define GVD_DBK_DBG_CTRL_SEL_SHIFT 0
    #define GVD_DBK_DBG_CTRL_MUX_MASK 0x00003F00
    #define GVD_DBK_DBG_CTRL_MUX_SHIFT 8
#define  GVD_DBK_FILT_C_ADR 0x896C
    #define GVD_DBK_FILT_C_ADR_BASE_MASK 0x7FFFFF00
    #define GVD_DBK_FILT_C_ADR_BASE_SHIFT 8
#define  GVD_DBK_FILT_Y_ADR 0x8968
    #define GVD_DBK_FILT_Y_ADR_BASE_MASK 0x7FFFFF00
    #define GVD_DBK_FILT_Y_ADR_BASE_SHIFT 8
#define  GVD_DBK_LINEAR_BUF 0x8980
    #define GVD_DBK_LINEAR_BUF_PITCH_MASK 0x00001FE0
    #define GVD_DBK_LINEAR_BUF_PITCH_SHIFT 5
    #define GVD_DBK_LINEAR_BUF_SIZE_MASK 0x7FFF0000
    #define GVD_DBK_LINEAR_BUF_SIZE_SHIFT 16
#define  GVD_DBK_LINEAR_CB_ADR 0x8978
    #define GVD_DBK_LINEAR_CB_ADR_BASE_MASK 0x7FFFFF00
    #define GVD_DBK_LINEAR_CB_ADR_BASE_SHIFT 8
#define  GVD_DBK_LINEAR_CR_ADR 0x897C
    #define GVD_DBK_LINEAR_CR_ADR_BASE_MASK 0x7FFFFF00
    #define GVD_DBK_LINEAR_CR_ADR_BASE_SHIFT 8
#define  GVD_DBK_LINEAR_Y_ADR 0x8974
    #define GVD_DBK_LINEAR_Y_ADR_BASE_MASK 0x7FFFFF00
    #define GVD_DBK_LINEAR_Y_ADR_BASE_SHIFT 8
#define  GVD_DBK_MARB_CTRL 0x8970
    #define GVD_DBK_MARB_CTRL_DBK_PF_ARB_DIS_MASK 0x00000001
    #define GVD_DBK_MARB_CTRL_DBK_PF_ARB_DIS_SHIFT 0
    #define GVD_DBK_MARB_CTRL_DBK_ABS_PRIORITY_MASK 0x00000002
    #define GVD_DBK_MARB_CTRL_DBK_ABS_PRIORITY_SHIFT 1
#define  GVD_DBK_RANGE_CTRL 0x8964
    #define MAPY_EN_MASK 0x00000001
    #define MAPY_EN_SHIFT 0
    #define MAPC_EN_MASK 0x00000010
    #define MAPC_EN_SHIFT 4
    #define RANGE_MAPY_MASK 0x00000700
    #define RANGE_MAPY_SHIFT 8
    #define RANGE_MAPC_MASK 0x00007000
    #define RANGE_MAPC_SHIFT 12
#define  GVD_DBK_START_MB 0x8940
    #define GVD_DBK_START_MB_START_MB_X_MASK 0x000000FF
    #define GVD_DBK_START_MB_START_MB_X_SHIFT 0
    #define GVD_DBK_START_MB_START_MB_Y_MASK 0x00007F00
    #define GVD_DBK_START_MB_START_MB_Y_SHIFT 8
#define  GVD_DBK_STATUS 0x8948
    #define GVD_DBK_STATUS_DBK_BUSY_MASK 0x00000001
    #define GVD_DBK_STATUS_DBK_BUSY_SHIFT 0
#define  GVD_DEBUG 0x8840
    #define GVD_DEBUG_DEBUG_MASK 0x000FFFFF
    #define GVD_DEBUG_DEBUG_SHIFT 0
#define  GVD_DMC_CACHE 0x89E8
    #define GVD_DMC_CACHE_INVALIDATE_MASK 0x00000002
    #define GVD_DMC_CACHE_INVALIDATE_SHIFT 1
#define  GVD_DMC_STATUS 0x88F0
    #define GVD_DMC_STATUS_MB_CNT_MASK 0x0007FFFF
    #define GVD_DMC_STATUS_MB_CNT_SHIFT 0
#define  GVD_DMC_VC1_CTRL 0x89D0
    #define PAD_OFFS_X_MASK 0x0000000F
    #define PAD_OFFS_X_SHIFT 0
    #define PAD_OFFS_Y_MASK 0x000000F0
    #define PAD_OFFS_Y_SHIFT 4
    #define RND_CTRL_MASK 0x00000100
    #define RND_CTRL_SHIFT 8
    #define FW_TOP_SLICE_STRUCT_MASK 0x00000600
    #define FW_TOP_SLICE_STRUCT_SHIFT 9
    #define FW_BOT_SLICE_STRUCT_MASK 0x00001800
    #define FW_BOT_SLICE_STRUCT_SHIFT 11
    #define INTERPOLATION_MODE_MASK 0x00002000
    #define INTERPOLATION_MODE_SHIFT 13
#define  GVD_DMC_VC1_INT_COMP_0 0x89D4
    #define I_SHIFT_0_MASK 0x0000FFFF
    #define I_SHIFT_0_SHIFT 0
    #define I_SCALE_0_MASK 0x00FF0000
    #define I_SCALE_0_SHIFT 16
    #define IC_EN_0_MASK 0x01000000
    #define IC_EN_0_SHIFT 24
    #define IC_EN_DUAL_IC2_MASK 0x02000000
    #define IC_EN_DUAL_IC2_SHIFT 25
    #define RR_EN_MASK 0x04000000
    #define RR_EN_SHIFT 26
    #define RR_DIR_MASK 0x08000000
    #define RR_DIR_SHIFT 27
#define  GVD_DMC_VC1_INT_COMP_1 0x89D8
    #define I_SHIFT_1_MASK 0x0000FFFF
    #define I_SHIFT_1_SHIFT 0
    #define I_SCALE_1_MASK 0x00FF0000
    #define I_SCALE_1_SHIFT 16
    #define IC_EN_1_MASK 0x01000000
    #define IC_EN_1_SHIFT 24
    #define IC_EN_DUAL_IC3_MASK 0x02000000
    #define IC_EN_DUAL_IC3_SHIFT 25
#define  GVD_DMC_VC1_INT_COMP_2 0x89DC
    #define I_SHIFT_2_MASK 0x0000FFFF
    #define I_SHIFT_2_SHIFT 0
    #define I_SCALE_2_MASK 0x00FF0000
    #define I_SCALE_2_SHIFT 16
    #define IC_EN_2_MASK 0x01000000
    #define IC_EN_2_SHIFT 24
    #define IC_EN_DUAL_IC0_MASK 0x02000000
    #define IC_EN_DUAL_IC0_SHIFT 25
#define  GVD_DMC_VC1_INT_COMP_3 0x89E0
    #define I_SHIFT_3_MASK 0x0000FFFF
    #define I_SHIFT_3_SHIFT 0
    #define I_SCALE_3_MASK 0x00FF0000
    #define I_SCALE_3_SHIFT 16
    #define IC_EN_3_MASK 0x01000000
    #define IC_EN_3_SHIFT 24
    #define IC_EN_DUAL_IC1_MASK 0x02000000
    #define IC_EN_DUAL_IC1_SHIFT 25
#define  GVD_DMC_VC1_INT_COMP_4 0x89E4
    #define I_SHIFT_4_MASK 0x0000FFFF
    #define I_SHIFT_4_SHIFT 0
    #define I_SCALE_4_MASK 0x00FF0000
    #define I_SCALE_4_SHIFT 16
    #define IC_EN_4_MASK 0x01000000
    #define IC_EN_4_SHIFT 24
    #define IC_BW_TOP_FIELD_MASK 0x02000000
    #define IC_BW_TOP_FIELD_SHIFT 25
#define  GVD_DMC_WEIGHT_CTRL 0x88E0
    #define LUMA_DNOM_MASK 0x00000007
    #define LUMA_DNOM_SHIFT 0
    #define CHROMA_DNOM_MASK 0x00000070
    #define CHROMA_DNOM_SHIFT 4
    #define WEIGHT_IMPLICIT_MODE_MASK 0x00000100
    #define WEIGHT_IMPLICIT_MODE_SHIFT 8
    #define GVD_DMC_WEIGHT_CTRL_WEIGHT_ENB_MASK 0x80000000
    #define GVD_DMC_WEIGHT_CTRL_WEIGHT_ENB_SHIFT 31
#define  GVD_DMC_WEIGHT_REFIDX_TABLE_C 0x88EC
    #define GVD_DMC_WEIGHT_REFIDX_TABLE_C_DATA_MASK 0xFFFFFFFF
    #define GVD_DMC_WEIGHT_REFIDX_TABLE_C_DATA_SHIFT 0
#define  GVD_DMC_WEIGHT_REFIDX_TABLE_CTRL 0x88E4
    #define GVD_DMC_WEIGHT_REFIDX_TABLE_CTRL_INDEX_MASK 0x0000003F
    #define GVD_DMC_WEIGHT_REFIDX_TABLE_CTRL_INDEX_SHIFT 0
#define  GVD_DMC_WEIGHT_REFIDX_TABLE_L 0x88E8
    #define GVD_DMC_WEIGHT_REFIDX_TABLE_L_DATA_MASK 0xFFFFFFFF
    #define GVD_DMC_WEIGHT_REFIDX_TABLE_L_DATA_SHIFT 0
#define  GVD_EDC_BB_POP 0x8B9C
    #define BB_POP_MASK 0x0000000F
    #define BB_POP_SHIFT 0
#define  GVD_EDC_BB_STATUS 0x8B98
    #define BB_DAT_MASK 0x00FFFFFF
    #define BB_DAT_SHIFT 0
    #define BB_CNT_MASK 0x3F000000
    #define BB_CNT_SHIFT 24
    #define BB_EPB_CNT_MASK 0xC0000000
    #define BB_EPB_CNT_SHIFT 30
#define  GVD_EDC_BUFFER_STATUS 0x8BC0
    #define GVD_EDC_BUFFER_STATUS_OUTPUT_NO_REQUESTS_MASK 0x00000001
    #define GVD_EDC_BUFFER_STATUS_OUTPUT_NO_REQUESTS_SHIFT 0
    #define GVD_EDC_BUFFER_STATUS_OUTPUT_FLUSHED_MASK 0x00000002
    #define GVD_EDC_BUFFER_STATUS_OUTPUT_FLUSHED_SHIFT 1
#define  GVD_EDC_CMD 0x8B80
    #define GVD_EDC_CMD_SLICE_COUNT_MASK 0x000000FF
    #define GVD_EDC_CMD_SLICE_COUNT_SHIFT 0
    #define VC1_OP_FLAG_MASK 0x00000100
    #define VC1_OP_FLAG_SHIFT 8
#define  GVD_EDC_CONFIG 0x8B88
    #define BYTE_ALIGN_MASK 0x00000001
    #define BYTE_ALIGN_SHIFT 0
    #define BIT_ALIGN_MASK 0x00000002
    #define BIT_ALIGN_SHIFT 1
    #define PPS_CFG_MASK 0x0000000C
    #define PPS_CFG_SHIFT 2
    #define SPS_CFG_MASK 0x00000030
    #define SPS_CFG_SHIFT 4
    #define PTR_CFG_MASK 0x00000040
    #define PTR_CFG_SHIFT 6
    #define CONTINUE_MASK 0x00000100
    #define CONTINUE_SHIFT 8
    #define SLICES_ONLY_MASK 0x00000200
    #define SLICES_ONLY_SHIFT 9
    #define START_CODE_ONLY_MASK 0x00000400
    #define START_CODE_ONLY_SHIFT 10
    #define DISABLE_UVLC_END_MASK 0x00000800
    #define DISABLE_UVLC_END_SHIFT 11
    #define CTRL_FAST_MASK 0x00001000
    #define CTRL_FAST_SHIFT 12
    #define SELECT_MAX_FIFO_MASK 0x00002000
    #define SELECT_MAX_FIFO_SHIFT 13
    #define BB_DISABLE_PTR_WRAP_MASK 0x00004000
    #define BB_DISABLE_PTR_WRAP_SHIFT 14
    #define RBSP_SLOW_MASK 0x00008000
    #define RBSP_SLOW_SHIFT 15
    #define RBSP_LAST_MB_MASK 0x00010000
    #define RBSP_LAST_MB_SHIFT 16
    #define DISABLE_FORCE_EPB_MASK 0x00020000
    #define DISABLE_FORCE_EPB_SHIFT 17
    #define DISABLE_SC_GIVEUP_MASK 0x00040000
    #define DISABLE_SC_GIVEUP_SHIFT 18
    #define DISABLE_SC_FORCE_POP_MASK 0x00080000
    #define DISABLE_SC_FORCE_POP_SHIFT 19
    #define DISABLE_BB_BIT_PULL_MASK 0x00100000
    #define DISABLE_BB_BIT_PULL_SHIFT 20
    #define DISABLE_BB_PCM_PULL_MASK 0x00200000
    #define DISABLE_BB_PCM_PULL_SHIFT 21
    #define NOSTOP_ON_RPTR_MASK 0x00400000
    #define NOSTOP_ON_RPTR_SHIFT 22
    #define RUN_CABAC_TEST_MASK 0x00800000
    #define RUN_CABAC_TEST_SHIFT 23
    #define NOFLUSH_SLICE_CONT_MASK 0x01000000
    #define NOFLUSH_SLICE_CONT_SHIFT 24
    #define INPUT_END_MODE_MASK 0x02000000
    #define INPUT_END_MODE_SHIFT 25
    #define CONT_ON_IL_ERR_MASK 0x04000000
    #define CONT_ON_IL_ERR_SHIFT 26
    #define CONT_ON_SC_ERR_MASK 0x08000000
    #define CONT_ON_SC_ERR_SHIFT 27
    #define CONT_ON_MB_ERR_MASK 0x10000000
    #define CONT_ON_MB_ERR_SHIFT 28
    #define CONT_ON_PPSSPS_ERR_MASK 0x20000000
    #define CONT_ON_PPSSPS_ERR_SHIFT 29
    #define CONT_ON_BB_ERR_MASK 0x40000000
    #define CONT_ON_BB_ERR_SHIFT 30
    #define CONT_ON_OTHER_ERR_MASK 0x80000000
    #define CONT_ON_OTHER_ERR_SHIFT 31
#define  GVD_EDC_CONFIG2 0x8BB4
    #define EPB_COUNT_MODE_MASK 0x00000001
    #define EPB_COUNT_MODE_SHIFT 0
    #define RBSP_VERIFY_EPB_MASK 0x00000006
    #define RBSP_VERIFY_EPB_SHIFT 1
    #define RBSP_VERIFY_MODE_MASK 0x00000008
    #define RBSP_VERIFY_MODE_SHIFT 3
    #define CHROMA_DC_SPEC_MODE_MASK 0x00000010
    #define CHROMA_DC_SPEC_MODE_SHIFT 4
    #define BB_24BITS_VAL_MASK 0x00000020
    #define BB_24BITS_VAL_SHIFT 5
    #define BB_CONSERVATIVE_MASK 0x00000040
    #define BB_CONSERVATIVE_SHIFT 6
    #define BB_CONSERVATIVE_END_MASK 0x00000080
    #define BB_CONSERVATIVE_END_SHIFT 7
    #define DISABLE_STOP_ON_ID_MASK 0x00000100
    #define DISABLE_STOP_ON_ID_SHIFT 8
    #define STOP_ON_ID_MODE_MASK 0x00000200
    #define STOP_ON_ID_MODE_SHIFT 9
    #define GVD_EDC_CONFIG2_OUTPUT_STOP_REQ_MASK 0x00000400
    #define GVD_EDC_CONFIG2_OUTPUT_STOP_REQ_SHIFT 10
    #define GVD_EDC_CONFIG2_OUTPUT_FLUSH_MASK 0x00000800
    #define GVD_EDC_CONFIG2_OUTPUT_FLUSH_SHIFT 11
    #define NAL_MODE_MASK 0x00003000
    #define NAL_MODE_SHIFT 12
    #define REF_IDX_MODE_MASK 0x00004000
    #define REF_IDX_MODE_SHIFT 14
    #define MVD_OF_MODE_MASK 0x00008000
    #define MVD_OF_MODE_SHIFT 15
    #define MCI_ENABLE_MASK 0x00010000
    #define MCI_ENABLE_SHIFT 16
    #define MCI_DISABLE_MASK 0x00020000
    #define MCI_DISABLE_SHIFT 17
    #define MCI_HOLDOFF_MASK 0x00040000
    #define MCI_HOLDOFF_SHIFT 18
    #define BB_CLEAR_MASK 0x00080000
    #define BB_CLEAR_SHIFT 19
    #define SYNTAX_STATUS_MUX_MASK 0x00700000
    #define SYNTAX_STATUS_MUX_SHIFT 20
    #define PANTHER_INPUT_STALL_MASK 0x00800000
    #define PANTHER_INPUT_STALL_SHIFT 23
    #define BB_CTRL_MODE_MASK 0xFF000000
    #define BB_CTRL_MODE_SHIFT 24
#define  GVD_EDC_CONFIG3 0x8B04
    #define VC1_PIC_MB_WIDTH_MASK 0x000000FF
    #define VC1_PIC_MB_WIDTH_SHIFT 0
    #define VC1_PIC_MB_HEIGHT_MASK 0x00007F00
    #define VC1_PIC_MB_HEIGHT_SHIFT 8
    #define GVD_EDC_CONFIG3_VC1_PROFILE_MASK 0x00030000
    #define GVD_EDC_CONFIG3_VC1_PROFILE_SHIFT 16
    #define VC1_RPIC_MASK 0x000C0000
    #define VC1_RPIC_SHIFT 18
    #define VC1_VSTRANSFORM_MASK 0x00100000
    #define VC1_VSTRANSFORM_SHIFT 20
    #define VC1_OVERLAP_MASK 0x00200000
    #define VC1_OVERLAP_SHIFT 21
    #define VC1_PULLDOWN_MASK 0x00400000
    #define VC1_PULLDOWN_SHIFT 22
    #define VC1_INTERLACE_MASK 0x00800000
    #define VC1_INTERLACE_SHIFT 23
    #define VC1_TFCNTRFLAG_MASK 0x01000000
    #define VC1_TFCNTRFLAG_SHIFT 24
    #define VC1_FINTERPFLAG_MASK 0x02000000
    #define VC1_FINTERPFLAG_SHIFT 25
    #define VC1_PSF_MASK 0x04000000
    #define VC1_PSF_SHIFT 26
    #define VC1_PANSCAN_FLAG_MASK 0x08000000
    #define VC1_PANSCAN_FLAG_SHIFT 27
    #define VC1_REFDIST_FLAG_MASK 0x10000000
    #define VC1_REFDIST_FLAG_SHIFT 28
    #define VC1_EXTENDED_MV_MASK 0x20000000
    #define VC1_EXTENDED_MV_SHIFT 29
    #define VC1_SEQ_VALID_FLAG_MASK 0x40000000
    #define VC1_SEQ_VALID_FLAG_SHIFT 30
    #define VC1_POST_PROC_FLAG_MASK 0x80000000
    #define VC1_POST_PROC_FLAG_SHIFT 31
#define  GVD_EDC_CONFIG4 0x8B2C
    #define VC1_DQUANT_MASK 0x00000003
    #define VC1_DQUANT_SHIFT 0
    #define VC1_QUANTIZER_MASK 0x0000000C
    #define VC1_QUANTIZER_SHIFT 2
    #define VC1_EXTENDED_DMV_MASK 0x00000010
    #define VC1_EXTENDED_DMV_SHIFT 4
    #define VC1_MUTIRES_MASK 0x00000020
    #define VC1_MUTIRES_SHIFT 5
    #define VC1_RANGERED_MASK 0x00000040
    #define VC1_RANGERED_SHIFT 6
    #define VC1_MAXBFRAMES_FLAG_MASK 0x00000080
    #define VC1_MAXBFRAMES_FLAG_SHIFT 7
    #define VC1_SYNC_MARKER_MASK 0x00000100
    #define VC1_SYNC_MARKER_SHIFT 8
    #define VC1_MAX_MB_NUM_MASK 0x0FFFF000
    #define VC1_MAX_MB_NUM_SHIFT 12
    #define VC1_DISABLE_OSTALL_MASK 0x10000000
    #define VC1_DISABLE_OSTALL_SHIFT 28
#define  GVD_EDC_CTRL_STATUS 0x8B8C
    #define CURR_MB_ADR_MASK 0x00007FFF
    #define CURR_MB_ADR_SHIFT 0
    #define GVD_EDC_CTRL_STATUS_SLICE_COUNT_MASK 0x03FF0000
    #define GVD_EDC_CTRL_STATUS_SLICE_COUNT_SHIFT 16
#define  GVD_EDC_DBG_CFG 0x8BB8
    #define DB_MUX_MASK 0x0000003F
    #define DB_MUX_SHIFT 0
#define  GVD_EDC_DBG_DAT 0x8BBC
    #define GVD_EDC_DBG_DAT_DATA_MASK 0x000FFFFF
    #define GVD_EDC_DBG_DAT_DATA_SHIFT 0
#define  GVD_EDC_ERR_DISABLE1 0x8BA4
    #define ERR_DISABLE1_MASK 0xFFFFFFFF
    #define ERR_DISABLE1_SHIFT 0
#define  GVD_EDC_ERR_DISABLE2 0x8BA8
    #define ERR_DISABLE2_MASK 0xFFFFFFFF
    #define ERR_DISABLE2_SHIFT 0
#define  GVD_EDC_INPUT_RB_BASE 0x8B30
    #define GVD_EDC_INPUT_RB_BASE_ADDR_MASK 0x7FFFFF80
    #define GVD_EDC_INPUT_RB_BASE_ADDR_SHIFT 7
#define  GVD_EDC_INPUT_RB_CTRL 0x8B34
    #define GVD_EDC_INPUT_RB_CTRL_SIZE_MASK 0x01FFFF80
    #define GVD_EDC_INPUT_RB_CTRL_SIZE_SHIFT 7
#define  GVD_EDC_INPUT_RB_RPTR 0x8B38
    #define GVD_EDC_INPUT_RB_RPTR_OFFSET_MASK 0x01FFFFFF
    #define GVD_EDC_INPUT_RB_RPTR_OFFSET_SHIFT 0
#define  GVD_EDC_INPUT_RB_RPTR_MEM 0x8B28
    #define GVD_EDC_INPUT_RB_RPTR_MEM_OFFSET_MASK 0x01FFFFFF
    #define GVD_EDC_INPUT_RB_RPTR_MEM_OFFSET_SHIFT 0
#define  GVD_EDC_INPUT_RB_WPTR 0x8B3C
    #define GVD_EDC_INPUT_RB_WPTR_OFFSET_MASK 0x01FFFFFF
    #define GVD_EDC_INPUT_RB_WPTR_OFFSET_SHIFT 0
    #define GVD_EDC_INPUT_RB_WPTR_END_FLAG_MASK 0x80000000
    #define GVD_EDC_INPUT_RB_WPTR_END_FLAG_SHIFT 31
#define  GVD_EDC_INT 0x8B94
    #define INT_PARSE_ERR_MASK 0x00000001
    #define INT_PARSE_ERR_SHIFT 0
    #define GVD_EDC_INT_INT_FINISHED_MASK 0x00000002
    #define GVD_EDC_INT_INT_FINISHED_SHIFT 1
    #define INT_INPUT_STALL_MASK 0x00000004
    #define INT_INPUT_STALL_SHIFT 2
    #define INT_OUTPUT_STALL_MASK 0x00000008
    #define INT_OUTPUT_STALL_SHIFT 3
    #define INT_SYNTAX_ERR_MASK 0x00000010
    #define INT_SYNTAX_ERR_SHIFT 4
    #define INT_FB_EMPTY_MASK 0x00000020
    #define INT_FB_EMPTY_SHIFT 5
#define  GVD_EDC_INT_MASK 0x8B90
    #define INT_MASK_PARSE_ERR_MASK 0x00000001
    #define INT_MASK_PARSE_ERR_SHIFT 0
    #define GVD_EDC_INT_MASK_INT_MASK_FINISHED_MASK 0x00000002
    #define GVD_EDC_INT_MASK_INT_MASK_FINISHED_SHIFT 1
    #define INT_MASK_INPUT_STALL_MASK 0x00000004
    #define INT_MASK_INPUT_STALL_SHIFT 2
    #define INT_MASK_OUTPUT_STALL_MASK 0x00000008
    #define INT_MASK_OUTPUT_STALL_SHIFT 3
    #define INT_MASK_SYNTAX_ERR_MASK 0x00000010
    #define INT_MASK_SYNTAX_ERR_SHIFT 4
    #define INT_MASK_FB_EMPTY_MASK 0x00000020
    #define INT_MASK_FB_EMPTY_SHIFT 5
#define  GVD_EDC_MBH_BASE_WPTR 0x8B00
    #define GVD_EDC_MBH_BASE_WPTR_DATA_MASK 0x7FFFFFF8
    #define GVD_EDC_MBH_BASE_WPTR_DATA_SHIFT 3
#define  GVD_EDC_MVD_RB_BASE 0x8B08
    #define GVD_EDC_MVD_RB_BASE_ADDR_MASK 0x7FFFFF80
    #define GVD_EDC_MVD_RB_BASE_ADDR_SHIFT 7
#define  GVD_EDC_MVD_RB_CTRL 0x8B0C
    #define GVD_EDC_MVD_RB_CTRL_SIZE_MASK 0x03FFFF80
    #define GVD_EDC_MVD_RB_CTRL_SIZE_SHIFT 7
#define  GVD_EDC_MVD_RB_RPTR 0x8B14
    #define GVD_EDC_MVD_RB_RPTR_OFFSET_MASK 0x03FFFFFC
    #define GVD_EDC_MVD_RB_RPTR_OFFSET_SHIFT 2
#define  GVD_EDC_MVD_RB_WPTR 0x8B10
    #define GVD_EDC_MVD_RB_WPTR_OFFSET_MASK 0x03FFFFFC
    #define GVD_EDC_MVD_RB_WPTR_OFFSET_SHIFT 2
#define  GVD_EDC_PPS_INFO_BASE 0x8B44
    #define GVD_EDC_PPS_INFO_BASE_ADDR_MASK 0x7FFFFFF0
    #define GVD_EDC_PPS_INFO_BASE_ADDR_SHIFT 4
#define  GVD_EDC_RESET 0x8BB0
    #define RESET_SYNTAX_MASK 0x00000001
    #define RESET_SYNTAX_SHIFT 0
    #define RESET_SYNTAX_FIFO_MASK 0x00000002
    #define RESET_SYNTAX_FIFO_SHIFT 1
    #define RESET_SYNTAX_ERR_MASK 0x00000004
    #define RESET_SYNTAX_ERR_SHIFT 2
    #define RESET_BB_MASK 0x00000008
    #define RESET_BB_SHIFT 3
    #define RESET_MCI_MASK 0x00000010
    #define RESET_MCI_SHIFT 4
    #define RESET_CTRL_MASK 0x00000020
    #define RESET_CTRL_SHIFT 5
    #define RESET_BIN_MASK 0x00000040
    #define RESET_BIN_SHIFT 6
    #define RESET_VC1_MASK 0x00000100
    #define RESET_VC1_SHIFT 8
    #define RESET_VC1_PL_MASK 0x00000200
    #define RESET_VC1_PL_SHIFT 9
    #define RESET_VC1_MBL_MASK 0x00000400
    #define RESET_VC1_MBL_SHIFT 10
    #define RESET_VC1_BP_MASK 0x00000800
    #define RESET_VC1_BP_SHIFT 11
    #define RESET_VC1_BL_MASK 0x00001000
    #define RESET_VC1_BL_SHIFT 12
    #define RESET_VC1_PMV_MASK 0x00002000
    #define RESET_VC1_PMV_SHIFT 13
    #define INIT_VC1_SE_MASK 0x00004000
    #define INIT_VC1_SE_SHIFT 14
    #define GVD_EDC_RESET_SOFT_RST_MASK 0x00010000
    #define GVD_EDC_RESET_SOFT_RST_SHIFT 16
#define  GVD_EDC_RLA_RB_BASE 0x8B18
    #define GVD_EDC_RLA_RB_BASE_ADDR_MASK 0x7FFFFF80
    #define GVD_EDC_RLA_RB_BASE_ADDR_SHIFT 7
#define  GVD_EDC_RLA_RB_CTRL 0x8B1C
    #define GVD_EDC_RLA_RB_CTRL_SIZE_MASK 0x03FFFF80
    #define GVD_EDC_RLA_RB_CTRL_SIZE_SHIFT 7
#define  GVD_EDC_RLA_RB_RPTR 0x8B24
    #define GVD_EDC_RLA_RB_RPTR_OFFSET_MASK 0x03FFFFFC
    #define GVD_EDC_RLA_RB_RPTR_OFFSET_SHIFT 2
#define  GVD_EDC_RLA_RB_WPTR 0x8B20
    #define GVD_EDC_RLA_RB_WPTR_OFFSET_MASK 0x03FFFFFC
    #define GVD_EDC_RLA_RB_WPTR_OFFSET_SHIFT 2
#define  GVD_EDC_SLICE_CNT 0x8B60
    #define GVD_EDC_SLICE_CNT_COUNT_MASK 0x000003FF
    #define GVD_EDC_SLICE_CNT_COUNT_SHIFT 0
#define  GVD_EDC_SLICE_HDR_RB_BASE 0x8B50
    #define GVD_EDC_SLICE_HDR_RB_BASE_ADDR_MASK 0x7FFFFFF0
    #define GVD_EDC_SLICE_HDR_RB_BASE_ADDR_SHIFT 4
#define  GVD_EDC_SLICE_HDR_RB_CTRL 0x8B54
    #define GVD_EDC_SLICE_HDR_RB_CTRL_SIZE_MASK 0x000FFFF8
    #define GVD_EDC_SLICE_HDR_RB_CTRL_SIZE_SHIFT 3
#define  GVD_EDC_SLICE_HDR_RB_RPTR 0x8B58
    #define GVD_EDC_SLICE_HDR_RB_RPTR_OFFSET_MASK 0x000FFFF8
    #define GVD_EDC_SLICE_HDR_RB_RPTR_OFFSET_SHIFT 3
#define  GVD_EDC_SLICE_HDR_RB_WPTR 0x8B5C
    #define GVD_EDC_SLICE_HDR_RB_WPTR_OFFSET_MASK 0x000FFFF8
    #define GVD_EDC_SLICE_HDR_RB_WPTR_OFFSET_SHIFT 3
#define  GVD_EDC_SLICE_INFO_RB_BASE 0x8B70
    #define GVD_EDC_SLICE_INFO_RB_BASE_ADDR_MASK 0x7FFFFFF0
    #define GVD_EDC_SLICE_INFO_RB_BASE_ADDR_SHIFT 4
#define  GVD_EDC_SLICE_INFO_RB_CTRL 0x8B74
    #define GVD_EDC_SLICE_INFO_RB_CTRL_SIZE_MASK 0x000FFFF8
    #define GVD_EDC_SLICE_INFO_RB_CTRL_SIZE_SHIFT 3
#define  GVD_EDC_SLICE_INFO_RB_RPTR 0x8B7C
    #define GVD_EDC_SLICE_INFO_RB_RPTR_OFFSET_MASK 0x000FFFFC
    #define GVD_EDC_SLICE_INFO_RB_RPTR_OFFSET_SHIFT 2
#define  GVD_EDC_SLICE_INFO_RB_WPTR 0x8B78
    #define GVD_EDC_SLICE_INFO_RB_WPTR_OFFSET_MASK 0x000FFFFC
    #define GVD_EDC_SLICE_INFO_RB_WPTR_OFFSET_SHIFT 2
#define  GVD_EDC_SPS_INFO_BASE 0x8B40
    #define GVD_EDC_SPS_INFO_BASE_ADDR_MASK 0x7FFFFFF0
    #define GVD_EDC_SPS_INFO_BASE_ADDR_SHIFT 4
#define  GVD_EDC_STATUS 0x8B84
    #define PARSE_ERR_CODE_MASK 0x00000007
    #define PARSE_ERR_CODE_SHIFT 0
    #define WAIT_FLAG_MASK 0x00000008
    #define WAIT_FLAG_SHIFT 3
    #define GVD_EDC_STATUS_END_FLAG_MASK 0x00000010
    #define GVD_EDC_STATUS_END_FLAG_SHIFT 4
    #define BB_WAIT_FLAG_MASK 0x00000020
    #define BB_WAIT_FLAG_SHIFT 5
    #define GVD_EDC_STATUS_BUSY_MASK 0x00000040
    #define GVD_EDC_STATUS_BUSY_SHIFT 6
    #define MCI_ACTIVE_MASK 0x00000080
    #define MCI_ACTIVE_SHIFT 7
    #define RLA_STALL_FLAG_MASK 0x00000100
    #define RLA_STALL_FLAG_SHIFT 8
    #define MVD_STALL_FLAG_MASK 0x00000200
    #define MVD_STALL_FLAG_SHIFT 9
    #define SLC_INFO_STALL_FLAG_MASK 0x00000400
    #define SLC_INFO_STALL_FLAG_SHIFT 10
    #define SLC_HDR_STALL_FLAG_MASK 0x00000800
    #define SLC_HDR_STALL_FLAG_SHIFT 11
    #define SYNTAX_ERR_CODE_MASK 0x000F0000
    #define SYNTAX_ERR_CODE_SHIFT 16
    #define IPCM_FLAG_MASK 0x00100000
    #define IPCM_FLAG_SHIFT 20
    #define SUB_8X8FLAG_MASK 0x00200000
    #define SUB_8X8FLAG_SHIFT 21
    #define FLD_REF1_FLAG_MASK 0x00400000
    #define FLD_REF1_FLAG_SHIFT 22
    #define FRM_REF0_FLAG_MASK 0x00800000
    #define FRM_REF0_FLAG_SHIFT 23
    #define GVD_EDC_STATUS_NAL_UNIT_TYPE_MASK 0x1F000000
    #define GVD_EDC_STATUS_NAL_UNIT_TYPE_SHIFT 24
    #define GVD_EDC_STATUS_NAL_REF_IDC_MASK 0x60000000
    #define GVD_EDC_STATUS_NAL_REF_IDC_SHIFT 29
#define  GVD_EDC_STATUS2 0x8BA0
    #define FIFO_LEVEL_MASK 0x000000FF
    #define FIFO_LEVEL_SHIFT 0
    #define SYNTAX_FIFO_FULL_MASK 0x00000100
    #define SYNTAX_FIFO_FULL_SHIFT 8
    #define SYNTAX_FIFO_EMPTY_MASK 0x00000200
    #define SYNTAX_FIFO_EMPTY_SHIFT 9
    #define SC_OVERRUN_ERR_MASK 0x00000400
    #define SC_OVERRUN_ERR_SHIFT 10
    #define ID_OVERRUN_ERR_MASK 0x00000800
    #define ID_OVERRUN_ERR_SHIFT 11
    #define CTRL_STATE_MASK 0x0000F000
    #define CTRL_STATE_SHIFT 12
    #define SYNTAX_STATE_MASK 0x00FF0000
    #define SYNTAX_STATE_SHIFT 16
    #define SUB_ERR_CODE_MASK 0x1F000000
    #define SUB_ERR_CODE_SHIFT 24
    #define SYNTAX_READY_MASK 0x40000000
    #define SYNTAX_READY_SHIFT 30
    #define BB_ERR_MASK 0x80000000
    #define BB_ERR_SHIFT 31
#define  GVD_EDC_STATUS3 0x8B48
    #define VC1_PARSE_ERR_CODE_MASK 0x00000007
    #define VC1_PARSE_ERR_CODE_SHIFT 0
    #define VC1_WAIT_FLAG_MASK 0x00000008
    #define VC1_WAIT_FLAG_SHIFT 3
    #define VC1_END_FLAG_MASK 0x00000010
    #define VC1_END_FLAG_SHIFT 4
    #define VC1_BB_WAIT_FLAG_MASK 0x00000020
    #define VC1_BB_WAIT_FLAG_SHIFT 5
    #define VC1_BUSY_MASK 0x00000040
    #define VC1_BUSY_SHIFT 6
    #define VC1_RLA_STALL_FLAG_MASK 0x00000080
    #define VC1_RLA_STALL_FLAG_SHIFT 7
    #define VC1_MVD_STALL_FLAG_MASK 0x00000100
    #define VC1_MVD_STALL_FLAG_SHIFT 8
    #define VC1_SLH_STALL_FLAG_MASK 0x00000200
    #define VC1_SLH_STALL_FLAG_SHIFT 9
    #define VC1_MCI_ACTIVE_MASK 0x00000400
    #define VC1_MCI_ACTIVE_SHIFT 10
    #define VC1_RESPIC_DECODED_MASK 0x00003000
    #define VC1_RESPIC_DECODED_SHIFT 12
    #define VC1_SUB_ERROR_CODE_MASK 0x000FC000
    #define VC1_SUB_ERROR_CODE_SHIFT 14
    #define VC1_PIC_TYPE_MASK 0x00F00000
    #define VC1_PIC_TYPE_SHIFT 20
    #define VC1_BDU_TYPE_MASK 0xFF000000
    #define VC1_BDU_TYPE_SHIFT 24
#define  GVD_EDC_STATUS4 0x8B4C
    #define VC1_SLICE_START_MB_Y_MASK 0x000001FF
    #define VC1_SLICE_START_MB_Y_SHIFT 0
    #define VC1_DECODE_MB_NUM_MASK 0xFFFF0000
    #define VC1_DECODE_MB_NUM_SHIFT 16
#define  GVD_EDC_TOTAL_BIT_CNT 0x8BAC
    #define BB_TOTAL_BIT_CNT_MASK 0x0FFFFFFF
    #define BB_TOTAL_BIT_CNT_SHIFT 0
#define  GVD_IIP_DEBUG 0x88D0
    #define GVD_IIP_DEBUG_DEBUG_MASK 0x000FFFFF
    #define GVD_IIP_DEBUG_DEBUG_SHIFT 0
#define  GVD_IIP_DEBUG_CTRL 0x88CC
    #define IIP_DB_MUX_MASK 0x0000003F
    #define IIP_DB_MUX_SHIFT 0
#define  GVD_IIP_WCOUNT 0x88C8
    #define GVD_IIP_WCOUNT_COUNT_MASK 0x000000FF
    #define GVD_IIP_WCOUNT_COUNT_SHIFT 0
#define  GVD_INT 0x8804
    #define GVD_INTERRUPT_MASK 0x00000001
    #define GVD_INTERRUPT_SHIFT 0
#define  GVD_INT_CTRL 0x8808
    #define GVD_INT_MIPS_EN_MASK 0x00000001
    #define GVD_INT_MIPS_EN_SHIFT 0
    #define GVD_INT_HOST_EN_MASK 0x00000002
    #define GVD_INT_HOST_EN_SHIFT 1
#define  GVD_IQT_CTRL 0x8928
    #define GVD_IQT_CTRL_ENTROPY_FLG_MASK 0x00000001
    #define GVD_IQT_CTRL_ENTROPY_FLG_SHIFT 0
    #define GVD_IQT_CTRL_WEIGHT_ENB_MASK 0x00000002
    #define GVD_IQT_CTRL_WEIGHT_ENB_SHIFT 1
    #define QP_CB_OFFSET_MASK 0x000001F0
    #define QP_CB_OFFSET_SHIFT 4
    #define QP_CR_OFFSET_MASK 0x0001F000
    #define QP_CR_OFFSET_SHIFT 12
    #define PQUANTIZER_MASK 0x00100000
    #define PQUANTIZER_SHIFT 20
#define  GVD_IQT_DBG 0x8A14
    #define GVD_IQT_DBG_DATA_MASK 0xFFFFFFFF
    #define GVD_IQT_DBG_DATA_SHIFT 0
#define  GVD_IQT_DBG_CTRL 0x8A10
    #define GVD_IQT_DBG_CTRL_SEL_MASK 0x0000003F
    #define GVD_IQT_DBG_CTRL_SEL_SHIFT 0
    #define GVD_IQT_DBG_CTRL_MUX_MASK 0x00001F00
    #define GVD_IQT_DBG_CTRL_MUX_SHIFT 8
#define  GVD_IQT_RLA_RB_BASE 0x8900
    #define GVD_IQT_RLA_RB_BASE_ADDR_MASK 0x7FFFFFE0
    #define GVD_IQT_RLA_RB_BASE_ADDR_SHIFT 5
#define  GVD_IQT_RLA_RB_CTRL 0x8904
    #define GVD_IQT_RLA_RB_CTRL_SIZE_MASK 0x03FFFFF8
    #define GVD_IQT_RLA_RB_CTRL_SIZE_SHIFT 3
#define  GVD_IQT_RLA_RB_RPTR 0x8908
    #define GVD_IQT_RLA_RB_RPTR_OFFSET_MASK 0x03FFFFFC
    #define GVD_IQT_RLA_RB_RPTR_OFFSET_SHIFT 2
#define  GVD_IQT_RLA_RB_WPTR 0x890C
    #define GVD_IQT_RLA_RB_WPTR_OFFSET_MASK 0x03FFFFFC
    #define GVD_IQT_RLA_RB_WPTR_OFFSET_SHIFT 2
#define  GVD_IQT_SLICE_INFO 0x892C
    #define NUM_RL_MASK 0x00FFFFFF
    #define NUM_RL_SHIFT 0
#define  GVD_IQT_WEIGHT_TABLE 0x8924
    #define GVD_IQT_WEIGHT_TABLE_INDEX_MASK 0x0000001F
    #define GVD_IQT_WEIGHT_TABLE_INDEX_SHIFT 0
#define  GVD_IQT_WEIGHT_TABLE_0 0x8914
    #define GVD_IQT_WEIGHT_TABLE_0_VALUE_MASK 0xFFFFFFFF
    #define GVD_IQT_WEIGHT_TABLE_0_VALUE_SHIFT 0
#define  GVD_IQT_WEIGHT_TABLE_1 0x8918
    #define GVD_IQT_WEIGHT_TABLE_1_VALUE_MASK 0xFFFFFFFF
    #define GVD_IQT_WEIGHT_TABLE_1_VALUE_SHIFT 0
#define  GVD_IQT_WEIGHT_TABLE_2 0x891C
    #define GVD_IQT_WEIGHT_TABLE_2_VALUE_MASK 0xFFFFFFFF
    #define GVD_IQT_WEIGHT_TABLE_2_VALUE_SHIFT 0
#define  GVD_IQT_WEIGHT_TABLE_3 0x8920
    #define GVD_IQT_WEIGHT_TABLE_3_VALUE_MASK 0xFFFFFFFF
    #define GVD_IQT_WEIGHT_TABLE_3_VALUE_SHIFT 0
#define  GVD_MARB_ARB0 0x8A08
    #define GVD_MARB_ARB0_CLI0_REQ_CNT_LIMIT_MASK 0x0000000F
    #define GVD_MARB_ARB0_CLI0_REQ_CNT_LIMIT_SHIFT 0
    #define GVD_MARB_ARB0_CLI1_REQ_CNT_LIMIT_MASK 0x000000F0
    #define GVD_MARB_ARB0_CLI1_REQ_CNT_LIMIT_SHIFT 4
    #define GVD_MARB_ARB0_CLI2_REQ_CNT_LIMIT_MASK 0x00000F00
    #define GVD_MARB_ARB0_CLI2_REQ_CNT_LIMIT_SHIFT 8
    #define GVD_MARB_ARB0_CLI3_REQ_CNT_LIMIT_MASK 0x0000F000
    #define GVD_MARB_ARB0_CLI3_REQ_CNT_LIMIT_SHIFT 12
    #define GVD_MARB_ARB0_CLI4_REQ_CNT_LIMIT_MASK 0x000F0000
    #define GVD_MARB_ARB0_CLI4_REQ_CNT_LIMIT_SHIFT 16
    #define GVD_MARB_ARB0_CLI5_REQ_CNT_LIMIT_MASK 0x00F00000
    #define GVD_MARB_ARB0_CLI5_REQ_CNT_LIMIT_SHIFT 20
    #define GVD_MARB_ARB0_CLI6_REQ_CNT_LIMIT_MASK 0x0F000000
    #define GVD_MARB_ARB0_CLI6_REQ_CNT_LIMIT_SHIFT 24
    #define GVD_MARB_ARB0_CLI7_REQ_CNT_LIMIT_MASK 0xF0000000
    #define GVD_MARB_ARB0_CLI7_REQ_CNT_LIMIT_SHIFT 28
#define  GVD_MARB_CTRL 0x8A00
    #define GVD_MARB_CTRL_MEM_CNT_RESET_MASK 0x00000001
    #define GVD_MARB_CTRL_MEM_CNT_RESET_SHIFT 0
    #define GVD_MARB_CTRL_MEM_CNT_EN_MASK 0x00000002
    #define GVD_MARB_CTRL_MEM_CNT_EN_SHIFT 1
    #define GVD_MARB_CTRL_MEM_CNT_SEL_MASK 0x00000004
    #define GVD_MARB_CTRL_MEM_CNT_SEL_SHIFT 2
    #define GVD_MARB_CTRL_READ_ACCEL_MASK 0x00000100
    #define GVD_MARB_CTRL_READ_ACCEL_SHIFT 8
    #define GVD_MARB_CTRL_PF_ARB_DIS_MASK 0x00000200
    #define GVD_MARB_CTRL_PF_ARB_DIS_SHIFT 9
    #define GVD_MARB_CTRL_WOP_ARB_DIS_MASK 0x00000400
    #define GVD_MARB_CTRL_WOP_ARB_DIS_SHIFT 10
#define  GVD_MARB_PRIORITY 0x8A04
    #define GVD_MARB_PRIORITY_ABSOLUTE_PRIORITY_MASK 0x000001FF
    #define GVD_MARB_PRIORITY_ABSOLUTE_PRIORITY_SHIFT 0
    #define GVD_MARB_PRIORITY_CLI8_REQ_CNT_LIMIT_MASK 0x000F0000
    #define GVD_MARB_PRIORITY_CLI8_REQ_CNT_LIMIT_SHIFT 16
#define  GVD_MEM_CNT 0x8A0C
    #define GVD_MEM_CNT_MEM_CNT_MASK 0x00FFFFFF
    #define GVD_MEM_CNT_MEM_CNT_SHIFT 0
#define  GVD_NMB_CMD_FIFO 0x8868
    #define GVD_NMB_CMD_FIFO_MBH_INDEX_MASK 0x00003FFF
    #define GVD_NMB_CMD_FIFO_MBH_INDEX_SHIFT 0
    #define GVD_NMB_CMD_FIFO_MB_COUNT_MASK 0x3FFF0000
    #define GVD_NMB_CMD_FIFO_MB_COUNT_SHIFT 16
#define  GVD_NMB_CTRL 0x8864
    #define GVD_NMB_CTRL_MODE_MASK 0x00000003
    #define GVD_NMB_CTRL_MODE_SHIFT 0
    #define DIRECT_8X8INFERENCE_MASK 0x00000004
    #define DIRECT_8X8INFERENCE_SHIFT 2
    #define MV_EXP_ENABLE_MASK 0x00000010
    #define MV_EXP_ENABLE_SHIFT 4
    #define ENB_SLICE_INFO_OUTPUT_MASK 0x00000020
    #define ENB_SLICE_INFO_OUTPUT_SHIFT 5
    #define CUR_MEM_REFIDX_MASK 0x00001F00
    #define CUR_MEM_REFIDX_SHIFT 8
    #define SPECIAL_DMV_FORMAT_MASK 0x00008000
    #define SPECIAL_DMV_FORMAT_SHIFT 15
    #define DISABLE_CHROMA_MV_OUTPUT_MASK 0x00010000
    #define DISABLE_CHROMA_MV_OUTPUT_SHIFT 16
    #define DSQA_CROSS_SLICE_BOUNDARY_FLAG_MASK 0x01000000
    #define DSQA_CROSS_SLICE_BOUNDARY_FLAG_SHIFT 24
    #define TEMPORAL_DMV_MASK 0x10000000
    #define TEMPORAL_DMV_SHIFT 28
    #define CO_PICT_STRUCT_MASK 0x60000000
    #define CO_PICT_STRUCT_SHIFT 29
#define  GVD_NMB_DBG 0x88B0
    #define GVD_NMB_DBG_DATA_MASK 0xFFFFFFFF
    #define GVD_NMB_DBG_DATA_SHIFT 0
#define  GVD_NMB_DBG_CTRL 0x88AC
    #define GVD_NMB_DBG_CTRL_SEL_MASK 0x0000003F
    #define GVD_NMB_DBG_CTRL_SEL_SHIFT 0
    #define GVD_NMB_DBG_CTRL_MUX_MASK 0x00001F00
    #define GVD_NMB_DBG_CTRL_MUX_SHIFT 8
#define  GVD_NMB_DMV_CODATA_READ0 0x8844
    #define GVD_NMB_DMV_CODATA_READ0_ADDRESS_MASK 0x7FFFFFF8
    #define GVD_NMB_DMV_CODATA_READ0_ADDRESS_SHIFT 3
#define  GVD_NMB_DMV_CODATA_READ1 0x8848
    #define GVD_NMB_DMV_CODATA_READ1_ADDRESS_MASK 0x7FFFFFF0
    #define GVD_NMB_DMV_CODATA_READ1_ADDRESS_SHIFT 4
#define  GVD_NMB_DMV_CODATA_WRITE 0x884C
    #define GVD_NMB_DMV_CODATA_WRITE_ADDRESS_MASK 0x7FFFFFF8
    #define GVD_NMB_DMV_CODATA_WRITE_ADDRESS_SHIFT 3
#define  GVD_NMB_MBH_BASE 0x8870
    #define GVD_NMB_MBH_BASE_ADDR_MASK 0x7FFFFFF0
    #define GVD_NMB_MBH_BASE_ADDR_SHIFT 4
#define  GVD_NMB_MBH_RPTR 0x88A8
    #define GVD_NMB_MBH_RPTR_OFFSET_MASK 0x0003FFFC
    #define GVD_NMB_MBH_RPTR_OFFSET_SHIFT 2
#define  GVD_NMB_MEMREF_INFO_TABLE 0x8858
    #define GVD_NMB_MEMREF_INFO_TABLE_DATA_MASK 0xFFFFFFFF
    #define GVD_NMB_MEMREF_INFO_TABLE_DATA_SHIFT 0
#define  GVD_NMB_MEMREF_INFO_TABLE_CTRL 0x885C
    #define GVD_NMB_MEMREF_INFO_TABLE_CTRL_INDEX_MASK 0x0000003F
    #define GVD_NMB_MEMREF_INFO_TABLE_CTRL_INDEX_SHIFT 0
#define  GVD_NMB_MVD_LENGTH 0x8884
    #define GVD_NMB_MVD_LENGTH_SIZE_MASK 0x007FFFFC
    #define GVD_NMB_MVD_LENGTH_SIZE_SHIFT 2
#define  GVD_NMB_MVD_RB_BASE 0x8874
    #define GVD_NMB_MVD_RB_BASE_ADDR_MASK 0x7FFFFFF0
    #define GVD_NMB_MVD_RB_BASE_ADDR_SHIFT 4
#define  GVD_NMB_MVD_RB_CTRL 0x8878
    #define GVD_NMB_MVD_RB_CTRL_SIZE_MASK 0x007FFFFC
    #define GVD_NMB_MVD_RB_CTRL_SIZE_SHIFT 2
#define  GVD_NMB_MVD_RB_RPTR 0x887C
    #define GVD_NMB_MVD_RB_RPTR_OFFSET_MASK 0x007FFFFC
    #define GVD_NMB_MVD_RB_RPTR_OFFSET_SHIFT 2
#define  GVD_NMB_MVD_RB_WPTR 0x8880
    #define GVD_NMB_MVD_RB_WPTR_OFFSET_MASK 0x007FFFFC
    #define GVD_NMB_MVD_RB_WPTR_OFFSET_SHIFT 2
#define  GVD_NMB_MV_RB_BASE 0x888C
    #define GVD_NMB_MV_RB_BASE_ADDR_MASK 0x7FFFFFF0
    #define GVD_NMB_MV_RB_BASE_ADDR_SHIFT 4
#define  GVD_NMB_MV_RB_CTRL 0x8890
    #define GVD_NMB_MV_RB_CTRL_SIZE_MASK 0x007FFFFC
    #define GVD_NMB_MV_RB_CTRL_SIZE_SHIFT 2
#define  GVD_NMB_MV_RB_RPTR 0x8894
    #define GVD_NMB_MV_RB_RPTR_OFFSET_MASK 0x007FFFFC
    #define GVD_NMB_MV_RB_RPTR_OFFSET_SHIFT 2
#define  GVD_NMB_MV_RB_WPTR 0x8898
    #define GVD_NMB_MV_RB_WPTR_OFFSET_MASK 0x007FFFFC
    #define GVD_NMB_MV_RB_WPTR_OFFSET_SHIFT 2
#define  GVD_NMB_REFIDX_MAP_TABLE 0x8850
    #define GVD_NMB_REFIDX_MAP_TABLE_DATA_MASK 0xFFFFFFFF
    #define GVD_NMB_REFIDX_MAP_TABLE_DATA_SHIFT 0
#define  GVD_NMB_REFIDX_MAP_TABLE_CTRL 0x8854
    #define GVD_NMB_REFIDX_MAP_TABLE_CTRL_INDEX_MASK 0x0000000F
    #define GVD_NMB_REFIDX_MAP_TABLE_CTRL_INDEX_SHIFT 0
#define  GVD_NMB_SLICE_INFO 0x88A4
    #define GVD_NMB_SLICE_INFO_ADDR_MASK 0x7FFFFFFC
    #define GVD_NMB_SLICE_INFO_ADDR_SHIFT 2
#define  GVD_NMB_START_MB 0x8860
    #define GVD_NMB_START_MB_START_MB_X_MASK 0x000000FF
    #define GVD_NMB_START_MB_START_MB_X_SHIFT 0
    #define GVD_NMB_START_MB_START_MB_Y_MASK 0x00007F00
    #define GVD_NMB_START_MB_START_MB_Y_SHIFT 8
#define  GVD_NMB_STATUS 0x886C
    #define GVD_NMB_STATUS_NMB_BUSY_MASK 0x00000001
    #define GVD_NMB_STATUS_NMB_BUSY_SHIFT 0
#define  GVD_NMB_TOP_NB_BASE 0x8888
    #define GVD_NMB_TOP_NB_BASE_ADDR_MASK 0x7FFFFFF0
    #define GVD_NMB_TOP_NB_BASE_ADDR_SHIFT 4
#define  GVD_NMB_VC1_CTRL 0x889C
    #define CUR_FIRST_FLD_MASK 0x00000001
    #define CUR_FIRST_FLD_SHIFT 0
    #define CUR_BOTFLD_FIRST_MASK 0x00000002
    #define CUR_BOTFLD_FIRST_SHIFT 1
    #define MV_PRECISION_MASK 0x00000004
    #define MV_PRECISION_SHIFT 2
    #define NUM_REF_MASK 0x00000008
    #define NUM_REF_SHIFT 3
    #define REF_FLD_MASK 0x00000010
    #define REF_FLD_SHIFT 4
    #define REF_DIST_MASK 0x00001F00
    #define REF_DIST_SHIFT 8
    #define BFRACTION_MASK 0x007F0000
    #define BFRACTION_SHIFT 16
    #define COPICT_SKIP_MASK 0x00800000
    #define COPICT_SKIP_SHIFT 23
    #define FAST_UVMC_MASK 0x80000000
    #define FAST_UVMC_SHIFT 31
#define  GVD_NMB_VC1_MV 0x88A0
    #define RANGE_X_MASK 0x00003FFF
    #define RANGE_X_SHIFT 0
    #define RANGE_Y_MASK 0x0FFF0000
    #define RANGE_Y_SHIFT 16
#define  GVD_OVL_DEBUG 0x8930
    #define GVD_OVL_DEBUG_DEBUG_MASK 0xFFFFFFFF
    #define GVD_OVL_DEBUG_DEBUG_SHIFT 0
#define  GVD_OVL_TOP_PIXEL_BASE 0x8938
    #define GVD_OVL_TOP_PIXEL_BASE_ADDR_MASK 0x7FFFFFF8
    #define GVD_OVL_TOP_PIXEL_BASE_ADDR_SHIFT 3
#define  GVD_PICT_SIZE 0x8824
    #define GVD_PICT_SIZE_PICT_MB_WIDTH_MASK 0x000000FF
    #define GVD_PICT_SIZE_PICT_MB_WIDTH_SHIFT 0
    #define GVD_PICT_SIZE_PICT_MB_HEIGHT_MASK 0x0000FF00
    #define GVD_PICT_SIZE_PICT_MB_HEIGHT_SHIFT 8
#define  GVD_REF_C_ADR 0x8838
    #define GVD_REF_C_ADR_BASE_MASK 0x7FFFFF00
    #define GVD_REF_C_ADR_BASE_SHIFT 8
#define  GVD_REF_PICT_SIZE 0x8830
    #define GVD_REF_PICT_SIZE_REF_Y_SIZE_MASK 0x00007FFF
    #define GVD_REF_PICT_SIZE_REF_Y_SIZE_SHIFT 0
    #define GVD_REF_PICT_SIZE_REF_C_SIZE_MASK 0x7FFF0000
    #define GVD_REF_PICT_SIZE_REF_C_SIZE_SHIFT 16
#define  GVD_REF_PITCH 0x882C
    #define GVD_REF_PITCH_REF_PITCH_MASK 0x00000FE0
    #define GVD_REF_PITCH_REF_PITCH_SHIFT 5
#define  GVD_REF_Y_ADR 0x8834
    #define GVD_REF_Y_ADR_BASE_MASK 0x7FFFFF00
    #define GVD_REF_Y_ADR_BASE_SHIFT 8
#define  GVD_SLICE_INFO 0x8820
    #define GVD_SLICE_INFO_SLICE_TYPE_MASK 0x00000003
    #define GVD_SLICE_INFO_SLICE_TYPE_SHIFT 0
    #define GVD_SLICE_INFO_SLICE_STRUCT_MASK 0x0000000C
    #define GVD_SLICE_INFO_SLICE_STRUCT_SHIFT 2
    #define GVD_SLICE_INFO_MBAFF_FLAG_MASK 0x00000010
    #define GVD_SLICE_INFO_MBAFF_FLAG_SHIFT 4
    #define MONOCHROME_FLAG_MASK 0x00000020
    #define MONOCHROME_FLAG_SHIFT 5
    #define GVD_SLICE_INFO_VC1_PROFILE_MASK 0x000000C0
    #define GVD_SLICE_INFO_VC1_PROFILE_SHIFT 6
    #define CONSTRAINED_INTRA_MASK 0x00000100
    #define CONSTRAINED_INTRA_SHIFT 8
    #define VC1_FLAG_MASK 0x00000200
    #define VC1_FLAG_SHIFT 9
    #define OVERLAP_MASK 0x00000400
    #define OVERLAP_SHIFT 10
    #define COND_OVERLAP_MASK 0x00000800
    #define COND_OVERLAP_SHIFT 11
    #define GVD_SLICE_INFO_MB_COUNT_MASK 0x03FFF000
    #define GVD_SLICE_INFO_MB_COUNT_SHIFT 12
    #define VC1_PQUANT_MASK 0x7C000000
    #define VC1_PQUANT_SHIFT 26
    #define GVD_SOFT_RESET_MASK 0x80000000
    #define GVD_SOFT_RESET_SHIFT 31
#define  GVD_START_MB 0x8828
    #define GVD_START_MB_START_MB_X_MASK 0x000000FF
    #define GVD_START_MB_START_MB_X_SHIFT 0
    #define GVD_START_MB_START_MB_Y_MASK 0x00007F00
    #define GVD_START_MB_START_MB_Y_SHIFT 8
#define  GVD_STATUS 0x8800
    #define GVD_STATUS_NMB_BUSY_MASK 0x00000001
    #define GVD_STATUS_NMB_BUSY_SHIFT 0
    #define IQT_BUSY_MASK 0x00000002
    #define IQT_BUSY_SHIFT 1
    #define IIP_BUSY_MASK 0x00000004
    #define IIP_BUSY_SHIFT 2
    #define DMC_BUSY_MASK 0x00000008
    #define DMC_BUSY_SHIFT 3
    #define DDB_BUSY_MASK 0x00000010
    #define DDB_BUSY_SHIFT 4
    #define DCP_BUSY_MASK 0x00000020
    #define DCP_BUSY_SHIFT 5
    #define OVL_BUSY_MASK 0x00000040
    #define OVL_BUSY_SHIFT 6
    #define GVD_W_BUSY_MASK 0x00010000
    #define GVD_W_BUSY_SHIFT 16
    #define GVD_R_BUSY_MASK 0x00020000
    #define GVD_R_BUSY_SHIFT 17
    #define MARB_W_BUSY_MASK 0x00040000
    #define MARB_W_BUSY_SHIFT 18
    #define EDC_W_BUSY_MASK 0x00080000
    #define EDC_W_BUSY_SHIFT 19
    #define GVD_BUSY_MASK 0x80000000
    #define GVD_BUSY_SHIFT 31
#define  GVD_TOP_MODE_ADR 0x88C4
    #define GVD_TOP_MODE_ADR_BASE_MASK 0x7FFFFFF0
    #define GVD_TOP_MODE_ADR_BASE_SHIFT 4
#define  GVD_TOP_PIXEL_ADR 0x88C0
    #define GVD_TOP_PIXEL_ADR_BASE_MASK 0x7FFFFFF0
    #define GVD_TOP_PIXEL_ADR_BASE_SHIFT 4
#define  GVP_CMD_STATUS 0x8398
    #define MS_CMD_STATUS_MASK 0x000000FF
    #define MS_CMD_STATUS_SHIFT 0
    #define IP_CMD_STATUS_MASK 0x00007F00
    #define IP_CMD_STATUS_SHIFT 8
    #define NMB_CMD_STATUS_MASK 0x00FF0000
    #define NMB_CMD_STATUS_SHIFT 16
    #define DBK_CMD_STATUS_MASK 0xFF000000
    #define DBK_CMD_STATUS_SHIFT 24
#define  GVP_CUR_C_ADR 0x801C
    #define GVP_CUR_C_ADR_BASE_MASK 0x1FFFFF00
    #define GVP_CUR_C_ADR_BASE_SHIFT 8
#define  GVP_CUR_PICT_SIZE 0x800C
    #define CUR_Y_SIZE_MASK 0x00007FFF
    #define CUR_Y_SIZE_SHIFT 0
    #define CUR_C_SIZE_MASK 0x7FFF0000
    #define CUR_C_SIZE_SHIFT 16
#define  GVP_CUR_PITCH 0x8008
    #define GVP_CUR_PITCH_CUR_PITCH_MASK 0x00000FE0
    #define GVP_CUR_PITCH_CUR_PITCH_SHIFT 5
#define  GVP_CUR_Y_ADR 0x8018
    #define GVP_CUR_Y_ADR_BASE_MASK 0x1FFFFF00
    #define GVP_CUR_Y_ADR_BASE_SHIFT 8
#define  GVP_DBK_C0_OFFSET 0x8190
    #define GVP_DBK_C0_OFFSET_ALPHA_C0_OFFSET_DIV2_MASK 0x0000000F
    #define GVP_DBK_C0_OFFSET_ALPHA_C0_OFFSET_DIV2_SHIFT 0
    #define GVP_DBK_C0_OFFSET_BETA_C0_OFFSET_DIV2_MASK 0x00000F00
    #define GVP_DBK_C0_OFFSET_BETA_C0_OFFSET_DIV2_SHIFT 8
#define  GVP_DBK_CHROMA_QP_INDEX_OFFSET 0x8194
    #define GVP_DBK_CHROMA_QP_INDEX_OFFSET_CHROMA_QP_INDEX_OFFSET_MASK 0x0000001F
    #define GVP_DBK_CHROMA_QP_INDEX_OFFSET_CHROMA_QP_INDEX_OFFSET_SHIFT 0
#define  GVP_DBK_CMD_FIFO 0x818C
    #define GVP_DBK_CMD_FIFO_COMMAND_TAG_MASK 0x000000FF
    #define GVP_DBK_CMD_FIFO_COMMAND_TAG_SHIFT 0
    #define GVP_DBK_CMD_FIFO_DSQA_INDEX_MASK 0x00000F00
    #define GVP_DBK_CMD_FIFO_DSQA_INDEX_SHIFT 8
    #define INPUT_MB_INDEX_MASK 0x000F0000
    #define INPUT_MB_INDEX_SHIFT 16
#define  GVP_DBK_CTRL 0x8184
    #define GVP_DBK_CTRL_DBK_BYPASS_MASK 0x00000001
    #define GVP_DBK_CTRL_DBK_BYPASS_SHIFT 0
    #define GVP_DBK_CTRL_DBK_DISABLE_MASK 0x00000002
    #define GVP_DBK_CTRL_DBK_DISABLE_SHIFT 1
    #define GVP_DBK_CTRL_DBK_REF_INDEX_MASK 0x00001F00
    #define GVP_DBK_CTRL_DBK_REF_INDEX_SHIFT 8
    #define DBK_FLD_TILE_MASK 0x00010000
    #define DBK_FLD_TILE_SHIFT 16
    #define GVP_DBK_CTRL_SOFT_RESET_MASK 0x80000000
    #define GVP_DBK_CTRL_SOFT_RESET_SHIFT 31
#define  GVP_DBK_DBG 0x81AC
    #define GVP_DBK_DBG_DATA_MASK 0xFFFFFFFF
    #define GVP_DBK_DBG_DATA_SHIFT 0
#define  GVP_DBK_DBG_CTRL 0x81A8
    #define GVP_DBK_DBG_CTRL_SEL_MASK 0x0000003F
    #define GVP_DBK_DBG_CTRL_SEL_SHIFT 0
    #define GVP_DBK_DBG_CTRL_MUX_MASK 0x00000F00
    #define GVP_DBK_DBG_CTRL_MUX_SHIFT 8
#define  GVP_DBK_DSQA_ADR 0x81A0
    #define GVP_DBK_DSQA_ADR_BASE_MASK 0x1FFFFFE0
    #define GVP_DBK_DSQA_ADR_BASE_SHIFT 5
#define  GVP_DBK_MARB_CTRL 0x8198
    #define GVP_DBK_MARB_CTRL_DBK_PF_ARB_DIS_MASK 0x00000001
    #define GVP_DBK_MARB_CTRL_DBK_PF_ARB_DIS_SHIFT 0
    #define GVP_DBK_MARB_CTRL_DBK_ABS_PRIORITY_MASK 0x00000002
    #define GVP_DBK_MARB_CTRL_DBK_ABS_PRIORITY_SHIFT 1
#define  GVP_DBK_START_MB 0x8180
    #define GVP_DBK_START_MB_START_MB_X_MASK 0x000000FF
    #define GVP_DBK_START_MB_START_MB_X_SHIFT 0
    #define GVP_DBK_START_MB_START_MB_Y_MASK 0x00007F00
    #define GVP_DBK_START_MB_START_MB_Y_SHIFT 8
#define  GVP_DBK_STATUS 0x8188
    #define GVP_DBK_STATUS_DBK_BUSY_MASK 0x00000001
    #define GVP_DBK_STATUS_DBK_BUSY_SHIFT 0
    #define GVP_DBK_STATUS_COMMAND_TAG_MASK 0x0000FF00
    #define GVP_DBK_STATUS_COMMAND_TAG_SHIFT 8
    #define GVP_DBK_STATUS_FREE_ENTRIES_MASK 0x00070000
    #define GVP_DBK_STATUS_FREE_ENTRIES_SHIFT 16
#define  GVP_DCP_FIFO_0 0x83A0
    #define GVP_DCP_FIFO_0_DATA_MASK 0xFFFFFFFF
    #define GVP_DCP_FIFO_0_DATA_SHIFT 0
#define  GVP_DCP_FIFO_1 0x83A4
    #define GVP_DCP_FIFO_1_VALUE_MASK 0x1FFFFFFF
    #define GVP_DCP_FIFO_1_VALUE_SHIFT 0
    #define GVP_CMD_MASK 0xE0000000
    #define GVP_CMD_SHIFT 29
#define  GVP_DCP_STATUS 0x83A8
    #define GVP_DCP_STATUS_FIFO_FREE_MASK 0x0000001F
    #define GVP_DCP_STATUS_FIFO_FREE_SHIFT 0
    #define GVP_DCP_BUSY_MASK 0x80000000
    #define GVP_DCP_BUSY_SHIFT 31
#define  GVP_DMV_CO_ADR 0x82C4
    #define GVP_DMV_CO_ADR_BASE_MASK 0x1FFFFFF0
    #define GVP_DMV_CO_ADR_BASE_SHIFT 4
#define  GVP_DMV_CO_ADR_WRITE 0x82CC
    #define GVP_DMV_CO_ADR_WRITE_BASE_MASK 0x1FFFFFF0
    #define GVP_DMV_CO_ADR_WRITE_BASE_SHIFT 4
#define  GVP_DMV_CTRL 0x82C8
    #define I_COPIC_MASK 0x00000001
    #define I_COPIC_SHIFT 0
    #define BOT_FLD_FIRST_MASK 0x00000002
    #define BOT_FLD_FIRST_SHIFT 1
    #define OUTPUT_CO_EN_B_MASK 0x00000004
    #define OUTPUT_CO_EN_B_SHIFT 2
#define  GVP_DMV_TOP_ADR 0x82C0
    #define GVP_DMV_TOP_ADR_BASE_MASK 0x1FFFFFF0
    #define GVP_DMV_TOP_ADR_BASE_SHIFT 4
#define  GVP_EE_BITCNT_MB_RES 0x81BC
    #define BITCNT_MB_RES_MASK 0xFFFFFFFF
    #define BITCNT_MB_RES_SHIFT 0
#define  GVP_EE_BITCNT_MB_TOTAL 0x81B8
    #define BITCNT_MB_TOTAL_MASK 0xFFFFFFFF
    #define BITCNT_MB_TOTAL_SHIFT 0
#define  GVP_EE_CMD 0x81FC
    #define INT_CLR_MASK 0x10000000
    #define INT_CLR_SHIFT 28
    #define BP_CONTINUE_MASK 0x20000000
    #define BP_CONTINUE_SHIFT 29
    #define CODE_OFFLINE_MASK 0x40000000
    #define CODE_OFFLINE_SHIFT 30
    #define CODE_SLICE_HDR_MASK 0x80000000
    #define CODE_SLICE_HDR_SHIFT 31
#define  GVP_EE_CTRL 0x81D0
    #define INT_MASK_MASK 0x00000001
    #define INT_MASK_SHIFT 0
    #define GVP_EE_CTRL_SOFT_RESET_MASK 0x00000002
    #define GVP_EE_CTRL_SOFT_RESET_SHIFT 1
    #define BAC_OP_MODE_MASK 0x00000030
    #define BAC_OP_MODE_SHIFT 4
    #define BP_RES_BLK_MASK 0x00010000
    #define BP_RES_BLK_SHIFT 16
    #define EE_DEBUG_MUX_SEL_MASK 0xFFF00000
    #define EE_DEBUG_MUX_SEL_SHIFT 20
#define  GVP_EE_CTXTBL_ADR 0x8208
    #define GVP_EE_CTXTBL_ADR_ADR_MASK 0x1FFFFFF8
    #define GVP_EE_CTXTBL_ADR_ADR_SHIFT 3
#define  GVP_EE_DEBUG 0x8258
    #define GVP_EE_DEBUG_DATA_MASK 0xFFFFFFFF
    #define GVP_EE_DEBUG_DATA_SHIFT 0
#define  GVP_EE_DUMMY_REG 0x825C
    #define GVP_EE_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define GVP_EE_DUMMY_REG_DATA_SHIFT 0
#define  GVP_EE_ERROR 0x81B4
    #define EXTRA_SLICE_TRIG_MASK 0x00000001
    #define EXTRA_SLICE_TRIG_SHIFT 0
    #define MISSING_SLICE_TRIG_MASK 0x00000002
    #define MISSING_SLICE_TRIG_SHIFT 1
    #define CMD_FIFO_OVERFLOW_MASK 0x00000004
    #define CMD_FIFO_OVERFLOW_SHIFT 2
    #define NAL_BUF_OVERFLOW_MASK 0x00000008
    #define NAL_BUF_OVERFLOW_SHIFT 3
    #define RL_OFFSET_OB_MASK 0x00000010
    #define RL_OFFSET_OB_SHIFT 4
    #define RL_ILLEGAL_NUM_PAIRS_MASK 0x00000020
    #define RL_ILLEGAL_NUM_PAIRS_SHIFT 5
    #define BP_RES_BLK_ACT_MASK 0x00010000
    #define BP_RES_BLK_ACT_SHIFT 16
#define  GVP_EE_MBBOT_HDR0 0x81E0
    #define MBBOT_MB_TYPE_MASK 0x0000000F
    #define MBBOT_MB_TYPE_SHIFT 0
    #define MBBOT_TRANS_8X8_MASK 0x00000020
    #define MBBOT_TRANS_8X8_SHIFT 5
    #define MBBOT_CBP_MASK 0x00003F00
    #define MBBOT_CBP_SHIFT 8
    #define MBBOT_ICPM_MASK 0x0000C000
    #define MBBOT_ICPM_SHIFT 14
    #define MBBOT_MB_QP_DELTA_MASK 0x003F0000
    #define MBBOT_MB_QP_DELTA_SHIFT 16
#define  GVP_EE_MBBOT_HDR1 0x81E4
    #define MBBOT_ILPM_0_MASK 0x0000000F
    #define MBBOT_ILPM_0_SHIFT 0
    #define MBBOT_ILPM_1_MASK 0x000000F0
    #define MBBOT_ILPM_1_SHIFT 4
    #define MBBOT_ILPM_2_MASK 0x00000F00
    #define MBBOT_ILPM_2_SHIFT 8
    #define MBBOT_ILPM_3_MASK 0x0000F000
    #define MBBOT_ILPM_3_SHIFT 12
    #define MBBOT_ILPM_4_MASK 0x000F0000
    #define MBBOT_ILPM_4_SHIFT 16
    #define MBBOT_ILPM_5_MASK 0x00F00000
    #define MBBOT_ILPM_5_SHIFT 20
    #define MBBOT_ILPM_6_MASK 0x0F000000
    #define MBBOT_ILPM_6_SHIFT 24
    #define MBBOT_ILPM_7_MASK 0xF0000000
    #define MBBOT_ILPM_7_SHIFT 28
#define  GVP_EE_MBBOT_HDR2 0x81E8
    #define MBBOT_ILPM_8_MASK 0x0000000F
    #define MBBOT_ILPM_8_SHIFT 0
    #define MBBOT_ILPM_9_MASK 0x000000F0
    #define MBBOT_ILPM_9_SHIFT 4
    #define MBBOT_ILPM_10_MASK 0x00000F00
    #define MBBOT_ILPM_10_SHIFT 8
    #define MBBOT_ILPM_11_MASK 0x0000F000
    #define MBBOT_ILPM_11_SHIFT 12
    #define MBBOT_ILPM_12_MASK 0x000F0000
    #define MBBOT_ILPM_12_SHIFT 16
    #define MBBOT_ILPM_13_MASK 0x00F00000
    #define MBBOT_ILPM_13_SHIFT 20
    #define MBBOT_ILPM_14_MASK 0x0F000000
    #define MBBOT_ILPM_14_SHIFT 24
    #define MBBOT_ILPM_15_MASK 0xF0000000
    #define MBBOT_ILPM_15_SHIFT 28
#define  GVP_EE_MBHDR_ADR 0x8360
    #define GVP_EE_MBHDR_ADR_BASE_MASK 0x1FFFFFF8
    #define GVP_EE_MBHDR_ADR_BASE_SHIFT 3
#define  GVP_EE_MBHDR_BUF_SIZE 0x8364
    #define GVP_EE_MBHDR_BUF_SIZE_SIZE_MASK 0x000FFFF8
    #define GVP_EE_MBHDR_BUF_SIZE_SIZE_SHIFT 3
#define  GVP_EE_MBHDR_CURR_ADR 0x8244
    #define GVP_EE_MBHDR_CURR_ADR_OFFSET_MASK 0x000FFFFC
    #define GVP_EE_MBHDR_CURR_ADR_OFFSET_SHIFT 2
#define  GVP_EE_MBHDR_OFFSET 0x81EC
    #define GVP_EE_MBHDR_OFFSET_OFFSET_MASK 0x000FFFF8
    #define GVP_EE_MBHDR_OFFSET_OFFSET_SHIFT 3
#define  GVP_EE_MBTOP_HDR0 0x81D4
    #define MBTOP_MB_TYPE_MASK 0x0000000F
    #define MBTOP_MB_TYPE_SHIFT 0
    #define MBTOP_MB_FIELD_MASK 0x00000010
    #define MBTOP_MB_FIELD_SHIFT 4
    #define MBTOP_TRANS_8X8_MASK 0x00000020
    #define MBTOP_TRANS_8X8_SHIFT 5
    #define MBTOP_CBP_MASK 0x00003F00
    #define MBTOP_CBP_SHIFT 8
    #define MBTOP_ICPM_MASK 0x0000C000
    #define MBTOP_ICPM_SHIFT 14
    #define MBTOP_MB_QP_DELTA_MASK 0x003F0000
    #define MBTOP_MB_QP_DELTA_SHIFT 16
#define  GVP_EE_MBTOP_HDR1 0x81D8
    #define MBTOP_ILPM_0_MASK 0x0000000F
    #define MBTOP_ILPM_0_SHIFT 0
    #define MBTOP_ILPM_1_MASK 0x000000F0
    #define MBTOP_ILPM_1_SHIFT 4
    #define MBTOP_ILPM_2_MASK 0x00000F00
    #define MBTOP_ILPM_2_SHIFT 8
    #define MBTOP_ILPM_3_MASK 0x0000F000
    #define MBTOP_ILPM_3_SHIFT 12
    #define MBTOP_ILPM_4_MASK 0x000F0000
    #define MBTOP_ILPM_4_SHIFT 16
    #define MBTOP_ILPM_5_MASK 0x00F00000
    #define MBTOP_ILPM_5_SHIFT 20
    #define MBTOP_ILPM_6_MASK 0x0F000000
    #define MBTOP_ILPM_6_SHIFT 24
    #define MBTOP_ILPM_7_MASK 0xF0000000
    #define MBTOP_ILPM_7_SHIFT 28
#define  GVP_EE_MBTOP_HDR2 0x81DC
    #define MBTOP_ILPM_8_MASK 0x0000000F
    #define MBTOP_ILPM_8_SHIFT 0
    #define MBTOP_ILPM_9_MASK 0x000000F0
    #define MBTOP_ILPM_9_SHIFT 4
    #define MBTOP_ILPM_10_MASK 0x00000F00
    #define MBTOP_ILPM_10_SHIFT 8
    #define MBTOP_ILPM_11_MASK 0x0000F000
    #define MBTOP_ILPM_11_SHIFT 12
    #define MBTOP_ILPM_12_MASK 0x000F0000
    #define MBTOP_ILPM_12_SHIFT 16
    #define MBTOP_ILPM_13_MASK 0x00F00000
    #define MBTOP_ILPM_13_SHIFT 20
    #define MBTOP_ILPM_14_MASK 0x0F000000
    #define MBTOP_ILPM_14_SHIFT 24
    #define MBTOP_ILPM_15_MASK 0xF0000000
    #define MBTOP_ILPM_15_SHIFT 28
#define  GVP_EE_MVD_ADR 0x8368
    #define GVP_EE_MVD_ADR_BASE_MASK 0x1FFFFFF8
    #define GVP_EE_MVD_ADR_BASE_SHIFT 3
#define  GVP_EE_MVD_BUF_SIZE 0x836C
    #define GVP_EE_MVD_BUF_SIZE_SIZE_MASK 0x007FFFF8
    #define GVP_EE_MVD_BUF_SIZE_SIZE_SHIFT 3
#define  GVP_EE_MVD_CURR_ADR 0x8248
    #define GVP_EE_MVD_CURR_ADR_OFFSET_MASK 0x007FFFFC
    #define GVP_EE_MVD_CURR_ADR_OFFSET_SHIFT 2
#define  GVP_EE_MVD_OFFSET 0x81F0
    #define GVP_EE_MVD_OFFSET_OFFSET_MASK 0x007FFFFC
    #define GVP_EE_MVD_OFFSET_OFFSET_SHIFT 2
#define  GVP_EE_NAL_ADR 0x8200
    #define GVP_EE_NAL_ADR_BASE_MASK 0x1FFFFFF8
    #define GVP_EE_NAL_ADR_BASE_SHIFT 3
#define  GVP_EE_NAL_BUF_SIZE 0x8204
    #define GVP_EE_NAL_BUF_SIZE_SIZE_MASK 0x007FFF00
    #define GVP_EE_NAL_BUF_SIZE_SIZE_SHIFT 8
#define  GVP_EE_NAL_CURR_ADR 0x8240
    #define GVP_EE_NAL_CURR_ADR_OFFSET_MASK 0x007FFFFF
    #define GVP_EE_NAL_CURR_ADR_OFFSET_SHIFT 0
#define  GVP_EE_RLAC_ADR 0x8378
    #define GVP_EE_RLAC_ADR_BASE_MASK 0x1FFFFFF8
    #define GVP_EE_RLAC_ADR_BASE_SHIFT 3
#define  GVP_EE_RLAC_BUF_SIZE 0x837C
    #define GVP_EE_RLAC_BUF_SIZE_SIZE_MASK 0x00FFFFF8
    #define GVP_EE_RLAC_BUF_SIZE_SIZE_SHIFT 3
#define  GVP_EE_RLAC_CURR_ADR 0x8250
    #define GVP_EE_RLAC_CURR_ADR_OFFSET_MASK 0x00FFFFFC
    #define GVP_EE_RLAC_CURR_ADR_OFFSET_SHIFT 2
#define  GVP_EE_RLAC_OFFSET 0x81F8
    #define GVP_EE_RLAC_OFFSET_OFFSET_MASK 0x00FFFFFC
    #define GVP_EE_RLAC_OFFSET_OFFSET_SHIFT 2
#define  GVP_EE_RLDC_ADR 0x8370
    #define GVP_EE_RLDC_ADR_BASE_MASK 0x1FFFFFF8
    #define GVP_EE_RLDC_ADR_BASE_SHIFT 3
#define  GVP_EE_RLDC_BUF_SIZE 0x8374
    #define GVP_EE_RLDC_BUF_SIZE_SIZE_MASK 0x000FFFF8
    #define GVP_EE_RLDC_BUF_SIZE_SIZE_SHIFT 3
#define  GVP_EE_RLDC_CURR_ADR 0x824C
    #define GVP_EE_RLDC_CURR_ADR_OFFSET_MASK 0x000FFFFC
    #define GVP_EE_RLDC_CURR_ADR_OFFSET_SHIFT 2
#define  GVP_EE_RLDC_OFFSET 0x81F4
    #define GVP_EE_RLDC_OFFSET_OFFSET_MASK 0x000FFFFC
    #define GVP_EE_RLDC_OFFSET_OFFSET_SHIFT 2
#define  GVP_EE_SLICE_HDR0 0x8218
    #define PIC_PARAMETER_SET_ID_MASK 0x000000FF
    #define PIC_PARAMETER_SET_ID_SHIFT 0
    #define GVP_EE_SLICE_HDR0_SLICE_TYPE_MASK 0x00000F00
    #define GVP_EE_SLICE_HDR0_SLICE_TYPE_SHIFT 8
    #define FIRST_MB_IN_SLICE_MASK 0x00FF0000
    #define FIRST_MB_IN_SLICE_SHIFT 16
#define  GVP_EE_SLICE_HDR1 0x821C
    #define FRAME_NUM_MASK 0x0000FFFF
    #define FRAME_NUM_SHIFT 0
#define  GVP_EE_SLICE_HDR10 0x8380
    #define GVP_EE_SLICE_HDR10_DATA_MASK 0xFFFFFFFF
    #define GVP_EE_SLICE_HDR10_DATA_SHIFT 0
#define  GVP_EE_SLICE_HDR2 0x8220
    #define IDR_PIC_ID_MASK 0x0000FFFF
    #define IDR_PIC_ID_SHIFT 0
    #define DELTA_PIC_ORDER_ALWAYS_ZERO_MASK 0x01000000
    #define DELTA_PIC_ORDER_ALWAYS_ZERO_SHIFT 24
    #define PIC_ORDER_PRESENT_FLAG_MASK 0x02000000
    #define PIC_ORDER_PRESENT_FLAG_SHIFT 25
    #define PIC_ORDER_CNT_TYPE_MASK 0x0C000000
    #define PIC_ORDER_CNT_TYPE_SHIFT 26
    #define FIELD_PIC_FLAG_MASK 0x40000000
    #define FIELD_PIC_FLAG_SHIFT 30
    #define FRAME_MBS_ONLY_FLAG_MASK 0x80000000
    #define FRAME_MBS_ONLY_FLAG_SHIFT 31
#define  GVP_EE_SLICE_HDR3 0x8224
    #define PIC_ORDER_CNT_LSB_MASK 0x0000FFFF
    #define PIC_ORDER_CNT_LSB_SHIFT 0
#define  GVP_EE_SLICE_HDR4 0x8228
    #define DELTA_PIC_ORDER_CNT_BOTTOM_MASK 0xFFFFFFFF
    #define DELTA_PIC_ORDER_CNT_BOTTOM_SHIFT 0
#define  GVP_EE_SLICE_HDR5 0x822C
    #define DELTA_PIC_ORDER_CNT0_MASK 0xFFFFFFFF
    #define DELTA_PIC_ORDER_CNT0_SHIFT 0
#define  GVP_EE_SLICE_HDR6 0x8230
    #define DELTA_PIC_ORDER_CNT1_MASK 0xFFFFFFFF
    #define DELTA_PIC_ORDER_CNT1_SHIFT 0
#define  GVP_EE_SLICE_HDR7 0x8234
    #define NUM_REF_IDX_L1_MINUS1_MASK 0x0000001F
    #define NUM_REF_IDX_L1_MINUS1_SHIFT 0
    #define NUM_REF_IDX_L0_MINUS1_MASK 0x00001F00
    #define NUM_REF_IDX_L0_MINUS1_SHIFT 8
    #define NUM_REF_IDX_OVERRIDE_MASK 0x01000000
    #define NUM_REF_IDX_OVERRIDE_SHIFT 24
    #define DIRECT_SPATIAL_MV_PRED_MASK 0x80000000
    #define DIRECT_SPATIAL_MV_PRED_SHIFT 31
#define  GVP_EE_SLICE_HDR8 0x8238
    #define SLICE_QP_DELTA_MASK 0x0000007F
    #define SLICE_QP_DELTA_SHIFT 0
    #define CABAC_INIT_IDC_MASK 0x00000300
    #define CABAC_INIT_IDC_SHIFT 8
    #define ADPT_REF_PIC_MARKING_MODE_MASK 0x00200000
    #define ADPT_REF_PIC_MARKING_MODE_SHIFT 21
    #define LONG_TERM_REFERENCE_FLAG_MASK 0x00400000
    #define LONG_TERM_REFERENCE_FLAG_SHIFT 22
    #define NO_OUTPUT_OF_PRIOR_PICS_FLAG_MASK 0x00800000
    #define NO_OUTPUT_OF_PRIOR_PICS_FLAG_SHIFT 23
    #define REF_PIC_LIST_REORDERING_L1_MASK 0x40000000
    #define REF_PIC_LIST_REORDERING_L1_SHIFT 30
    #define REF_PIC_LIST_REORDERING_L0_MASK 0x80000000
    #define REF_PIC_LIST_REORDERING_L0_SHIFT 31
#define  GVP_EE_SLICE_HDR9 0x823C
    #define SLICE_BETA_OFFSET_DIV2_MASK 0x0000001F
    #define SLICE_BETA_OFFSET_DIV2_SHIFT 0
    #define SLICE_ALPHA_OFFSET_MASK 0x00001F00
    #define SLICE_ALPHA_OFFSET_SHIFT 8
    #define DISABLE_DBF_IDC_MASK 0x30000000
    #define DISABLE_DBF_IDC_SHIFT 28
    #define DBF_CONTROL_PRESENT_MASK 0x80000000
    #define DBF_CONTROL_PRESENT_SHIFT 31
#define  GVP_EE_SLICE_INF0 0x820C
    #define DEF_NUM_REF_IDX_L1_MINUS1_MASK 0x0000001F
    #define DEF_NUM_REF_IDX_L1_MINUS1_SHIFT 0
    #define DEF_NUM_REF_IDX_L0_MINUS1_MASK 0x00001F00
    #define DEF_NUM_REF_IDX_L0_MINUS1_SHIFT 8
    #define GVP_EE_SLICE_INF0_START_CODE_MASK 0x00030000
    #define GVP_EE_SLICE_INF0_START_CODE_SHIFT 16
    #define SYMBOL_MODE_MASK 0x00040000
    #define SYMBOL_MODE_SHIFT 18
    #define GVP_EE_SLICE_INF0_MBAFF_FLAG_MASK 0x00080000
    #define GVP_EE_SLICE_INF0_MBAFF_FLAG_SHIFT 19
    #define TRANSFORM_8X8_MODE_FLAG_MASK 0x00200000
    #define TRANSFORM_8X8_MODE_FLAG_SHIFT 21
    #define GVP_EE_SLICE_INF0_NAL_UNIT_TYPE_MASK 0x1F000000
    #define GVP_EE_SLICE_INF0_NAL_UNIT_TYPE_SHIFT 24
    #define GVP_EE_SLICE_INF0_NAL_REF_IDC_MASK 0x60000000
    #define GVP_EE_SLICE_INF0_NAL_REF_IDC_SHIFT 29
#define  GVP_EE_SLICE_INF1 0x8210
    #define FRAME_SIZE_IN_MB_MASK 0x0000FFFF
    #define FRAME_SIZE_IN_MB_SHIFT 0
    #define GVP_EE_SLICE_INF1_PICT_MB_WIDTH_MASK 0x00FF0000
    #define GVP_EE_SLICE_INF1_PICT_MB_WIDTH_SHIFT 16
#define  GVP_EE_SLICE_INF2 0x8214
    #define MAX_FRAME_NUM_BITS_MASK 0x0000003F
    #define MAX_FRAME_NUM_BITS_SHIFT 0
    #define MAX_PIC_ORDER_CNT_LSB_BITS_MASK 0x00003F00
    #define MAX_PIC_ORDER_CNT_LSB_BITS_SHIFT 8
#define  GVP_EE_STATUS 0x81B0
    #define LAST_CPL_MB_MASK 0x0000FFFF
    #define LAST_CPL_MB_SHIFT 0
    #define GVP_EE_STATUS_FREE_ENTRIES_MASK 0x00F00000
    #define GVP_EE_STATUS_FREE_ENTRIES_SHIFT 20
    #define SLICE_IN_PROGRESS_MASK 0x01000000
    #define SLICE_IN_PROGRESS_SHIFT 24
    #define GVP_EE_STATUS_ERROR_MASK 0x02000000
    #define GVP_EE_STATUS_ERROR_SHIFT 25
    #define GVP_EE_STATUS_BUSY_MASK 0x04000000
    #define GVP_EE_STATUS_BUSY_SHIFT 26
    #define GVP_EE_STATUS_INT_MASK 0x08000000
    #define GVP_EE_STATUS_INT_SHIFT 27
#define  GVP_FREE_STATUS 0x839C
    #define MS_FREE_ENTRIES_MASK 0x0000003F
    #define MS_FREE_ENTRIES_SHIFT 0
    #define IP_FREE_ENTRIES_MASK 0x00001F00
    #define IP_FREE_ENTRIES_SHIFT 8
    #define NMB_FREE_ENTRIES_MASK 0x00070000
    #define NMB_FREE_ENTRIES_SHIFT 16
    #define DBK_FREE_ENTRIES_MASK 0x00700000
    #define DBK_FREE_ENTRIES_SHIFT 20
    #define MR_FREE_ENTRIES_MASK 0x1F000000
    #define MR_FREE_ENTRIES_SHIFT 24
#define  GVP_IPTQZ_TOPNBR_C_ADR 0x8144
    #define GVP_IPTQZ_TOPNBR_C_ADR_BASE_MASK 0x1FFFFF00
    #define GVP_IPTQZ_TOPNBR_C_ADR_BASE_SHIFT 8
#define  GVP_IPTQZ_TOPNBR_Y_ADR 0x8140
    #define GVP_IPTQZ_TOPNBR_Y_ADR_BASE_MASK 0x1FFFFF00
    #define GVP_IPTQZ_TOPNBR_Y_ADR_BASE_SHIFT 8
#define  GVP_IP_CMDFIFO_0 0x80F0
    #define MODE0_8X8L_MASK 0x00000001
    #define MODE0_8X8L_SHIFT 0
    #define MODE1_8X8L_MASK 0x00000002
    #define MODE1_8X8L_SHIFT 1
    #define MODE2_8X8L_MASK 0x00000004
    #define MODE2_8X8L_SHIFT 2
    #define MODE3_8X8L_MASK 0x00000008
    #define MODE3_8X8L_SHIFT 3
    #define MODE0_4X4_MASK 0x00000010
    #define MODE0_4X4_SHIFT 4
    #define MODE1_4X4_MASK 0x00000020
    #define MODE1_4X4_SHIFT 5
    #define MODE2_4X4_MASK 0x00000040
    #define MODE2_4X4_SHIFT 6
    #define MODE3_4X4_MASK 0x00000080
    #define MODE3_4X4_SHIFT 7
    #define MODE4_4X4_MASK 0x00000100
    #define MODE4_4X4_SHIFT 8
    #define MODE5_4X4_MASK 0x00000200
    #define MODE5_4X4_SHIFT 9
    #define MODE6_4X4_MASK 0x00000400
    #define MODE6_4X4_SHIFT 10
    #define MODE7_4X4_MASK 0x00000800
    #define MODE7_4X4_SHIFT 11
    #define MODE8_4X4_MASK 0x00001000
    #define MODE8_4X4_SHIFT 12
    #define MODE4_8X8L_MASK 0x00002000
    #define MODE4_8X8L_SHIFT 13
    #define MODE5_8X8L_MASK 0x00004000
    #define MODE5_8X8L_SHIFT 14
    #define MODE6_8X8L_MASK 0x00008000
    #define MODE6_8X8L_SHIFT 15
    #define MODE0_16X16_MASK 0x00010000
    #define MODE0_16X16_SHIFT 16
    #define MODE1_16X16_MASK 0x00020000
    #define MODE1_16X16_SHIFT 17
    #define MODE2_16X16_MASK 0x00040000
    #define MODE2_16X16_SHIFT 18
    #define MODE3_16X16_MASK 0x00080000
    #define MODE3_16X16_SHIFT 19
    #define MODE0_8X8_MASK 0x00100000
    #define MODE0_8X8_SHIFT 20
    #define MODE1_8X8_MASK 0x00200000
    #define MODE1_8X8_SHIFT 21
    #define MODE2_8X8_MASK 0x00400000
    #define MODE2_8X8_SHIFT 22
    #define MODE3_8X8_MASK 0x00800000
    #define MODE3_8X8_SHIFT 23
    #define FRAME_PRED_DIS_MASK 0x01000000
    #define FRAME_PRED_DIS_SHIFT 24
    #define FIELD_PRED_DIS_MASK 0x02000000
    #define FIELD_PRED_DIS_SHIFT 25
    #define FRAME_PRED_DIS_8X8L_MASK 0x04000000
    #define FRAME_PRED_DIS_8X8L_SHIFT 26
    #define FIELD_PRED_DIS_8X8L_MASK 0x08000000
    #define FIELD_PRED_DIS_8X8L_SHIFT 27
    #define MODE7_8X8L_MASK 0x10000000
    #define MODE7_8X8L_SHIFT 28
    #define MODE8_8X8L_MASK 0x20000000
    #define MODE8_8X8L_SHIFT 29
#define  GVP_IP_CMDFIFO_1 0x80F4
    #define CURRENT_Y_MASK 0x0000000F
    #define CURRENT_Y_SHIFT 0
    #define CURRENT_C_MASK 0x000000F0
    #define CURRENT_C_SHIFT 4
    #define TOPNBR_MASK 0x00FF0000
    #define TOPNBR_SHIFT 16
#define  GVP_IP_CMDFIFO_2 0x80FC
    #define MODE_A_TOP_MASK 0x0000000F
    #define MODE_A_TOP_SHIFT 0
    #define MODE_B_TOP_MASK 0x000000F0
    #define MODE_B_TOP_SHIFT 4
    #define MODE_C_TOP_MASK 0x00000F00
    #define MODE_C_TOP_SHIFT 8
    #define MODE_D_TOP_MASK 0x0000F000
    #define MODE_D_TOP_SHIFT 12
    #define MODE_A_BOT_MASK 0x000F0000
    #define MODE_A_BOT_SHIFT 16
    #define MODE_B_BOT_MASK 0x00F00000
    #define MODE_B_BOT_SHIFT 20
    #define MODE_C_BOT_MASK 0x0F000000
    #define MODE_C_BOT_SHIFT 24
    #define MODE_D_BOT_MASK 0xF0000000
    #define MODE_D_BOT_SHIFT 28
#define  GVP_IP_CMDFIFO_3 0x8100
    #define SATD_SAD_MASK 0x00000001
    #define SATD_SAD_SHIFT 0
    #define TOP_AVAIL_MASK 0x00000010
    #define TOP_AVAIL_SHIFT 4
    #define LEFT_AVAIL_MASK 0x00000020
    #define LEFT_AVAIL_SHIFT 5
    #define TOP_LEFT_AVAIL_MASK 0x00000040
    #define TOP_LEFT_AVAIL_SHIFT 6
    #define TOP_RIGHT_AVAIL_MASK 0x00000080
    #define TOP_RIGHT_AVAIL_SHIFT 7
    #define GVP_IP_CMDFIFO_3_LAMBDA_MASK 0x00007F00
    #define GVP_IP_CMDFIFO_3_LAMBDA_SHIFT 8
    #define GVP_IP_CMDFIFO_3_CMD_TAG_MASK 0x07F00000
    #define GVP_IP_CMDFIFO_3_CMD_TAG_SHIFT 20
#define  GVP_IP_CMDFIFO_4 0x8104
    #define PAR_INDX_MASK 0x000000FF
    #define PAR_INDX_SHIFT 0
    #define IP_ROW_INDX_MASK 0x0000FF00
    #define IP_ROW_INDX_SHIFT 8
    #define RECON_INDX_MASK 0x000F0000
    #define RECON_INDX_SHIFT 16
    #define QP_MASK 0x03F00000
    #define QP_SHIFT 20
#define  GVP_IP_TQZ_DUMMY_REG 0x8108
    #define GVP_IP_TQZ_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define GVP_IP_TQZ_DUMMY_REG_DATA_SHIFT 0
#define  GVP_IP_TQZ_STATUS 0x810C
    #define GVP_IP_TQZ_STATUS_IP_BUSY_MASK 0x00000001
    #define GVP_IP_TQZ_STATUS_IP_BUSY_SHIFT 0
    #define IP_DONE_MASK 0x00000002
    #define IP_DONE_SHIFT 1
    #define GVP_IP_TQZ_STATUS_TQZ_BUSY_MASK 0x00000010
    #define GVP_IP_TQZ_STATUS_TQZ_BUSY_SHIFT 4
    #define TQZ_FWD_BUSY_MASK 0x00000020
    #define TQZ_FWD_BUSY_SHIFT 5
    #define TQZ_INV_BUSY_MASK 0x00000040
    #define TQZ_INV_BUSY_SHIFT 6
    #define TQZ_RL_BUSY_MASK 0x00000080
    #define TQZ_RL_BUSY_SHIFT 7
    #define TQZ_RL_WBUSY_MASK 0x00000100
    #define TQZ_RL_WBUSY_SHIFT 8
    #define TQZ_RECON_WBUSY_MASK 0x00000200
    #define TQZ_RECON_WBUSY_SHIFT 9
    #define TQZ_PAR_WBUSY_MASK 0x00000400
    #define TQZ_PAR_WBUSY_SHIFT 10
    #define GVP_IP_TQZ_STATUS_CMD_STATUS_MASK 0x0007F000
    #define GVP_IP_TQZ_STATUS_CMD_STATUS_SHIFT 12
    #define GVP_IP_TQZ_STATUS_FREE_ENTRIES_MASK 0x01F00000
    #define GVP_IP_TQZ_STATUS_FREE_ENTRIES_SHIFT 20
#define  GVP_MD_BIAS_0 0x82F0
    #define BIAS_INTRA_FRM_MASK 0x0000001F
    #define BIAS_INTRA_FRM_SHIFT 0
    #define BIAS_INTRA_FLD_MASK 0x000003E0
    #define BIAS_INTRA_FLD_SHIFT 5
    #define BIAS_DIRECT_16X16_FRM_MASK 0x00007C00
    #define BIAS_DIRECT_16X16_FRM_SHIFT 10
    #define BIAS_DIRECT_16X16_FLD_MASK 0x000F8000
    #define BIAS_DIRECT_16X16_FLD_SHIFT 15
    #define BIAS_16X16_FLD_MASK 0x01F00000
    #define BIAS_16X16_FLD_SHIFT 20
#define  GVP_MD_BIAS_1 0x82F4
    #define BIAS_16X8_FRM_MASK 0x0000001F
    #define BIAS_16X8_FRM_SHIFT 0
    #define BIAS_8X16_FRM_MASK 0x000003E0
    #define BIAS_8X16_FRM_SHIFT 5
    #define BIAS_8X8_ONE_DIR_FRM_MASK 0x00007C00
    #define BIAS_8X8_ONE_DIR_FRM_SHIFT 10
    #define BIAS_8X8_BIDIR_FRM_MASK 0x000F8000
    #define BIAS_8X8_BIDIR_FRM_SHIFT 15
    #define BIAS_8X8_DIRECT_FRM_MASK 0x01F00000
    #define BIAS_8X8_DIRECT_FRM_SHIFT 20
#define  GVP_MD_BIAS_2 0x82F8
    #define BIAS_16X8_FLD_MASK 0x0000001F
    #define BIAS_16X8_FLD_SHIFT 0
    #define BIAS_8X16_FLD_MASK 0x000003E0
    #define BIAS_8X16_FLD_SHIFT 5
    #define BIAS_8X8_ONE_DIR_FLD_MASK 0x00007C00
    #define BIAS_8X8_ONE_DIR_FLD_SHIFT 10
    #define BIAS_8X8_BIDIR_FLD_MASK 0x000F8000
    #define BIAS_8X8_BIDIR_FLD_SHIFT 15
    #define BIAS_8X8_DIRECT_FLD_MASK 0x01F00000
    #define BIAS_8X8_DIRECT_FLD_SHIFT 20
#define  GVP_MR_CMD_FIFO_0 0x80B4
    #define GVP_MR_CMD_FIFO_0_DIRECTION_MASK 0x0000001C
    #define GVP_MR_CMD_FIFO_0_DIRECTION_SHIFT 2
    #define GVP_MR_CMD_FIFO_0_PARTITIONS_MASK 0xFFFFFFC0
    #define GVP_MR_CMD_FIFO_0_PARTITIONS_SHIFT 6
#define  GVP_MR_CMD_FIFO_1 0x80B8
    #define GVP_MR_CMD_FIFO_1_PARTITIONS_MASK 0x000FFFFF
    #define GVP_MR_CMD_FIFO_1_PARTITIONS_SHIFT 0
    #define GVP_MR_CMD_FIFO_1_CMD_TAG_MASK 0x07F00000
    #define GVP_MR_CMD_FIFO_1_CMD_TAG_SHIFT 20
#define  GVP_MR_CMD_FIFO_2 0x80BC
    #define CUR_Y_INDEX_MASK 0x0000000F
    #define CUR_Y_INDEX_SHIFT 0
    #define CUR_C_INDEX_MASK 0x000000F0
    #define CUR_C_INDEX_SHIFT 4
    #define FWD_INDEX_MASK 0x00000F00
    #define FWD_INDEX_SHIFT 8
    #define BWD_INDEX_MASK 0x0000F000
    #define BWD_INDEX_SHIFT 12
    #define BLEND_INDEX_MASK 0x000F0000
    #define BLEND_INDEX_SHIFT 16
    #define DIRECT_TOP_FRM_FLD_SEL_MASK 0x03000000
    #define DIRECT_TOP_FRM_FLD_SEL_SHIFT 24
    #define DIRECT_BOT_FRM_FLD_SEL_MASK 0x0C000000
    #define DIRECT_BOT_FRM_FLD_SEL_SHIFT 26
#define  GVP_MR_CMD_FIFO_3 0x80C0
    #define CUR_MB_X_MASK 0x0000007F
    #define CUR_MB_X_SHIFT 0
    #define CUR_MB_Y_MASK 0x00007F00
    #define CUR_MB_Y_SHIFT 8
    #define GVP_MR_CMD_FIFO_3_LAMBDA_MASK 0x007F0000
    #define GVP_MR_CMD_FIFO_3_LAMBDA_SHIFT 16
    #define BWD_REF_INDEX_MASK 0x1C000000
    #define BWD_REF_INDEX_SHIFT 26
    #define FWD_REF_INDEX_MASK 0xE0000000
    #define FWD_REF_INDEX_SHIFT 29
#define  GVP_MR_CTRL 0x80C4
    #define FULL_PEL_REFINE_MASK 0x00000008
    #define FULL_PEL_REFINE_SHIFT 3
    #define GVP_MR_CTRL_HALF_PEL_REFINE_MASK 0x00000010
    #define GVP_MR_CTRL_HALF_PEL_REFINE_SHIFT 4
    #define QUARTER_PEL_REFINE_MASK 0x00000020
    #define QUARTER_PEL_REFINE_SHIFT 5
    #define FULL_PEL_4X1_REFINE_MASK 0x00000200
    #define FULL_PEL_4X1_REFINE_SHIFT 9
    #define SELECT_FRM_OR_FLD_MASK 0x00000400
    #define SELECT_FRM_OR_FLD_SHIFT 10
    #define DMV_16X16_ONLY_MASK 0x00000800
    #define DMV_16X16_ONLY_SHIFT 11
    #define SELECT_FWD_OR_BWD_MASK 0x00001000
    #define SELECT_FWD_OR_BWD_SHIFT 12
    #define PARTITION_DISABLE_MASK 0x00002000
    #define PARTITION_DISABLE_SHIFT 13
    #define SELECT_BEST_FRM_OR_FLD_MASK 0x00004000
    #define SELECT_BEST_FRM_OR_FLD_SHIFT 14
    #define CHECK_DMV_IF_STATIONARY_MASK 0x00040000
    #define CHECK_DMV_IF_STATIONARY_SHIFT 18
    #define DISABLE_BLD_WR_MASK 0x00100000
    #define DISABLE_BLD_WR_SHIFT 20
    #define MS_LOCK_STEP_EN_MASK 0x00200000
    #define MS_LOCK_STEP_EN_SHIFT 21
    #define USE_DMV_AS_PMV_MASK 0x00400000
    #define USE_DMV_AS_PMV_SHIFT 22
    #define GVP_MR_CTRL_SOFT_RESET_MASK 0x80000000
    #define GVP_MR_CTRL_SOFT_RESET_SHIFT 31
#define  GVP_MR_FWD_BWD_THRESHOLD 0x80DC
    #define MR_FWD_BWD_THRESHOLD_MASK 0x0007FFFF
    #define MR_FWD_BWD_THRESHOLD_SHIFT 0
#define  GVP_MR_MV_SCALE 0x80E8
    #define MR_MV_SCL_X_MASK 0x0000FFFF
    #define MR_MV_SCL_X_SHIFT 0
    #define MR_MV_SCL_Y_MASK 0xFFFF0000
    #define MR_MV_SCL_Y_SHIFT 16
#define  GVP_MR_REFINE_THRESHOLD 0x80E0
    #define THRESHOLD_COST_MASK 0x003FFFFF
    #define THRESHOLD_COST_SHIFT 0
#define  GVP_MR_STATUS 0x80B0
    #define GVP_MR_STATUS_CMD_STATUS_MASK 0x0000007F
    #define GVP_MR_STATUS_CMD_STATUS_SHIFT 0
    #define GVP_MR_STATUS_FREE_ENTRIES_MASK 0x001F0000
    #define GVP_MR_STATUS_FREE_ENTRIES_SHIFT 16
    #define GVP_MR_STATUS_BUSY_MASK 0x80000000
    #define GVP_MR_STATUS_BUSY_SHIFT 31
#define  GVP_MSR_BIAS 0x80C8
    #define DEFAULT_PRED_BIAS_MASK 0x00000001
    #define DEFAULT_PRED_BIAS_SHIFT 0
    #define DEFAULT_FIELD_BIAS_MASK 0x00000002
    #define DEFAULT_FIELD_BIAS_SHIFT 1
    #define PRED_BIAS_MASK 0x00001FFC
    #define PRED_BIAS_SHIFT 2
    #define FIELD_REF0_BIAS_MASK 0x003FE000
    #define FIELD_REF0_BIAS_SHIFT 13
    #define FIELD_REF1_BIAS_MASK 0xFFC00000
    #define FIELD_REF1_BIAS_SHIFT 22
#define  GVP_MSR_COST_ADR 0x8038
    #define GVP_MSR_COST_ADR_BASE_MASK 0x1FFFFF00
    #define GVP_MSR_COST_ADR_BASE_SHIFT 8
#define  GVP_MSR_DUMMY_REG 0x80CC
    #define GVP_MSR_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define GVP_MSR_DUMMY_REG_DATA_SHIFT 0
#define  GVP_MSR_MV_SCALE 0x80E4
    #define GVP_MSR_MV_SCALE_MV_SCL_X_MASK 0x0000FFFF
    #define GVP_MSR_MV_SCALE_MV_SCL_X_SHIFT 0
    #define GVP_MSR_MV_SCALE_MV_SCL_Y_MASK 0xFFFF0000
    #define GVP_MSR_MV_SCALE_MV_SCL_Y_SHIFT 16
#define  GVP_MS_BIAS 0x80A4
    #define BIAS_16X8_MASK 0x0000FFFF
    #define BIAS_16X8_SHIFT 0
    #define BIAS_8X8_MASK 0xFFFF0000
    #define BIAS_8X8_SHIFT 16
#define  GVP_MS_CMD_FIFO_0 0x8074
    #define SMV_Y_MASK 0x000003FF
    #define SMV_Y_SHIFT 0
    #define SMV_X_MASK 0x0FFF0000
    #define SMV_X_SHIFT 16
    #define LAST_CMD_MASK 0x80000000
    #define LAST_CMD_SHIFT 31
#define  GVP_MS_CMD_FIFO_1 0x8078
    #define PMV_Y_MASK 0x00000FFF
    #define PMV_Y_SHIFT 0
    #define SML_SRCH_DIS_MASK 0x00001000
    #define SML_SRCH_DIS_SHIFT 12
    #define LRG_SRCH_DIS_MASK 0x00002000
    #define LRG_SRCH_DIS_SHIFT 13
    #define ET_SML_FLAG_MASK 0x00004000
    #define ET_SML_FLAG_SHIFT 14
    #define ET_LRG_FLAG_MASK 0x00008000
    #define ET_LRG_FLAG_SHIFT 15
    #define PMV_X_MASK 0x3FFF0000
    #define PMV_X_SHIFT 16
    #define ET_MED_FLAG_MASK 0x40000000
    #define ET_MED_FLAG_SHIFT 30
    #define ET_NEG_COST_MASK 0x80000000
    #define ET_NEG_COST_SHIFT 31
#define  GVP_MS_CMD_FIFO_2 0x807C
    #define GVP_MS_CMD_FIFO_2_LAMBDA_MASK 0x0000007F
    #define GVP_MS_CMD_FIFO_2_LAMBDA_SHIFT 0
    #define HOLD_PREV_COST_MASK 0x00000080
    #define HOLD_PREV_COST_SHIFT 7
    #define CUR_INDEX_MASK 0x00000F00
    #define CUR_INDEX_SHIFT 8
    #define OUT_INDEX_MASK 0x0000F000
    #define OUT_INDEX_SHIFT 12
    #define REF_INDEX_MASK 0x00070000
    #define REF_INDEX_SHIFT 16
    #define OUTPUT_MV_DIS_MASK 0x00080000
    #define OUTPUT_MV_DIS_SHIFT 19
    #define MB_INCREMENT_MASK 0x00100000
    #define MB_INCREMENT_SHIFT 20
    #define PMV_EQ_SMV_MASK 0x00200000
    #define PMV_EQ_SMV_SHIFT 21
    #define ONE_FLD_FLAG_MASK 0x00C00000
    #define ONE_FLD_FLAG_SHIFT 22
    #define GVP_MS_CMD_FIFO_2_CMD_TAG_MASK 0xFF000000
    #define GVP_MS_CMD_FIFO_2_CMD_TAG_SHIFT 24
#define  GVP_MS_CTRL 0x8094
    #define GVP_MS_CTRL_SOFT_RESET_MASK 0x00000001
    #define GVP_MS_CTRL_SOFT_RESET_SHIFT 0
    #define SCALE_PIC_MASK 0x0000000C
    #define SCALE_PIC_SHIFT 2
    #define LO_HI_DIS_MASK 0x00000010
    #define LO_HI_DIS_SHIFT 4
    #define MBAFF_OFF_X2_MASK 0x00000020
    #define MBAFF_OFF_X2_SHIFT 5
    #define OUTPUT_COST_MASK 0x00000100
    #define OUTPUT_COST_SHIFT 8
    #define OUTPUT_STAT_MASK 0x00000200
    #define OUTPUT_STAT_SHIFT 9
    #define OUTPUT_XTRA_HINT_MASK 0x00000400
    #define OUTPUT_XTRA_HINT_SHIFT 10
    #define PARTN_RATIO_MASK 0x00007000
    #define PARTN_RATIO_SHIFT 12
    #define FRFL_RATIO_MASK 0x00070000
    #define FRFL_RATIO_SHIFT 16
    #define ET_16X16_FRM_DIS_MASK 0x00100000
    #define ET_16X16_FRM_DIS_SHIFT 20
    #define ET_16X8_FRM_DIS_MASK 0x00200000
    #define ET_16X8_FRM_DIS_SHIFT 21
    #define ET_8X16_FRM_DIS_MASK 0x00400000
    #define ET_8X16_FRM_DIS_SHIFT 22
    #define ET_8X8_FRM_DIS_MASK 0x00800000
    #define ET_8X8_FRM_DIS_SHIFT 23
    #define ET_S8X8_FRM_DIS_MASK 0x01000000
    #define ET_S8X8_FRM_DIS_SHIFT 24
    #define ET_16X16_FLD_DIS_MASK 0x02000000
    #define ET_16X16_FLD_DIS_SHIFT 25
    #define ET_16X8_FLD_DIS_MASK 0x04000000
    #define ET_16X8_FLD_DIS_SHIFT 26
    #define ET_8X16_FLD_DIS_MASK 0x08000000
    #define ET_8X16_FLD_DIS_SHIFT 27
    #define ET_8X8_FLD_DIS_MASK 0x10000000
    #define ET_8X8_FLD_DIS_SHIFT 28
    #define STATIONARY_MASK 0x80000000
    #define STATIONARY_SHIFT 31
#define  GVP_MS_LRG_16_THRESH 0x808C
    #define GVP_MS_LRG_16_THRESH_COST_16X16_MASK 0x0001FFFF
    #define GVP_MS_LRG_16_THRESH_COST_16X16_SHIFT 0
#define  GVP_MS_LRG_8_THRESH 0x8090
    #define GVP_MS_LRG_8_THRESH_COST_16X8_MASK 0x0000FFFF
    #define GVP_MS_LRG_8_THRESH_COST_16X8_SHIFT 0
    #define GVP_MS_LRG_8_THRESH_COST_8X8_MASK 0xFFFF0000
    #define GVP_MS_LRG_8_THRESH_COST_8X8_SHIFT 16
#define  GVP_MS_MED_16_THRESH 0x809C
    #define GVP_MS_MED_16_THRESH_COST_16X16_MASK 0x0001FFFF
    #define GVP_MS_MED_16_THRESH_COST_16X16_SHIFT 0
#define  GVP_MS_MED_8_THRESH 0x80A0
    #define GVP_MS_MED_8_THRESH_COST_16X8_MASK 0x0000FFFF
    #define GVP_MS_MED_8_THRESH_COST_16X8_SHIFT 0
    #define GVP_MS_MED_8_THRESH_COST_8X8_MASK 0xFFFF0000
    #define GVP_MS_MED_8_THRESH_COST_8X8_SHIFT 16
#define  GVP_MS_SML_16_THRESH 0x8084
    #define GVP_MS_SML_16_THRESH_COST_16X16_MASK 0x0001FFFF
    #define GVP_MS_SML_16_THRESH_COST_16X16_SHIFT 0
    #define COST_STATN_MASK 0xFFF00000
    #define COST_STATN_SHIFT 20
#define  GVP_MS_SML_8_THRESH 0x8088
    #define GVP_MS_SML_8_THRESH_COST_16X8_MASK 0x0000FFFF
    #define GVP_MS_SML_8_THRESH_COST_16X8_SHIFT 0
    #define GVP_MS_SML_8_THRESH_COST_8X8_MASK 0xFFFF0000
    #define GVP_MS_SML_8_THRESH_COST_8X8_SHIFT 16
#define  GVP_MS_SRCH_RANGE 0x8080
    #define SML_SRCH_XY_MASK 0x0000003F
    #define SML_SRCH_XY_SHIFT 0
    #define SML_SRCH_Y_MASK 0x00003F00
    #define SML_SRCH_Y_SHIFT 8
    #define SML_SRCH_Y_EN_MASK 0x00008000
    #define SML_SRCH_Y_EN_SHIFT 15
    #define LRG_SRCH_X_MASK 0x00FF0000
    #define LRG_SRCH_X_SHIFT 16
    #define LRG_SRCH_Y_MASK 0xFF000000
    #define LRG_SRCH_Y_SHIFT 24
#define  GVP_MS_START_MB 0x8098
    #define GVP_MS_START_MB_START_MB_X_MASK 0x000000FF
    #define GVP_MS_START_MB_START_MB_X_SHIFT 0
    #define GVP_MS_START_MB_START_MB_Y_MASK 0x00007F00
    #define GVP_MS_START_MB_START_MB_Y_SHIFT 8
#define  GVP_MS_STATUS 0x8070
    #define GVP_MS_STATUS_CMD_STATUS_MASK 0x000000FF
    #define GVP_MS_STATUS_CMD_STATUS_SHIFT 0
    #define GVP_MS_STATUS_FREE_ENTRIES_MASK 0x003F0000
    #define GVP_MS_STATUS_FREE_ENTRIES_SHIFT 16
    #define GVP_MS_STATUS_BUSY_MASK 0x80000000
    #define GVP_MS_STATUS_BUSY_SHIFT 31
#define  GVP_NMB_CMD_FIFO 0x8318
    #define GVP_NMB_CMD_FIFO_COMMAND_TAG_MASK 0x000000FF
    #define GVP_NMB_CMD_FIFO_COMMAND_TAG_SHIFT 0
    #define GVP_NMB_CMD_FIFO_MBH_INDEX_MASK 0x00000F00
    #define GVP_NMB_CMD_FIFO_MBH_INDEX_SHIFT 8
    #define GVP_NMB_CMD_FIFO_DSQA_INDEX_MASK 0x0000F000
    #define GVP_NMB_CMD_FIFO_DSQA_INDEX_SHIFT 12
    #define SMV_INDEX_MASK 0x000F0000
    #define SMV_INDEX_SHIFT 16
    #define MV_SIZE_MASK 0x03F00000
    #define MV_SIZE_SHIFT 20
#define  GVP_NMB_CTRL 0x8314
    #define GVP_NMB_CTRL_MODE_MASK 0x00000003
    #define GVP_NMB_CTRL_MODE_SHIFT 0
    #define GVP_NMB_CTRL_SOFT_RESET_MASK 0x80000000
    #define GVP_NMB_CTRL_SOFT_RESET_SHIFT 31
#define  GVP_NMB_DBG 0x8350
    #define GVP_NMB_DBG_DATA_MASK 0xFFFFFFFF
    #define GVP_NMB_DBG_DATA_SHIFT 0
#define  GVP_NMB_DBG_CTRL 0x834C
    #define GVP_NMB_DBG_CTRL_SEL_MASK 0x0000003F
    #define GVP_NMB_DBG_CTRL_SEL_SHIFT 0
    #define GVP_NMB_DBG_CTRL_MUX_MASK 0x00001F00
    #define GVP_NMB_DBG_CTRL_MUX_SHIFT 8
#define  GVP_NMB_MBH_BASE 0x8320
    #define GVP_NMB_MBH_BASE_ADDR_MASK 0x1FFFFFF8
    #define GVP_NMB_MBH_BASE_ADDR_SHIFT 3
#define  GVP_NMB_MVA_RB_BASE 0x8324
    #define GVP_NMB_MVA_RB_BASE_ADDR_MASK 0x1FFFFFF8
    #define GVP_NMB_MVA_RB_BASE_ADDR_SHIFT 3
#define  GVP_NMB_MVA_RB_CTRL 0x8328
    #define GVP_NMB_MVA_RB_CTRL_SIZE_MASK 0x007FFFFC
    #define GVP_NMB_MVA_RB_CTRL_SIZE_SHIFT 2
#define  GVP_NMB_MVA_RB_RPTR 0x832C
    #define GVP_NMB_MVA_RB_RPTR_OFFSET_MASK 0x007FFFFC
    #define GVP_NMB_MVA_RB_RPTR_OFFSET_SHIFT 2
#define  GVP_NMB_MVA_RB_WPTR 0x8330
    #define GVP_NMB_MVA_RB_WPTR_OFFSET_MASK 0x007FFFFC
    #define GVP_NMB_MVA_RB_WPTR_OFFSET_SHIFT 2
#define  GVP_NMB_MVD_RB_BASE 0x8338
    #define GVP_NMB_MVD_RB_BASE_ADDR_MASK 0x1FFFFFF8
    #define GVP_NMB_MVD_RB_BASE_ADDR_SHIFT 3
#define  GVP_NMB_MVD_RB_CTRL 0x833C
    #define GVP_NMB_MVD_RB_CTRL_SIZE_MASK 0x007FFFFC
    #define GVP_NMB_MVD_RB_CTRL_SIZE_SHIFT 2
#define  GVP_NMB_MVD_RB_RPTR 0x8340
    #define GVP_NMB_MVD_RB_RPTR_OFFSET_MASK 0x007FFFFC
    #define GVP_NMB_MVD_RB_RPTR_OFFSET_SHIFT 2
#define  GVP_NMB_MVD_RB_WPTR 0x8344
    #define GVP_NMB_MVD_RB_WPTR_OFFSET_MASK 0x007FFFFC
    #define GVP_NMB_MVD_RB_WPTR_OFFSET_SHIFT 2
#define  GVP_NMB_SMV_BASE 0x8348
    #define GVP_NMB_SMV_BASE_ADDR_MASK 0x1FFFFFF8
    #define GVP_NMB_SMV_BASE_ADDR_SHIFT 3
#define  GVP_NMB_START_MB 0x8310
    #define GVP_NMB_START_MB_START_MB_X_MASK 0x000000FF
    #define GVP_NMB_START_MB_START_MB_X_SHIFT 0
    #define GVP_NMB_START_MB_START_MB_Y_MASK 0x00007F00
    #define GVP_NMB_START_MB_START_MB_Y_SHIFT 8
#define  GVP_NMB_STATUS 0x831C
    #define GVP_NMB_STATUS_NMB_BUSY_MASK 0x00000001
    #define GVP_NMB_STATUS_NMB_BUSY_SHIFT 0
    #define GVP_NMB_STATUS_COMMAND_TAG_MASK 0x0000FF00
    #define GVP_NMB_STATUS_COMMAND_TAG_SHIFT 8
    #define GVP_NMB_STATUS_FREE_ENTRIES_MASK 0x00070000
    #define GVP_NMB_STATUS_FREE_ENTRIES_SHIFT 16
#define  GVP_NMB_TOP_NB_BASE 0x8334
    #define GVP_NMB_TOP_NB_BASE_ADDR_MASK 0x1FFFFFF8
    #define GVP_NMB_TOP_NB_BASE_ADDR_SHIFT 3
#define  GVP_PAR_ADDR 0x8158
    #define GVP_PAR_ADDR_BASE_MASK 0x1FFFFFF8
    #define GVP_PAR_ADDR_BASE_SHIFT 3
#define  GVP_PICT_SIZE 0x8004
    #define GVP_PICT_SIZE_PICT_MB_WIDTH_MASK 0x000000FF
    #define GVP_PICT_SIZE_PICT_MB_WIDTH_SHIFT 0
    #define GVP_PICT_SIZE_PICT_MB_HEIGHT_MASK 0x0000FF00
    #define GVP_PICT_SIZE_PICT_MB_HEIGHT_SHIFT 8
#define  GVP_PRED_C_ADR 0x8034
    #define GVP_PRED_C_ADR_BASE_MASK 0x1FFFFF00
    #define GVP_PRED_C_ADR_BASE_SHIFT 8
#define  GVP_PRED_Y_ADR 0x8030
    #define GVP_PRED_Y_ADR_BASE_MASK 0x1FFFFF00
    #define GVP_PRED_Y_ADR_BASE_SHIFT 8
#define  GVP_RECON_C_ADR 0x8044
    #define GVP_RECON_C_ADR_BASE_MASK 0x1FFFFF00
    #define GVP_RECON_C_ADR_BASE_SHIFT 8
#define  GVP_RECON_Y_ADR 0x8040
    #define GVP_RECON_Y_ADR_BASE_MASK 0x1FFFFF00
    #define GVP_RECON_Y_ADR_BASE_SHIFT 8
#define  GVP_REF_CACHE 0x8060
    #define GVP_REF_CACHE_PARTITIONS_MASK 0x00000001
    #define GVP_REF_CACHE_PARTITIONS_SHIFT 0
    #define GVP_REF_CACHE_INVALIDATE_MASK 0x00000002
    #define GVP_REF_CACHE_INVALIDATE_SHIFT 1
    #define PARTN_MODE_MASK 0x00000004
    #define PARTN_MODE_SHIFT 2
    #define LOCK_STEP_EN_MASK 0x00000008
    #define LOCK_STEP_EN_SHIFT 3
    #define LOCK_STEP_NUM_MASK 0x00000030
    #define LOCK_STEP_NUM_SHIFT 4
    #define REF_PARTN_0_MASK 0x00000700
    #define REF_PARTN_0_SHIFT 8
    #define REF_PARTN_1_MASK 0x00007000
    #define REF_PARTN_1_SHIFT 12
    #define MS_CHROMA_PREFETCH_MASK 0x00010000
    #define MS_CHROMA_PREFETCH_SHIFT 16
    #define MS_REF_FRAME_MODE_MASK 0x00020000
    #define MS_REF_FRAME_MODE_SHIFT 17
    #define MS_PREFETCH_CNT_MASK 0x01F00000
    #define MS_PREFETCH_CNT_SHIFT 20
    #define MS_PREFETCH_Y_OFFSET_MASK 0xF0000000
    #define MS_PREFETCH_Y_OFFSET_SHIFT 28
#define  GVP_REF_CACHE_PERF_COUNTER 0x8068
    #define COUNTER_MASK 0xFFFFFFFF
    #define COUNTER_SHIFT 0
#define  GVP_REF_CACHE_PERF_CTRL 0x8064
    #define CLEAR_MASK 0x00000001
    #define CLEAR_SHIFT 0
    #define GVP_REF_CACHE_PERF_CTRL_ENABLE_MASK 0x00000002
    #define GVP_REF_CACHE_PERF_CTRL_ENABLE_SHIFT 1
    #define SELECT_MASK 0x0000007C
    #define SELECT_SHIFT 2
    #define GVP_REF_CACHE_PERF_CTRL_SOFT_RESET_MASK 0x80000000
    #define GVP_REF_CACHE_PERF_CTRL_SOFT_RESET_SHIFT 31
#define  GVP_REF_C_ADR 0x8024
    #define GVP_REF_C_ADR_BASE_MASK 0x1FFFFF00
    #define GVP_REF_C_ADR_BASE_SHIFT 8
#define  GVP_REF_PICT_SIZE 0x8014
    #define GVP_REF_PICT_SIZE_REF_Y_SIZE_MASK 0x00007FFF
    #define GVP_REF_PICT_SIZE_REF_Y_SIZE_SHIFT 0
    #define GVP_REF_PICT_SIZE_REF_C_SIZE_MASK 0x7FFF0000
    #define GVP_REF_PICT_SIZE_REF_C_SIZE_SHIFT 16
#define  GVP_REF_PITCH 0x8010
    #define GVP_REF_PITCH_REF_PITCH_MASK 0x00000FE0
    #define GVP_REF_PITCH_REF_PITCH_SHIFT 5
#define  GVP_REF_Y_ADR 0x8020
    #define GVP_REF_Y_ADR_BASE_MASK 0x1FFFFF00
    #define GVP_REF_Y_ADR_BASE_SHIFT 8
#define  GVP_RES_C_ADR 0x802C
    #define GVP_RES_C_ADR_BASE_MASK 0x1FFFFF00
    #define GVP_RES_C_ADR_BASE_SHIFT 8
#define  GVP_RES_Y_ADR 0x8028
    #define GVP_RES_Y_ADR_BASE_MASK 0x1FFFFF00
    #define GVP_RES_Y_ADR_BASE_SHIFT 8
#define  GVP_RLAC_ADR 0x8050
    #define GVP_RLAC_ADR_BASE_MASK 0x1FFFFFF8
    #define GVP_RLAC_ADR_BASE_SHIFT 3
#define  GVP_RLAC_BUF_SIZE 0x8054
    #define GVP_RLAC_BUF_SIZE_SIZE_MASK 0x00FFFFF8
    #define GVP_RLAC_BUF_SIZE_SIZE_SHIFT 3
#define  GVP_RLDC_ADR 0x8048
    #define GVP_RLDC_ADR_BASE_MASK 0x1FFFFFF8
    #define GVP_RLDC_ADR_BASE_SHIFT 3
#define  GVP_RLDC_BUF_SIZE 0x804C
    #define GVP_RLDC_BUF_SIZE_SIZE_MASK 0x000FFFF8
    #define GVP_RLDC_BUF_SIZE_SIZE_SHIFT 3
#define  GVP_SCRATCH_00 0x83B0
    #define GVP_SCRATCH_00_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_00_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_01 0x83B4
    #define GVP_SCRATCH_01_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_01_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_02 0x83B8
    #define GVP_SCRATCH_02_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_02_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_03 0x83BC
    #define GVP_SCRATCH_03_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_03_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_04 0x83C0
    #define GVP_SCRATCH_04_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_04_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_05 0x83C4
    #define GVP_SCRATCH_05_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_05_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_06 0x83C8
    #define GVP_SCRATCH_06_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_06_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_07 0x83CC
    #define GVP_SCRATCH_07_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_07_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_08 0x83D0
    #define GVP_SCRATCH_08_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_08_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_09 0x83D4
    #define GVP_SCRATCH_09_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_09_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_10 0x83D8
    #define GVP_SCRATCH_10_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_10_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_11 0x83DC
    #define GVP_SCRATCH_11_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_11_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_12 0x83E0
    #define GVP_SCRATCH_12_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_12_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_13 0x83E4
    #define GVP_SCRATCH_13_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_13_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_14 0x83E8
    #define GVP_SCRATCH_14_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_14_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_15 0x83EC
    #define GVP_SCRATCH_15_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_15_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_16 0x83F0
    #define GVP_SCRATCH_16_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_16_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_17 0x83F4
    #define GVP_SCRATCH_17_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_17_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_18 0x83F8
    #define GVP_SCRATCH_18_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_18_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_19 0x83FC
    #define GVP_SCRATCH_19_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_19_SCRATCH_SHIFT 0
#define  GVP_SLICE_INFO 0x8000
    #define GVP_SLICE_INFO_SLICE_TYPE_MASK 0x00000003
    #define GVP_SLICE_INFO_SLICE_TYPE_SHIFT 0
    #define GVP_SLICE_INFO_SLICE_STRUCT_MASK 0x0000000C
    #define GVP_SLICE_INFO_SLICE_STRUCT_SHIFT 2
    #define GVP_SLICE_INFO_MBAFF_FLAG_MASK 0x00000010
    #define GVP_SLICE_INFO_MBAFF_FLAG_SHIFT 4
#define  GVP_SMB_ARB0 0x82A8
    #define GVP_SMB_ARB0_CLI0_REQ_CNT_LIMIT_MASK 0x0000000F
    #define GVP_SMB_ARB0_CLI0_REQ_CNT_LIMIT_SHIFT 0
    #define GVP_SMB_ARB0_CLI1_REQ_CNT_LIMIT_MASK 0x000000F0
    #define GVP_SMB_ARB0_CLI1_REQ_CNT_LIMIT_SHIFT 4
    #define GVP_SMB_ARB0_CLI2_REQ_CNT_LIMIT_MASK 0x00000F00
    #define GVP_SMB_ARB0_CLI2_REQ_CNT_LIMIT_SHIFT 8
    #define GVP_SMB_ARB0_CLI3_REQ_CNT_LIMIT_MASK 0x0000F000
    #define GVP_SMB_ARB0_CLI3_REQ_CNT_LIMIT_SHIFT 12
    #define GVP_SMB_ARB0_CLI4_REQ_CNT_LIMIT_MASK 0x000F0000
    #define GVP_SMB_ARB0_CLI4_REQ_CNT_LIMIT_SHIFT 16
    #define GVP_SMB_ARB0_CLI5_REQ_CNT_LIMIT_MASK 0x00F00000
    #define GVP_SMB_ARB0_CLI5_REQ_CNT_LIMIT_SHIFT 20
    #define GVP_SMB_ARB0_CLI6_REQ_CNT_LIMIT_MASK 0x0F000000
    #define GVP_SMB_ARB0_CLI6_REQ_CNT_LIMIT_SHIFT 24
    #define GVP_SMB_ARB0_CLI7_REQ_CNT_LIMIT_MASK 0xF0000000
    #define GVP_SMB_ARB0_CLI7_REQ_CNT_LIMIT_SHIFT 28
#define  GVP_SMB_ARB1 0x82AC
    #define GVP_SMB_ARB1_CLI8_REQ_CNT_LIMIT_MASK 0x0000000F
    #define GVP_SMB_ARB1_CLI8_REQ_CNT_LIMIT_SHIFT 0
#define  GVP_SMB_CTRL 0x82A0
    #define HOLE_ENABLE_MASK 0x00000001
    #define HOLE_ENABLE_SHIFT 0
    #define HOLE_1K_LOCATION_MASK 0x00003F00
    #define HOLE_1K_LOCATION_SHIFT 8
    #define GVP_SETTLE_MASK 0x00070000
    #define GVP_SETTLE_SHIFT 16
    #define GVP_SMB_CTRL_MEM_CNT_RESET_MASK 0x00100000
    #define GVP_SMB_CTRL_MEM_CNT_RESET_SHIFT 20
    #define GVP_SMB_CTRL_MEM_CNT_EN_MASK 0x00200000
    #define GVP_SMB_CTRL_MEM_CNT_EN_SHIFT 21
    #define GVP_SMB_CTRL_MEM_CNT_SEL_MASK 0x00400000
    #define GVP_SMB_CTRL_MEM_CNT_SEL_SHIFT 22
    #define GVP_SMB_CTRL_READ_ACCEL_MASK 0x01000000
    #define GVP_SMB_CTRL_READ_ACCEL_SHIFT 24
    #define GVP_SMB_CTRL_PF_ARB_MASK 0x02000000
    #define GVP_SMB_CTRL_PF_ARB_SHIFT 25
    #define MCLK_SOFT_RESET_MASK 0x40000000
    #define MCLK_SOFT_RESET_SHIFT 30
    #define GVPCLK_SOFT_RESET_MASK 0x80000000
    #define GVPCLK_SOFT_RESET_SHIFT 31
#define  GVP_SMB_MEM_CNT 0x82B0
    #define GVP_SMB_MEM_CNT_MEM_CNT_MASK 0x00FFFFFF
    #define GVP_SMB_MEM_CNT_MEM_CNT_SHIFT 0
#define  GVP_SMB_PRIORITY 0x82A4
    #define GVP_SMB_PRIORITY_ABSOLUTE_PRIORITY_MASK 0x000001FF
    #define GVP_SMB_PRIORITY_ABSOLUTE_PRIORITY_SHIFT 0
#define  GVP_STATUS 0x805C
    #define SMB_W_BUSY_MASK 0x00000001
    #define SMB_W_BUSY_SHIFT 0
    #define SMB_R_BUSY_MASK 0x00000002
    #define SMB_R_BUSY_SHIFT 1
    #define VMA_A_BUSY_MASK 0x00000004
    #define VMA_A_BUSY_SHIFT 2
    #define VMA_B_BUSY_MASK 0x00000008
    #define VMA_B_BUSY_SHIFT 3
    #define VMA_C_BUSY_MASK 0x00000010
    #define VMA_C_BUSY_SHIFT 4
    #define CCH_BUSY_MASK 0x00000020
    #define CCH_BUSY_SHIFT 5
    #define MS_BUSY_MASK 0x00000040
    #define MS_BUSY_SHIFT 6
    #define MR_BUSY_MASK 0x00000080
    #define MR_BUSY_SHIFT 7
    #define GVP_STATUS_IP_BUSY_MASK 0x00000100
    #define GVP_STATUS_IP_BUSY_SHIFT 8
    #define GVP_STATUS_TQZ_BUSY_MASK 0x00000200
    #define GVP_STATUS_TQZ_BUSY_SHIFT 9
    #define GVP_STATUS_DBK_BUSY_MASK 0x00000400
    #define GVP_STATUS_DBK_BUSY_SHIFT 10
    #define EE_BUSY_MASK 0x00000800
    #define EE_BUSY_SHIFT 11
    #define GVP_STATUS_NMB_BUSY_MASK 0x00001000
    #define GVP_STATUS_NMB_BUSY_SHIFT 12
#define  GVP_TQZ_CTRL 0x814C
    #define GVP_TQZ_CTRL_ENTROPY_FLG_MASK 0x00000001
    #define GVP_TQZ_CTRL_ENTROPY_FLG_SHIFT 0
    #define RECON_ENB_MASK 0x00000002
    #define RECON_ENB_SHIFT 1
    #define COST_ENB_MASK 0x00000004
    #define COST_ENB_SHIFT 2
    #define INTRA_CHROMA_COST_ENB_MASK 0x00000008
    #define INTRA_CHROMA_COST_ENB_SHIFT 3
    #define GVP_TQZ_CTRL_WEIGHT_ENB_MASK 0x00000010
    #define GVP_TQZ_CTRL_WEIGHT_ENB_SHIFT 4
    #define INTER_DECISION_MASK 0x00000060
    #define INTER_DECISION_SHIFT 5
    #define Y_8X8_COST_MASK 0x00000F00
    #define Y_8X8_COST_SHIFT 8
    #define UV_MB_COST_MASK 0x0000F000
    #define UV_MB_COST_SHIFT 12
    #define QP_C_OFFSET_MASK 0x001F0000
    #define QP_C_OFFSET_SHIFT 16
    #define IP_SFT_RST_MASK 0x01000000
    #define IP_SFT_RST_SHIFT 24
    #define TQZ_SFT_RST_MASK 0x10000000
    #define TQZ_SFT_RST_SHIFT 28
#define  GVP_TQZ_RL_HD_AC_PTR 0x8150
    #define HEAD_AC_PTR_MASK 0x00FFFFFC
    #define HEAD_AC_PTR_SHIFT 2
#define  GVP_TQZ_RL_HD_DC_PTR 0x8164
    #define HEAD_DC_PTR_MASK 0x000FFFFC
    #define HEAD_DC_PTR_SHIFT 2
#define  GVP_TQZ_RL_TAIL_AC_PTR 0x8154
    #define TAIL_AC_PTR_MASK 0x00FFFFFC
    #define TAIL_AC_PTR_SHIFT 2
#define  GVP_TQZ_RL_TAIL_DC_PTR 0x8168
    #define TAIL_DC_PTR_MASK 0x000FFFFC
    #define TAIL_DC_PTR_SHIFT 2
#define  GVP_TQZ_SAD 0x816C
    #define VAL_MASK 0xFFFFFFFF
    #define VAL_SHIFT 0
#define  GVP_TQZ_WEIGHT_TABLE_0 0x812C
    #define GVP_TQZ_WEIGHT_TABLE_0_VALUE_MASK 0xFFFFFFFF
    #define GVP_TQZ_WEIGHT_TABLE_0_VALUE_SHIFT 0
#define  GVP_TQZ_WEIGHT_TABLE_1 0x8130
    #define GVP_TQZ_WEIGHT_TABLE_1_VALUE_MASK 0xFFFFFFFF
    #define GVP_TQZ_WEIGHT_TABLE_1_VALUE_SHIFT 0
#define  GVP_TQZ_WEIGHT_TABLE_2 0x8134
    #define GVP_TQZ_WEIGHT_TABLE_2_VALUE_MASK 0xFFFFFFFF
    #define GVP_TQZ_WEIGHT_TABLE_2_VALUE_SHIFT 0
#define  GVP_TQZ_WEIGHT_TABLE_3 0x8138
    #define GVP_TQZ_WEIGHT_TABLE_3_VALUE_MASK 0xFFFFFFFF
    #define GVP_TQZ_WEIGHT_TABLE_3_VALUE_SHIFT 0
#define  GVP_TQZ_WEIGHT_TABLE_CTRL 0x813C
    #define GVP_TQZ_WEIGHT_TABLE_CTRL_INDEX_MASK 0x0000001F
    #define GVP_TQZ_WEIGHT_TABLE_CTRL_INDEX_SHIFT 0
#define  GVP_VMA_CMD_A 0x8268
    #define GVP_VMA_CMD_A_BYTECNT_MASK 0x000FFFF8
    #define GVP_VMA_CMD_A_BYTECNT_SHIFT 3
    #define GVP_VMA_CMD_A_XFER_MODE_MASK 0x00F00000
    #define GVP_VMA_CMD_A_XFER_MODE_SHIFT 20
    #define GVP_VMA_CMD_A_COMMAND_TAG_MASK 0xFF000000
    #define GVP_VMA_CMD_A_COMMAND_TAG_SHIFT 24
#define  GVP_VMA_CMD_B 0x8278
    #define GVP_VMA_CMD_B_BYTECNT_MASK 0x000FFFF8
    #define GVP_VMA_CMD_B_BYTECNT_SHIFT 3
    #define GVP_VMA_CMD_B_XFER_MODE_MASK 0x00F00000
    #define GVP_VMA_CMD_B_XFER_MODE_SHIFT 20
    #define GVP_VMA_CMD_B_COMMAND_TAG_MASK 0xFF000000
    #define GVP_VMA_CMD_B_COMMAND_TAG_SHIFT 24
#define  GVP_VMA_CMD_C 0x8288
    #define GVP_VMA_CMD_C_BYTECNT_MASK 0x000FFFF8
    #define GVP_VMA_CMD_C_BYTECNT_SHIFT 3
    #define GVP_VMA_CMD_C_XFER_MODE_MASK 0x00F00000
    #define GVP_VMA_CMD_C_XFER_MODE_SHIFT 20
#define  GVP_VMA_CRC 0x829C
    #define CRC_MASK 0xFFFFFFFF
    #define CRC_SHIFT 0
#define  GVP_VMA_CTRL 0x8294
    #define Y_PITCH_MASK 0x00000FE0
    #define Y_PITCH_SHIFT 5
    #define ARB_TYPE_MASK 0x00010000
    #define ARB_TYPE_SHIFT 16
    #define C_PITCH_MASK 0x0FE00000
    #define C_PITCH_SHIFT 21
    #define GVP_VMA_CTRL_SOFT_RESET_MASK 0x80000000
    #define GVP_VMA_CTRL_SOFT_RESET_SHIFT 31
#define  GVP_VMA_DST_ADR_A 0x8264
    #define GVP_VMA_DST_ADR_A_DST_ADDRESS_MASK 0x1FFFFFF8
    #define GVP_VMA_DST_ADR_A_DST_ADDRESS_SHIFT 3
#define  GVP_VMA_DST_ADR_B 0x8274
    #define GVP_VMA_DST_ADR_B_DST_ADDRESS_MASK 0x1FFFFFF8
    #define GVP_VMA_DST_ADR_B_DST_ADDRESS_SHIFT 3
#define  GVP_VMA_DST_ADR_C 0x8284
    #define GVP_VMA_DST_ADR_C_DST_ADDRESS_MASK 0x1FFFFFF8
    #define GVP_VMA_DST_ADR_C_DST_ADDRESS_SHIFT 3
#define  GVP_VMA_DUMMY_REG 0x8298
    #define GVP_VMA_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define GVP_VMA_DUMMY_REG_DATA_SHIFT 0
#define  GVP_VMA_SRC2_ADR_A 0x826C
    #define GVP_VMA_SRC2_ADR_A_SRC2_ADDRESS_MASK 0x1FFFFFF8
    #define GVP_VMA_SRC2_ADR_A_SRC2_ADDRESS_SHIFT 3
#define  GVP_VMA_SRC2_ADR_B 0x827C
    #define GVP_VMA_SRC2_ADR_B_SRC2_ADDRESS_MASK 0x1FFFFFF8
    #define GVP_VMA_SRC2_ADR_B_SRC2_ADDRESS_SHIFT 3
#define  GVP_VMA_SRC2_ADR_C 0x828C
    #define GVP_VMA_SRC2_ADR_C_SRC2_ADDRESS_MASK 0x1FFFFFF8
    #define GVP_VMA_SRC2_ADR_C_SRC2_ADDRESS_SHIFT 3
#define  GVP_VMA_SRC3_ADR_A 0x82D0
    #define GVP_VMA_SRC3_ADR_A_SRC3_ADDRESS_MASK 0x1FFFFFF8
    #define GVP_VMA_SRC3_ADR_A_SRC3_ADDRESS_SHIFT 3
#define  GVP_VMA_SRC3_ADR_B 0x82D8
    #define GVP_VMA_SRC3_ADR_B_SRC3_ADDRESS_MASK 0x1FFFFFF8
    #define GVP_VMA_SRC3_ADR_B_SRC3_ADDRESS_SHIFT 3
#define  GVP_VMA_SRC4_ADR_A 0x82D4
    #define GVP_VMA_SRC4_ADR_A_SRC4_ADDRESS_MASK 0x1FFFFFF8
    #define GVP_VMA_SRC4_ADR_A_SRC4_ADDRESS_SHIFT 3
#define  GVP_VMA_SRC4_ADR_B 0x82DC
    #define GVP_VMA_SRC4_ADR_B_SRC4_ADDRESS_MASK 0x1FFFFFF8
    #define GVP_VMA_SRC4_ADR_B_SRC4_ADDRESS_SHIFT 3
#define  GVP_VMA_SRC_ADR_A 0x8260
    #define GVP_VMA_SRC_ADR_A_SRC_ADDRESS_MASK 0xFFFFFFFF
    #define GVP_VMA_SRC_ADR_A_SRC_ADDRESS_SHIFT 0
#define  GVP_VMA_SRC_ADR_B 0x8270
    #define GVP_VMA_SRC_ADR_B_SRC_ADDRESS_MASK 0xFFFFFFFF
    #define GVP_VMA_SRC_ADR_B_SRC_ADDRESS_SHIFT 0
#define  GVP_VMA_SRC_ADR_C 0x8280
    #define GVP_VMA_SRC_ADR_C_SRC_ADDRESS_MASK 0xFFFFFFFF
    #define GVP_VMA_SRC_ADR_C_SRC_ADDRESS_SHIFT 0
#define  GVP_VMA_STATUS 0x8290
    #define COMMAND_STATUS_A_MASK 0x000000FF
    #define COMMAND_STATUS_A_SHIFT 0
    #define FIFO_FREE_A_MASK 0x00000F00
    #define FIFO_FREE_A_SHIFT 8
    #define VMA_BUSY_A_MASK 0x00001000
    #define VMA_BUSY_A_SHIFT 12
    #define COMMAND_STATUS_B_MASK 0x00FF0000
    #define COMMAND_STATUS_B_SHIFT 16
    #define FIFO_FREE_B_MASK 0x0F000000
    #define FIFO_FREE_B_SHIFT 24
    #define VMA_BUSY_B_MASK 0x10000000
    #define VMA_BUSY_B_SHIFT 28
    #define VMA_BUSY_C_MASK 0x80000000
    #define VMA_BUSY_C_SHIFT 31
#define  HBI_CTRL_REG 0x2200
    #define HBI_MC2_ACCESS_MASK 0x00000001
    #define HBI_MC2_ACCESS_SHIFT 0
    #define HBI_DMA_ACCESS_MASK 0x00000002
    #define HBI_DMA_ACCESS_SHIFT 1
#define  HBI_DUMMY_REG 0x2208
    #define HBI_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define HBI_DUMMY_REG_DATA_SHIFT 0
#define  HBI_MC_UPPER_ADDR_REG 0x2204
    #define HBI_UPPER_ADDR_MASK 0x0000000F
    #define HBI_UPPER_ADDR_SHIFT 0
#define  HOST_CPU_INTERRUPT 0x0464
    #define HOST_CPU_INTERRUPT_INT0_MASK 0x00000001
    #define HOST_CPU_INTERRUPT_INT0_SHIFT 0
    #define HOST_CPU_INTERRUPT_INT1_MASK 0x00000002
    #define HOST_CPU_INTERRUPT_INT1_SHIFT 1
    #define HOST_CPU_INTERRUPT_INT2_MASK 0x00000004
    #define HOST_CPU_INTERRUPT_INT2_SHIFT 2
    #define HOST_CPU_INTERRUPT_INT3_MASK 0x00000008
    #define HOST_CPU_INTERRUPT_INT3_SHIFT 3
    #define HOST_CPU_INTERRUPT_INT4_MASK 0x00000010
    #define HOST_CPU_INTERRUPT_INT4_SHIFT 4
#define  HOST_CPU_INTERRUPT_MASK 0x0468
    #define HOST_CPU_INTERRUPT_MASK_INT0_MASK 0x00000001
    #define HOST_CPU_INTERRUPT_MASK_INT0_SHIFT 0
    #define HOST_CPU_INTERRUPT_MASK_INT1_MASK 0x00000002
    #define HOST_CPU_INTERRUPT_MASK_INT1_SHIFT 1
    #define HOST_CPU_INTERRUPT_MASK_INT2_MASK 0x00000004
    #define HOST_CPU_INTERRUPT_MASK_INT2_SHIFT 2
    #define HOST_CPU_INTERRUPT_MASK_INT3_MASK 0x00000008
    #define HOST_CPU_INTERRUPT_MASK_INT3_SHIFT 3
    #define HOST_CPU_INTERRUPT_MASK_INT4_MASK 0x00000010
    #define HOST_CPU_INTERRUPT_MASK_INT4_SHIFT 4
#define  HOST_INTERRUPT 0x0414
    #define HOST_INTERRUPT_TSD_INT0_MASK 0x00000001
    #define HOST_INTERRUPT_TSD_INT0_SHIFT 0
    #define HOST_INTERRUPT_TSD_INT1_MASK 0x00000002
    #define HOST_INTERRUPT_TSD_INT1_SHIFT 1
    #define HOST_INTERRUPT_USBD_INT_MASK 0x00000004
    #define HOST_INTERRUPT_USBD_INT_SHIFT 2
    #define HOST_INTERRUPT_USBH_INT_MASK 0x00000008
    #define HOST_INTERRUPT_USBH_INT_SHIFT 3
    #define HOST_INTERRUPT_TSD_INT4_MASK 0x00000010
    #define HOST_INTERRUPT_TSD_INT4_SHIFT 4
    #define HOST_INTERRUPT_ETH0_INT_MASK 0x00000020
    #define HOST_INTERRUPT_ETH0_INT_SHIFT 5
    #define HOST_INTERRUPT_ETH1_INT_MASK 0x00000040
    #define HOST_INTERRUPT_ETH1_INT_SHIFT 6
    #define HOST_INTERRUPT_PPC_INT_MASK 0x00000080
    #define HOST_INTERRUPT_PPC_INT_SHIFT 7
    #define HOST_INTERRUPT_DMA_INT_MASK 0x00000100
    #define HOST_INTERRUPT_DMA_INT_SHIFT 8
    #define HOST_INTERRUPT_RBM_INT_MASK 0x00000400
    #define HOST_INTERRUPT_RBM_INT_SHIFT 10
    #define HOST_INTERRUPT_MPP_INT_MASK 0x00000800
    #define HOST_INTERRUPT_MPP_INT_SHIFT 11
    #define HOST_INTERRUPT_RSA_INT_MASK 0x00004000
    #define HOST_INTERRUPT_RSA_INT_SHIFT 14
    #define HOST_INTERRUPT_I2S_INT_MASK 0x00008000
    #define HOST_INTERRUPT_I2S_INT_SHIFT 15
    #define HOST_INTERRUPT_RMX_INT_MASK 0x00010000
    #define HOST_INTERRUPT_RMX_INT_SHIFT 16
    #define HOST_INTERRUPT_VHE_INT_MASK 0x00020000
    #define HOST_INTERRUPT_VHE_INT_SHIFT 17
    #define HOST_INTERRUPT_VFE_INT_MASK 0x00040000
    #define HOST_INTERRUPT_VFE_INT_SHIFT 18
    #define HOST_INTERRUPT_VNE_INT_MASK 0x00080000
    #define HOST_INTERRUPT_VNE_INT_SHIFT 19
    #define HOST_INTERRUPT_GVD_INT_MASK 0x00400000
    #define HOST_INTERRUPT_GVD_INT_SHIFT 22
    #define HOST_INTERRUPT_DVE_INT_MASK 0x00800000
    #define HOST_INTERRUPT_DVE_INT_SHIFT 23
    #define HOST_INTERRUPT_SATA_INT_MASK 0x01000000
    #define HOST_INTERRUPT_SATA_INT_SHIFT 24
    #define HOST_INTERRUPT_I2STX_INT_MASK 0x02000000
    #define HOST_INTERRUPT_I2STX_INT_SHIFT 25
    #define HOST_INTERRUPT_SPDIFRX_INT_MASK 0x04000000
    #define HOST_INTERRUPT_SPDIFRX_INT_SHIFT 26
    #define HOST_INTERRUPT_SPDIFTX_INT_MASK 0x08000000
    #define HOST_INTERRUPT_SPDIFTX_INT_SHIFT 27
    #define HOST_INTERRUPT_EDC_INT_MASK 0x10000000
    #define HOST_INTERRUPT_EDC_INT_SHIFT 28
    #define HOST_INTERRUPT_DSCL_INT_MASK 0x20000000
    #define HOST_INTERRUPT_DSCL_INT_SHIFT 29
    #define HOST_INTERRUPT_EE_INT_MASK 0x40000000
    #define HOST_INTERRUPT_EE_INT_SHIFT 30
    #define HOST_INTERRUPT_NFC_INT_MASK 0x80000000
    #define HOST_INTERRUPT_NFC_INT_SHIFT 31
#define  HOST_INTERRUPT1 0x055C
    #define HOST_INTERRUPT1_SMS_INT_MASK 0x00000001
    #define HOST_INTERRUPT1_SMS_INT_SHIFT 0
    #define HOST_INTERRUPT1_VNH_INT_MASK 0x00000002
    #define HOST_INTERRUPT1_VNH_INT_SHIFT 1
    #define HOST_INTERRUPT1_DISP_INT_MASK 0x00000004
    #define HOST_INTERRUPT1_DISP_INT_SHIFT 2
    #define HOST_INTERRUPT1_MAD_INT_MASK 0x00000008
    #define HOST_INTERRUPT1_MAD_INT_SHIFT 3
    #define HOST_INTERRUPT1_GIC_INT_MASK 0x00000010
    #define HOST_INTERRUPT1_GIC_INT_SHIFT 4
    #define HOST_INTERRUPT1_FES_INT_MASK 0x00000020
    #define HOST_INTERRUPT1_FES_INT_SHIFT 5
    #define HOST_INTERRUPT1_G2D_INT_MASK 0x00000040
    #define HOST_INTERRUPT1_G2D_INT_SHIFT 6
    #define HOST_INTERRUPT1_IRC_INT_MASK 0x00000080
    #define HOST_INTERRUPT1_IRC_INT_SHIFT 7
    #define HOST_INTERRUPT1_NRFC_INT_MASK 0x00000100
    #define HOST_INTERRUPT1_NRFC_INT_SHIFT 8
    #define HOST_INTERRUPT1_SMCC_INT_MASK 0x00000200
    #define HOST_INTERRUPT1_SMCC_INT_SHIFT 9
    #define HOST_INTERRUPT1_MAFE_INT_MASK 0x00000400
    #define HOST_INTERRUPT1_MAFE_INT_SHIFT 10
    #define HOST_INTERRUPT1_RMX1_INT_MASK 0x00000800
    #define HOST_INTERRUPT1_RMX1_INT_SHIFT 11
    #define HOST_INTERRUPT1_G3D_INT_MASK 0x00001000
    #define HOST_INTERRUPT1_G3D_INT_SHIFT 12
    #define HOST_INTERRUPT1_UART0_INT_MASK 0x00002000
    #define HOST_INTERRUPT1_UART0_INT_SHIFT 13
    #define HOST_INTERRUPT1_UART1_INT_MASK 0x00004000
    #define HOST_INTERRUPT1_UART1_INT_SHIFT 14
    #define HOST_INTERRUPT1_INT15_MASK 0x00008000
    #define HOST_INTERRUPT1_INT15_SHIFT 15
    #define HOST_INTERRUPT1_INT16_MASK 0x00010000
    #define HOST_INTERRUPT1_INT16_SHIFT 16
    #define HOST_INTERRUPT1_INT17_MASK 0x00020000
    #define HOST_INTERRUPT1_INT17_SHIFT 17
    #define HOST_INTERRUPT1_INT18_MASK 0x00040000
    #define HOST_INTERRUPT1_INT18_SHIFT 18
    #define HOST_INTERRUPT1_INT19_MASK 0x00080000
    #define HOST_INTERRUPT1_INT19_SHIFT 19
    #define HOST_INTERRUPT1_INT20_MASK 0x00100000
    #define HOST_INTERRUPT1_INT20_SHIFT 20
    #define HOST_INTERRUPT1_INT21_MASK 0x00200000
    #define HOST_INTERRUPT1_INT21_SHIFT 21
    #define HOST_INTERRUPT1_INT22_MASK 0x00400000
    #define HOST_INTERRUPT1_INT22_SHIFT 22
    #define HOST_INTERRUPT1_INT23_MASK 0x00800000
    #define HOST_INTERRUPT1_INT23_SHIFT 23
    #define HOST_INTERRUPT1_INT24_MASK 0x01000000
    #define HOST_INTERRUPT1_INT24_SHIFT 24
    #define HOST_INTERRUPT1_INT25_MASK 0x02000000
    #define HOST_INTERRUPT1_INT25_SHIFT 25
    #define HOST_INTERRUPT1_INT26_MASK 0x04000000
    #define HOST_INTERRUPT1_INT26_SHIFT 26
    #define HOST_INTERRUPT1_INT27_MASK 0x08000000
    #define HOST_INTERRUPT1_INT27_SHIFT 27
    #define HOST_INTERRUPT1_INT28_MASK 0x10000000
    #define HOST_INTERRUPT1_INT28_SHIFT 28
    #define HOST_INTERRUPT1_INT29_MASK 0x20000000
    #define HOST_INTERRUPT1_INT29_SHIFT 29
    #define HOST_INTERRUPT1_INT30_MASK 0x40000000
    #define HOST_INTERRUPT1_INT30_SHIFT 30
    #define HOST_INTERRUPT1_INT31_MASK 0x80000000
    #define HOST_INTERRUPT1_INT31_SHIFT 31
#define  HOST_INTERRUPT1_MASK 0x0560
    #define HOST_INTERRUPT1_MASK_SMS_INT_MASK 0x00000001
    #define HOST_INTERRUPT1_MASK_SMS_INT_SHIFT 0
    #define HOST_INTERRUPT1_MASK_VNH_INT_MASK 0x00000002
    #define HOST_INTERRUPT1_MASK_VNH_INT_SHIFT 1
    #define HOST_INTERRUPT1_MASK_DISP_INT_MASK 0x00000004
    #define HOST_INTERRUPT1_MASK_DISP_INT_SHIFT 2
    #define HOST_INTERRUPT1_MASK_MAD_INT_MASK 0x00000008
    #define HOST_INTERRUPT1_MASK_MAD_INT_SHIFT 3
    #define HOST_INTERRUPT1_MASK_GIC_INT_MASK 0x00000010
    #define HOST_INTERRUPT1_MASK_GIC_INT_SHIFT 4
    #define HOST_INTERRUPT1_MASK_FES_INT_MASK 0x00000020
    #define HOST_INTERRUPT1_MASK_FES_INT_SHIFT 5
    #define HOST_INTERRUPT1_MASK_G2D_INT_MASK 0x00000040
    #define HOST_INTERRUPT1_MASK_G2D_INT_SHIFT 6
    #define HOST_INTERRUPT1_MASK_IRC_INT_MASK 0x00000080
    #define HOST_INTERRUPT1_MASK_IRC_INT_SHIFT 7
    #define HOST_INTERRUPT1_MASK_NRFC_INT_MASK 0x00000100
    #define HOST_INTERRUPT1_MASK_NRFC_INT_SHIFT 8
    #define HOST_INTERRUPT1_MASK_SMCC_INT_MASK 0x00000200
    #define HOST_INTERRUPT1_MASK_SMCC_INT_SHIFT 9
    #define HOST_INTERRUPT1_MASK_MAFE_INT_MASK 0x00000400
    #define HOST_INTERRUPT1_MASK_MAFE_INT_SHIFT 10
    #define HOST_INTERRUPT1_MASK_RMX1_INT_MASK 0x00000800
    #define HOST_INTERRUPT1_MASK_RMX1_INT_SHIFT 11
    #define HOST_INTERRUPT1_MASK_G3D_INT_MASK 0x00001000
    #define HOST_INTERRUPT1_MASK_G3D_INT_SHIFT 12
    #define HOST_INTERRUPT1_MASK_UART0_INT_MASK 0x00002000
    #define HOST_INTERRUPT1_MASK_UART0_INT_SHIFT 13
    #define HOST_INTERRUPT1_MASK_UART1_INT_MASK 0x00004000
    #define HOST_INTERRUPT1_MASK_UART1_INT_SHIFT 14
    #define HOST_INTERRUPT1_MASK_INT15_MASK 0x00008000
    #define HOST_INTERRUPT1_MASK_INT15_SHIFT 15
    #define HOST_INTERRUPT1_MASK_INT16_MASK 0x00010000
    #define HOST_INTERRUPT1_MASK_INT16_SHIFT 16
    #define HOST_INTERRUPT1_MASK_INT17_MASK 0x00020000
    #define HOST_INTERRUPT1_MASK_INT17_SHIFT 17
    #define HOST_INTERRUPT1_MASK_INT18_MASK 0x00040000
    #define HOST_INTERRUPT1_MASK_INT18_SHIFT 18
    #define HOST_INTERRUPT1_MASK_INT19_MASK 0x00080000
    #define HOST_INTERRUPT1_MASK_INT19_SHIFT 19
    #define HOST_INTERRUPT1_MASK_INT20_MASK 0x00100000
    #define HOST_INTERRUPT1_MASK_INT20_SHIFT 20
    #define HOST_INTERRUPT1_MASK_INT21_MASK 0x00200000
    #define HOST_INTERRUPT1_MASK_INT21_SHIFT 21
    #define HOST_INTERRUPT1_MASK_INT22_MASK 0x00400000
    #define HOST_INTERRUPT1_MASK_INT22_SHIFT 22
    #define HOST_INTERRUPT1_MASK_INT23_MASK 0x00800000
    #define HOST_INTERRUPT1_MASK_INT23_SHIFT 23
    #define HOST_INTERRUPT1_MASK_INT24_MASK 0x01000000
    #define HOST_INTERRUPT1_MASK_INT24_SHIFT 24
    #define HOST_INTERRUPT1_MASK_INT25_MASK 0x02000000
    #define HOST_INTERRUPT1_MASK_INT25_SHIFT 25
    #define HOST_INTERRUPT1_MASK_INT26_MASK 0x04000000
    #define HOST_INTERRUPT1_MASK_INT26_SHIFT 26
    #define HOST_INTERRUPT1_MASK_INT27_MASK 0x08000000
    #define HOST_INTERRUPT1_MASK_INT27_SHIFT 27
    #define HOST_INTERRUPT1_MASK_INT28_MASK 0x10000000
    #define HOST_INTERRUPT1_MASK_INT28_SHIFT 28
    #define HOST_INTERRUPT1_MASK_INT29_MASK 0x20000000
    #define HOST_INTERRUPT1_MASK_INT29_SHIFT 29
    #define HOST_INTERRUPT1_MASK_INT30_MASK 0x40000000
    #define HOST_INTERRUPT1_MASK_INT30_SHIFT 30
    #define HOST_INTERRUPT1_MASK_INT31_MASK 0x80000000
    #define HOST_INTERRUPT1_MASK_INT31_SHIFT 31
#define  HOST_INTERRUPT_MASK 0x0418
    #define HOST_INTERRUPT_MASK_TSD_INT0_MASK 0x00000001
    #define HOST_INTERRUPT_MASK_TSD_INT0_SHIFT 0
    #define HOST_INTERRUPT_MASK_TSD_INT1_MASK 0x00000002
    #define HOST_INTERRUPT_MASK_TSD_INT1_SHIFT 1
    #define HOST_INTERRUPT_MASK_USBD_INT_MASK 0x00000004
    #define HOST_INTERRUPT_MASK_USBD_INT_SHIFT 2
    #define HOST_INTERRUPT_MASK_USBH_INT_MASK 0x00000008
    #define HOST_INTERRUPT_MASK_USBH_INT_SHIFT 3
    #define HOST_INTERRUPT_MASK_TSD_INT4_MASK 0x00000010
    #define HOST_INTERRUPT_MASK_TSD_INT4_SHIFT 4
    #define HOST_INTERRUPT_MASK_ETH0_INT_MASK 0x00000020
    #define HOST_INTERRUPT_MASK_ETH0_INT_SHIFT 5
    #define HOST_INTERRUPT_MASK_ETH1_INT_MASK 0x00000040
    #define HOST_INTERRUPT_MASK_ETH1_INT_SHIFT 6
    #define HOST_INTERRUPT_MASK_PPC_INT_MASK 0x00000080
    #define HOST_INTERRUPT_MASK_PPC_INT_SHIFT 7
    #define HOST_INTERRUPT_MASK_DMA_INT_MASK 0x00000100
    #define HOST_INTERRUPT_MASK_DMA_INT_SHIFT 8
    #define HOST_INTERRUPT_MASK_RBM_INT_MASK 0x00000400
    #define HOST_INTERRUPT_MASK_RBM_INT_SHIFT 10
    #define HOST_INTERRUPT_MASK_MPP_INT_MASK 0x00000800
    #define HOST_INTERRUPT_MASK_MPP_INT_SHIFT 11
    #define HOST_INTERRUPT_MASK_RSA_INT_MASK 0x00004000
    #define HOST_INTERRUPT_MASK_RSA_INT_SHIFT 14
    #define HOST_INTERRUPT_MASK_I2S_INT_MASK 0x00008000
    #define HOST_INTERRUPT_MASK_I2S_INT_SHIFT 15
    #define HOST_INTERRUPT_MASK_RMX_INT_MASK 0x00010000
    #define HOST_INTERRUPT_MASK_RMX_INT_SHIFT 16
    #define HOST_INTERRUPT_MASK_VHE_INT_MASK 0x00020000
    #define HOST_INTERRUPT_MASK_VHE_INT_SHIFT 17
    #define HOST_INTERRUPT_MASK_VFE_INT_MASK 0x00040000
    #define HOST_INTERRUPT_MASK_VFE_INT_SHIFT 18
    #define HOST_INTERRUPT_MASK_VNE_INT_MASK 0x00080000
    #define HOST_INTERRUPT_MASK_VNE_INT_SHIFT 19
    #define HOST_INTERRUPT_MASK_GVD_INT_MASK 0x00400000
    #define HOST_INTERRUPT_MASK_GVD_INT_SHIFT 22
    #define HOST_INTERRUPT_MASK_DVE_INT_MASK 0x00800000
    #define HOST_INTERRUPT_MASK_DVE_INT_SHIFT 23
    #define HOST_INTERRUPT_MASK_SATA_INT_MASK 0x01000000
    #define HOST_INTERRUPT_MASK_SATA_INT_SHIFT 24
    #define HOST_INTERRUPT_MASK_I2STX_INT_MASK 0x02000000
    #define HOST_INTERRUPT_MASK_I2STX_INT_SHIFT 25
    #define HOST_INTERRUPT_MASK_SPDIFRX_INT_MASK 0x04000000
    #define HOST_INTERRUPT_MASK_SPDIFRX_INT_SHIFT 26
    #define HOST_INTERRUPT_MASK_SPDIFTX_INT_MASK 0x08000000
    #define HOST_INTERRUPT_MASK_SPDIFTX_INT_SHIFT 27
    #define HOST_INTERRUPT_MASK_EDC_INT_MASK 0x10000000
    #define HOST_INTERRUPT_MASK_EDC_INT_SHIFT 28
    #define HOST_INTERRUPT_MASK_DSCL_INT_MASK 0x20000000
    #define HOST_INTERRUPT_MASK_DSCL_INT_SHIFT 29
    #define HOST_INTERRUPT_MASK_EE_INT_MASK 0x40000000
    #define HOST_INTERRUPT_MASK_EE_INT_SHIFT 30
    #define HOST_INTERRUPT_MASK_NFC_INT_MASK 0x80000000
    #define HOST_INTERRUPT_MASK_NFC_INT_SHIFT 31
#define  HUE_MEM_ARB_CTRL 0x2220
    #define NFC_TIMER_MASK 0x0000000F
    #define NFC_TIMER_SHIFT 0
    #define HUE_MEM_ARB_CTRL_PF_ARB_DIS_MASK 0x00010000
    #define HUE_MEM_ARB_CTRL_PF_ARB_DIS_SHIFT 16
    #define ABS_PRI_MASK 0x00020000
    #define ABS_PRI_SHIFT 17
#define  I2C0_COMMAND 0x100C
    #define I2C0_COMMAND_BYTE_CNT_MASK 0x0000007F
    #define I2C0_COMMAND_BYTE_CNT_SHIFT 0
    #define I2C0_COMMAND_START_EN_MASK 0x00000100
    #define I2C0_COMMAND_START_EN_SHIFT 8
    #define I2C0_COMMAND_STOP_EN_MASK 0x00000200
    #define I2C0_COMMAND_STOP_EN_SHIFT 9
    #define I2C0_COMMAND_WOP_MASK 0x00001000
    #define I2C0_COMMAND_WOP_SHIFT 12
    #define I2C0_COMMAND_SLAVE_ADR_MASK 0x03FF0000
    #define I2C0_COMMAND_SLAVE_ADR_SHIFT 16
    #define I2C0_COMMAND_MSTR_BUSY_MASK 0x10000000
    #define I2C0_COMMAND_MSTR_BUSY_SHIFT 28
    #define I2C0_COMMAND_BUS_BUSY_MASK 0x20000000
    #define I2C0_COMMAND_BUS_BUSY_SHIFT 29
    #define I2C0_COMMAND_ACTIVE_MASK 0x40000000
    #define I2C0_COMMAND_ACTIVE_SHIFT 30
    #define I2C0_COMMAND_ERROR_MASK 0x80000000
    #define I2C0_COMMAND_ERROR_SHIFT 31
#define  I2C0_CONFIG 0x1000
    #define I2C0_CONFIG_ATOMIC_PERIOD_MASK 0x000003FF
    #define I2C0_CONFIG_ATOMIC_PERIOD_SHIFT 0
    #define I2C0_CONFIG_SOLE_MASTER_MASK 0x00000400
    #define I2C0_CONFIG_SOLE_MASTER_SHIFT 10
    #define I2C0_CONFIG_ADR_MODE_MASK 0x00008000
    #define I2C0_CONFIG_ADR_MODE_SHIFT 15
    #define I2C0_CONFIG_TIMEOUT_MASK 0xFFFF0000
    #define I2C0_CONFIG_TIMEOUT_SHIFT 16
#define  I2C0_DATA_LOAD 0x1004
    #define I2C0_DATA_LOAD_PORT_MASK 0xFFFFFFFF
    #define I2C0_DATA_LOAD_PORT_SHIFT 0
#define  I2C0_DATA_READ 0x1008
    #define I2C0_DATA_READ_PORT_MASK 0xFFFFFFFF
    #define I2C0_DATA_READ_PORT_SHIFT 0
#define  I2C1_COMMAND 0x101C
    #define I2C1_COMMAND_BYTE_CNT_MASK 0x0000007F
    #define I2C1_COMMAND_BYTE_CNT_SHIFT 0
    #define I2C1_COMMAND_START_EN_MASK 0x00000100
    #define I2C1_COMMAND_START_EN_SHIFT 8
    #define I2C1_COMMAND_STOP_EN_MASK 0x00000200
    #define I2C1_COMMAND_STOP_EN_SHIFT 9
    #define I2C1_COMMAND_WOP_MASK 0x00001000
    #define I2C1_COMMAND_WOP_SHIFT 12
    #define I2C1_COMMAND_SLAVE_ADR_MASK 0x03FF0000
    #define I2C1_COMMAND_SLAVE_ADR_SHIFT 16
    #define I2C1_COMMAND_MSTR_BUSY_MASK 0x10000000
    #define I2C1_COMMAND_MSTR_BUSY_SHIFT 28
    #define I2C1_COMMAND_BUS_BUSY_MASK 0x20000000
    #define I2C1_COMMAND_BUS_BUSY_SHIFT 29
    #define I2C1_COMMAND_ACTIVE_MASK 0x40000000
    #define I2C1_COMMAND_ACTIVE_SHIFT 30
    #define I2C1_COMMAND_ERROR_MASK 0x80000000
    #define I2C1_COMMAND_ERROR_SHIFT 31
#define  I2C1_CONFIG 0x1010
    #define I2C1_CONFIG_ATOMIC_PERIOD_MASK 0x000003FF
    #define I2C1_CONFIG_ATOMIC_PERIOD_SHIFT 0
    #define I2C1_CONFIG_SOLE_MASTER_MASK 0x00000400
    #define I2C1_CONFIG_SOLE_MASTER_SHIFT 10
    #define I2C1_CONFIG_ADR_MODE_MASK 0x00008000
    #define I2C1_CONFIG_ADR_MODE_SHIFT 15
    #define I2C1_CONFIG_TIMEOUT_MASK 0xFFFF0000
    #define I2C1_CONFIG_TIMEOUT_SHIFT 16
#define  I2C1_DATA_LOAD 0x1014
    #define I2C1_DATA_LOAD_PORT_MASK 0xFFFFFFFF
    #define I2C1_DATA_LOAD_PORT_SHIFT 0
#define  I2C1_DATA_READ 0x1018
    #define I2C1_DATA_READ_PORT_MASK 0xFFFFFFFF
    #define I2C1_DATA_READ_PORT_SHIFT 0
#define  I2C_SLAVE_ADDR_OVERRIDE 0x10A8
    #define I2C_SLAVE_ADDR_OVERRIDE_MASK 0x000003FF
    #define I2C_SLAVE_ADDR_OVERRIDE_SHIFT 0
#define  I2S0_90KHZ_DEN 0x14D8
    #define I2S0_90KHZ_DEN_DEN_MASK 0xFFFFFFFF
    #define I2S0_90KHZ_DEN_DEN_SHIFT 0
#define  I2S0_90KHZ_NUM 0x14D4
    #define I2S0_90KHZ_NUM_NUM_MASK 0xFFFFFFFF
    #define I2S0_90KHZ_NUM_NUM_SHIFT 0
#define  I2S0_CONFIG 0x1430
    #define I2S0_CONFIG_CHANNEL_EN_MASK 0x00000001
    #define I2S0_CONFIG_CHANNEL_EN_SHIFT 0
    #define I2S0_CONFIG_MASTER_EN_MASK 0x00000002
    #define I2S0_CONFIG_MASTER_EN_SHIFT 1
    #define I2S0_CONFIG_WORD_WIDTH_MASK 0x0000000C
    #define I2S0_CONFIG_WORD_WIDTH_SHIFT 2
    #define I2S0_CONFIG_FRAME_SIZE_MASK 0x0000FFF0
    #define I2S0_CONFIG_FRAME_SIZE_SHIFT 4
    #define I2S0_CONFIG_INT_FREQ_MASK 0x003F0000
    #define I2S0_CONFIG_INT_FREQ_SHIFT 16
    #define I2S0_CONFIG_STAMP_FREQ_MASK 0x0FC00000
    #define I2S0_CONFIG_STAMP_FREQ_SHIFT 22
    #define I2S0_CONFIG_PACK_ORDER_MASK 0x10000000
    #define I2S0_CONFIG_PACK_ORDER_SHIFT 28
    #define I2S0_CONFIG_URGENT_LVL_MASK 0x60000000
    #define I2S0_CONFIG_URGENT_LVL_SHIFT 29
    #define I2S0_CONFIG_URGENT_EN_MASK 0x80000000
    #define I2S0_CONFIG_URGENT_EN_SHIFT 31
#define  I2S0_GENLOCK_DEN 0x144C
    #define I2S0_GENLOCK_DEN_DEN_MASK 0xFFFFFFFF
    #define I2S0_GENLOCK_DEN_DEN_SHIFT 0
#define  I2S0_GENLOCK_LOWER 0x1428
    #define I2S0_GENLOCK_LOWER_GENLOCK_L_MASK 0xFFFFFFFF
    #define I2S0_GENLOCK_LOWER_GENLOCK_L_SHIFT 0
#define  I2S0_GENLOCK_NUM 0x142C
    #define I2S0_GENLOCK_NUM_NUM_MASK 0xFFFFFFFF
    #define I2S0_GENLOCK_NUM_NUM_SHIFT 0
#define  I2S0_GENLOCK_UPPER 0x1424
    #define I2S0_GENLOCK_UPPER_GENLOCK_U_MASK 0x000003FF
    #define I2S0_GENLOCK_UPPER_GENLOCK_U_SHIFT 0
#define  I2S0_PCM_BASE 0x1434
    #define I2S0_PCM_BASE_ADR_MASK 0x7FFFFE00
    #define I2S0_PCM_BASE_ADR_SHIFT 9
#define  I2S0_PCM_TOP 0x1438
    #define I2S0_PCM_TOP_ADR_MASK 0x7FFFFE00
    #define I2S0_PCM_TOP_ADR_SHIFT 9
#define  I2S0_TIMESTAMP_BASE 0x143C
    #define I2S0_TIMESTAMP_BASE_ADR_MASK 0x7FFFFE00
    #define I2S0_TIMESTAMP_BASE_ADR_SHIFT 9
#define  I2S0_TIMESTAMP_CTRL 0x1448
    #define I2S0_TIMESTAMP_CTRL_OFFSET_MASK 0xFFFFFFFF
    #define I2S0_TIMESTAMP_CTRL_OFFSET_SHIFT 0
#define  I2S0_TIMESTAMP_SEL 0x14DC
    #define I2S0_TIMESTAMP_SEL_TIMESTAMP_SEL_MASK 0x00000007
    #define I2S0_TIMESTAMP_SEL_TIMESTAMP_SEL_SHIFT 0
#define  I2S0_TIMESTAMP_TOP 0x1440
    #define I2S0_TIMESTAMP_TOP_ADR_MASK 0x7FFFFE00
    #define I2S0_TIMESTAMP_TOP_ADR_SHIFT 9
#define  I2S0_TIMESTAMP_WPTR 0x14B4
    #define I2S0_TIMESTAMP_WPTR_WPTR_MASK 0x7FFFFFF8
    #define I2S0_TIMESTAMP_WPTR_WPTR_SHIFT 3
#define  I2S1_90KHZ_DEN 0x14E4
    #define I2S1_90KHZ_DEN_DEN_MASK 0xFFFFFFFF
    #define I2S1_90KHZ_DEN_DEN_SHIFT 0
#define  I2S1_90KHZ_NUM 0x14E0
    #define I2S1_90KHZ_NUM_NUM_MASK 0xFFFFFFFF
    #define I2S1_90KHZ_NUM_NUM_SHIFT 0
#define  I2S1_CONFIG 0x1450
    #define I2S1_CONFIG_CHANNEL_EN_MASK 0x00000001
    #define I2S1_CONFIG_CHANNEL_EN_SHIFT 0
    #define I2S1_CONFIG_MASTER_EN_MASK 0x00000002
    #define I2S1_CONFIG_MASTER_EN_SHIFT 1
    #define I2S1_CONFIG_WORD_WIDTH_MASK 0x0000000C
    #define I2S1_CONFIG_WORD_WIDTH_SHIFT 2
    #define I2S1_CONFIG_FRAME_SIZE_MASK 0x0000FFF0
    #define I2S1_CONFIG_FRAME_SIZE_SHIFT 4
    #define I2S1_CONFIG_INT_FREQ_MASK 0x003F0000
    #define I2S1_CONFIG_INT_FREQ_SHIFT 16
    #define I2S1_CONFIG_STAMP_FREQ_MASK 0x0FC00000
    #define I2S1_CONFIG_STAMP_FREQ_SHIFT 22
    #define I2S1_CONFIG_PACK_ORDER_MASK 0x10000000
    #define I2S1_CONFIG_PACK_ORDER_SHIFT 28
    #define I2S1_CONFIG_URGENT_LVL_MASK 0x60000000
    #define I2S1_CONFIG_URGENT_LVL_SHIFT 29
    #define I2S1_CONFIG_URGENT_EN_MASK 0x80000000
    #define I2S1_CONFIG_URGENT_EN_SHIFT 31
#define  I2S1_GENLOCK_DEN 0x14AC
    #define I2S1_GENLOCK_DEN_DEN_MASK 0xFFFFFFFF
    #define I2S1_GENLOCK_DEN_DEN_SHIFT 0
#define  I2S1_GENLOCK_LOWER 0x148C
    #define I2S1_GENLOCK_LOWER_GENLOCK_L_MASK 0xFFFFFFFF
    #define I2S1_GENLOCK_LOWER_GENLOCK_L_SHIFT 0
#define  I2S1_GENLOCK_NUM 0x14A8
    #define I2S1_GENLOCK_NUM_NUM_MASK 0xFFFFFFFF
    #define I2S1_GENLOCK_NUM_NUM_SHIFT 0
#define  I2S1_GENLOCK_UPPER 0x1488
    #define I2S1_GENLOCK_UPPER_GENLOCK_U_MASK 0x000003FF
    #define I2S1_GENLOCK_UPPER_GENLOCK_U_SHIFT 0
#define  I2S1_PCM_BASE 0x1454
    #define I2S1_PCM_BASE_ADR_MASK 0x7FFFFE00
    #define I2S1_PCM_BASE_ADR_SHIFT 9
#define  I2S1_PCM_TOP 0x1458
    #define I2S1_PCM_TOP_ADR_MASK 0x7FFFFE00
    #define I2S1_PCM_TOP_ADR_SHIFT 9
#define  I2S1_TIMESTAMP_BASE 0x145C
    #define I2S1_TIMESTAMP_BASE_ADR_MASK 0x7FFFFE00
    #define I2S1_TIMESTAMP_BASE_ADR_SHIFT 9
#define  I2S1_TIMESTAMP_CTRL 0x1464
    #define I2S1_TIMESTAMP_CTRL_OFFSET_MASK 0xFFFFFFFF
    #define I2S1_TIMESTAMP_CTRL_OFFSET_SHIFT 0
#define  I2S1_TIMESTAMP_SEL 0x14E8
    #define I2S1_TIMESTAMP_SEL_TIMESTAMP_SEL_MASK 0x00000007
    #define I2S1_TIMESTAMP_SEL_TIMESTAMP_SEL_SHIFT 0
#define  I2S1_TIMESTAMP_TOP 0x1460
    #define I2S1_TIMESTAMP_TOP_ADR_MASK 0x7FFFFE00
    #define I2S1_TIMESTAMP_TOP_ADR_SHIFT 9
#define  I2S1_TIMESTAMP_WPTR 0x14B8
    #define I2S1_TIMESTAMP_WPTR_WPTR_MASK 0x7FFFFFF8
    #define I2S1_TIMESTAMP_WPTR_WPTR_SHIFT 3
#define  I2S2_CONFIG 0x1470
    #define I2S2_CONFIG_CHANNEL_EN_MASK 0x00000001
    #define I2S2_CONFIG_CHANNEL_EN_SHIFT 0
    #define I2S2_CONFIG_WORD_WIDTH_MASK 0x0000000C
    #define I2S2_CONFIG_WORD_WIDTH_SHIFT 2
    #define I2S2_CONFIG_FRAME_SIZE_MASK 0x0000FFF0
    #define I2S2_CONFIG_FRAME_SIZE_SHIFT 4
    #define I2S2_CONFIG_INT_FREQ_MASK 0x003F0000
    #define I2S2_CONFIG_INT_FREQ_SHIFT 16
    #define I2S2_CONFIG_STAMP_FREQ_MASK 0x0FC00000
    #define I2S2_CONFIG_STAMP_FREQ_SHIFT 22
    #define I2S2_CONFIG_PACK_ORDER_MASK 0x10000000
    #define I2S2_CONFIG_PACK_ORDER_SHIFT 28
    #define I2S2_CONFIG_URGENT_LVL_MASK 0x60000000
    #define I2S2_CONFIG_URGENT_LVL_SHIFT 29
    #define I2S2_CONFIG_URGENT_EN_MASK 0x80000000
    #define I2S2_CONFIG_URGENT_EN_SHIFT 31
#define  I2S2_PCM_BASE 0x1474
    #define I2S2_PCM_BASE_ADR_MASK 0x7FFFFE00
    #define I2S2_PCM_BASE_ADR_SHIFT 9
#define  I2S2_PCM_TOP 0x1478
    #define I2S2_PCM_TOP_ADR_MASK 0x7FFFFE00
    #define I2S2_PCM_TOP_ADR_SHIFT 9
#define  I2S2_TIMESTAMP_BASE 0x147C
    #define I2S2_TIMESTAMP_BASE_ADR_MASK 0x7FFFFE00
    #define I2S2_TIMESTAMP_BASE_ADR_SHIFT 9
#define  I2S2_TIMESTAMP_CTRL 0x1484
    #define I2S2_TIMESTAMP_CTRL_OFFSET_MASK 0xFFFFFFFF
    #define I2S2_TIMESTAMP_CTRL_OFFSET_SHIFT 0
#define  I2S2_TIMESTAMP_TOP 0x1480
    #define I2S2_TIMESTAMP_TOP_ADR_MASK 0x7FFFFE00
    #define I2S2_TIMESTAMP_TOP_ADR_SHIFT 9
#define  I2S2_TIMESTAMP_WPTR 0x14BC
    #define I2S2_TIMESTAMP_WPTR_WPTR_MASK 0x7FFFFFF8
    #define I2S2_TIMESTAMP_WPTR_WPTR_SHIFT 3
#define  I2S3_CONFIG 0x1490
    #define I2S3_CONFIG_CHANNEL_EN_MASK 0x00000001
    #define I2S3_CONFIG_CHANNEL_EN_SHIFT 0
    #define I2S3_CONFIG_WORD_WIDTH_MASK 0x0000000C
    #define I2S3_CONFIG_WORD_WIDTH_SHIFT 2
    #define I2S3_CONFIG_FRAME_SIZE_MASK 0x0000FFF0
    #define I2S3_CONFIG_FRAME_SIZE_SHIFT 4
    #define I2S3_CONFIG_INT_FREQ_MASK 0x003F0000
    #define I2S3_CONFIG_INT_FREQ_SHIFT 16
    #define I2S3_CONFIG_STAMP_FREQ_MASK 0x0FC00000
    #define I2S3_CONFIG_STAMP_FREQ_SHIFT 22
    #define I2S3_CONFIG_PACK_ORDER_MASK 0x10000000
    #define I2S3_CONFIG_PACK_ORDER_SHIFT 28
    #define I2S3_CONFIG_URGENT_LVL_MASK 0x60000000
    #define I2S3_CONFIG_URGENT_LVL_SHIFT 29
    #define I2S3_CONFIG_URGENT_EN_MASK 0x80000000
    #define I2S3_CONFIG_URGENT_EN_SHIFT 31
#define  I2S3_PCM_BASE 0x1494
    #define I2S3_PCM_BASE_ADR_MASK 0x7FFFFE00
    #define I2S3_PCM_BASE_ADR_SHIFT 9
#define  I2S3_PCM_TOP 0x1498
    #define I2S3_PCM_TOP_ADR_MASK 0x7FFFFE00
    #define I2S3_PCM_TOP_ADR_SHIFT 9
#define  I2S3_TIMESTAMP_BASE 0x149C
    #define I2S3_TIMESTAMP_BASE_ADR_MASK 0x7FFFFE00
    #define I2S3_TIMESTAMP_BASE_ADR_SHIFT 9
#define  I2S3_TIMESTAMP_CTRL 0x14A4
    #define I2S3_TIMESTAMP_CTRL_OFFSET_MASK 0xFFFFFFFF
    #define I2S3_TIMESTAMP_CTRL_OFFSET_SHIFT 0
#define  I2S3_TIMESTAMP_TOP 0x14A0
    #define I2S3_TIMESTAMP_TOP_ADR_MASK 0x7FFFFE00
    #define I2S3_TIMESTAMP_TOP_ADR_SHIFT 9
#define  I2S3_TIMESTAMP_WPTR 0x14C0
    #define I2S3_TIMESTAMP_WPTR_WPTR_MASK 0x7FFFFFF8
    #define I2S3_TIMESTAMP_WPTR_WPTR_SHIFT 3
#define  I2S_4CH_EN 0x1468
    #define I2S_4CH_EN_MASK 0x00000001
    #define I2S_4CH_EN_SHIFT 0
#define  I2S_DUMMY_REG 0x14FC
    #define I2S_DUMMY_REG_DUMMY_BITS_MASK 0xFFFFFFFF
    #define I2S_DUMMY_REG_DUMMY_BITS_SHIFT 0
#define  I2S_DYNAMIC_CLOCK_GATE 0x14C4
    #define CLOCK_GATE_EN_MASK 0x00000001
    #define CLOCK_GATE_EN_SHIFT 0
#define  I2S_HOST_INT_ERR_MASK 0x140C
    #define I2S_HOST_INT_ERR_MASK_INT_EN_I2S0_ERR_MASK 0x00000001
    #define I2S_HOST_INT_ERR_MASK_INT_EN_I2S0_ERR_SHIFT 0
    #define I2S_HOST_INT_ERR_MASK_INT_EN_I2S1_ERR_MASK 0x00000002
    #define I2S_HOST_INT_ERR_MASK_INT_EN_I2S1_ERR_SHIFT 1
    #define I2S_HOST_INT_ERR_MASK_INT_EN_I2S2_ERR_MASK 0x00000004
    #define I2S_HOST_INT_ERR_MASK_INT_EN_I2S2_ERR_SHIFT 2
    #define I2S_HOST_INT_ERR_MASK_INT_EN_I2S3_ERR_MASK 0x00000008
    #define I2S_HOST_INT_ERR_MASK_INT_EN_I2S3_ERR_SHIFT 3
#define  I2S_HOST_INT_ERR_STATUS 0x1414
    #define I2S_HOST_INT_ERR_STATUS_I2S0_ERR_MASK 0x00000001
    #define I2S_HOST_INT_ERR_STATUS_I2S0_ERR_SHIFT 0
    #define I2S_HOST_INT_ERR_STATUS_I2S1_ERR_MASK 0x00000002
    #define I2S_HOST_INT_ERR_STATUS_I2S1_ERR_SHIFT 1
    #define I2S_HOST_INT_ERR_STATUS_I2S2_ERR_MASK 0x00000004
    #define I2S_HOST_INT_ERR_STATUS_I2S2_ERR_SHIFT 2
    #define I2S_HOST_INT_ERR_STATUS_I2S3_ERR_MASK 0x00000008
    #define I2S_HOST_INT_ERR_STATUS_I2S3_ERR_SHIFT 3
#define  I2S_HOST_INT_MASK 0x1408
    #define I2S_HOST_INT_MASK_INT_EN_I2S0_INT_MASK 0x00000001
    #define I2S_HOST_INT_MASK_INT_EN_I2S0_INT_SHIFT 0
    #define I2S_HOST_INT_MASK_INT_EN_I2S1_INT_MASK 0x00000002
    #define I2S_HOST_INT_MASK_INT_EN_I2S1_INT_SHIFT 1
    #define I2S_HOST_INT_MASK_INT_EN_I2S2_INT_MASK 0x00000004
    #define I2S_HOST_INT_MASK_INT_EN_I2S2_INT_SHIFT 2
    #define I2S_HOST_INT_MASK_INT_EN_I2S3_INT_MASK 0x00000008
    #define I2S_HOST_INT_MASK_INT_EN_I2S3_INT_SHIFT 3
#define  I2S_HOST_INT_STATUS 0x1410
    #define I2S_HOST_INT_STATUS_I2S0_INT_MASK 0x00000001
    #define I2S_HOST_INT_STATUS_I2S0_INT_SHIFT 0
    #define I2S_HOST_INT_STATUS_I2S1_INT_MASK 0x00000002
    #define I2S_HOST_INT_STATUS_I2S1_INT_SHIFT 1
    #define I2S_HOST_INT_STATUS_I2S2_INT_MASK 0x00000004
    #define I2S_HOST_INT_STATUS_I2S2_INT_SHIFT 2
    #define I2S_HOST_INT_STATUS_I2S3_INT_MASK 0x00000008
    #define I2S_HOST_INT_STATUS_I2S3_INT_SHIFT 3
#define  I2S_MDEBUG_DATA 0x14CC
    #define I2S_MDEBUG_DATA_DEBUG_DATA_MASK 0xFFFFFFFF
    #define I2S_MDEBUG_DATA_DEBUG_DATA_SHIFT 0
#define  I2S_MIPS_INT_ERR_MASK 0x1404
    #define I2S_MIPS_INT_ERR_MASK_INT_EN_I2S0_ERR_MASK 0x00000001
    #define I2S_MIPS_INT_ERR_MASK_INT_EN_I2S0_ERR_SHIFT 0
    #define I2S_MIPS_INT_ERR_MASK_INT_EN_I2S1_ERR_MASK 0x00000002
    #define I2S_MIPS_INT_ERR_MASK_INT_EN_I2S1_ERR_SHIFT 1
    #define I2S_MIPS_INT_ERR_MASK_INT_EN_I2S2_ERR_MASK 0x00000004
    #define I2S_MIPS_INT_ERR_MASK_INT_EN_I2S2_ERR_SHIFT 2
    #define I2S_MIPS_INT_ERR_MASK_INT_EN_I2S3_ERR_MASK 0x00000008
    #define I2S_MIPS_INT_ERR_MASK_INT_EN_I2S3_ERR_SHIFT 3
#define  I2S_MIPS_INT_ERR_STATUS 0x141C
    #define I2S_MIPS_INT_ERR_STATUS_I2S0_ERR_MASK 0x00000001
    #define I2S_MIPS_INT_ERR_STATUS_I2S0_ERR_SHIFT 0
    #define I2S_MIPS_INT_ERR_STATUS_I2S1_ERR_MASK 0x00000002
    #define I2S_MIPS_INT_ERR_STATUS_I2S1_ERR_SHIFT 1
    #define I2S_MIPS_INT_ERR_STATUS_I2S2_ERR_MASK 0x00000004
    #define I2S_MIPS_INT_ERR_STATUS_I2S2_ERR_SHIFT 2
    #define I2S_MIPS_INT_ERR_STATUS_I2S3_ERR_MASK 0x00000008
    #define I2S_MIPS_INT_ERR_STATUS_I2S3_ERR_SHIFT 3
#define  I2S_MIPS_INT_MASK 0x1400
    #define I2S_MIPS_INT_MASK_INT_EN_I2S0_INT_MASK 0x00000001
    #define I2S_MIPS_INT_MASK_INT_EN_I2S0_INT_SHIFT 0
    #define I2S_MIPS_INT_MASK_INT_EN_I2S1_INT_MASK 0x00000002
    #define I2S_MIPS_INT_MASK_INT_EN_I2S1_INT_SHIFT 1
    #define I2S_MIPS_INT_MASK_INT_EN_I2S2_INT_MASK 0x00000004
    #define I2S_MIPS_INT_MASK_INT_EN_I2S2_INT_SHIFT 2
    #define I2S_MIPS_INT_MASK_INT_EN_I2S3_INT_MASK 0x00000008
    #define I2S_MIPS_INT_MASK_INT_EN_I2S3_INT_SHIFT 3
#define  I2S_MIPS_INT_STATUS 0x1418
    #define I2S_MIPS_INT_STATUS_I2S0_INT_MASK 0x00000001
    #define I2S_MIPS_INT_STATUS_I2S0_INT_SHIFT 0
    #define I2S_MIPS_INT_STATUS_I2S1_INT_MASK 0x00000002
    #define I2S_MIPS_INT_STATUS_I2S1_INT_SHIFT 1
    #define I2S_MIPS_INT_STATUS_I2S2_INT_MASK 0x00000004
    #define I2S_MIPS_INT_STATUS_I2S2_INT_SHIFT 2
    #define I2S_MIPS_INT_STATUS_I2S3_INT_MASK 0x00000008
    #define I2S_MIPS_INT_STATUS_I2S3_INT_SHIFT 3
#define  I2S_MSTR_CTRL 0x1420
    #define RATIO_MASK 0x000003FF
    #define RATIO_SHIFT 0
    #define INPUT_LATCH_EN_MASK 0x10000000
    #define INPUT_LATCH_EN_SHIFT 28
    #define XTAL_CLR_MASK 0x20000000
    #define XTAL_CLR_SHIFT 29
    #define XTAL_EN_MASK 0x40000000
    #define XTAL_EN_SHIFT 30
    #define XTAL_DIV_EN_MASK 0x80000000
    #define XTAL_DIV_EN_SHIFT 31
#define  I2S_ODEBUG_DATA 0x14D0
    #define I2S_ODEBUG_DATA_DEBUG_DATA_MASK 0xFFFFFFFF
    #define I2S_ODEBUG_DATA_DEBUG_DATA_SHIFT 0
#define  I2S_SELF_TEST 0x14C8
    #define WORD_SIZE_MASK 0x00000007
    #define WORD_SIZE_SHIFT 0
    #define I2S0_LOOPBACK_ENABLE_MASK 0x00000010
    #define I2S0_LOOPBACK_ENABLE_SHIFT 4
    #define I2S0_LOOPBACK_CTRL_MASK 0x000000E0
    #define I2S0_LOOPBACK_CTRL_SHIFT 5
    #define I2S1_LOOPBACK_ENABLE_MASK 0x00000100
    #define I2S1_LOOPBACK_ENABLE_SHIFT 8
    #define I2S1_LOOPBACK_CTRL_MASK 0x00000E00
    #define I2S1_LOOPBACK_CTRL_SHIFT 9
#define  I2S_SFT_RSTN 0x14B0
    #define I2S0_SFT_RSTN_MASK 0x00000001
    #define I2S0_SFT_RSTN_SHIFT 0
    #define I2S1_SFT_RSTN_MASK 0x00000002
    #define I2S1_SFT_RSTN_SHIFT 1
    #define I2S2_SFT_RSTN_MASK 0x00000004
    #define I2S2_SFT_RSTN_SHIFT 2
    #define I2S3_SFT_RSTN_MASK 0x00000008
    #define I2S3_SFT_RSTN_SHIFT 3
    #define I2S_ALL_SFT_RSTN_MASK 0x00000010
    #define I2S_ALL_SFT_RSTN_SHIFT 4
#define  I2S_TX1_CONFIG 0x1580
    #define I2S_TX1_CONFIG_WORD_WIDTH_MASK 0x00000040
    #define I2S_TX1_CONFIG_WORD_WIDTH_SHIFT 6
    #define I2S_TX1_CONFIG_PACK_ORDER_MASK 0x00000080
    #define I2S_TX1_CONFIG_PACK_ORDER_SHIFT 7
    #define I2S_TX1_CONFIG_ENDIAN_MASK 0x00000100
    #define I2S_TX1_CONFIG_ENDIAN_SHIFT 8
    #define I2S_TX1_CONFIG_FRAME_SIZE_MASK 0x001FFE00
    #define I2S_TX1_CONFIG_FRAME_SIZE_SHIFT 9
    #define I2S_TX1_CONFIG_UF_CTRL_EN_MASK 0x00200000
    #define I2S_TX1_CONFIG_UF_CTRL_EN_SHIFT 21
    #define WS_NEGEDGE_MASK 0x00400000
    #define WS_NEGEDGE_SHIFT 22
    #define I2S_TX1_CONFIG_RESETN_MASK 0x80000000
    #define I2S_TX1_CONFIG_RESETN_SHIFT 31
#define  I2S_TX1_DEBUG_REG 0x15C0
    #define I2S_TX1_DEBUG_REG_DEBUG_DATA_MASK 0xFFFFFFFF
    #define I2S_TX1_DEBUG_REG_DEBUG_DATA_SHIFT 0
#define  I2S_TX1_DEN 0x15B4
    #define I2S_TX1_DEN_DEN_MASK 0xFFFFFFFF
    #define I2S_TX1_DEN_DEN_SHIFT 0
#define  I2S_TX1_DESC_STATUS 0x15A0
    #define I2S_TX1_DESC_STATUS_CURR_FRAME_NUM_MASK 0x000000FF
    #define I2S_TX1_DESC_STATUS_CURR_FRAME_NUM_SHIFT 0
    #define I2S_TX1_DESC_STATUS_FILLED_ENTRIES_MASK 0x00000700
    #define I2S_TX1_DESC_STATUS_FILLED_ENTRIES_SHIFT 8
    #define I2S_TX1_DESC_STATUS_DESC_FULL_MASK 0x40000000
    #define I2S_TX1_DESC_STATUS_DESC_FULL_SHIFT 30
    #define I2S_TX1_DESC_STATUS_DESC_EMPTY_MASK 0x80000000
    #define I2S_TX1_DESC_STATUS_DESC_EMPTY_SHIFT 31
#define  I2S_TX1_DUMMY_REG 0x159C
    #define I2S_TX1_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define I2S_TX1_DUMMY_REG_DATA_SHIFT 0
#define  I2S_TX1_EN 0x1584
    #define I2S_TX1_EN_CHANNEL_EN_MASK 0x00000001
    #define I2S_TX1_EN_CHANNEL_EN_SHIFT 0
#define  I2S_TX1_GENLOCK_LOWER 0x15BC
    #define I2S_TX1_GENLOCK_LOWER_GENLOCK_L_MASK 0xFFFFFFFF
    #define I2S_TX1_GENLOCK_LOWER_GENLOCK_L_SHIFT 0
#define  I2S_TX1_GENLOCK_UPPER 0x15B8
    #define I2S_TX1_GENLOCK_UPPER_GENLOCK_U_MASK 0x000003FF
    #define I2S_TX1_GENLOCK_UPPER_GENLOCK_U_SHIFT 0
#define  I2S_TX1_HOST_INT_MASK 0x1588
    #define I2S_TX1_HOST_INT_MASK_UF_INT_MASK 0x00000001
    #define I2S_TX1_HOST_INT_MASK_UF_INT_SHIFT 0
    #define I2S_TX1_HOST_INT_MASK_INT_MASK 0x00000100
    #define I2S_TX1_HOST_INT_MASK_INT_SHIFT 8
#define  I2S_TX1_INT_STATUS 0x1590
    #define I2S_TX1_INT_STATUS_UF_INT_MASK 0x00000001
    #define I2S_TX1_INT_STATUS_UF_INT_SHIFT 0
    #define I2S_TX1_INT_STATUS_INT_MASK 0x00000100
    #define I2S_TX1_INT_STATUS_INT_SHIFT 8
#define  I2S_TX1_MIPS_INT_MASK 0x158C
    #define I2S_TX1_MIPS_INT_MASK_UF_INT_MASK 0x00000001
    #define I2S_TX1_MIPS_INT_MASK_UF_INT_SHIFT 0
    #define I2S_TX1_MIPS_INT_MASK_INT_MASK 0x00000100
    #define I2S_TX1_MIPS_INT_MASK_INT_SHIFT 8
#define  I2S_TX1_NUM 0x15B0
    #define I2S_TX1_NUM_NUM_MASK 0xFFFFFFFF
    #define I2S_TX1_NUM_NUM_SHIFT 0
#define  I2S_TX1_RD_ADDR 0x15A4
    #define I2S_TX1_RD_ADDR_CURR_RD_ADDR_MASK 0x7FFFFFF0
    #define I2S_TX1_RD_ADDR_CURR_RD_ADDR_SHIFT 4
#define  I2S_TX1_TDES0 0x15A8
    #define I2S_TX1_TDES0_NUM_FRAME_MASK 0x000000FF
    #define I2S_TX1_TDES0_NUM_FRAME_SHIFT 0
    #define I2S_TX1_TDES0_IOC_MASK 0x00008000
    #define I2S_TX1_TDES0_IOC_SHIFT 15
    #define I2S_TX1_TDES0_RDWRN_MASK 0x80000000
    #define I2S_TX1_TDES0_RDWRN_SHIFT 31
#define  I2S_TX1_TDES1 0x15AC
    #define I2S_TX1_TDES1_DATA_BUF_ADDR_MASK 0x7FFFFFE0
    #define I2S_TX1_TDES1_DATA_BUF_ADDR_SHIFT 5
#define  IBB_ADV_PTR 0x0084
    #define IBB_ADV_PTR_NODATA_MASK 0xFFFFFFFF
    #define IBB_ADV_PTR_NODATA_SHIFT 0
#define  IBB_BIT_OFFSET 0x0114
    #define IBB_BIT_OFFSET_OFFSET_MASK 0x0000001F
    #define IBB_BIT_OFFSET_OFFSET_SHIFT 0
#define  IBB_BYTE_ALIGN 0x00D0
    #define IBB_BYTE_ALIGN_DATA_MASK 0xFFFFFFFF
    #define IBB_BYTE_ALIGN_DATA_SHIFT 0
#define  IBB_CTRL 0x0100
    #define LB_LOW_WM_MASK 0x00000003
    #define LB_LOW_WM_SHIFT 0
    #define FETCH_WM_MASK 0x0000003C
    #define FETCH_WM_SHIFT 2
    #define LB_HIGH_WM_MASK 0x000003C0
    #define LB_HIGH_WM_SHIFT 6
    #define IBB_CTRL_MPEG_FRMT_MASK 0x00000C00
    #define IBB_CTRL_MPEG_FRMT_SHIFT 10
    #define INPUT_BIT_SWAP_MASK 0x00001000
    #define INPUT_BIT_SWAP_SHIFT 12
    #define ESC_MASK 0x00002000
    #define ESC_SHIFT 13
    #define IBB_CTRL_BIT_SWAP_MASK 0x00004000
    #define IBB_CTRL_BIT_SWAP_SHIFT 14
    #define DIS_OVERREAD_MASK 0x00008000
    #define DIS_OVERREAD_SHIFT 15
    #define INTRA_VLC_MASK 0x00010000
    #define INTRA_VLC_SHIFT 16
    #define INPUT_CTRL_MASK 0x00020000
    #define INPUT_CTRL_SHIFT 17
    #define IBB_STOP_MASK 0x00040000
    #define IBB_STOP_SHIFT 18
#define  IBB_GET_BITS1 0x0004
    #define IBB_GET_BITS1_DATA_MASK 0x00000001
    #define IBB_GET_BITS1_DATA_SHIFT 0
#define  IBB_GET_BITS10 0x0028
    #define IBB_GET_BITS10_DATA_MASK 0x000003FF
    #define IBB_GET_BITS10_DATA_SHIFT 0
#define  IBB_GET_BITS11 0x002C
    #define IBB_GET_BITS11_DATA_MASK 0x000007FF
    #define IBB_GET_BITS11_DATA_SHIFT 0
#define  IBB_GET_BITS12 0x0030
    #define IBB_GET_BITS12_DATA_MASK 0x00000FFF
    #define IBB_GET_BITS12_DATA_SHIFT 0
#define  IBB_GET_BITS13 0x0034
    #define IBB_GET_BITS13_DATA_MASK 0x00001FFF
    #define IBB_GET_BITS13_DATA_SHIFT 0
#define  IBB_GET_BITS14 0x0038
    #define IBB_GET_BITS14_DATA_MASK 0x00003FFF
    #define IBB_GET_BITS14_DATA_SHIFT 0
#define  IBB_GET_BITS15 0x003C
    #define IBB_GET_BITS15_DATA_MASK 0x00007FFF
    #define IBB_GET_BITS15_DATA_SHIFT 0
#define  IBB_GET_BITS16 0x0040
    #define IBB_GET_BITS16_DATA_MASK 0x0000FFFF
    #define IBB_GET_BITS16_DATA_SHIFT 0
#define  IBB_GET_BITS17 0x0044
    #define IBB_GET_BITS17_DATA_MASK 0x0001FFFF
    #define IBB_GET_BITS17_DATA_SHIFT 0
#define  IBB_GET_BITS18 0x0048
    #define IBB_GET_BITS18_DATA_MASK 0x0003FFFF
    #define IBB_GET_BITS18_DATA_SHIFT 0
#define  IBB_GET_BITS19 0x004C
    #define IBB_GET_BITS19_DATA_MASK 0x0007FFFF
    #define IBB_GET_BITS19_DATA_SHIFT 0
#define  IBB_GET_BITS2 0x0008
    #define IBB_GET_BITS2_DATA_MASK 0x00000003
    #define IBB_GET_BITS2_DATA_SHIFT 0
#define  IBB_GET_BITS20 0x0050
    #define IBB_GET_BITS20_DATA_MASK 0x000FFFFF
    #define IBB_GET_BITS20_DATA_SHIFT 0
#define  IBB_GET_BITS21 0x0054
    #define IBB_GET_BITS21_DATA_MASK 0x001FFFFF
    #define IBB_GET_BITS21_DATA_SHIFT 0
#define  IBB_GET_BITS22 0x0058
    #define IBB_GET_BITS22_DATA_MASK 0x003FFFFF
    #define IBB_GET_BITS22_DATA_SHIFT 0
#define  IBB_GET_BITS23 0x005C
    #define IBB_GET_BITS23_DATA_MASK 0x007FFFFF
    #define IBB_GET_BITS23_DATA_SHIFT 0
#define  IBB_GET_BITS24 0x0060
    #define IBB_GET_BITS24_DATA_MASK 0x00FFFFFF
    #define IBB_GET_BITS24_DATA_SHIFT 0
#define  IBB_GET_BITS25 0x0064
    #define IBB_GET_BITS25_DATA_MASK 0x01FFFFFF
    #define IBB_GET_BITS25_DATA_SHIFT 0
#define  IBB_GET_BITS26 0x0068
    #define IBB_GET_BITS26_DATA_MASK 0x03FFFFFF
    #define IBB_GET_BITS26_DATA_SHIFT 0
#define  IBB_GET_BITS27 0x006C
    #define IBB_GET_BITS27_DATA_MASK 0x07FFFFFF
    #define IBB_GET_BITS27_DATA_SHIFT 0
#define  IBB_GET_BITS28 0x0070
    #define IBB_GET_BITS28_DATA_MASK 0x0FFFFFFF
    #define IBB_GET_BITS28_DATA_SHIFT 0
#define  IBB_GET_BITS29 0x0074
    #define IBB_GET_BITS29_DATA_MASK 0x1FFFFFFF
    #define IBB_GET_BITS29_DATA_SHIFT 0
#define  IBB_GET_BITS3 0x000C
    #define IBB_GET_BITS3_DATA_MASK 0x00000007
    #define IBB_GET_BITS3_DATA_SHIFT 0
#define  IBB_GET_BITS30 0x0078
    #define IBB_GET_BITS30_DATA_MASK 0x3FFFFFFF
    #define IBB_GET_BITS30_DATA_SHIFT 0
#define  IBB_GET_BITS31 0x007C
    #define IBB_GET_BITS31_DATA_MASK 0x7FFFFFFF
    #define IBB_GET_BITS31_DATA_SHIFT 0
#define  IBB_GET_BITS32 0x0080
    #define IBB_GET_BITS32_DATA_MASK 0xFFFFFFFF
    #define IBB_GET_BITS32_DATA_SHIFT 0
#define  IBB_GET_BITS4 0x0010
    #define IBB_GET_BITS4_DATA_MASK 0x0000000F
    #define IBB_GET_BITS4_DATA_SHIFT 0
#define  IBB_GET_BITS5 0x0014
    #define IBB_GET_BITS5_DATA_MASK 0x0000001F
    #define IBB_GET_BITS5_DATA_SHIFT 0
#define  IBB_GET_BITS6 0x0018
    #define IBB_GET_BITS6_DATA_MASK 0x0000003F
    #define IBB_GET_BITS6_DATA_SHIFT 0
#define  IBB_GET_BITS7 0x001C
    #define IBB_GET_BITS7_DATA_MASK 0x0000007F
    #define IBB_GET_BITS7_DATA_SHIFT 0
#define  IBB_GET_BITS8 0x0020
    #define IBB_GET_BITS8_DATA_MASK 0x000000FF
    #define IBB_GET_BITS8_DATA_SHIFT 0
#define  IBB_GET_BITS9 0x0024
    #define IBB_GET_BITS9_DATA_MASK 0x000001FF
    #define IBB_GET_BITS9_DATA_SHIFT 0
#define  IBB_HUFFMAN_B10_GET 0x00B4
    #define IBB_HUFFMAN_B10_GET_DATA_MASK 0xFFFFFFFF
    #define IBB_HUFFMAN_B10_GET_DATA_SHIFT 0
#define  IBB_HUFFMAN_B11_GET 0x00B8
    #define IBB_HUFFMAN_B11_GET_DATA_MASK 0xFFFFFFFF
    #define IBB_HUFFMAN_B11_GET_DATA_SHIFT 0
#define  IBB_HUFFMAN_B12_GET 0x00BC
    #define IBB_HUFFMAN_B12_GET_LEVEL_MASK 0x00007FFF
    #define IBB_HUFFMAN_B12_GET_LEVEL_SHIFT 0
    #define IBB_HUFFMAN_B12_GET_LEVEL_SIGN_MASK 0x00008000
    #define IBB_HUFFMAN_B12_GET_LEVEL_SIGN_SHIFT 15
    #define IBB_HUFFMAN_B12_GET_RUN_MASK 0x007F0000
    #define IBB_HUFFMAN_B12_GET_RUN_SHIFT 16
#define  IBB_HUFFMAN_B13_GET 0x00C0
    #define IBB_HUFFMAN_B13_GET_LEVEL_MASK 0x00007FFF
    #define IBB_HUFFMAN_B13_GET_LEVEL_SHIFT 0
    #define IBB_HUFFMAN_B13_GET_LEVEL_SIGN_MASK 0x00008000
    #define IBB_HUFFMAN_B13_GET_LEVEL_SIGN_SHIFT 15
    #define IBB_HUFFMAN_B13_GET_RUN_MASK 0x007F0000
    #define IBB_HUFFMAN_B13_GET_RUN_SHIFT 16
#define  IBB_HUFFMAN_B14AC_GET 0x00C8
    #define IBB_HUFFMAN_B14AC_GET_LEVEL_MASK 0x00007FFF
    #define IBB_HUFFMAN_B14AC_GET_LEVEL_SHIFT 0
    #define IBB_HUFFMAN_B14AC_GET_LEVEL_SIGN_MASK 0x00008000
    #define IBB_HUFFMAN_B14AC_GET_LEVEL_SIGN_SHIFT 15
    #define IBB_HUFFMAN_B14AC_GET_RUN_MASK 0x007F0000
    #define IBB_HUFFMAN_B14AC_GET_RUN_SHIFT 16
#define  IBB_HUFFMAN_B14DC_GET 0x00C4
    #define IBB_HUFFMAN_B14DC_GET_LEVEL_MASK 0x00007FFF
    #define IBB_HUFFMAN_B14DC_GET_LEVEL_SHIFT 0
    #define IBB_HUFFMAN_B14DC_GET_LEVEL_SIGN_MASK 0x00008000
    #define IBB_HUFFMAN_B14DC_GET_LEVEL_SIGN_SHIFT 15
    #define IBB_HUFFMAN_B14DC_GET_RUN_MASK 0x007F0000
    #define IBB_HUFFMAN_B14DC_GET_RUN_SHIFT 16
#define  IBB_HUFFMAN_B15_GET 0x00CC
    #define IBB_HUFFMAN_B15_GET_DATA_MASK 0xFFFFFFFF
    #define IBB_HUFFMAN_B15_GET_DATA_SHIFT 0
#define  IBB_HUFFMAN_B1_GET 0x0090
    #define IBB_HUFFMAN_B1_GET_LEVEL_MASK 0x00007FFF
    #define IBB_HUFFMAN_B1_GET_LEVEL_SHIFT 0
    #define IBB_HUFFMAN_B1_GET_RUN_MASK 0x007F0000
    #define IBB_HUFFMAN_B1_GET_RUN_SHIFT 16
#define  IBB_HUFFMAN_B2_GET 0x0094
    #define IBB_HUFFMAN_B2_GET_DATA_MASK 0xFFFFFFFF
    #define IBB_HUFFMAN_B2_GET_DATA_SHIFT 0
#define  IBB_HUFFMAN_B3_GET 0x0098
    #define IBB_HUFFMAN_B3_GET_DATA_MASK 0xFFFFFFFF
    #define IBB_HUFFMAN_B3_GET_DATA_SHIFT 0
#define  IBB_HUFFMAN_B4_GET 0x009C
    #define IBB_HUFFMAN_B4_GET_DATA_MASK 0xFFFFFFFF
    #define IBB_HUFFMAN_B4_GET_DATA_SHIFT 0
#define  IBB_HUFFMAN_B5_GET 0x00A0
    #define IBB_HUFFMAN_B5_GET_DATA_MASK 0xFFFFFFFF
    #define IBB_HUFFMAN_B5_GET_DATA_SHIFT 0
#define  IBB_HUFFMAN_B6_GET 0x00A4
    #define IBB_HUFFMAN_B6_GET_DATA_MASK 0xFFFFFFFF
    #define IBB_HUFFMAN_B6_GET_DATA_SHIFT 0
#define  IBB_HUFFMAN_B7_GET 0x00A8
    #define IBB_HUFFMAN_B7_GET_DATA_MASK 0xFFFFFFFF
    #define IBB_HUFFMAN_B7_GET_DATA_SHIFT 0
#define  IBB_HUFFMAN_B8_GET 0x00AC
    #define IBB_HUFFMAN_B8_GET_DATA_MASK 0xFFFFFFFF
    #define IBB_HUFFMAN_B8_GET_DATA_SHIFT 0
#define  IBB_HUFFMAN_B9_GET 0x00B0
    #define IBB_HUFFMAN_B9_GET_DATA_MASK 0xFFFFFFFF
    #define IBB_HUFFMAN_B9_GET_DATA_SHIFT 0
#define  IBB_INT_MASK 0x0124
    #define IBB_INT_MASK_IBB_NOT_READY_MASK 0x00000001
    #define IBB_INT_MASK_IBB_NOT_READY_SHIFT 0
    #define IBB_INT_MASK_IBB_READY_MASK 0x00000002
    #define IBB_INT_MASK_IBB_READY_SHIFT 1
    #define IBB_INT_MASK_HUFFMAN_ERROR_MASK 0x00000004
    #define IBB_INT_MASK_HUFFMAN_ERROR_SHIFT 2
#define  IBB_INT_STATUS 0x0120
    #define IBB_INT_STATUS_IBB_NOT_READY_MASK 0x00000001
    #define IBB_INT_STATUS_IBB_NOT_READY_SHIFT 0
    #define IBB_INT_STATUS_IBB_READY_MASK 0x00000002
    #define IBB_INT_STATUS_IBB_READY_SHIFT 1
    #define IBB_INT_STATUS_HUFFMAN_ERROR_MASK 0x00000004
    #define IBB_INT_STATUS_HUFFMAN_ERROR_SHIFT 2
#define  IBB_MC_PENDING 0x011C
    #define NUMBER_MASK 0x000000FF
    #define NUMBER_SHIFT 0
#define  IBB_RB_ADR 0x0108
    #define IBB_RB_ADR_BASE_MASK 0x0000FFFF
    #define IBB_RB_ADR_BASE_SHIFT 0
    #define TOP_MASK 0xFFFF0000
    #define TOP_SHIFT 16
#define  IBB_RB_HEAD 0x0118
    #define IBB_RB_HEAD_BASE_MASK 0x0FFFFFF0
    #define IBB_RB_HEAD_BASE_SHIFT 4
#define  IBB_RB_TAIL_INI 0x010C
    #define IBB_RB_TAIL_INI_BASE_MASK 0x0FFFFFFC
    #define IBB_RB_TAIL_INI_BASE_SHIFT 2
#define  IBB_RB_TAIL_READ 0x0110
    #define IBB_RB_TAIL_READ_BASE_MASK 0x0FFFFFFC
    #define IBB_RB_TAIL_READ_BASE_SHIFT 2
#define  IBB_SHOW_BITS32 0x0000
    #define IBB_SHOW_BITS32_DATA_MASK 0xFFFFFFFF
    #define IBB_SHOW_BITS32_DATA_SHIFT 0
#define  IBB_STATUS 0x0104
    #define LB_CNT_MASK 0x000001FF
    #define LB_CNT_SHIFT 0
    #define IBB_MC_PENDING_MASK 0x10000000
    #define IBB_MC_PENDING_SHIFT 28
    #define HUFMAN_ERR_MASK 0x20000000
    #define HUFMAN_ERR_SHIFT 29
    #define READY_MASK 0x40000000
    #define READY_SHIFT 30
    #define NOT_READY_MASK 0x80000000
    #define NOT_READY_SHIFT 31
#define  IDCT_CTRL 0x7304
    #define IDCT_DCT_TYPE_MASK 0x00000001
    #define IDCT_DCT_TYPE_SHIFT 0
    #define IDCT_OUT_ORDER_MASK 0x00000002
    #define IDCT_OUT_ORDER_SHIFT 1
    #define IDCT_CTRL_MB_PATTERN_MASK 0x000000FC
    #define IDCT_CTRL_MB_PATTERN_SHIFT 2
    #define IDCT_CTRL_QSCALE_MASK 0x00007F00
    #define IDCT_CTRL_QSCALE_SHIFT 8
    #define IDCT_CTRL_MB_TYPE_MASK 0x40000000
    #define IDCT_CTRL_MB_TYPE_SHIFT 30
    #define RESET_DCPRED_MASK 0x80000000
    #define RESET_DCPRED_SHIFT 31
#define  IDQS_CLK_CTRL 0x74C0
    #define IDQS_ECLK_GATE_EN_MASK 0x00000001
    #define IDQS_ECLK_GATE_EN_SHIFT 0
    #define IDQS_MCLK_GATE_EN_MASK 0x00000002
    #define IDQS_MCLK_GATE_EN_SHIFT 1
    #define IDQS_CLK_CTRL_XCODE_ECLK_GATE_EN_MASK 0x00000004
    #define IDQS_CLK_CTRL_XCODE_ECLK_GATE_EN_SHIFT 2
    #define XCODE_MCLK_GATE_EN_MASK 0x00000008
    #define XCODE_MCLK_GATE_EN_SHIFT 3
#define  IDQS_DUMMY_REG 0x72D4
    #define IDQS_DUMMY_REG_DUMMY_MASK 0xFFFFFFFF
    #define IDQS_DUMMY_REG_DUMMY_SHIFT 0
#define  IDQS_SCL_SPRAM_RM 0x72E4
    #define SPRAM_RM_MASK 0x0000000F
    #define SPRAM_RM_SHIFT 0
#define  IDQS_STAT_MUX 0x7268
    #define IDQS_STAT_MUX_STAT_MUX_MASK 0x0000001F
    #define IDQS_STAT_MUX_STAT_MUX_SHIFT 0
#define  IDQS_STAT_MUX_RB 0x7264
    #define IDQS_STAT_MUX_RB_STAT_RB_MASK 0xFFFFFFFF
    #define IDQS_STAT_MUX_RB_STAT_RB_SHIFT 0
#define  INDIRECT_IO_DATA 0x0004
    #define INDIRECT_IO_DATA_DATA_MASK 0xFFFFFFFF
    #define INDIRECT_IO_DATA_DATA_SHIFT 0
#define  INDIRECT_IO_INDEX 0x0000
    #define INDIRECT_IO_INDEX_DATA_MASK 0x0000FFFF
    #define INDIRECT_IO_INDEX_DATA_SHIFT 0
#define  LP_FILTER_BYPASS 0x111C
    #define I2C0_MASTER_FILTER_BYPASS_MASK 0x00000001
    #define I2C0_MASTER_FILTER_BYPASS_SHIFT 0
    #define I2C1_MASTER_FILTER_BYPASS_MASK 0x00000002
    #define I2C1_MASTER_FILTER_BYPASS_SHIFT 1
    #define I2C_SLAVE_FILTER_BYPASS_MASK 0x00000004
    #define I2C_SLAVE_FILTER_BYPASS_SHIFT 2
#define  MBD0_CQA_ADR 0xA124
    #define MBD0_CQA_ADR_BASE_MASK 0x07FFFFFE
    #define MBD0_CQA_ADR_BASE_SHIFT 1
#define  MBD0_INFO 0xA178
    #define MBD0_INFO_MB_TYPE_MASK 0x0000000F
    #define MBD0_INFO_MB_TYPE_SHIFT 0
    #define MBD0_INFO_MO_TYPE_MASK 0x00000030
    #define MBD0_INFO_MO_TYPE_SHIFT 4
    #define MBD0_INFO_DCT_TYPE_MASK 0x00000040
    #define MBD0_INFO_DCT_TYPE_SHIFT 6
    #define MBD0_INFO_MB_PATTERN_MASK 0x00003F00
    #define MBD0_INFO_MB_PATTERN_SHIFT 8
    #define MBD0_INFO_QSCALE_MASK 0x007F0000
    #define MBD0_INFO_QSCALE_SHIFT 16
#define  MBD0_SLICE_QSCALE 0xA16C
    #define MBD0_SLICE_QSCALE_QSCALE_MASK 0x0000007F
    #define MBD0_SLICE_QSCALE_QSCALE_SHIFT 0
#define  MBD0_STATUS 0xA174
    #define MBD0_STATUS_DONE_MASK 0x00000001
    #define MBD0_STATUS_DONE_SHIFT 0
    #define MBD0_STATUS_DIP_END_MASK 0x07FFFFFC
    #define MBD0_STATUS_DIP_END_SHIFT 2
    #define MBD0_STATUS_ERROR_MASK 0xF0000000
    #define MBD0_STATUS_ERROR_SHIFT 28
#define  MBD0_TRIG 0xA170
    #define MBD0_TRIG_SKIP_MB_CNT_MASK 0x0000007F
    #define MBD0_TRIG_SKIP_MB_CNT_SHIFT 0
    #define MBD0_TRIG_MB_IDX_X_MASK 0x007F0000
    #define MBD0_TRIG_MB_IDX_X_SHIFT 16
    #define MBD0_TRIG_MB_IDX_Y_MASK 0x7F000000
    #define MBD0_TRIG_MB_IDX_Y_SHIFT 24
#define  MBD1_CQA_ADR 0xA524
    #define MBD1_CQA_ADR_BASE_MASK 0x07FFFFFE
    #define MBD1_CQA_ADR_BASE_SHIFT 1
#define  MBD1_INFO 0xA578
    #define MBD1_INFO_MB_TYPE_MASK 0x0000000F
    #define MBD1_INFO_MB_TYPE_SHIFT 0
    #define MBD1_INFO_MO_TYPE_MASK 0x00000030
    #define MBD1_INFO_MO_TYPE_SHIFT 4
    #define MBD1_INFO_DCT_TYPE_MASK 0x00000040
    #define MBD1_INFO_DCT_TYPE_SHIFT 6
    #define MBD1_INFO_MB_PATTERN_MASK 0x00003F00
    #define MBD1_INFO_MB_PATTERN_SHIFT 8
    #define MBD1_INFO_QSCALE_MASK 0x007F0000
    #define MBD1_INFO_QSCALE_SHIFT 16
#define  MBD1_SLICE_QSCALE 0xA56C
    #define MBD1_SLICE_QSCALE_QSCALE_MASK 0x0000007F
    #define MBD1_SLICE_QSCALE_QSCALE_SHIFT 0
#define  MBD1_STATUS 0xA574
    #define MBD1_STATUS_DONE_MASK 0x00000001
    #define MBD1_STATUS_DONE_SHIFT 0
    #define MBD1_STATUS_DIP_END_MASK 0x07FFFFFC
    #define MBD1_STATUS_DIP_END_SHIFT 2
    #define MBD1_STATUS_ERROR_MASK 0xF0000000
    #define MBD1_STATUS_ERROR_SHIFT 28
#define  MBD1_TRIG 0xA570
    #define MBD1_TRIG_SKIP_MB_CNT_MASK 0x0000007F
    #define MBD1_TRIG_SKIP_MB_CNT_SHIFT 0
    #define MBD1_TRIG_MB_IDX_X_MASK 0x007F0000
    #define MBD1_TRIG_MB_IDX_X_SHIFT 16
    #define MBD1_TRIG_MB_IDX_Y_MASK 0x7F000000
    #define MBD1_TRIG_MB_IDX_Y_SHIFT 24
#define  MC_CH0_ARB_CTRLA 0x9130
    #define MC_CH0_ARB_CTRLA_CL0_TIMER_MASK 0x0000000F
    #define MC_CH0_ARB_CTRLA_CL0_TIMER_SHIFT 0
    #define MC_CH0_ARB_CTRLA_CL1_TIMER_MASK 0x000000F0
    #define MC_CH0_ARB_CTRLA_CL1_TIMER_SHIFT 4
    #define MC_CH0_ARB_CTRLA_CL2_TIMER_MASK 0x00000F00
    #define MC_CH0_ARB_CTRLA_CL2_TIMER_SHIFT 8
    #define MC_CH0_ARB_CTRLA_CL3_TIMER_MASK 0x0000F000
    #define MC_CH0_ARB_CTRLA_CL3_TIMER_SHIFT 12
    #define MC_CH0_ARB_CTRLA_CL4_TIMER_MASK 0x000F0000
    #define MC_CH0_ARB_CTRLA_CL4_TIMER_SHIFT 16
    #define MC_CH0_ARB_CTRLA_CL5_TIMER_MASK 0x00F00000
    #define MC_CH0_ARB_CTRLA_CL5_TIMER_SHIFT 20
    #define MC_CH0_ARB_CTRLA_CL6_TIMER_MASK 0x0F000000
    #define MC_CH0_ARB_CTRLA_CL6_TIMER_SHIFT 24
    #define MC_CH0_ARB_CTRLA_CL7_TIMER_MASK 0xF0000000
    #define MC_CH0_ARB_CTRLA_CL7_TIMER_SHIFT 28
#define  MC_CH0_ARB_CTRLB 0x9134
    #define MC_CH0_ARB_CTRLB_CL8_TIMER_MASK 0x0000000F
    #define MC_CH0_ARB_CTRLB_CL8_TIMER_SHIFT 0
    #define MC_CH0_ARB_CTRLB_CL9_TIMER_MASK 0x000000F0
    #define MC_CH0_ARB_CTRLB_CL9_TIMER_SHIFT 4
    #define MC_CH0_ARB_CTRLB_CL10_TIMER_MASK 0x00000F00
    #define MC_CH0_ARB_CTRLB_CL10_TIMER_SHIFT 8
    #define MC_CH0_ARB_CTRLB_CL11_TIMER_MASK 0x0000F000
    #define MC_CH0_ARB_CTRLB_CL11_TIMER_SHIFT 12
    #define MC_CH0_ARB_CTRLB_CL12_TIMER_MASK 0x000F0000
    #define MC_CH0_ARB_CTRLB_CL12_TIMER_SHIFT 16
    #define MC_CH0_ARB_CTRLB_CL13_TIMER_MASK 0x00F00000
    #define MC_CH0_ARB_CTRLB_CL13_TIMER_SHIFT 20
    #define MC_CH0_ARB_CTRLB_CL14_TIMER_MASK 0x0F000000
    #define MC_CH0_ARB_CTRLB_CL14_TIMER_SHIFT 24
    #define MC_CH0_ARB_CTRLB_CL15_TIMER_MASK 0xF0000000
    #define MC_CH0_ARB_CTRLB_CL15_TIMER_SHIFT 28
#define  MC_CH0_ARB_CTRLC 0x9138
    #define MC_CH0_ARB_CTRLC_CL16_TIMER_MASK 0x0000000F
    #define MC_CH0_ARB_CTRLC_CL16_TIMER_SHIFT 0
#define  MC_CH0_ARB_LATENCY_TIMER_CTRLA 0x9150
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLA_CL0_LATENCY_TIMER_MASK 0x000000FF
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLA_CL0_LATENCY_TIMER_SHIFT 0
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLA_CL1_LATENCY_TIMER_MASK 0x0000FF00
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLA_CL1_LATENCY_TIMER_SHIFT 8
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLA_CL2_LATENCY_TIMER_MASK 0x00FF0000
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLA_CL2_LATENCY_TIMER_SHIFT 16
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLA_CL3_LATENCY_TIMER_MASK 0xFF000000
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLA_CL3_LATENCY_TIMER_SHIFT 24
#define  MC_CH0_ARB_LATENCY_TIMER_CTRLB 0x9154
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLB_CL4_LATENCY_TIMER_MASK 0x000000FF
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLB_CL4_LATENCY_TIMER_SHIFT 0
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLB_CL5_LATENCY_TIMER_MASK 0x0000FF00
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLB_CL5_LATENCY_TIMER_SHIFT 8
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLB_CL6_LATENCY_TIMER_MASK 0x00FF0000
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLB_CL6_LATENCY_TIMER_SHIFT 16
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLB_CL7_LATENCY_TIMER_MASK 0xFF000000
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLB_CL7_LATENCY_TIMER_SHIFT 24
#define  MC_CH0_ARB_LATENCY_TIMER_CTRLC 0x9158
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLC_CL8_LATENCY_TIMER_MASK 0x000000FF
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLC_CL8_LATENCY_TIMER_SHIFT 0
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLC_CL9_LATENCY_TIMER_MASK 0x0000FF00
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLC_CL9_LATENCY_TIMER_SHIFT 8
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLC_CL10_LATENCY_TIMER_MASK 0x00FF0000
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLC_CL10_LATENCY_TIMER_SHIFT 16
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLC_CL11_LATENCY_TIMER_MASK 0xFF000000
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLC_CL11_LATENCY_TIMER_SHIFT 24
#define  MC_CH0_ARB_LATENCY_TIMER_CTRLD 0x915C
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLD_CL12_LATENCY_TIMER_MASK 0x000000FF
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLD_CL12_LATENCY_TIMER_SHIFT 0
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLD_CL13_LATENCY_TIMER_MASK 0x0000FF00
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLD_CL13_LATENCY_TIMER_SHIFT 8
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLD_CL14_LATENCY_TIMER_MASK 0x00FF0000
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLD_CL14_LATENCY_TIMER_SHIFT 16
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLD_CL15_LATENCY_TIMER_MASK 0xFF000000
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLD_CL15_LATENCY_TIMER_SHIFT 24
#define  MC_CH0_ARB_LATENCY_TIMER_CTRLE 0x9160
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLE_CL16_LATENCY_TIMER_MASK 0x000000FF
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLE_CL16_LATENCY_TIMER_SHIFT 0
#define  MC_CH0_ARB_MAIN_CTRL 0x9170
    #define MC_CH0_ARB_MAIN_CTRL_CLI_URGENT_SET_MASK 0x0001FFFF
    #define MC_CH0_ARB_MAIN_CTRL_CLI_URGENT_SET_SHIFT 0
    #define MC_CH0_ARB_MAIN_CTRL_LVL1_PRI_DIS_MASK 0x10000000
    #define MC_CH0_ARB_MAIN_CTRL_LVL1_PRI_DIS_SHIFT 28
    #define MC_CH0_ARB_MAIN_CTRL_URG_PRI_DIS_MASK 0x20000000
    #define MC_CH0_ARB_MAIN_CTRL_URG_PRI_DIS_SHIFT 29
    #define MC_CH0_ARB_MAIN_CTRL_LAT_PRI_DIS_MASK 0x40000000
    #define MC_CH0_ARB_MAIN_CTRL_LAT_PRI_DIS_SHIFT 30
    #define MC_CH0_ARB_MAIN_CTRL_ALT_PRI_DIS_MASK 0x80000000
    #define MC_CH0_ARB_MAIN_CTRL_ALT_PRI_DIS_SHIFT 31
#define  MC_CH0_ARB_PAGE_TIMER_CTRLA 0x9140
    #define MC_CH0_ARB_PAGE_TIMER_CTRLA_CL0_PAGE_TIMER_MASK 0x0000000F
    #define MC_CH0_ARB_PAGE_TIMER_CTRLA_CL0_PAGE_TIMER_SHIFT 0
    #define MC_CH0_ARB_PAGE_TIMER_CTRLA_CL1_PAGE_TIMER_MASK 0x000000F0
    #define MC_CH0_ARB_PAGE_TIMER_CTRLA_CL1_PAGE_TIMER_SHIFT 4
    #define MC_CH0_ARB_PAGE_TIMER_CTRLA_CL2_PAGE_TIMER_MASK 0x00000F00
    #define MC_CH0_ARB_PAGE_TIMER_CTRLA_CL2_PAGE_TIMER_SHIFT 8
    #define MC_CH0_ARB_PAGE_TIMER_CTRLA_CL3_PAGE_TIMER_MASK 0x0000F000
    #define MC_CH0_ARB_PAGE_TIMER_CTRLA_CL3_PAGE_TIMER_SHIFT 12
    #define MC_CH0_ARB_PAGE_TIMER_CTRLA_CL4_PAGE_TIMER_MASK 0x000F0000
    #define MC_CH0_ARB_PAGE_TIMER_CTRLA_CL4_PAGE_TIMER_SHIFT 16
    #define MC_CH0_ARB_PAGE_TIMER_CTRLA_CL5_PAGE_TIMER_MASK 0x00F00000
    #define MC_CH0_ARB_PAGE_TIMER_CTRLA_CL5_PAGE_TIMER_SHIFT 20
    #define MC_CH0_ARB_PAGE_TIMER_CTRLA_CL6_PAGE_TIMER_MASK 0x0F000000
    #define MC_CH0_ARB_PAGE_TIMER_CTRLA_CL6_PAGE_TIMER_SHIFT 24
    #define MC_CH0_ARB_PAGE_TIMER_CTRLA_CL7_PAGE_TIMER_MASK 0xF0000000
    #define MC_CH0_ARB_PAGE_TIMER_CTRLA_CL7_PAGE_TIMER_SHIFT 28
#define  MC_CH0_ARB_PAGE_TIMER_CTRLB 0x9144
    #define MC_CH0_ARB_PAGE_TIMER_CTRLB_CL8_PAGE_TIMER_MASK 0x0000000F
    #define MC_CH0_ARB_PAGE_TIMER_CTRLB_CL8_PAGE_TIMER_SHIFT 0
    #define MC_CH0_ARB_PAGE_TIMER_CTRLB_CL9_PAGE_TIMER_MASK 0x000000F0
    #define MC_CH0_ARB_PAGE_TIMER_CTRLB_CL9_PAGE_TIMER_SHIFT 4
    #define MC_CH0_ARB_PAGE_TIMER_CTRLB_CL10_PAGE_TIMER_MASK 0x00000F00
    #define MC_CH0_ARB_PAGE_TIMER_CTRLB_CL10_PAGE_TIMER_SHIFT 8
    #define MC_CH0_ARB_PAGE_TIMER_CTRLB_CL11_PAGE_TIMER_MASK 0x0000F000
    #define MC_CH0_ARB_PAGE_TIMER_CTRLB_CL11_PAGE_TIMER_SHIFT 12
    #define MC_CH0_ARB_PAGE_TIMER_CTRLB_CL12_PAGE_TIMER_MASK 0x000F0000
    #define MC_CH0_ARB_PAGE_TIMER_CTRLB_CL12_PAGE_TIMER_SHIFT 16
    #define MC_CH0_ARB_PAGE_TIMER_CTRLB_CL13_PAGE_TIMER_MASK 0x00F00000
    #define MC_CH0_ARB_PAGE_TIMER_CTRLB_CL13_PAGE_TIMER_SHIFT 20
    #define MC_CH0_ARB_PAGE_TIMER_CTRLB_CL14_PAGE_TIMER_MASK 0x0F000000
    #define MC_CH0_ARB_PAGE_TIMER_CTRLB_CL14_PAGE_TIMER_SHIFT 24
    #define MC_CH0_ARB_PAGE_TIMER_CTRLB_CL15_PAGE_TIMER_MASK 0xF0000000
    #define MC_CH0_ARB_PAGE_TIMER_CTRLB_CL15_PAGE_TIMER_SHIFT 28
#define  MC_CH0_ARB_PAGE_TIMER_CTRLC 0x9148
    #define MC_CH0_ARB_PAGE_TIMER_CTRLC_CL16_PAGE_TIMER_MASK 0x0000000F
    #define MC_CH0_ARB_PAGE_TIMER_CTRLC_CL16_PAGE_TIMER_SHIFT 0
#define  MC_CH0_ARB_PRIORITY_CTRLA 0x9174
    #define MC_CH0_ARB_PRIORITY_CTRLA_CL_DISABLE_LAT_PRIORITY_MASK 0x0001FFFF
    #define MC_CH0_ARB_PRIORITY_CTRLA_CL_DISABLE_LAT_PRIORITY_SHIFT 0
#define  MC_CH0_ARB_PRIORITY_CTRLB 0x9178
    #define MC_CH0_ARB_PRIORITY_CTRLB_CL_DISABLE_URG_PRIORITY_MASK 0x0001FFFF
    #define MC_CH0_ARB_PRIORITY_CTRLB_CL_DISABLE_URG_PRIORITY_SHIFT 0
#define  MC_CH0_ARB_PRIORITY_CTRLC 0x917C
    #define MC_CH0_ARB_PRIORITY_CTRLC_CL_DISABLE_PF_PENALTY_MASK 0x0001FFFF
    #define MC_CH0_ARB_PRIORITY_CTRLC_CL_DISABLE_PF_PENALTY_SHIFT 0
#define  MC_CH0_ARB_PRIORITY_CTRLD 0x9180
    #define MC_CH0_ARB_PRIORITY_CTRLD_CL_DISABLE_RW_PENALTY_MASK 0x0001FFFF
    #define MC_CH0_ARB_PRIORITY_CTRLD_CL_DISABLE_RW_PENALTY_SHIFT 0
#define  MC_CH0_LOCK_EN 0x9110
    #define MC_CH0_LOCK_EN_LOCK_CL_ID_MASK 0x0001FFFF
    #define MC_CH0_LOCK_EN_LOCK_CL_ID_SHIFT 0
#define  MC_CH0_MEM_CONFIG 0x9100
    #define MC_CH0_MEM_CONFIG_BANKPINS_MASK 0x00000003
    #define MC_CH0_MEM_CONFIG_BANKPINS_SHIFT 0
    #define MC_CH0_MEM_CONFIG_ADDRPINS_MASK 0x0000007C
    #define MC_CH0_MEM_CONFIG_ADDRPINS_SHIFT 2
    #define MC_CH0_MEM_CONFIG_COLCOUNT_MASK 0x00000F80
    #define MC_CH0_MEM_CONFIG_COLCOUNT_SHIFT 7
    #define MC_CH0_MEM_CONFIG_ROWBANKCOL_MASK 0x00001000
    #define MC_CH0_MEM_CONFIG_ROWBANKCOL_SHIFT 12
    #define MC_CH0_MEM_CONFIG_EXTMEMSIZE_MASK 0x00006000
    #define MC_CH0_MEM_CONFIG_EXTMEMSIZE_SHIFT 13
#define  MC_CH0_MISC_REG 0x9104
    #define MC_CH0_MISC_REG_MRLOGIC_RSTN_MASK 0x00000001
    #define MC_CH0_MISC_REG_MRLOGIC_RSTN_SHIFT 0
#define  MC_CH1_ARB_CTRLA 0x9230
    #define MC_CH1_ARB_CTRLA_CL0_TIMER_MASK 0x0000000F
    #define MC_CH1_ARB_CTRLA_CL0_TIMER_SHIFT 0
    #define MC_CH1_ARB_CTRLA_CL1_TIMER_MASK 0x000000F0
    #define MC_CH1_ARB_CTRLA_CL1_TIMER_SHIFT 4
    #define MC_CH1_ARB_CTRLA_CL2_TIMER_MASK 0x00000F00
    #define MC_CH1_ARB_CTRLA_CL2_TIMER_SHIFT 8
    #define MC_CH1_ARB_CTRLA_CL3_TIMER_MASK 0x0000F000
    #define MC_CH1_ARB_CTRLA_CL3_TIMER_SHIFT 12
    #define MC_CH1_ARB_CTRLA_CL4_TIMER_MASK 0x000F0000
    #define MC_CH1_ARB_CTRLA_CL4_TIMER_SHIFT 16
    #define MC_CH1_ARB_CTRLA_CL5_TIMER_MASK 0x00F00000
    #define MC_CH1_ARB_CTRLA_CL5_TIMER_SHIFT 20
    #define MC_CH1_ARB_CTRLA_CL6_TIMER_MASK 0x0F000000
    #define MC_CH1_ARB_CTRLA_CL6_TIMER_SHIFT 24
    #define MC_CH1_ARB_CTRLA_CL7_TIMER_MASK 0xF0000000
    #define MC_CH1_ARB_CTRLA_CL7_TIMER_SHIFT 28
#define  MC_CH1_ARB_CTRLB 0x9234
    #define MC_CH1_ARB_CTRLB_CL8_TIMER_MASK 0x0000000F
    #define MC_CH1_ARB_CTRLB_CL8_TIMER_SHIFT 0
    #define MC_CH1_ARB_CTRLB_CL9_TIMER_MASK 0x000000F0
    #define MC_CH1_ARB_CTRLB_CL9_TIMER_SHIFT 4
    #define MC_CH1_ARB_CTRLB_CL10_TIMER_MASK 0x00000F00
    #define MC_CH1_ARB_CTRLB_CL10_TIMER_SHIFT 8
    #define MC_CH1_ARB_CTRLB_CL11_TIMER_MASK 0x0000F000
    #define MC_CH1_ARB_CTRLB_CL11_TIMER_SHIFT 12
    #define MC_CH1_ARB_CTRLB_CL12_TIMER_MASK 0x000F0000
    #define MC_CH1_ARB_CTRLB_CL12_TIMER_SHIFT 16
    #define MC_CH1_ARB_CTRLB_CL13_TIMER_MASK 0x00F00000
    #define MC_CH1_ARB_CTRLB_CL13_TIMER_SHIFT 20
    #define MC_CH1_ARB_CTRLB_CL14_TIMER_MASK 0x0F000000
    #define MC_CH1_ARB_CTRLB_CL14_TIMER_SHIFT 24
    #define MC_CH1_ARB_CTRLB_CL15_TIMER_MASK 0xF0000000
    #define MC_CH1_ARB_CTRLB_CL15_TIMER_SHIFT 28
#define  MC_CH1_ARB_CTRLC 0x9238
    #define MC_CH1_ARB_CTRLC_CL16_TIMER_MASK 0x0000000F
    #define MC_CH1_ARB_CTRLC_CL16_TIMER_SHIFT 0
#define  MC_CH1_ARB_LATENCY_TIMER_CTRLA 0x9250
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLA_CL0_LATENCY_TIMER_MASK 0x000000FF
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLA_CL0_LATENCY_TIMER_SHIFT 0
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLA_CL1_LATENCY_TIMER_MASK 0x0000FF00
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLA_CL1_LATENCY_TIMER_SHIFT 8
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLA_CL2_LATENCY_TIMER_MASK 0x00FF0000
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLA_CL2_LATENCY_TIMER_SHIFT 16
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLA_CL3_LATENCY_TIMER_MASK 0xFF000000
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLA_CL3_LATENCY_TIMER_SHIFT 24
#define  MC_CH1_ARB_LATENCY_TIMER_CTRLB 0x9254
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLB_CL4_LATENCY_TIMER_MASK 0x000000FF
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLB_CL4_LATENCY_TIMER_SHIFT 0
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLB_CL5_LATENCY_TIMER_MASK 0x0000FF00
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLB_CL5_LATENCY_TIMER_SHIFT 8
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLB_CL6_LATENCY_TIMER_MASK 0x00FF0000
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLB_CL6_LATENCY_TIMER_SHIFT 16
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLB_CL7_LATENCY_TIMER_MASK 0xFF000000
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLB_CL7_LATENCY_TIMER_SHIFT 24
#define  MC_CH1_ARB_LATENCY_TIMER_CTRLC 0x9258
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLC_CL8_LATENCY_TIMER_MASK 0x000000FF
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLC_CL8_LATENCY_TIMER_SHIFT 0
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLC_CL9_LATENCY_TIMER_MASK 0x0000FF00
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLC_CL9_LATENCY_TIMER_SHIFT 8
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLC_CL10_LATENCY_TIMER_MASK 0x00FF0000
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLC_CL10_LATENCY_TIMER_SHIFT 16
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLC_CL11_LATENCY_TIMER_MASK 0xFF000000
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLC_CL11_LATENCY_TIMER_SHIFT 24
#define  MC_CH1_ARB_LATENCY_TIMER_CTRLD 0x925C
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLD_CL12_LATENCY_TIMER_MASK 0x000000FF
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLD_CL12_LATENCY_TIMER_SHIFT 0
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLD_CL13_LATENCY_TIMER_MASK 0x0000FF00
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLD_CL13_LATENCY_TIMER_SHIFT 8
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLD_CL14_LATENCY_TIMER_MASK 0x00FF0000
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLD_CL14_LATENCY_TIMER_SHIFT 16
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLD_CL15_LATENCY_TIMER_MASK 0xFF000000
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLD_CL15_LATENCY_TIMER_SHIFT 24
#define  MC_CH1_ARB_LATENCY_TIMER_CTRLE 0x9260
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLE_CL16_LATENCY_TIMER_MASK 0x000000FF
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLE_CL16_LATENCY_TIMER_SHIFT 0
#define  MC_CH1_ARB_MAIN_CTRL 0x9270
    #define MC_CH1_ARB_MAIN_CTRL_CLI_URGENT_SET_MASK 0x0001FFFF
    #define MC_CH1_ARB_MAIN_CTRL_CLI_URGENT_SET_SHIFT 0
    #define MC_CH1_ARB_MAIN_CTRL_LVL1_PRI_DIS_MASK 0x10000000
    #define MC_CH1_ARB_MAIN_CTRL_LVL1_PRI_DIS_SHIFT 28
    #define MC_CH1_ARB_MAIN_CTRL_URG_PRI_DIS_MASK 0x20000000
    #define MC_CH1_ARB_MAIN_CTRL_URG_PRI_DIS_SHIFT 29
    #define MC_CH1_ARB_MAIN_CTRL_LAT_PRI_DIS_MASK 0x40000000
    #define MC_CH1_ARB_MAIN_CTRL_LAT_PRI_DIS_SHIFT 30
    #define MC_CH1_ARB_MAIN_CTRL_ALT_PRI_DIS_MASK 0x80000000
    #define MC_CH1_ARB_MAIN_CTRL_ALT_PRI_DIS_SHIFT 31
#define  MC_CH1_ARB_PAGE_TIMER_CTRLA 0x9240
    #define MC_CH1_ARB_PAGE_TIMER_CTRLA_CL0_PAGE_TIMER_MASK 0x0000000F
    #define MC_CH1_ARB_PAGE_TIMER_CTRLA_CL0_PAGE_TIMER_SHIFT 0
    #define MC_CH1_ARB_PAGE_TIMER_CTRLA_CL1_PAGE_TIMER_MASK 0x000000F0
    #define MC_CH1_ARB_PAGE_TIMER_CTRLA_CL1_PAGE_TIMER_SHIFT 4
    #define MC_CH1_ARB_PAGE_TIMER_CTRLA_CL2_PAGE_TIMER_MASK 0x00000F00
    #define MC_CH1_ARB_PAGE_TIMER_CTRLA_CL2_PAGE_TIMER_SHIFT 8
    #define MC_CH1_ARB_PAGE_TIMER_CTRLA_CL3_PAGE_TIMER_MASK 0x0000F000
    #define MC_CH1_ARB_PAGE_TIMER_CTRLA_CL3_PAGE_TIMER_SHIFT 12
    #define MC_CH1_ARB_PAGE_TIMER_CTRLA_CL4_PAGE_TIMER_MASK 0x000F0000
    #define MC_CH1_ARB_PAGE_TIMER_CTRLA_CL4_PAGE_TIMER_SHIFT 16
    #define MC_CH1_ARB_PAGE_TIMER_CTRLA_CL5_PAGE_TIMER_MASK 0x00F00000
    #define MC_CH1_ARB_PAGE_TIMER_CTRLA_CL5_PAGE_TIMER_SHIFT 20
    #define MC_CH1_ARB_PAGE_TIMER_CTRLA_CL6_PAGE_TIMER_MASK 0x0F000000
    #define MC_CH1_ARB_PAGE_TIMER_CTRLA_CL6_PAGE_TIMER_SHIFT 24
    #define MC_CH1_ARB_PAGE_TIMER_CTRLA_CL7_PAGE_TIMER_MASK 0xF0000000
    #define MC_CH1_ARB_PAGE_TIMER_CTRLA_CL7_PAGE_TIMER_SHIFT 28
#define  MC_CH1_ARB_PAGE_TIMER_CTRLB 0x9244
    #define MC_CH1_ARB_PAGE_TIMER_CTRLB_CL8_PAGE_TIMER_MASK 0x0000000F
    #define MC_CH1_ARB_PAGE_TIMER_CTRLB_CL8_PAGE_TIMER_SHIFT 0
    #define MC_CH1_ARB_PAGE_TIMER_CTRLB_CL9_PAGE_TIMER_MASK 0x000000F0
    #define MC_CH1_ARB_PAGE_TIMER_CTRLB_CL9_PAGE_TIMER_SHIFT 4
    #define MC_CH1_ARB_PAGE_TIMER_CTRLB_CL10_PAGE_TIMER_MASK 0x00000F00
    #define MC_CH1_ARB_PAGE_TIMER_CTRLB_CL10_PAGE_TIMER_SHIFT 8
    #define MC_CH1_ARB_PAGE_TIMER_CTRLB_CL11_PAGE_TIMER_MASK 0x0000F000
    #define MC_CH1_ARB_PAGE_TIMER_CTRLB_CL11_PAGE_TIMER_SHIFT 12
    #define MC_CH1_ARB_PAGE_TIMER_CTRLB_CL12_PAGE_TIMER_MASK 0x000F0000
    #define MC_CH1_ARB_PAGE_TIMER_CTRLB_CL12_PAGE_TIMER_SHIFT 16
    #define MC_CH1_ARB_PAGE_TIMER_CTRLB_CL13_PAGE_TIMER_MASK 0x00F00000
    #define MC_CH1_ARB_PAGE_TIMER_CTRLB_CL13_PAGE_TIMER_SHIFT 20
    #define MC_CH1_ARB_PAGE_TIMER_CTRLB_CL14_PAGE_TIMER_MASK 0x0F000000
    #define MC_CH1_ARB_PAGE_TIMER_CTRLB_CL14_PAGE_TIMER_SHIFT 24
    #define MC_CH1_ARB_PAGE_TIMER_CTRLB_CL15_PAGE_TIMER_MASK 0xF0000000
    #define MC_CH1_ARB_PAGE_TIMER_CTRLB_CL15_PAGE_TIMER_SHIFT 28
#define  MC_CH1_ARB_PAGE_TIMER_CTRLC 0x9248
    #define MC_CH1_ARB_PAGE_TIMER_CTRLC_CL16_PAGE_TIMER_MASK 0x0000000F
    #define MC_CH1_ARB_PAGE_TIMER_CTRLC_CL16_PAGE_TIMER_SHIFT 0
#define  MC_CH1_ARB_PRIORITY_CTRLA 0x9274
    #define MC_CH1_ARB_PRIORITY_CTRLA_CL_DISABLE_LAT_PRIORITY_MASK 0x0001FFFF
    #define MC_CH1_ARB_PRIORITY_CTRLA_CL_DISABLE_LAT_PRIORITY_SHIFT 0
#define  MC_CH1_ARB_PRIORITY_CTRLB 0x9278
    #define MC_CH1_ARB_PRIORITY_CTRLB_CL_DISABLE_URG_PRIORITY_MASK 0x0001FFFF
    #define MC_CH1_ARB_PRIORITY_CTRLB_CL_DISABLE_URG_PRIORITY_SHIFT 0
#define  MC_CH1_ARB_PRIORITY_CTRLC 0x927C
    #define MC_CH1_ARB_PRIORITY_CTRLC_CL_DISABLE_PF_PENALTY_MASK 0x0001FFFF
    #define MC_CH1_ARB_PRIORITY_CTRLC_CL_DISABLE_PF_PENALTY_SHIFT 0
#define  MC_CH1_ARB_PRIORITY_CTRLD 0x9280
    #define MC_CH1_ARB_PRIORITY_CTRLD_CL_DISABLE_RW_PENALTY_MASK 0x0001FFFF
    #define MC_CH1_ARB_PRIORITY_CTRLD_CL_DISABLE_RW_PENALTY_SHIFT 0
#define  MC_CH1_LOCK_EN 0x9210
    #define MC_CH1_LOCK_EN_LOCK_CL_ID_MASK 0x0001FFFF
    #define MC_CH1_LOCK_EN_LOCK_CL_ID_SHIFT 0
#define  MC_CH1_MEM_CONFIG 0x9200
    #define MC_CH1_MEM_CONFIG_BANKPINS_MASK 0x00000003
    #define MC_CH1_MEM_CONFIG_BANKPINS_SHIFT 0
    #define MC_CH1_MEM_CONFIG_ADDRPINS_MASK 0x0000007C
    #define MC_CH1_MEM_CONFIG_ADDRPINS_SHIFT 2
    #define MC_CH1_MEM_CONFIG_COLCOUNT_MASK 0x00000F80
    #define MC_CH1_MEM_CONFIG_COLCOUNT_SHIFT 7
    #define MC_CH1_MEM_CONFIG_ROWBANKCOL_MASK 0x00001000
    #define MC_CH1_MEM_CONFIG_ROWBANKCOL_SHIFT 12
    #define MC_CH1_MEM_CONFIG_EXTMEMSIZE_MASK 0x00006000
    #define MC_CH1_MEM_CONFIG_EXTMEMSIZE_SHIFT 13
#define  MC_CH1_MISC_REG 0x9204
    #define MC_CH1_MISC_REG_MRLOGIC_RSTN_MASK 0x00000001
    #define MC_CH1_MISC_REG_MRLOGIC_RSTN_SHIFT 0
#define  MC_CONFIG_REG 0x9004
    #define MC_CONFIG_REG_CHANNELBIT_MASK 0x0000001F
    #define MC_CONFIG_REG_CHANNELBIT_SHIFT 0
    #define COLDIS_MASK 0x00001000
    #define COLDIS_SHIFT 12
    #define CHANNEL_MAP_MASK 0x00070000
    #define CHANNEL_MAP_SHIFT 16
    #define MC_CONFIG_REG_MEM_DENSITY_MASK 0x03000000
    #define MC_CONFIG_REG_MEM_DENSITY_SHIFT 24
#define  MC_DEBUG_BUS 0x900C
    #define MC_DEBUG_BUS_REG_MASK 0xFFFFFFFF
    #define MC_DEBUG_BUS_REG_SHIFT 0
#define  MC_DUMMY_REG 0x9000
    #define MC_DUMMY_REG_REG_MASK 0xFFFFFFFF
    #define MC_DUMMY_REG_REG_SHIFT 0
#define  MC_LOCK_EN 0x9014
    #define MC_LOCK_EN_LOCK_CL_ID_MASK 0x0001FFFF
    #define MC_LOCK_EN_LOCK_CL_ID_SHIFT 0
    #define MC_LOCK_EN_FIX_RANGE_MASK 0x40000000
    #define MC_LOCK_EN_FIX_RANGE_SHIFT 30
#define  MC_MISC_REG 0x9008
    #define MC_MISC_REG_MRLOGIC_RSTN_MASK 0x00000001
    #define MC_MISC_REG_MRLOGIC_RSTN_SHIFT 0
#define  MC_STATS_BW1 0x903C
    #define CLI_ID1_BW_MASK 0xFFFFFFFF
    #define CLI_ID1_BW_SHIFT 0
#define  MC_STATS_BW2 0x9040
    #define CLI_ID2_BW_MASK 0xFFFFFFFF
    #define CLI_ID2_BW_SHIFT 0
#define  MC_STATS_BW3 0x9044
    #define CLI_ID3_BW_MASK 0xFFFFFFFF
    #define CLI_ID3_BW_SHIFT 0
#define  MC_STATS_BW4 0x9048
    #define CLI_ID4_BW_MASK 0xFFFFFFFF
    #define CLI_ID4_BW_SHIFT 0
#define  MC_STATS_LATENCY1 0x9024
    #define CLI_ID1_LAT_MASK 0x00000FFF
    #define CLI_ID1_LAT_SHIFT 0
    #define CLI_ID2_LAT_MASK 0x0FFF0000
    #define CLI_ID2_LAT_SHIFT 16
#define  MC_STATS_LATENCY2 0x9028
    #define CLI_ID3_LAT_MASK 0x00000FFF
    #define CLI_ID3_LAT_SHIFT 0
    #define CLI_ID4_LAT_MASK 0x0FFF0000
    #define CLI_ID4_LAT_SHIFT 16
#define  MC_STATS_NUM_REQ1 0x902C
    #define CLI_ID1_NREQ_MASK 0xFFFFFFFF
    #define CLI_ID1_NREQ_SHIFT 0
#define  MC_STATS_NUM_REQ2 0x9030
    #define CLI_ID2_NREQ_MASK 0xFFFFFFFF
    #define CLI_ID2_NREQ_SHIFT 0
#define  MC_STATS_NUM_REQ3 0x9034
    #define CLI_ID3_NREQ_MASK 0xFFFFFFFF
    #define CLI_ID3_NREQ_SHIFT 0
#define  MC_STATS_NUM_REQ4 0x9038
    #define CLI_ID4_NREQ_MASK 0xFFFFFFFF
    #define CLI_ID4_NREQ_SHIFT 0
#define  MC_STATS_REG 0x9020
    #define CLI_ID1_MASK 0x0000001F
    #define CLI_ID1_SHIFT 0
    #define RESET_CLI1_MASK 0x00000020
    #define RESET_CLI1_SHIFT 5
    #define CH_SEL_CLI1_MASK 0x000000C0
    #define CH_SEL_CLI1_SHIFT 6
    #define CLI_ID2_MASK 0x00001F00
    #define CLI_ID2_SHIFT 8
    #define RESET_CLI2_MASK 0x00002000
    #define RESET_CLI2_SHIFT 13
    #define CH_SEL_CLI2_MASK 0x0000C000
    #define CH_SEL_CLI2_SHIFT 14
    #define CLI_ID3_MASK 0x001F0000
    #define CLI_ID3_SHIFT 16
    #define RESET_CLI3_MASK 0x00200000
    #define RESET_CLI3_SHIFT 21
    #define CH_SEL_CLI3_MASK 0x00C00000
    #define CH_SEL_CLI3_SHIFT 22
    #define CLI_ID4_MASK 0x1F000000
    #define CLI_ID4_SHIFT 24
    #define RESET_CLI4_MASK 0x20000000
    #define RESET_CLI4_SHIFT 29
    #define CH_SEL_CLI4_MASK 0xC0000000
    #define CH_SEL_CLI4_SHIFT 30
#define  MC_STATUS 0x9010
    #define INITRDY_MASK 0x00000001
    #define INITRDY_SHIFT 0
#define  MC_UNLOCK_RANGE 0x9018
    #define MC_UNLOCK_RANGE_START_ADDR_MASK 0x000007FF
    #define MC_UNLOCK_RANGE_START_ADDR_SHIFT 0
    #define MC_UNLOCK_RANGE_END_ADDR_MASK 0x07FF0000
    #define MC_UNLOCK_RANGE_END_ADDR_SHIFT 16
#define  MDM_BUFFFLUSH 0xEC58
    #define MDM_BUFFFLUSH_FLUSH_MASK 0x00000001
    #define MDM_BUFFFLUSH_FLUSH_SHIFT 0
#define  MDM_BUFFFLUSH1 0xECD8
    #define MDM_BUFFFLUSH1_FLUSH_MASK 0x00000001
    #define MDM_BUFFFLUSH1_FLUSH_SHIFT 0
#define  MDM_BUF_SIZE 0xEC3C
    #define MDM_BUF_SIZE_BUF_SIZE_MASK 0x000003FF
    #define MDM_BUF_SIZE_BUF_SIZE_SHIFT 0
#define  MDM_BUF_SIZE1 0xECBC
    #define MDM_BUF_SIZE1_BUF_SIZE_MASK 0x000003FF
    #define MDM_BUF_SIZE1_BUF_SIZE_SHIFT 0
#define  MDM_BYTEPAUSE 0xEC0C
    #define MDM_BYTEPAUSE_BYTEPAUSE_MASK 0x0000FFFF
    #define MDM_BYTEPAUSE_BYTEPAUSE_SHIFT 0
#define  MDM_BYTEPAUSE1 0xEC8C
    #define MDM_BYTEPAUSE1_BYTEPAUSE_MASK 0x0000FFFF
    #define MDM_BYTEPAUSE1_BYTEPAUSE_SHIFT 0
#define  MDM_CTRLDATA_READ 0xEC30
    #define MDM_CTRLDATA_READ_CTRLDATA_READ_MASK 0x0000FFFF
    #define MDM_CTRLDATA_READ_CTRLDATA_READ_SHIFT 0
#define  MDM_CTRLDATA_READ1 0xECB0
    #define MDM_CTRLDATA_READ1_CTRLDATA_READ_MASK 0x0000FFFF
    #define MDM_CTRLDATA_READ1_CTRLDATA_READ_SHIFT 0
#define  MDM_CTRLDATA_WRITE 0xEC2C
    #define MDM_CTRLDATA_WRITE_CTRLDATA_WRITE_MASK 0x0000FFFF
    #define MDM_CTRLDATA_WRITE_CTRLDATA_WRITE_SHIFT 0
#define  MDM_CTRLDATA_WRITE1 0xECAC
    #define MDM_CTRLDATA_WRITE1_CTRLDATA_WRITE_MASK 0x0000FFFF
    #define MDM_CTRLDATA_WRITE1_CTRLDATA_WRITE_SHIFT 0
#define  MDM_DEBUG 0xEC60
    #define MDM_DEBUG_DEBUG_DATA_MASK 0xFFFFFFFF
    #define MDM_DEBUG_DEBUG_DATA_SHIFT 0
#define  MDM_DEBUG1 0xECE0
    #define MDM_DEBUG1_DEBUG_DATA_MASK 0xFFFFFFFF
    #define MDM_DEBUG1_DEBUG_DATA_SHIFT 0
#define  MDM_DUMMY_REG 0xEC64
    #define MDM_DUMMY_REG_DUMMY_BITS_MASK 0xFFFFFFFF
    #define MDM_DUMMY_REG_DUMMY_BITS_SHIFT 0
#define  MDM_DUMMY_REG1 0xECE4
    #define MDM_DUMMY_REG1_DUMMY_BITS_MASK 0xFFFFFFFF
    #define MDM_DUMMY_REG1_DUMMY_BITS_SHIFT 0
#define  MDM_FRAMECNT 0xEC20
    #define MDM_FRAMECNT_FRMAECNT_MASK 0x0000FFFF
    #define MDM_FRAMECNT_FRMAECNT_SHIFT 0
#define  MDM_FRAMECNT1 0xECA0
    #define MDM_FRAMECNT1_FRMAECNT_MASK 0x0000FFFF
    #define MDM_FRAMECNT1_FRMAECNT_SHIFT 0
#define  MDM_FRAMESIZE 0xEC00
    #define MDM_FRAMESIZE_FRAMESIZE_MASK 0x000003FF
    #define MDM_FRAMESIZE_FRAMESIZE_SHIFT 0
#define  MDM_FRAMESIZE1 0xEC80
    #define MDM_FRAMESIZE1_FRAMESIZE_MASK 0x000003FF
    #define MDM_FRAMESIZE1_FRAMESIZE_SHIFT 0
#define  MDM_FS_HI 0xEC10
    #define MDM_FS_HI_FS_HI_MASK 0x0000FFFF
    #define MDM_FS_HI_FS_HI_SHIFT 0
#define  MDM_FS_HI1 0xEC90
    #define MDM_FS_HI1_FS_HI_MASK 0x0000FFFF
    #define MDM_FS_HI1_FS_HI_SHIFT 0
#define  MDM_FS_LO 0xEC14
    #define MDM_FS_LO_FS_LO_MASK 0x0000FFFF
    #define MDM_FS_LO_FS_LO_SHIFT 0
#define  MDM_FS_LO1 0xEC94
    #define MDM_FS_LO1_FS_LO_MASK 0x0000FFFF
    #define MDM_FS_LO1_FS_LO_SHIFT 0
#define  MDM_GSCLK_HI 0xEC04
    #define MDM_GSCLK_HI_GSCLK_HI_MASK 0xFFFFFFFF
    #define MDM_GSCLK_HI_GSCLK_HI_SHIFT 0
#define  MDM_GSCLK_HI1 0xEC84
    #define MDM_GSCLK_HI1_GSCLK_HI_MASK 0xFFFFFFFF
    #define MDM_GSCLK_HI1_GSCLK_HI_SHIFT 0
#define  MDM_GSCLK_LO 0xEC08
    #define MDM_GSCLK_LO_GSCLK_LO_MASK 0xFFFFFFFF
    #define MDM_GSCLK_LO_GSCLK_LO_SHIFT 0
#define  MDM_GSCLK_LO1 0xEC88
    #define MDM_GSCLK_LO1_GSCLK_LO_MASK 0xFFFFFFFF
    #define MDM_GSCLK_LO1_GSCLK_LO_SHIFT 0
#define  MDM_GSICFG 0xEC18
    #define MDM_GSICFG_GSI_INPUTEDGE_MASK 0x00000001
    #define MDM_GSICFG_GSI_INPUTEDGE_SHIFT 0
    #define MDM_GSICFG_GSI_OUTPUTEDGE_MASK 0x00000002
    #define MDM_GSICFG_GSI_OUTPUTEDGE_SHIFT 1
    #define MDM_GSICFG_GSI_GSCLK_DEFAULT_MASK 0x00000004
    #define MDM_GSICFG_GSI_GSCLK_DEFAULT_SHIFT 2
    #define MDM_GSICFG_GSI_FSCS_DEFAULT_MASK 0x00000008
    #define MDM_GSICFG_GSI_FSCS_DEFAULT_SHIFT 3
    #define MDM_GSICFG_GSI_V92MODE_MASK 0x00000010
    #define MDM_GSICFG_GSI_V92MODE_SHIFT 4
    #define MDM_GSICFG_GSI_USEEXTCLK_MASK 0x00000020
    #define MDM_GSICFG_GSI_USEEXTCLK_SHIFT 5
    #define MDM_GSICFG_GSI_USEEXTFS_MASK 0x00000040
    #define MDM_GSICFG_GSI_USEEXTFS_SHIFT 6
    #define MDM_GSICFG_GSI_STLED316S_MODE_MASK 0x00000080
    #define MDM_GSICFG_GSI_STLED316S_MODE_SHIFT 7
    #define MDM_GSICFG_GSI_FLIP_FINE_TUNE_MASK 0x00000100
    #define MDM_GSICFG_GSI_FLIP_FINE_TUNE_SHIFT 8
    #define MDM_GSICFG_GSI_BITORDER_MASK 0x00000200
    #define MDM_GSICFG_GSI_BITORDER_SHIFT 9
    #define MDM_GSICFG_GSI_BYTEORDER_MASK 0x00000400
    #define MDM_GSICFG_GSI_BYTEORDER_SHIFT 10
    #define MDM_GSICFG_GSI_AUTOFLUSH_MASK 0x00000800
    #define MDM_GSICFG_GSI_AUTOFLUSH_SHIFT 11
#define  MDM_GSICFG1 0xEC98
    #define MDM_GSICFG1_GSI_INPUTEDGE_MASK 0x00000001
    #define MDM_GSICFG1_GSI_INPUTEDGE_SHIFT 0
    #define MDM_GSICFG1_GSI_OUTPUTEDGE_MASK 0x00000002
    #define MDM_GSICFG1_GSI_OUTPUTEDGE_SHIFT 1
    #define MDM_GSICFG1_GSI_GSCLK_DEFAULT_MASK 0x00000004
    #define MDM_GSICFG1_GSI_GSCLK_DEFAULT_SHIFT 2
    #define MDM_GSICFG1_GSI_FSCS_DEFAULT_MASK 0x00000008
    #define MDM_GSICFG1_GSI_FSCS_DEFAULT_SHIFT 3
    #define MDM_GSICFG1_GSI_V92MODE_MASK 0x00000010
    #define MDM_GSICFG1_GSI_V92MODE_SHIFT 4
    #define MDM_GSICFG1_GSI_USEEXTCLK_MASK 0x00000020
    #define MDM_GSICFG1_GSI_USEEXTCLK_SHIFT 5
    #define MDM_GSICFG1_GSI_USEEXTFS_MASK 0x00000040
    #define MDM_GSICFG1_GSI_USEEXTFS_SHIFT 6
    #define MDM_GSICFG1_GSI_STLED316S_MODE_MASK 0x00000080
    #define MDM_GSICFG1_GSI_STLED316S_MODE_SHIFT 7
    #define MDM_GSICFG1_GSI_FLIP_FINE_TUNE_MASK 0x00000100
    #define MDM_GSICFG1_GSI_FLIP_FINE_TUNE_SHIFT 8
    #define MDM_GSICFG1_GSI_BITORDER_MASK 0x00000200
    #define MDM_GSICFG1_GSI_BITORDER_SHIFT 9
    #define MDM_GSICFG1_GSI_BYTEORDER_MASK 0x00000400
    #define MDM_GSICFG1_GSI_BYTEORDER_SHIFT 10
    #define MDM_GSICFG1_GSI_AUTOFLUSH_MASK 0x00000800
    #define MDM_GSICFG1_GSI_AUTOFLUSH_SHIFT 11
#define  MDM_INTMASK 0xEC28
    #define MDM_INTMASK_INTCTRL_MASK_MASK 0x00000001
    #define MDM_INTMASK_INTCTRL_MASK_SHIFT 0
    #define MDM_INTMASK_INTTIMER_MASK_MASK 0x00000002
    #define MDM_INTMASK_INTTIMER_MASK_SHIFT 1
    #define MDM_INTMASK_EXTINT_MASK_MASK 0x00000004
    #define MDM_INTMASK_EXTINT_MASK_SHIFT 2
    #define MDM_INTMASK_INTEMPTY_MASK_MASK 0x00000008
    #define MDM_INTMASK_INTEMPTY_MASK_SHIFT 3
#define  MDM_INTMASK1 0xECA8
    #define MDM_INTMASK1_INTCTRL_MASK_MASK 0x00000001
    #define MDM_INTMASK1_INTCTRL_MASK_SHIFT 0
    #define MDM_INTMASK1_INTTIMER_MASK_MASK 0x00000002
    #define MDM_INTMASK1_INTTIMER_MASK_SHIFT 1
    #define MDM_INTMASK1_EXTINT_MASK_MASK 0x00000004
    #define MDM_INTMASK1_EXTINT_MASK_SHIFT 2
    #define MDM_INTMASK1_INTEMPTY_MASK_MASK 0x00000008
    #define MDM_INTMASK1_INTEMPTY_MASK_SHIFT 3
#define  MDM_INTSTATUS 0xEC24
    #define MDM_INTSTATUS_INTCTRL_MASK 0x00000001
    #define MDM_INTSTATUS_INTCTRL_SHIFT 0
    #define MDM_INTSTATUS_INTTIMER_MASK 0x00000002
    #define MDM_INTSTATUS_INTTIMER_SHIFT 1
    #define MDM_INTSTATUS_EXTINT_MASK 0x00000004
    #define MDM_INTSTATUS_EXTINT_SHIFT 2
    #define MDM_INTSTATUS_INTEMPTY_MASK 0x00000008
    #define MDM_INTSTATUS_INTEMPTY_SHIFT 3
    #define MDM_INTSTATUS_RXFREE_ENTRIES_MASK 0x00000030
    #define MDM_INTSTATUS_RXFREE_ENTRIES_SHIFT 4
#define  MDM_INTSTATUS1 0xECA4
    #define MDM_INTSTATUS1_INTCTRL_MASK 0x00000001
    #define MDM_INTSTATUS1_INTCTRL_SHIFT 0
    #define MDM_INTSTATUS1_INTTIMER_MASK 0x00000002
    #define MDM_INTSTATUS1_INTTIMER_SHIFT 1
    #define MDM_INTSTATUS1_EXTINT_MASK 0x00000004
    #define MDM_INTSTATUS1_EXTINT_SHIFT 2
    #define MDM_INTSTATUS1_INTEMPTY_MASK 0x00000008
    #define MDM_INTSTATUS1_INTEMPTY_SHIFT 3
    #define MDM_INTSTATUS1_RXFREE_ENTRIES_MASK 0x00000030
    #define MDM_INTSTATUS1_RXFREE_ENTRIES_SHIFT 4
#define  MDM_INT_SIZE 0xEC40
    #define MDM_INT_SIZE_INT_SIZE_MASK 0x000003FF
    #define MDM_INT_SIZE_INT_SIZE_SHIFT 0
#define  MDM_INT_SIZE1 0xECC0
    #define MDM_INT_SIZE1_INT_SIZE_MASK 0x000003FF
    #define MDM_INT_SIZE1_INT_SIZE_SHIFT 0
#define  MDM_OFFSET 0xEC54
    #define MDM_OFFSET_OFFSET_MASK 0x000003FF
    #define MDM_OFFSET_OFFSET_SHIFT 0
#define  MDM_OFFSET1 0xECD4
    #define MDM_OFFSET1_OFFSET_MASK 0x000003FF
    #define MDM_OFFSET1_OFFSET_SHIFT 0
#define  MDM_RX_ADDR 0xEC50
    #define MDM_RX_ADDR_RX_ADDR_MASK 0x7FFFFFE0
    #define MDM_RX_ADDR_RX_ADDR_SHIFT 5
#define  MDM_RX_ADDR1 0xECD0
    #define MDM_RX_ADDR1_RX_ADDR_MASK 0x7FFFFFE0
    #define MDM_RX_ADDR1_RX_ADDR_SHIFT 5
#define  MDM_RX_BASE 0xEC38
    #define MDM_RX_BASE_RX_BASE_MASK 0x7FFFFFE0
    #define MDM_RX_BASE_RX_BASE_SHIFT 5
#define  MDM_RX_BASE1 0xECB8
    #define MDM_RX_BASE1_RX_BASE_MASK 0x7FFFFFE0
    #define MDM_RX_BASE1_RX_BASE_SHIFT 5
#define  MDM_SDINCACHE 0xEC5C
    #define MDM_SDINCACHE_SDINCACHE_MASK 0xFFFFFFFF
    #define MDM_SDINCACHE_SDINCACHE_SHIFT 0
#define  MDM_SDINCACHE1 0xECDC
    #define MDM_SDINCACHE1_SDINCACHE_MASK 0xFFFFFFFF
    #define MDM_SDINCACHE1_SDINCACHE_SHIFT 0
#define  MDM_SOFTRST 0xEC48
    #define MDM_SOFTRST_SOFT_RESET_MASK 0x00000001
    #define MDM_SOFTRST_SOFT_RESET_SHIFT 0
    #define MDM_SOFTRST_RESET_EXT_MASK 0x00000002
    #define MDM_SOFTRST_RESET_EXT_SHIFT 1
#define  MDM_SOFTRST1 0xECC8
    #define MDM_SOFTRST1_SOFT_RESET_MASK 0x00000001
    #define MDM_SOFTRST1_SOFT_RESET_SHIFT 0
    #define MDM_SOFTRST1_RESET_EXT_MASK 0x00000002
    #define MDM_SOFTRST1_RESET_EXT_SHIFT 1
#define  MDM_STATE 0xEC44
    #define MDM_STATE_STATE_MASK 0x00000001
    #define MDM_STATE_STATE_SHIFT 0
    #define MDM_STATE_TMODE_MASK 0x00000002
    #define MDM_STATE_TMODE_SHIFT 1
#define  MDM_STATE1 0xECC4
    #define MDM_STATE1_STATE_MASK 0x00000001
    #define MDM_STATE1_STATE_SHIFT 0
    #define MDM_STATE1_TMODE_MASK 0x00000002
    #define MDM_STATE1_TMODE_SHIFT 1
#define  MDM_STLED316S_CMDLENGTH 0xEC1C
    #define MDM_STLED316S_CMDLENGTH_GSI_STLED316S_CMDLENTH_MASK 0x0000001F
    #define MDM_STLED316S_CMDLENGTH_GSI_STLED316S_CMDLENTH_SHIFT 0
#define  MDM_STLED316S_CMDLENGTH1 0xEC9C
    #define MDM_STLED316S_CMDLENGTH1_GSI_STLED316S_CMDLENTH_MASK 0x0000001F
    #define MDM_STLED316S_CMDLENGTH1_GSI_STLED316S_CMDLENTH_SHIFT 0
#define  MDM_TX_ADDR 0xEC4C
    #define MDM_TX_ADDR_TX_ADDR_MASK 0x7FFFFFE0
    #define MDM_TX_ADDR_TX_ADDR_SHIFT 5
#define  MDM_TX_ADDR1 0xECCC
    #define MDM_TX_ADDR1_TX_ADDR_MASK 0x7FFFFFE0
    #define MDM_TX_ADDR1_TX_ADDR_SHIFT 5
#define  MDM_TX_BASE 0xEC34
    #define MDM_TX_BASE_TX_BASE_MASK 0x7FFFFFE0
    #define MDM_TX_BASE_TX_BASE_SHIFT 5
#define  MDM_TX_BASE1 0xECB4
    #define MDM_TX_BASE1_TX_BASE_MASK 0x7FFFFFE0
    #define MDM_TX_BASE1_TX_BASE_SHIFT 5
#define  MGE0_INFO 0xA168
    #define MGE0_INFO_MVA_ADR_MASK 0x07FFFFFE
    #define MGE0_INFO_MVA_ADR_SHIFT 1
#define  MGE0_MVA_ADR 0xA11C
    #define MGE0_MVA_ADR_BASE_MASK 0x07FFFFF0
    #define MGE0_MVA_ADR_BASE_SHIFT 4
#define  MGE0_STATUS 0xA160
    #define MGE0_STATUS_DONE_MASK 0x04000000
    #define MGE0_STATUS_DONE_SHIFT 26
    #define MGE0_STATUS_ERROR_MASK 0xF0000000
    #define MGE0_STATUS_ERROR_SHIFT 28
#define  MGE0_TRIG 0xA164
    #define MGE0_TRIG_MB_TYPE_MASK 0x0000000F
    #define MGE0_TRIG_MB_TYPE_SHIFT 0
    #define MGE0_TRIG_MO_TYPE_MASK 0x00000030
    #define MGE0_TRIG_MO_TYPE_SHIFT 4
    #define MGE0_TRIG_MV_CNT_MASK 0x80000000
    #define MGE0_TRIG_MV_CNT_SHIFT 31
#define  MGE1_INFO 0xA568
    #define MGE1_INFO_MVA_ADR_MASK 0x07FFFFFE
    #define MGE1_INFO_MVA_ADR_SHIFT 1
#define  MGE1_MVA_ADR 0xA51C
    #define MGE1_MVA_ADR_BASE_MASK 0x07FFFFF0
    #define MGE1_MVA_ADR_BASE_SHIFT 4
#define  MGE1_STATUS 0xA560
    #define MGE1_STATUS_DONE_MASK 0x04000000
    #define MGE1_STATUS_DONE_SHIFT 26
    #define MGE1_STATUS_ERROR_MASK 0xF0000000
    #define MGE1_STATUS_ERROR_SHIFT 28
#define  MGE1_TRIG 0xA564
    #define MGE1_TRIG_MB_TYPE_MASK 0x0000000F
    #define MGE1_TRIG_MB_TYPE_SHIFT 0
    #define MGE1_TRIG_MO_TYPE_MASK 0x00000030
    #define MGE1_TRIG_MO_TYPE_SHIFT 4
    #define MGE1_TRIG_MV_CNT_MASK 0x80000000
    #define MGE1_TRIG_MV_CNT_SHIFT 31
#define  MIPS0_INTERRUPT 0x041C
    #define MIPS0_INTERRUPT_TSD_INT0_MASK 0x00000001
    #define MIPS0_INTERRUPT_TSD_INT0_SHIFT 0
    #define MIPS0_INTERRUPT_TSD_INT1_MASK 0x00000002
    #define MIPS0_INTERRUPT_TSD_INT1_SHIFT 1
    #define MIPS0_INTERRUPT_USBD_INT_MASK 0x00000004
    #define MIPS0_INTERRUPT_USBD_INT_SHIFT 2
    #define MIPS0_INTERRUPT_USBH_INT_MASK 0x00000008
    #define MIPS0_INTERRUPT_USBH_INT_SHIFT 3
    #define MIPS0_INTERRUPT_TSD_INT4_MASK 0x00000010
    #define MIPS0_INTERRUPT_TSD_INT4_SHIFT 4
    #define MIPS0_INTERRUPT_ETH0_INT_MASK 0x00000020
    #define MIPS0_INTERRUPT_ETH0_INT_SHIFT 5
    #define MIPS0_INTERRUPT_ETH1_INT_MASK 0x00000040
    #define MIPS0_INTERRUPT_ETH1_INT_SHIFT 6
    #define MIPS0_INTERRUPT_PPC_INT_MASK 0x00000080
    #define MIPS0_INTERRUPT_PPC_INT_SHIFT 7
    #define MIPS0_INTERRUPT_DMA_INT_MASK 0x00000100
    #define MIPS0_INTERRUPT_DMA_INT_SHIFT 8
    #define MIPS0_INTERRUPT_RBM_INT_MASK 0x00000200
    #define MIPS0_INTERRUPT_RBM_INT_SHIFT 9
    #define MIPS0_INTERRUPT_MPP_INT_MASK 0x00000400
    #define MIPS0_INTERRUPT_MPP_INT_SHIFT 10
    #define MIPS0_INTERRUPT_RSA_INT_MASK 0x00000800
    #define MIPS0_INTERRUPT_RSA_INT_SHIFT 11
    #define MIPS0_INTERRUPT_I2S_INT_MASK 0x00001000
    #define MIPS0_INTERRUPT_I2S_INT_SHIFT 12
    #define MIPS0_INTERRUPT_RMX_INT_MASK 0x00002000
    #define MIPS0_INTERRUPT_RMX_INT_SHIFT 13
    #define MIPS0_INTERRUPT_VHE_INT_MASK 0x00004000
    #define MIPS0_INTERRUPT_VHE_INT_SHIFT 14
    #define MIPS0_INTERRUPT_VFE_INT_MASK 0x00008000
    #define MIPS0_INTERRUPT_VFE_INT_SHIFT 15
    #define MIPS0_INTERRUPT_VNE_INT_MASK 0x00010000
    #define MIPS0_INTERRUPT_VNE_INT_SHIFT 16
    #define MIPS0_INTERRUPT_GVD_INT_MASK 0x00020000
    #define MIPS0_INTERRUPT_GVD_INT_SHIFT 17
    #define MIPS0_INTERRUPT_DVE_INT_MASK 0x00040000
    #define MIPS0_INTERRUPT_DVE_INT_SHIFT 18
    #define MIPS0_INTERRUPT_SATA_INT_MASK 0x00080000
    #define MIPS0_INTERRUPT_SATA_INT_SHIFT 19
    #define MIPS0_INTERRUPT_I2STX_INT_MASK 0x00100000
    #define MIPS0_INTERRUPT_I2STX_INT_SHIFT 20
    #define MIPS0_INTERRUPT_SPDIFRX_INT_MASK 0x00200000
    #define MIPS0_INTERRUPT_SPDIFRX_INT_SHIFT 21
    #define MIPS0_INTERRUPT_SPDIFTX_INT_MASK 0x00400000
    #define MIPS0_INTERRUPT_SPDIFTX_INT_SHIFT 22
    #define MIPS0_INTERRUPT_EDC_INT_MASK 0x00800000
    #define MIPS0_INTERRUPT_EDC_INT_SHIFT 23
    #define MIPS0_INTERRUPT_DSCL_INT_MASK 0x01000000
    #define MIPS0_INTERRUPT_DSCL_INT_SHIFT 24
    #define MIPS0_INTERRUPT_EE_INT_MASK 0x02000000
    #define MIPS0_INTERRUPT_EE_INT_SHIFT 25
    #define MIPS0_INTERRUPT_NFC_INT_MASK 0x04000000
    #define MIPS0_INTERRUPT_NFC_INT_SHIFT 26
#define  MIPS0_INTERRUPT1 0x0514
    #define MIPS0_INTERRUPT1_SMS_INT_MASK 0x00000001
    #define MIPS0_INTERRUPT1_SMS_INT_SHIFT 0
    #define MIPS0_INTERRUPT1_VNH_INT_MASK 0x00000002
    #define MIPS0_INTERRUPT1_VNH_INT_SHIFT 1
    #define MIPS0_INTERRUPT1_DISP_INT_MASK 0x00000004
    #define MIPS0_INTERRUPT1_DISP_INT_SHIFT 2
    #define MIPS0_INTERRUPT1_MAD_INT_MASK 0x00000008
    #define MIPS0_INTERRUPT1_MAD_INT_SHIFT 3
    #define MIPS0_INTERRUPT1_GIC_INT_MASK 0x00000010
    #define MIPS0_INTERRUPT1_GIC_INT_SHIFT 4
    #define MIPS0_INTERRUPT1_FES_INT_MASK 0x00000020
    #define MIPS0_INTERRUPT1_FES_INT_SHIFT 5
    #define MIPS0_INTERRUPT1_G2D_INT_MASK 0x00000040
    #define MIPS0_INTERRUPT1_G2D_INT_SHIFT 6
    #define MIPS0_INTERRUPT1_IRC_INT_MASK 0x00000080
    #define MIPS0_INTERRUPT1_IRC_INT_SHIFT 7
    #define MIPS0_INTERRUPT1_NRFC_INT_MASK 0x00000100
    #define MIPS0_INTERRUPT1_NRFC_INT_SHIFT 8
    #define MIPS0_INTERRUPT1_SMCC_INT_MASK 0x00000200
    #define MIPS0_INTERRUPT1_SMCC_INT_SHIFT 9
    #define MIPS0_INTERRUPT1_MAFE_INT_MASK 0x00000400
    #define MIPS0_INTERRUPT1_MAFE_INT_SHIFT 10
    #define MIPS0_INTERRUPT1_RMX1_INT_MASK 0x00000800
    #define MIPS0_INTERRUPT1_RMX1_INT_SHIFT 11
    #define MIPS0_INTERRUPT1_G3D_INT_MASK 0x00001000
    #define MIPS0_INTERRUPT1_G3D_INT_SHIFT 12
    #define MIPS0_INTERRUPT1_UART0_INT_MASK 0x00002000
    #define MIPS0_INTERRUPT1_UART0_INT_SHIFT 13
    #define MIPS0_INTERRUPT1_UART1_INT_MASK 0x00004000
    #define MIPS0_INTERRUPT1_UART1_INT_SHIFT 14
    #define MIPS0_INTERRUPT1_INT15_MASK 0x00008000
    #define MIPS0_INTERRUPT1_INT15_SHIFT 15
    #define MIPS0_INTERRUPT1_INT16_MASK 0x00010000
    #define MIPS0_INTERRUPT1_INT16_SHIFT 16
    #define MIPS0_INTERRUPT1_INT17_MASK 0x00020000
    #define MIPS0_INTERRUPT1_INT17_SHIFT 17
    #define MIPS0_INTERRUPT1_INT18_MASK 0x00040000
    #define MIPS0_INTERRUPT1_INT18_SHIFT 18
    #define MIPS0_INTERRUPT1_INT19_MASK 0x00080000
    #define MIPS0_INTERRUPT1_INT19_SHIFT 19
    #define MIPS0_INTERRUPT1_INT20_MASK 0x00100000
    #define MIPS0_INTERRUPT1_INT20_SHIFT 20
    #define MIPS0_INTERRUPT1_INT21_MASK 0x00200000
    #define MIPS0_INTERRUPT1_INT21_SHIFT 21
    #define MIPS0_INTERRUPT1_INT22_MASK 0x00400000
    #define MIPS0_INTERRUPT1_INT22_SHIFT 22
    #define MIPS0_INTERRUPT1_INT23_MASK 0x00800000
    #define MIPS0_INTERRUPT1_INT23_SHIFT 23
    #define MIPS0_INTERRUPT1_INT24_MASK 0x01000000
    #define MIPS0_INTERRUPT1_INT24_SHIFT 24
    #define MIPS0_INTERRUPT1_INT25_MASK 0x02000000
    #define MIPS0_INTERRUPT1_INT25_SHIFT 25
    #define MIPS0_INTERRUPT1_INT26_MASK 0x04000000
    #define MIPS0_INTERRUPT1_INT26_SHIFT 26
    #define MIPS0_INTERRUPT1_INT27_MASK 0x08000000
    #define MIPS0_INTERRUPT1_INT27_SHIFT 27
    #define MIPS0_INTERRUPT1_INT28_MASK 0x10000000
    #define MIPS0_INTERRUPT1_INT28_SHIFT 28
    #define MIPS0_INTERRUPT1_INT29_MASK 0x20000000
    #define MIPS0_INTERRUPT1_INT29_SHIFT 29
    #define MIPS0_INTERRUPT1_INT30_MASK 0x40000000
    #define MIPS0_INTERRUPT1_INT30_SHIFT 30
    #define MIPS0_INTERRUPT1_INT31_MASK 0x80000000
    #define MIPS0_INTERRUPT1_INT31_SHIFT 31
#define  MIPS0_INTERRUPT1_MASK 0x0518
    #define MIPS0_INTERRUPT1_MASK_SMS_INT_MASK 0x00000001
    #define MIPS0_INTERRUPT1_MASK_SMS_INT_SHIFT 0
    #define MIPS0_INTERRUPT1_MASK_VNH_INT_MASK 0x00000002
    #define MIPS0_INTERRUPT1_MASK_VNH_INT_SHIFT 1
    #define MIPS0_INTERRUPT1_MASK_DISP_INT_MASK 0x00000004
    #define MIPS0_INTERRUPT1_MASK_DISP_INT_SHIFT 2
    #define MIPS0_INTERRUPT1_MASK_MAD_INT_MASK 0x00000008
    #define MIPS0_INTERRUPT1_MASK_MAD_INT_SHIFT 3
    #define MIPS0_INTERRUPT1_MASK_GIC_INT_MASK 0x00000010
    #define MIPS0_INTERRUPT1_MASK_GIC_INT_SHIFT 4
    #define MIPS0_INTERRUPT1_MASK_FES_INT_MASK 0x00000020
    #define MIPS0_INTERRUPT1_MASK_FES_INT_SHIFT 5
    #define MIPS0_INTERRUPT1_MASK_G2D_INT_MASK 0x00000040
    #define MIPS0_INTERRUPT1_MASK_G2D_INT_SHIFT 6
    #define MIPS0_INTERRUPT1_MASK_IRC_INT_MASK 0x00000080
    #define MIPS0_INTERRUPT1_MASK_IRC_INT_SHIFT 7
    #define MIPS0_INTERRUPT1_MASK_NRFC_INT_MASK 0x00000100
    #define MIPS0_INTERRUPT1_MASK_NRFC_INT_SHIFT 8
    #define MIPS0_INTERRUPT1_MASK_SMCC_INT_MASK 0x00000200
    #define MIPS0_INTERRUPT1_MASK_SMCC_INT_SHIFT 9
    #define MIPS0_INTERRUPT1_MASK_MAFE_INT_MASK 0x00000400
    #define MIPS0_INTERRUPT1_MASK_MAFE_INT_SHIFT 10
    #define MIPS0_INTERRUPT1_MASK_RMX1_INT_MASK 0x00000800
    #define MIPS0_INTERRUPT1_MASK_RMX1_INT_SHIFT 11
    #define MIPS0_INTERRUPT1_MASK_G3D_INT_MASK 0x00001000
    #define MIPS0_INTERRUPT1_MASK_G3D_INT_SHIFT 12
    #define MIPS0_INTERRUPT1_MASK_UART0_INT_MASK 0x00002000
    #define MIPS0_INTERRUPT1_MASK_UART0_INT_SHIFT 13
    #define MIPS0_INTERRUPT1_MASK_UART1_INT_MASK 0x00004000
    #define MIPS0_INTERRUPT1_MASK_UART1_INT_SHIFT 14
    #define MIPS0_INTERRUPT1_MASK_INT15_MASK 0x00008000
    #define MIPS0_INTERRUPT1_MASK_INT15_SHIFT 15
    #define MIPS0_INTERRUPT1_MASK_INT16_MASK 0x00010000
    #define MIPS0_INTERRUPT1_MASK_INT16_SHIFT 16
    #define MIPS0_INTERRUPT1_MASK_INT17_MASK 0x00020000
    #define MIPS0_INTERRUPT1_MASK_INT17_SHIFT 17
    #define MIPS0_INTERRUPT1_MASK_INT18_MASK 0x00040000
    #define MIPS0_INTERRUPT1_MASK_INT18_SHIFT 18
    #define MIPS0_INTERRUPT1_MASK_INT19_MASK 0x00080000
    #define MIPS0_INTERRUPT1_MASK_INT19_SHIFT 19
    #define MIPS0_INTERRUPT1_MASK_INT20_MASK 0x00100000
    #define MIPS0_INTERRUPT1_MASK_INT20_SHIFT 20
    #define MIPS0_INTERRUPT1_MASK_INT21_MASK 0x00200000
    #define MIPS0_INTERRUPT1_MASK_INT21_SHIFT 21
    #define MIPS0_INTERRUPT1_MASK_INT22_MASK 0x00400000
    #define MIPS0_INTERRUPT1_MASK_INT22_SHIFT 22
    #define MIPS0_INTERRUPT1_MASK_INT23_MASK 0x00800000
    #define MIPS0_INTERRUPT1_MASK_INT23_SHIFT 23
    #define MIPS0_INTERRUPT1_MASK_INT24_MASK 0x01000000
    #define MIPS0_INTERRUPT1_MASK_INT24_SHIFT 24
    #define MIPS0_INTERRUPT1_MASK_INT25_MASK 0x02000000
    #define MIPS0_INTERRUPT1_MASK_INT25_SHIFT 25
    #define MIPS0_INTERRUPT1_MASK_INT26_MASK 0x04000000
    #define MIPS0_INTERRUPT1_MASK_INT26_SHIFT 26
    #define MIPS0_INTERRUPT1_MASK_INT27_MASK 0x08000000
    #define MIPS0_INTERRUPT1_MASK_INT27_SHIFT 27
    #define MIPS0_INTERRUPT1_MASK_INT28_MASK 0x10000000
    #define MIPS0_INTERRUPT1_MASK_INT28_SHIFT 28
    #define MIPS0_INTERRUPT1_MASK_INT29_MASK 0x20000000
    #define MIPS0_INTERRUPT1_MASK_INT29_SHIFT 29
    #define MIPS0_INTERRUPT1_MASK_INT30_MASK 0x40000000
    #define MIPS0_INTERRUPT1_MASK_INT30_SHIFT 30
    #define MIPS0_INTERRUPT1_MASK_INT31_MASK 0x80000000
    #define MIPS0_INTERRUPT1_MASK_INT31_SHIFT 31
#define  MIPS0_INTERRUPT_MASK 0x0420
    #define MIPS0_INTERRUPT_MASK_TSD_INT0_MASK 0x00000001
    #define MIPS0_INTERRUPT_MASK_TSD_INT0_SHIFT 0
    #define MIPS0_INTERRUPT_MASK_TSD_INT1_MASK 0x00000002
    #define MIPS0_INTERRUPT_MASK_TSD_INT1_SHIFT 1
    #define MIPS0_INTERRUPT_MASK_USBD_INT_MASK 0x00000004
    #define MIPS0_INTERRUPT_MASK_USBD_INT_SHIFT 2
    #define MIPS0_INTERRUPT_MASK_USBH_INT_MASK 0x00000008
    #define MIPS0_INTERRUPT_MASK_USBH_INT_SHIFT 3
    #define MIPS0_INTERRUPT_MASK_TSD_INT4_MASK 0x00000010
    #define MIPS0_INTERRUPT_MASK_TSD_INT4_SHIFT 4
    #define MIPS0_INTERRUPT_MASK_ETH0_INT_MASK 0x00000020
    #define MIPS0_INTERRUPT_MASK_ETH0_INT_SHIFT 5
    #define MIPS0_INTERRUPT_MASK_ETH1_INT_MASK 0x00000040
    #define MIPS0_INTERRUPT_MASK_ETH1_INT_SHIFT 6
    #define MIPS0_INTERRUPT_MASK_PPC_INT_MASK 0x00000080
    #define MIPS0_INTERRUPT_MASK_PPC_INT_SHIFT 7
    #define MIPS0_INTERRUPT_MASK_DMA_INT_MASK 0x00000100
    #define MIPS0_INTERRUPT_MASK_DMA_INT_SHIFT 8
    #define MIPS0_INTERRUPT_MASK_RBM_INT_MASK 0x00000200
    #define MIPS0_INTERRUPT_MASK_RBM_INT_SHIFT 9
    #define MIPS0_INTERRUPT_MASK_MPP_INT_MASK 0x00000400
    #define MIPS0_INTERRUPT_MASK_MPP_INT_SHIFT 10
    #define MIPS0_INTERRUPT_MASK_RSA_INT_MASK 0x00000800
    #define MIPS0_INTERRUPT_MASK_RSA_INT_SHIFT 11
    #define MIPS0_INTERRUPT_MASK_I2S_INT_MASK 0x00001000
    #define MIPS0_INTERRUPT_MASK_I2S_INT_SHIFT 12
    #define MIPS0_INTERRUPT_MASK_RMX_INT_MASK 0x00002000
    #define MIPS0_INTERRUPT_MASK_RMX_INT_SHIFT 13
    #define MIPS0_INTERRUPT_MASK_VHE_INT_MASK 0x00004000
    #define MIPS0_INTERRUPT_MASK_VHE_INT_SHIFT 14
    #define MIPS0_INTERRUPT_MASK_VFE_INT_MASK 0x00008000
    #define MIPS0_INTERRUPT_MASK_VFE_INT_SHIFT 15
    #define MIPS0_INTERRUPT_MASK_VNE_INT_MASK 0x00010000
    #define MIPS0_INTERRUPT_MASK_VNE_INT_SHIFT 16
    #define MIPS0_INTERRUPT_MASK_GVD_INT_MASK 0x00020000
    #define MIPS0_INTERRUPT_MASK_GVD_INT_SHIFT 17
    #define MIPS0_INTERRUPT_MASK_DVE_INT_MASK 0x00040000
    #define MIPS0_INTERRUPT_MASK_DVE_INT_SHIFT 18
    #define MIPS0_INTERRUPT_MASK_SATA_INT_MASK 0x00080000
    #define MIPS0_INTERRUPT_MASK_SATA_INT_SHIFT 19
    #define MIPS0_INTERRUPT_MASK_I2STX_INT_MASK 0x00100000
    #define MIPS0_INTERRUPT_MASK_I2STX_INT_SHIFT 20
    #define MIPS0_INTERRUPT_MASK_SPDIFRX_INT_MASK 0x00200000
    #define MIPS0_INTERRUPT_MASK_SPDIFRX_INT_SHIFT 21
    #define MIPS0_INTERRUPT_MASK_SPDIFTX_INT_MASK 0x00400000
    #define MIPS0_INTERRUPT_MASK_SPDIFTX_INT_SHIFT 22
    #define MIPS0_INTERRUPT_MASK_EDC_INT_MASK 0x00800000
    #define MIPS0_INTERRUPT_MASK_EDC_INT_SHIFT 23
    #define MIPS0_INTERRUPT_MASK_DSCL_INT_MASK 0x01000000
    #define MIPS0_INTERRUPT_MASK_DSCL_INT_SHIFT 24
    #define MIPS0_INTERRUPT_MASK_EE_INT_MASK 0x02000000
    #define MIPS0_INTERRUPT_MASK_EE_INT_SHIFT 25
    #define MIPS0_INTERRUPT_MASK_NFC_INT_MASK 0x04000000
    #define MIPS0_INTERRUPT_MASK_NFC_INT_SHIFT 26
#define  MIPS1_INTERRUPT 0x0424
    #define MIPS1_INTERRUPT_TSD_INT0_MASK 0x00000001
    #define MIPS1_INTERRUPT_TSD_INT0_SHIFT 0
    #define MIPS1_INTERRUPT_TSD_INT1_MASK 0x00000002
    #define MIPS1_INTERRUPT_TSD_INT1_SHIFT 1
    #define MIPS1_INTERRUPT_USBD_INT_MASK 0x00000004
    #define MIPS1_INTERRUPT_USBD_INT_SHIFT 2
    #define MIPS1_INTERRUPT_USBH_INT_MASK 0x00000008
    #define MIPS1_INTERRUPT_USBH_INT_SHIFT 3
    #define MIPS1_INTERRUPT_TSD_INT4_MASK 0x00000010
    #define MIPS1_INTERRUPT_TSD_INT4_SHIFT 4
    #define MIPS1_INTERRUPT_ETH0_INT_MASK 0x00000020
    #define MIPS1_INTERRUPT_ETH0_INT_SHIFT 5
    #define MIPS1_INTERRUPT_ETH1_INT_MASK 0x00000040
    #define MIPS1_INTERRUPT_ETH1_INT_SHIFT 6
    #define MIPS1_INTERRUPT_PPC_INT_MASK 0x00000080
    #define MIPS1_INTERRUPT_PPC_INT_SHIFT 7
    #define MIPS1_INTERRUPT_DMA_INT_MASK 0x00000100
    #define MIPS1_INTERRUPT_DMA_INT_SHIFT 8
    #define MIPS1_INTERRUPT_RBM_INT_MASK 0x00000200
    #define MIPS1_INTERRUPT_RBM_INT_SHIFT 9
    #define MIPS1_INTERRUPT_MPP_INT_MASK 0x00000400
    #define MIPS1_INTERRUPT_MPP_INT_SHIFT 10
    #define MIPS1_INTERRUPT_RSA_INT_MASK 0x00000800
    #define MIPS1_INTERRUPT_RSA_INT_SHIFT 11
    #define MIPS1_INTERRUPT_I2S_INT_MASK 0x00001000
    #define MIPS1_INTERRUPT_I2S_INT_SHIFT 12
    #define MIPS1_INTERRUPT_RMX_INT_MASK 0x00002000
    #define MIPS1_INTERRUPT_RMX_INT_SHIFT 13
    #define MIPS1_INTERRUPT_VHE_INT_MASK 0x00004000
    #define MIPS1_INTERRUPT_VHE_INT_SHIFT 14
    #define MIPS1_INTERRUPT_VFE_INT_MASK 0x00008000
    #define MIPS1_INTERRUPT_VFE_INT_SHIFT 15
    #define MIPS1_INTERRUPT_VNE_INT_MASK 0x00010000
    #define MIPS1_INTERRUPT_VNE_INT_SHIFT 16
    #define MIPS1_INTERRUPT_GVD_INT_MASK 0x00020000
    #define MIPS1_INTERRUPT_GVD_INT_SHIFT 17
    #define MIPS1_INTERRUPT_DVE_INT_MASK 0x00040000
    #define MIPS1_INTERRUPT_DVE_INT_SHIFT 18
    #define MIPS1_INTERRUPT_SATA_INT_MASK 0x00080000
    #define MIPS1_INTERRUPT_SATA_INT_SHIFT 19
    #define MIPS1_INTERRUPT_I2STX_INT_MASK 0x00100000
    #define MIPS1_INTERRUPT_I2STX_INT_SHIFT 20
    #define MIPS1_INTERRUPT_SPDIFRX_INT_MASK 0x00200000
    #define MIPS1_INTERRUPT_SPDIFRX_INT_SHIFT 21
    #define MIPS1_INTERRUPT_SPDIFTX_INT_MASK 0x00400000
    #define MIPS1_INTERRUPT_SPDIFTX_INT_SHIFT 22
    #define MIPS1_INTERRUPT_EDC_INT_MASK 0x00800000
    #define MIPS1_INTERRUPT_EDC_INT_SHIFT 23
    #define MIPS1_INTERRUPT_DSCL_INT_MASK 0x01000000
    #define MIPS1_INTERRUPT_DSCL_INT_SHIFT 24
    #define MIPS1_INTERRUPT_EE_INT_MASK 0x02000000
    #define MIPS1_INTERRUPT_EE_INT_SHIFT 25
    #define MIPS1_INTERRUPT_NFC_INT_MASK 0x04000000
    #define MIPS1_INTERRUPT_NFC_INT_SHIFT 26
#define  MIPS1_INTERRUPT1 0x051C
    #define MIPS1_INTERRUPT1_SMS_INT_MASK 0x00000001
    #define MIPS1_INTERRUPT1_SMS_INT_SHIFT 0
    #define MIPS1_INTERRUPT1_VNH_INT_MASK 0x00000002
    #define MIPS1_INTERRUPT1_VNH_INT_SHIFT 1
    #define MIPS1_INTERRUPT1_DISP_INT_MASK 0x00000004
    #define MIPS1_INTERRUPT1_DISP_INT_SHIFT 2
    #define MIPS1_INTERRUPT1_MAD_INT_MASK 0x00000008
    #define MIPS1_INTERRUPT1_MAD_INT_SHIFT 3
    #define MIPS1_INTERRUPT1_GIC_INT_MASK 0x00000010
    #define MIPS1_INTERRUPT1_GIC_INT_SHIFT 4
    #define MIPS1_INTERRUPT1_FES_INT_MASK 0x00000020
    #define MIPS1_INTERRUPT1_FES_INT_SHIFT 5
    #define MIPS1_INTERRUPT1_G2D_INT_MASK 0x00000040
    #define MIPS1_INTERRUPT1_G2D_INT_SHIFT 6
    #define MIPS1_INTERRUPT1_IRC_INT_MASK 0x00000080
    #define MIPS1_INTERRUPT1_IRC_INT_SHIFT 7
    #define MIPS1_INTERRUPT1_NRFC_INT_MASK 0x00000100
    #define MIPS1_INTERRUPT1_NRFC_INT_SHIFT 8
    #define MIPS1_INTERRUPT1_SMCC_INT_MASK 0x00000200
    #define MIPS1_INTERRUPT1_SMCC_INT_SHIFT 9
    #define MIPS1_INTERRUPT1_MAFE_INT_MASK 0x00000400
    #define MIPS1_INTERRUPT1_MAFE_INT_SHIFT 10
    #define MIPS1_INTERRUPT1_RMX1_INT_MASK 0x00000800
    #define MIPS1_INTERRUPT1_RMX1_INT_SHIFT 11
    #define MIPS1_INTERRUPT1_G3D_INT_MASK 0x00001000
    #define MIPS1_INTERRUPT1_G3D_INT_SHIFT 12
    #define MIPS1_INTERRUPT1_UART0_INT_MASK 0x00002000
    #define MIPS1_INTERRUPT1_UART0_INT_SHIFT 13
    #define MIPS1_INTERRUPT1_UART1_INT_MASK 0x00004000
    #define MIPS1_INTERRUPT1_UART1_INT_SHIFT 14
    #define MIPS1_INTERRUPT1_INT15_MASK 0x00008000
    #define MIPS1_INTERRUPT1_INT15_SHIFT 15
    #define MIPS1_INTERRUPT1_INT16_MASK 0x00010000
    #define MIPS1_INTERRUPT1_INT16_SHIFT 16
    #define MIPS1_INTERRUPT1_INT17_MASK 0x00020000
    #define MIPS1_INTERRUPT1_INT17_SHIFT 17
    #define MIPS1_INTERRUPT1_INT18_MASK 0x00040000
    #define MIPS1_INTERRUPT1_INT18_SHIFT 18
    #define MIPS1_INTERRUPT1_INT19_MASK 0x00080000
    #define MIPS1_INTERRUPT1_INT19_SHIFT 19
    #define MIPS1_INTERRUPT1_INT20_MASK 0x00100000
    #define MIPS1_INTERRUPT1_INT20_SHIFT 20
    #define MIPS1_INTERRUPT1_INT21_MASK 0x00200000
    #define MIPS1_INTERRUPT1_INT21_SHIFT 21
    #define MIPS1_INTERRUPT1_INT22_MASK 0x00400000
    #define MIPS1_INTERRUPT1_INT22_SHIFT 22
    #define MIPS1_INTERRUPT1_INT23_MASK 0x00800000
    #define MIPS1_INTERRUPT1_INT23_SHIFT 23
    #define MIPS1_INTERRUPT1_INT24_MASK 0x01000000
    #define MIPS1_INTERRUPT1_INT24_SHIFT 24
    #define MIPS1_INTERRUPT1_INT25_MASK 0x02000000
    #define MIPS1_INTERRUPT1_INT25_SHIFT 25
    #define MIPS1_INTERRUPT1_INT26_MASK 0x04000000
    #define MIPS1_INTERRUPT1_INT26_SHIFT 26
    #define MIPS1_INTERRUPT1_INT27_MASK 0x08000000
    #define MIPS1_INTERRUPT1_INT27_SHIFT 27
    #define MIPS1_INTERRUPT1_INT28_MASK 0x10000000
    #define MIPS1_INTERRUPT1_INT28_SHIFT 28
    #define MIPS1_INTERRUPT1_INT29_MASK 0x20000000
    #define MIPS1_INTERRUPT1_INT29_SHIFT 29
    #define MIPS1_INTERRUPT1_INT30_MASK 0x40000000
    #define MIPS1_INTERRUPT1_INT30_SHIFT 30
    #define MIPS1_INTERRUPT1_INT31_MASK 0x80000000
    #define MIPS1_INTERRUPT1_INT31_SHIFT 31
#define  MIPS1_INTERRUPT1_MASK 0x0520
    #define MIPS1_INTERRUPT1_MASK_SMS_INT_MASK 0x00000001
    #define MIPS1_INTERRUPT1_MASK_SMS_INT_SHIFT 0
    #define MIPS1_INTERRUPT1_MASK_VNH_INT_MASK 0x00000002
    #define MIPS1_INTERRUPT1_MASK_VNH_INT_SHIFT 1
    #define MIPS1_INTERRUPT1_MASK_DISP_INT_MASK 0x00000004
    #define MIPS1_INTERRUPT1_MASK_DISP_INT_SHIFT 2
    #define MIPS1_INTERRUPT1_MASK_MAD_INT_MASK 0x00000008
    #define MIPS1_INTERRUPT1_MASK_MAD_INT_SHIFT 3
    #define MIPS1_INTERRUPT1_MASK_GIC_INT_MASK 0x00000010
    #define MIPS1_INTERRUPT1_MASK_GIC_INT_SHIFT 4
    #define MIPS1_INTERRUPT1_MASK_FES_INT_MASK 0x00000020
    #define MIPS1_INTERRUPT1_MASK_FES_INT_SHIFT 5
    #define MIPS1_INTERRUPT1_MASK_G2D_INT_MASK 0x00000040
    #define MIPS1_INTERRUPT1_MASK_G2D_INT_SHIFT 6
    #define MIPS1_INTERRUPT1_MASK_IRC_INT_MASK 0x00000080
    #define MIPS1_INTERRUPT1_MASK_IRC_INT_SHIFT 7
    #define MIPS1_INTERRUPT1_MASK_NRFC_INT_MASK 0x00000100
    #define MIPS1_INTERRUPT1_MASK_NRFC_INT_SHIFT 8
    #define MIPS1_INTERRUPT1_MASK_SMCC_INT_MASK 0x00000200
    #define MIPS1_INTERRUPT1_MASK_SMCC_INT_SHIFT 9
    #define MIPS1_INTERRUPT1_MASK_MAFE_INT_MASK 0x00000400
    #define MIPS1_INTERRUPT1_MASK_MAFE_INT_SHIFT 10
    #define MIPS1_INTERRUPT1_MASK_RMX1_INT_MASK 0x00000800
    #define MIPS1_INTERRUPT1_MASK_RMX1_INT_SHIFT 11
    #define MIPS1_INTERRUPT1_MASK_G3D_INT_MASK 0x00001000
    #define MIPS1_INTERRUPT1_MASK_G3D_INT_SHIFT 12
    #define MIPS1_INTERRUPT1_MASK_UART0_INT_MASK 0x00002000
    #define MIPS1_INTERRUPT1_MASK_UART0_INT_SHIFT 13
    #define MIPS1_INTERRUPT1_MASK_UART1_INT_MASK 0x00004000
    #define MIPS1_INTERRUPT1_MASK_UART1_INT_SHIFT 14
    #define MIPS1_INTERRUPT1_MASK_INT15_MASK 0x00008000
    #define MIPS1_INTERRUPT1_MASK_INT15_SHIFT 15
    #define MIPS1_INTERRUPT1_MASK_INT16_MASK 0x00010000
    #define MIPS1_INTERRUPT1_MASK_INT16_SHIFT 16
    #define MIPS1_INTERRUPT1_MASK_INT17_MASK 0x00020000
    #define MIPS1_INTERRUPT1_MASK_INT17_SHIFT 17
    #define MIPS1_INTERRUPT1_MASK_INT18_MASK 0x00040000
    #define MIPS1_INTERRUPT1_MASK_INT18_SHIFT 18
    #define MIPS1_INTERRUPT1_MASK_INT19_MASK 0x00080000
    #define MIPS1_INTERRUPT1_MASK_INT19_SHIFT 19
    #define MIPS1_INTERRUPT1_MASK_INT20_MASK 0x00100000
    #define MIPS1_INTERRUPT1_MASK_INT20_SHIFT 20
    #define MIPS1_INTERRUPT1_MASK_INT21_MASK 0x00200000
    #define MIPS1_INTERRUPT1_MASK_INT21_SHIFT 21
    #define MIPS1_INTERRUPT1_MASK_INT22_MASK 0x00400000
    #define MIPS1_INTERRUPT1_MASK_INT22_SHIFT 22
    #define MIPS1_INTERRUPT1_MASK_INT23_MASK 0x00800000
    #define MIPS1_INTERRUPT1_MASK_INT23_SHIFT 23
    #define MIPS1_INTERRUPT1_MASK_INT24_MASK 0x01000000
    #define MIPS1_INTERRUPT1_MASK_INT24_SHIFT 24
    #define MIPS1_INTERRUPT1_MASK_INT25_MASK 0x02000000
    #define MIPS1_INTERRUPT1_MASK_INT25_SHIFT 25
    #define MIPS1_INTERRUPT1_MASK_INT26_MASK 0x04000000
    #define MIPS1_INTERRUPT1_MASK_INT26_SHIFT 26
    #define MIPS1_INTERRUPT1_MASK_INT27_MASK 0x08000000
    #define MIPS1_INTERRUPT1_MASK_INT27_SHIFT 27
    #define MIPS1_INTERRUPT1_MASK_INT28_MASK 0x10000000
    #define MIPS1_INTERRUPT1_MASK_INT28_SHIFT 28
    #define MIPS1_INTERRUPT1_MASK_INT29_MASK 0x20000000
    #define MIPS1_INTERRUPT1_MASK_INT29_SHIFT 29
    #define MIPS1_INTERRUPT1_MASK_INT30_MASK 0x40000000
    #define MIPS1_INTERRUPT1_MASK_INT30_SHIFT 30
    #define MIPS1_INTERRUPT1_MASK_INT31_MASK 0x80000000
    #define MIPS1_INTERRUPT1_MASK_INT31_SHIFT 31
#define  MIPS1_INTERRUPT_MASK 0x0428
    #define MIPS1_INTERRUPT_MASK_TSD_INT0_MASK 0x00000001
    #define MIPS1_INTERRUPT_MASK_TSD_INT0_SHIFT 0
    #define MIPS1_INTERRUPT_MASK_TSD_INT1_MASK 0x00000002
    #define MIPS1_INTERRUPT_MASK_TSD_INT1_SHIFT 1
    #define MIPS1_INTERRUPT_MASK_USBD_INT_MASK 0x00000004
    #define MIPS1_INTERRUPT_MASK_USBD_INT_SHIFT 2
    #define MIPS1_INTERRUPT_MASK_USBH_INT_MASK 0x00000008
    #define MIPS1_INTERRUPT_MASK_USBH_INT_SHIFT 3
    #define MIPS1_INTERRUPT_MASK_TSD_INT4_MASK 0x00000010
    #define MIPS1_INTERRUPT_MASK_TSD_INT4_SHIFT 4
    #define MIPS1_INTERRUPT_MASK_ETH0_INT_MASK 0x00000020
    #define MIPS1_INTERRUPT_MASK_ETH0_INT_SHIFT 5
    #define MIPS1_INTERRUPT_MASK_ETH1_INT_MASK 0x00000040
    #define MIPS1_INTERRUPT_MASK_ETH1_INT_SHIFT 6
    #define MIPS1_INTERRUPT_MASK_PPC_INT_MASK 0x00000080
    #define MIPS1_INTERRUPT_MASK_PPC_INT_SHIFT 7
    #define MIPS1_INTERRUPT_MASK_DMA_INT_MASK 0x00000100
    #define MIPS1_INTERRUPT_MASK_DMA_INT_SHIFT 8
    #define MIPS1_INTERRUPT_MASK_RBM_INT_MASK 0x00000200
    #define MIPS1_INTERRUPT_MASK_RBM_INT_SHIFT 9
    #define MIPS1_INTERRUPT_MASK_MPP_INT_MASK 0x00000400
    #define MIPS1_INTERRUPT_MASK_MPP_INT_SHIFT 10
    #define MIPS1_INTERRUPT_MASK_RSA_INT_MASK 0x00000800
    #define MIPS1_INTERRUPT_MASK_RSA_INT_SHIFT 11
    #define MIPS1_INTERRUPT_MASK_I2S_INT_MASK 0x00001000
    #define MIPS1_INTERRUPT_MASK_I2S_INT_SHIFT 12
    #define MIPS1_INTERRUPT_MASK_RMX_INT_MASK 0x00002000
    #define MIPS1_INTERRUPT_MASK_RMX_INT_SHIFT 13
    #define MIPS1_INTERRUPT_MASK_VHE_INT_MASK 0x00004000
    #define MIPS1_INTERRUPT_MASK_VHE_INT_SHIFT 14
    #define MIPS1_INTERRUPT_MASK_VFE_INT_MASK 0x00008000
    #define MIPS1_INTERRUPT_MASK_VFE_INT_SHIFT 15
    #define MIPS1_INTERRUPT_MASK_VNE_INT_MASK 0x00010000
    #define MIPS1_INTERRUPT_MASK_VNE_INT_SHIFT 16
    #define MIPS1_INTERRUPT_MASK_GVD_INT_MASK 0x00020000
    #define MIPS1_INTERRUPT_MASK_GVD_INT_SHIFT 17
    #define MIPS1_INTERRUPT_MASK_DVE_INT_MASK 0x00040000
    #define MIPS1_INTERRUPT_MASK_DVE_INT_SHIFT 18
    #define MIPS1_INTERRUPT_MASK_SATA_INT_MASK 0x00080000
    #define MIPS1_INTERRUPT_MASK_SATA_INT_SHIFT 19
    #define MIPS1_INTERRUPT_MASK_I2STX_INT_MASK 0x00100000
    #define MIPS1_INTERRUPT_MASK_I2STX_INT_SHIFT 20
    #define MIPS1_INTERRUPT_MASK_SPDIFRX_INT_MASK 0x00200000
    #define MIPS1_INTERRUPT_MASK_SPDIFRX_INT_SHIFT 21
    #define MIPS1_INTERRUPT_MASK_SPDIFTX_INT_MASK 0x00400000
    #define MIPS1_INTERRUPT_MASK_SPDIFTX_INT_SHIFT 22
    #define MIPS1_INTERRUPT_MASK_EDC_INT_MASK 0x00800000
    #define MIPS1_INTERRUPT_MASK_EDC_INT_SHIFT 23
    #define MIPS1_INTERRUPT_MASK_DSCL_INT_MASK 0x01000000
    #define MIPS1_INTERRUPT_MASK_DSCL_INT_SHIFT 24
    #define MIPS1_INTERRUPT_MASK_EE_INT_MASK 0x02000000
    #define MIPS1_INTERRUPT_MASK_EE_INT_SHIFT 25
    #define MIPS1_INTERRUPT_MASK_NFC_INT_MASK 0x04000000
    #define MIPS1_INTERRUPT_MASK_NFC_INT_SHIFT 26
#define  MIPS2_DBG_INBOUND 0x3860
    #define MIPS2_DBG_INBOUND_DATA_MASK 0xFFFFFFFF
    #define MIPS2_DBG_INBOUND_DATA_SHIFT 0
#define  MIPS2_DBG_OUTBOUND 0x3864
    #define MIPS2_DBG_OUTBOUND_DATA_MASK 0xFFFFFFFF
    #define MIPS2_DBG_OUTBOUND_DATA_SHIFT 0
#define  MIPS2_DUMMY_REG 0x38FC
    #define MIPS2_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define MIPS2_DUMMY_REG_DATA_SHIFT 0
#define  MIPS2_FB_TOP 0x3800
    #define MIPS2_FB_TOP_BASE_MASK 0x07FFFC00
    #define MIPS2_FB_TOP_BASE_SHIFT 10
#define  MIPS2_HOST_INT_MASK 0x38E4
    #define MIPS2_HOST_INT_MASK_INT_EN_OUTBOUND_CALL0_MASK 0x00000001
    #define MIPS2_HOST_INT_MASK_INT_EN_OUTBOUND_CALL0_SHIFT 0
    #define MIPS2_HOST_INT_MASK_INT_EN_OUTBOUND_CALL1_MASK 0x00000002
    #define MIPS2_HOST_INT_MASK_INT_EN_OUTBOUND_CALL1_SHIFT 1
    #define MIPS2_HOST_INT_MASK_INT_EN_OUTBOUND_DBG_MASK 0x00000004
    #define MIPS2_HOST_INT_MASK_INT_EN_OUTBOUND_DBG_SHIFT 2
    #define INT_EN_MIPS2_HANG_MASK 0x80000000
    #define INT_EN_MIPS2_HANG_SHIFT 31
#define  MIPS2_HOST_INT_STATUS 0x38E0
    #define MIPS2_HOST_INT_STATUS_OUTBOUND_CALL0_MASK 0x00000001
    #define MIPS2_HOST_INT_STATUS_OUTBOUND_CALL0_SHIFT 0
    #define MIPS2_HOST_INT_STATUS_OUTBOUND_CALL1_MASK 0x00000002
    #define MIPS2_HOST_INT_STATUS_OUTBOUND_CALL1_SHIFT 1
    #define MIPS2_HOST_INT_STATUS_OUTBOUND_DBG_MASK 0x00000004
    #define MIPS2_HOST_INT_STATUS_OUTBOUND_DBG_SHIFT 2
    #define MIPS2_HANG_MASK 0x80000000
    #define MIPS2_HANG_SHIFT 31
#define  MIPS2_INBOUND_CALL_0 0x3820
    #define MIPS2_INBOUND_CALL_0_DATA_MASK 0xFFFFFFFF
    #define MIPS2_INBOUND_CALL_0_DATA_SHIFT 0
#define  MIPS2_INBOUND_CALL_1 0x3824
    #define MIPS2_INBOUND_CALL_1_DATA_MASK 0xFFFFFFFF
    #define MIPS2_INBOUND_CALL_1_DATA_SHIFT 0
#define  MIPS2_INTERRUPT 0x042C
    #define MIPS2_INTERRUPT_TSD_INT0_MASK 0x00000001
    #define MIPS2_INTERRUPT_TSD_INT0_SHIFT 0
    #define MIPS2_INTERRUPT_TSD_INT1_MASK 0x00000002
    #define MIPS2_INTERRUPT_TSD_INT1_SHIFT 1
    #define MIPS2_INTERRUPT_USBD_INT_MASK 0x00000004
    #define MIPS2_INTERRUPT_USBD_INT_SHIFT 2
    #define MIPS2_INTERRUPT_USBH_INT_MASK 0x00000008
    #define MIPS2_INTERRUPT_USBH_INT_SHIFT 3
    #define MIPS2_INTERRUPT_TSD_INT4_MASK 0x00000010
    #define MIPS2_INTERRUPT_TSD_INT4_SHIFT 4
    #define MIPS2_INTERRUPT_ETH0_INT_MASK 0x00000020
    #define MIPS2_INTERRUPT_ETH0_INT_SHIFT 5
    #define MIPS2_INTERRUPT_ETH1_INT_MASK 0x00000040
    #define MIPS2_INTERRUPT_ETH1_INT_SHIFT 6
    #define MIPS2_INTERRUPT_PPC_INT_MASK 0x00000080
    #define MIPS2_INTERRUPT_PPC_INT_SHIFT 7
    #define MIPS2_INTERRUPT_DMA_INT_MASK 0x00000100
    #define MIPS2_INTERRUPT_DMA_INT_SHIFT 8
    #define MIPS2_INTERRUPT_RBM_INT_MASK 0x00000200
    #define MIPS2_INTERRUPT_RBM_INT_SHIFT 9
    #define MIPS2_INTERRUPT_MPP_INT_MASK 0x00000400
    #define MIPS2_INTERRUPT_MPP_INT_SHIFT 10
    #define MIPS2_INTERRUPT_RSA_INT_MASK 0x00000800
    #define MIPS2_INTERRUPT_RSA_INT_SHIFT 11
    #define MIPS2_INTERRUPT_I2S_INT_MASK 0x00001000
    #define MIPS2_INTERRUPT_I2S_INT_SHIFT 12
    #define MIPS2_INTERRUPT_RMX_INT_MASK 0x00002000
    #define MIPS2_INTERRUPT_RMX_INT_SHIFT 13
    #define MIPS2_INTERRUPT_VHE_INT_MASK 0x00004000
    #define MIPS2_INTERRUPT_VHE_INT_SHIFT 14
    #define MIPS2_INTERRUPT_VFE_INT_MASK 0x00008000
    #define MIPS2_INTERRUPT_VFE_INT_SHIFT 15
    #define MIPS2_INTERRUPT_VNE_INT_MASK 0x00010000
    #define MIPS2_INTERRUPT_VNE_INT_SHIFT 16
    #define MIPS2_INTERRUPT_GVD_INT_MASK 0x00020000
    #define MIPS2_INTERRUPT_GVD_INT_SHIFT 17
    #define MIPS2_INTERRUPT_DVE_INT_MASK 0x00040000
    #define MIPS2_INTERRUPT_DVE_INT_SHIFT 18
    #define MIPS2_INTERRUPT_SATA_INT_MASK 0x00080000
    #define MIPS2_INTERRUPT_SATA_INT_SHIFT 19
    #define MIPS2_INTERRUPT_I2STX_INT_MASK 0x00100000
    #define MIPS2_INTERRUPT_I2STX_INT_SHIFT 20
    #define MIPS2_INTERRUPT_SPDIFRX_INT_MASK 0x00200000
    #define MIPS2_INTERRUPT_SPDIFRX_INT_SHIFT 21
    #define MIPS2_INTERRUPT_SPDIFTX_INT_MASK 0x00400000
    #define MIPS2_INTERRUPT_SPDIFTX_INT_SHIFT 22
    #define MIPS2_INTERRUPT_EDC_INT_MASK 0x00800000
    #define MIPS2_INTERRUPT_EDC_INT_SHIFT 23
    #define MIPS2_INTERRUPT_DSCL_INT_MASK 0x01000000
    #define MIPS2_INTERRUPT_DSCL_INT_SHIFT 24
    #define MIPS2_INTERRUPT_EE_INT_MASK 0x02000000
    #define MIPS2_INTERRUPT_EE_INT_SHIFT 25
    #define MIPS2_INTERRUPT_NFC_INT_MASK 0x04000000
    #define MIPS2_INTERRUPT_NFC_INT_SHIFT 26
#define  MIPS2_INTERRUPT1 0x0524
    #define MIPS2_INTERRUPT1_SMS_INT_MASK 0x00000001
    #define MIPS2_INTERRUPT1_SMS_INT_SHIFT 0
    #define MIPS2_INTERRUPT1_VNH_INT_MASK 0x00000002
    #define MIPS2_INTERRUPT1_VNH_INT_SHIFT 1
    #define MIPS2_INTERRUPT1_DISP_INT_MASK 0x00000004
    #define MIPS2_INTERRUPT1_DISP_INT_SHIFT 2
    #define MIPS2_INTERRUPT1_MAD_INT_MASK 0x00000008
    #define MIPS2_INTERRUPT1_MAD_INT_SHIFT 3
    #define MIPS2_INTERRUPT1_GIC_INT_MASK 0x00000010
    #define MIPS2_INTERRUPT1_GIC_INT_SHIFT 4
    #define MIPS2_INTERRUPT1_FES_INT_MASK 0x00000020
    #define MIPS2_INTERRUPT1_FES_INT_SHIFT 5
    #define MIPS2_INTERRUPT1_G2D_INT_MASK 0x00000040
    #define MIPS2_INTERRUPT1_G2D_INT_SHIFT 6
    #define MIPS2_INTERRUPT1_IRC_INT_MASK 0x00000080
    #define MIPS2_INTERRUPT1_IRC_INT_SHIFT 7
    #define MIPS2_INTERRUPT1_NRFC_INT_MASK 0x00000100
    #define MIPS2_INTERRUPT1_NRFC_INT_SHIFT 8
    #define MIPS2_INTERRUPT1_SMCC_INT_MASK 0x00000200
    #define MIPS2_INTERRUPT1_SMCC_INT_SHIFT 9
    #define MIPS2_INTERRUPT1_MAFE_INT_MASK 0x00000400
    #define MIPS2_INTERRUPT1_MAFE_INT_SHIFT 10
    #define MIPS2_INTERRUPT1_RMX1_INT_MASK 0x00000800
    #define MIPS2_INTERRUPT1_RMX1_INT_SHIFT 11
    #define MIPS2_INTERRUPT1_G3D_INT_MASK 0x00001000
    #define MIPS2_INTERRUPT1_G3D_INT_SHIFT 12
    #define MIPS2_INTERRUPT1_UART0_INT_MASK 0x00002000
    #define MIPS2_INTERRUPT1_UART0_INT_SHIFT 13
    #define MIPS2_INTERRUPT1_UART1_INT_MASK 0x00004000
    #define MIPS2_INTERRUPT1_UART1_INT_SHIFT 14
    #define MIPS2_INTERRUPT1_INT15_MASK 0x00008000
    #define MIPS2_INTERRUPT1_INT15_SHIFT 15
    #define MIPS2_INTERRUPT1_INT16_MASK 0x00010000
    #define MIPS2_INTERRUPT1_INT16_SHIFT 16
    #define MIPS2_INTERRUPT1_INT17_MASK 0x00020000
    #define MIPS2_INTERRUPT1_INT17_SHIFT 17
    #define MIPS2_INTERRUPT1_INT18_MASK 0x00040000
    #define MIPS2_INTERRUPT1_INT18_SHIFT 18
    #define MIPS2_INTERRUPT1_INT19_MASK 0x00080000
    #define MIPS2_INTERRUPT1_INT19_SHIFT 19
    #define MIPS2_INTERRUPT1_INT20_MASK 0x00100000
    #define MIPS2_INTERRUPT1_INT20_SHIFT 20
    #define MIPS2_INTERRUPT1_INT21_MASK 0x00200000
    #define MIPS2_INTERRUPT1_INT21_SHIFT 21
    #define MIPS2_INTERRUPT1_INT22_MASK 0x00400000
    #define MIPS2_INTERRUPT1_INT22_SHIFT 22
    #define MIPS2_INTERRUPT1_INT23_MASK 0x00800000
    #define MIPS2_INTERRUPT1_INT23_SHIFT 23
    #define MIPS2_INTERRUPT1_INT24_MASK 0x01000000
    #define MIPS2_INTERRUPT1_INT24_SHIFT 24
    #define MIPS2_INTERRUPT1_INT25_MASK 0x02000000
    #define MIPS2_INTERRUPT1_INT25_SHIFT 25
    #define MIPS2_INTERRUPT1_INT26_MASK 0x04000000
    #define MIPS2_INTERRUPT1_INT26_SHIFT 26
    #define MIPS2_INTERRUPT1_INT27_MASK 0x08000000
    #define MIPS2_INTERRUPT1_INT27_SHIFT 27
    #define MIPS2_INTERRUPT1_INT28_MASK 0x10000000
    #define MIPS2_INTERRUPT1_INT28_SHIFT 28
    #define MIPS2_INTERRUPT1_INT29_MASK 0x20000000
    #define MIPS2_INTERRUPT1_INT29_SHIFT 29
    #define MIPS2_INTERRUPT1_INT30_MASK 0x40000000
    #define MIPS2_INTERRUPT1_INT30_SHIFT 30
    #define MIPS2_INTERRUPT1_INT31_MASK 0x80000000
    #define MIPS2_INTERRUPT1_INT31_SHIFT 31
#define  MIPS2_INTERRUPT1_MASK 0x0528
    #define MIPS2_INTERRUPT1_MASK_SMS_INT_MASK 0x00000001
    #define MIPS2_INTERRUPT1_MASK_SMS_INT_SHIFT 0
    #define MIPS2_INTERRUPT1_MASK_VNH_INT_MASK 0x00000002
    #define MIPS2_INTERRUPT1_MASK_VNH_INT_SHIFT 1
    #define MIPS2_INTERRUPT1_MASK_DISP_INT_MASK 0x00000004
    #define MIPS2_INTERRUPT1_MASK_DISP_INT_SHIFT 2
    #define MIPS2_INTERRUPT1_MASK_MAD_INT_MASK 0x00000008
    #define MIPS2_INTERRUPT1_MASK_MAD_INT_SHIFT 3
    #define MIPS2_INTERRUPT1_MASK_GIC_INT_MASK 0x00000010
    #define MIPS2_INTERRUPT1_MASK_GIC_INT_SHIFT 4
    #define MIPS2_INTERRUPT1_MASK_FES_INT_MASK 0x00000020
    #define MIPS2_INTERRUPT1_MASK_FES_INT_SHIFT 5
    #define MIPS2_INTERRUPT1_MASK_G2D_INT_MASK 0x00000040
    #define MIPS2_INTERRUPT1_MASK_G2D_INT_SHIFT 6
    #define MIPS2_INTERRUPT1_MASK_IRC_INT_MASK 0x00000080
    #define MIPS2_INTERRUPT1_MASK_IRC_INT_SHIFT 7
    #define MIPS2_INTERRUPT1_MASK_NRFC_INT_MASK 0x00000100
    #define MIPS2_INTERRUPT1_MASK_NRFC_INT_SHIFT 8
    #define MIPS2_INTERRUPT1_MASK_SMCC_INT_MASK 0x00000200
    #define MIPS2_INTERRUPT1_MASK_SMCC_INT_SHIFT 9
    #define MIPS2_INTERRUPT1_MASK_MAFE_INT_MASK 0x00000400
    #define MIPS2_INTERRUPT1_MASK_MAFE_INT_SHIFT 10
    #define MIPS2_INTERRUPT1_MASK_RMX1_INT_MASK 0x00000800
    #define MIPS2_INTERRUPT1_MASK_RMX1_INT_SHIFT 11
    #define MIPS2_INTERRUPT1_MASK_G3D_INT_MASK 0x00001000
    #define MIPS2_INTERRUPT1_MASK_G3D_INT_SHIFT 12
    #define MIPS2_INTERRUPT1_MASK_UART0_INT_MASK 0x00002000
    #define MIPS2_INTERRUPT1_MASK_UART0_INT_SHIFT 13
    #define MIPS2_INTERRUPT1_MASK_UART1_INT_MASK 0x00004000
    #define MIPS2_INTERRUPT1_MASK_UART1_INT_SHIFT 14
    #define MIPS2_INTERRUPT1_MASK_INT15_MASK 0x00008000
    #define MIPS2_INTERRUPT1_MASK_INT15_SHIFT 15
    #define MIPS2_INTERRUPT1_MASK_INT16_MASK 0x00010000
    #define MIPS2_INTERRUPT1_MASK_INT16_SHIFT 16
    #define MIPS2_INTERRUPT1_MASK_INT17_MASK 0x00020000
    #define MIPS2_INTERRUPT1_MASK_INT17_SHIFT 17
    #define MIPS2_INTERRUPT1_MASK_INT18_MASK 0x00040000
    #define MIPS2_INTERRUPT1_MASK_INT18_SHIFT 18
    #define MIPS2_INTERRUPT1_MASK_INT19_MASK 0x00080000
    #define MIPS2_INTERRUPT1_MASK_INT19_SHIFT 19
    #define MIPS2_INTERRUPT1_MASK_INT20_MASK 0x00100000
    #define MIPS2_INTERRUPT1_MASK_INT20_SHIFT 20
    #define MIPS2_INTERRUPT1_MASK_INT21_MASK 0x00200000
    #define MIPS2_INTERRUPT1_MASK_INT21_SHIFT 21
    #define MIPS2_INTERRUPT1_MASK_INT22_MASK 0x00400000
    #define MIPS2_INTERRUPT1_MASK_INT22_SHIFT 22
    #define MIPS2_INTERRUPT1_MASK_INT23_MASK 0x00800000
    #define MIPS2_INTERRUPT1_MASK_INT23_SHIFT 23
    #define MIPS2_INTERRUPT1_MASK_INT24_MASK 0x01000000
    #define MIPS2_INTERRUPT1_MASK_INT24_SHIFT 24
    #define MIPS2_INTERRUPT1_MASK_INT25_MASK 0x02000000
    #define MIPS2_INTERRUPT1_MASK_INT25_SHIFT 25
    #define MIPS2_INTERRUPT1_MASK_INT26_MASK 0x04000000
    #define MIPS2_INTERRUPT1_MASK_INT26_SHIFT 26
    #define MIPS2_INTERRUPT1_MASK_INT27_MASK 0x08000000
    #define MIPS2_INTERRUPT1_MASK_INT27_SHIFT 27
    #define MIPS2_INTERRUPT1_MASK_INT28_MASK 0x10000000
    #define MIPS2_INTERRUPT1_MASK_INT28_SHIFT 28
    #define MIPS2_INTERRUPT1_MASK_INT29_MASK 0x20000000
    #define MIPS2_INTERRUPT1_MASK_INT29_SHIFT 29
    #define MIPS2_INTERRUPT1_MASK_INT30_MASK 0x40000000
    #define MIPS2_INTERRUPT1_MASK_INT30_SHIFT 30
    #define MIPS2_INTERRUPT1_MASK_INT31_MASK 0x80000000
    #define MIPS2_INTERRUPT1_MASK_INT31_SHIFT 31
#define  MIPS2_INTERRUPT_MASK 0x0430
    #define MIPS2_INTERRUPT_MASK_TSD_INT0_MASK 0x00000001
    #define MIPS2_INTERRUPT_MASK_TSD_INT0_SHIFT 0
    #define MIPS2_INTERRUPT_MASK_TSD_INT1_MASK 0x00000002
    #define MIPS2_INTERRUPT_MASK_TSD_INT1_SHIFT 1
    #define MIPS2_INTERRUPT_MASK_USBD_INT_MASK 0x00000004
    #define MIPS2_INTERRUPT_MASK_USBD_INT_SHIFT 2
    #define MIPS2_INTERRUPT_MASK_USBH_INT_MASK 0x00000008
    #define MIPS2_INTERRUPT_MASK_USBH_INT_SHIFT 3
    #define MIPS2_INTERRUPT_MASK_TSD_INT4_MASK 0x00000010
    #define MIPS2_INTERRUPT_MASK_TSD_INT4_SHIFT 4
    #define MIPS2_INTERRUPT_MASK_ETH0_INT_MASK 0x00000020
    #define MIPS2_INTERRUPT_MASK_ETH0_INT_SHIFT 5
    #define MIPS2_INTERRUPT_MASK_ETH1_INT_MASK 0x00000040
    #define MIPS2_INTERRUPT_MASK_ETH1_INT_SHIFT 6
    #define MIPS2_INTERRUPT_MASK_PPC_INT_MASK 0x00000080
    #define MIPS2_INTERRUPT_MASK_PPC_INT_SHIFT 7
    #define MIPS2_INTERRUPT_MASK_DMA_INT_MASK 0x00000100
    #define MIPS2_INTERRUPT_MASK_DMA_INT_SHIFT 8
    #define MIPS2_INTERRUPT_MASK_RBM_INT_MASK 0x00000200
    #define MIPS2_INTERRUPT_MASK_RBM_INT_SHIFT 9
    #define MIPS2_INTERRUPT_MASK_MPP_INT_MASK 0x00000400
    #define MIPS2_INTERRUPT_MASK_MPP_INT_SHIFT 10
    #define MIPS2_INTERRUPT_MASK_RSA_INT_MASK 0x00000800
    #define MIPS2_INTERRUPT_MASK_RSA_INT_SHIFT 11
    #define MIPS2_INTERRUPT_MASK_I2S_INT_MASK 0x00001000
    #define MIPS2_INTERRUPT_MASK_I2S_INT_SHIFT 12
    #define MIPS2_INTERRUPT_MASK_RMX_INT_MASK 0x00002000
    #define MIPS2_INTERRUPT_MASK_RMX_INT_SHIFT 13
    #define MIPS2_INTERRUPT_MASK_VHE_INT_MASK 0x00004000
    #define MIPS2_INTERRUPT_MASK_VHE_INT_SHIFT 14
    #define MIPS2_INTERRUPT_MASK_VFE_INT_MASK 0x00008000
    #define MIPS2_INTERRUPT_MASK_VFE_INT_SHIFT 15
    #define MIPS2_INTERRUPT_MASK_VNE_INT_MASK 0x00010000
    #define MIPS2_INTERRUPT_MASK_VNE_INT_SHIFT 16
    #define MIPS2_INTERRUPT_MASK_GVD_INT_MASK 0x00020000
    #define MIPS2_INTERRUPT_MASK_GVD_INT_SHIFT 17
    #define MIPS2_INTERRUPT_MASK_DVE_INT_MASK 0x00040000
    #define MIPS2_INTERRUPT_MASK_DVE_INT_SHIFT 18
    #define MIPS2_INTERRUPT_MASK_SATA_INT_MASK 0x00080000
    #define MIPS2_INTERRUPT_MASK_SATA_INT_SHIFT 19
    #define MIPS2_INTERRUPT_MASK_I2STX_INT_MASK 0x00100000
    #define MIPS2_INTERRUPT_MASK_I2STX_INT_SHIFT 20
    #define MIPS2_INTERRUPT_MASK_SPDIFRX_INT_MASK 0x00200000
    #define MIPS2_INTERRUPT_MASK_SPDIFRX_INT_SHIFT 21
    #define MIPS2_INTERRUPT_MASK_SPDIFTX_INT_MASK 0x00400000
    #define MIPS2_INTERRUPT_MASK_SPDIFTX_INT_SHIFT 22
    #define MIPS2_INTERRUPT_MASK_EDC_INT_MASK 0x00800000
    #define MIPS2_INTERRUPT_MASK_EDC_INT_SHIFT 23
    #define MIPS2_INTERRUPT_MASK_DSCL_INT_MASK 0x01000000
    #define MIPS2_INTERRUPT_MASK_DSCL_INT_SHIFT 24
    #define MIPS2_INTERRUPT_MASK_EE_INT_MASK 0x02000000
    #define MIPS2_INTERRUPT_MASK_EE_INT_SHIFT 25
    #define MIPS2_INTERRUPT_MASK_NFC_INT_MASK 0x04000000
    #define MIPS2_INTERRUPT_MASK_NFC_INT_SHIFT 26
#define  MIPS2_IPC_CALL 0x38F0
    #define MIPS2_IPC_CALL_DATA_MASK 0xFFFFFFFF
    #define MIPS2_IPC_CALL_DATA_SHIFT 0
#define  MIPS2_MIPS_INT_MASK 0x38EC
    #define MIPS2_MIPS_INT_MASK_INT_EN_INBOUND_CALL0_MASK 0x00000001
    #define MIPS2_MIPS_INT_MASK_INT_EN_INBOUND_CALL0_SHIFT 0
    #define MIPS2_MIPS_INT_MASK_INT_EN_INBOUND_CALL1_MASK 0x00000002
    #define MIPS2_MIPS_INT_MASK_INT_EN_INBOUND_CALL1_SHIFT 1
    #define INT_EN_INBOUND_DBG_MASK 0x00000004
    #define INT_EN_INBOUND_DBG_SHIFT 2
    #define MIPS2_MIPS_INT_MASK_INT_EN_IPC_CALL_MASK 0x00000008
    #define MIPS2_MIPS_INT_MASK_INT_EN_IPC_CALL_SHIFT 3
#define  MIPS2_MIPS_INT_STATUS 0x38E8
    #define MIPS2_MIPS_INT_STATUS_INBOUND_CALL0_MASK 0x00000001
    #define MIPS2_MIPS_INT_STATUS_INBOUND_CALL0_SHIFT 0
    #define MIPS2_MIPS_INT_STATUS_INBOUND_CALL1_MASK 0x00000002
    #define MIPS2_MIPS_INT_STATUS_INBOUND_CALL1_SHIFT 1
    #define INBOUND_DBG_MASK 0x00000004
    #define INBOUND_DBG_SHIFT 2
    #define MIPS2_MIPS_INT_STATUS_IPC_CALL_MASK 0x00000008
    #define MIPS2_MIPS_INT_STATUS_IPC_CALL_SHIFT 3
#define  MIPS2_MISC_STATUS 0x3890
    #define SI_ERL_MASK 0x00000001
    #define SI_ERL_SHIFT 0
    #define EB_BLAST_MASK 0x00000002
    #define EB_BLAST_SHIFT 1
    #define EB_INSTR_MASK 0x00000004
    #define EB_INSTR_SHIFT 2
    #define SI_SLEEP_MASK 0x00000008
    #define SI_SLEEP_SHIFT 3
    #define SI_RP_MASK 0x00000010
    #define SI_RP_SHIFT 4
    #define SI_EXL_MASK 0x00000020
    #define SI_EXL_SHIFT 5
#define  MIPS2_MMREG_APER 0x3808
    #define MIPS2_MMREG_APER_BASE_MASK 0x00001FFF
    #define MIPS2_MMREG_APER_BASE_SHIFT 0
    #define MIPS2_MMREG_APER_SIZE_MASK 0x1FFF0000
    #define MIPS2_MMREG_APER_SIZE_SHIFT 16
#define  MIPS2_MSG_DATA_0 0x3830
    #define MIPS2_MSG_DATA_0_DATA_MASK 0xFFFFFFFF
    #define MIPS2_MSG_DATA_0_DATA_SHIFT 0
#define  MIPS2_MSG_DATA_1 0x3834
    #define MIPS2_MSG_DATA_1_DATA_MASK 0xFFFFFFFF
    #define MIPS2_MSG_DATA_1_DATA_SHIFT 0
#define  MIPS2_MSG_DATA_10 0x3858
    #define MIPS2_MSG_DATA_10_DATA_MASK 0xFFFFFFFF
    #define MIPS2_MSG_DATA_10_DATA_SHIFT 0
#define  MIPS2_MSG_DATA_11 0x385C
    #define MIPS2_MSG_DATA_11_DATA_MASK 0xFFFFFFFF
    #define MIPS2_MSG_DATA_11_DATA_SHIFT 0
#define  MIPS2_MSG_DATA_2 0x3838
    #define MIPS2_MSG_DATA_2_DATA_MASK 0xFFFFFFFF
    #define MIPS2_MSG_DATA_2_DATA_SHIFT 0
#define  MIPS2_MSG_DATA_3 0x383C
    #define MIPS2_MSG_DATA_3_DATA_MASK 0xFFFFFFFF
    #define MIPS2_MSG_DATA_3_DATA_SHIFT 0
#define  MIPS2_MSG_DATA_4 0x3840
    #define MIPS2_MSG_DATA_4_DATA_MASK 0xFFFFFFFF
    #define MIPS2_MSG_DATA_4_DATA_SHIFT 0
#define  MIPS2_MSG_DATA_5 0x3844
    #define MIPS2_MSG_DATA_5_DATA_MASK 0xFFFFFFFF
    #define MIPS2_MSG_DATA_5_DATA_SHIFT 0
#define  MIPS2_MSG_DATA_6 0x3848
    #define MIPS2_MSG_DATA_6_DATA_MASK 0xFFFFFFFF
    #define MIPS2_MSG_DATA_6_DATA_SHIFT 0
#define  MIPS2_MSG_DATA_7 0x384C
    #define MIPS2_MSG_DATA_7_DATA_MASK 0xFFFFFFFF
    #define MIPS2_MSG_DATA_7_DATA_SHIFT 0
#define  MIPS2_MSG_DATA_8 0x3850
    #define MIPS2_MSG_DATA_8_DATA_MASK 0xFFFFFFFF
    #define MIPS2_MSG_DATA_8_DATA_SHIFT 0
#define  MIPS2_MSG_DATA_9 0x3854
    #define MIPS2_MSG_DATA_9_DATA_MASK 0xFFFFFFFF
    #define MIPS2_MSG_DATA_9_DATA_SHIFT 0
#define  MIPS2_NMI_TRIG 0x3870
    #define MIPS2_NMI_TRIG_NODATA_MASK 0x00000001
    #define MIPS2_NMI_TRIG_NODATA_SHIFT 0
#define  MIPS2_OUTBOUND_CALL_0 0x3828
    #define MIPS2_OUTBOUND_CALL_0_DATA_MASK 0xFFFFFFFF
    #define MIPS2_OUTBOUND_CALL_0_DATA_SHIFT 0
#define  MIPS2_OUTBOUND_CALL_1 0x382C
    #define MIPS2_OUTBOUND_CALL_1_DATA_MASK 0xFFFFFFFF
    #define MIPS2_OUTBOUND_CALL_1_DATA_SHIFT 0
#define  MIPS2_PERF_CNTA_STAT 0x3888
    #define MIPS2_PERF_CNTA_STAT_DATA_MASK 0xFFFFFFFF
    #define MIPS2_PERF_CNTA_STAT_DATA_SHIFT 0
#define  MIPS2_PERF_CNTB_STAT 0x388C
    #define MIPS2_PERF_CNTB_STAT_DATA_MASK 0xFFFFFFFF
    #define MIPS2_PERF_CNTB_STAT_DATA_SHIFT 0
#define  MIPS2_RST 0x38F8
    #define MIPS2_RST_SOFT_RSTN_MASK 0x00000001
    #define MIPS2_RST_SOFT_RSTN_SHIFT 0
    #define HARD_RSTN_MASK 0x00000002
    #define HARD_RSTN_SHIFT 1
#define  MIPS2_SHADOW_IBB_CTRL 0x38B0
    #define MIPS2_SHADOW_IBB_CTRL_SHADOW_IBB_CTRL_MASK 0xFFFFFFFF
    #define MIPS2_SHADOW_IBB_CTRL_SHADOW_IBB_CTRL_SHIFT 0
#define  MIPS2_SHADOW_IBB_RB_ADR 0x38B8
    #define MIPS2_SHADOW_IBB_RB_ADR_SHADOW_IBB_RB_ADR_MASK 0xFFFFFFFF
    #define MIPS2_SHADOW_IBB_RB_ADR_SHADOW_IBB_RB_ADR_SHIFT 0
#define  MIPS2_SHADOW_IBB_RB_HEAD 0x38C8
    #define MIPS2_SHADOW_IBB_RB_HEAD_SHADOW_IBB_RB_HEAD_MASK 0xFFFFFFFF
    #define MIPS2_SHADOW_IBB_RB_HEAD_SHADOW_IBB_RB_HEAD_SHIFT 0
#define  MIPS2_SHADOW_IBB_RB_TAIL 0x38BC
    #define MIPS2_SHADOW_IBB_RB_TAIL_SHADOW_IBB_RB_TAIL_MASK 0xFFFFFFFF
    #define MIPS2_SHADOW_IBB_RB_TAIL_SHADOW_IBB_RB_TAIL_SHIFT 0
#define  MIPS2_SHADOW_IBB_RB_TAIL_READ 0x38C0
    #define MIPS2_SHADOW_IBB_RB_TAIL_READ_SHADOW_IBB_RB_TAIL_READ_MASK 0xFFFFFFFF
    #define MIPS2_SHADOW_IBB_RB_TAIL_READ_SHADOW_IBB_RB_TAIL_READ_SHIFT 0
#define  MIPS2_SPRAM_RM 0x3814
    #define IDATA_MASK 0x0000000F
    #define IDATA_SHIFT 0
    #define ITAG_MASK 0x000000F0
    #define ITAG_SHIFT 4
    #define DDATA_MASK 0x00000F00
    #define DDATA_SHIFT 8
    #define DTAG_MASK 0x0000F000
    #define DTAG_SHIFT 12
    #define DWS_MASK 0x0F000000
    #define DWS_SHIFT 24
    #define IWS_MASK 0xF0000000
    #define IWS_SHIFT 28
#define  MIPS2_STATIC_CONFIG 0x3810
    #define MIPS2_STATIC_CONFIG_ENDIAN_MASK 0x00000001
    #define MIPS2_STATIC_CONFIG_ENDIAN_SHIFT 0
    #define MERGE_MODE_MASK 0x00000006
    #define MERGE_MODE_SHIFT 1
    #define PERF_CNTA_MUX_MASK 0x000000F0
    #define PERF_CNTA_MUX_SHIFT 4
    #define PERF_CNTA_EN_MASK 0x00000100
    #define PERF_CNTA_EN_SHIFT 8
    #define PERF_CNTB_MUX_MASK 0x00001E00
    #define PERF_CNTB_MUX_SHIFT 9
    #define PERF_CNTB_EN_MASK 0x00002000
    #define PERF_CNTB_EN_SHIFT 13
    #define SPRAM_DELAY_MASK 0x00004000
    #define SPRAM_DELAY_SHIFT 14
    #define SIMPLEBE_MASK 0x00030000
    #define SIMPLEBE_SHIFT 16
#define  MIPS2_WATCHDOG_CNT 0x3880
    #define MIPS2_WATCHDOG_CNT_DATA_MASK 0xFFFFFFFF
    #define MIPS2_WATCHDOG_CNT_DATA_SHIFT 0
#define  MIPS2_WATCHDOG_COMPARE 0x3884
    #define MIPS2_WATCHDOG_COMPARE_DATA_MASK 0xFFFFFFFF
    #define MIPS2_WATCHDOG_COMPARE_DATA_SHIFT 0
#define  MIPS3_INTERRUPT 0x04D0
    #define MIPS3_INTERRUPT_TSD_INT0_MASK 0x00000001
    #define MIPS3_INTERRUPT_TSD_INT0_SHIFT 0
    #define MIPS3_INTERRUPT_TSD_INT1_MASK 0x00000002
    #define MIPS3_INTERRUPT_TSD_INT1_SHIFT 1
    #define MIPS3_INTERRUPT_USBD_INT_MASK 0x00000004
    #define MIPS3_INTERRUPT_USBD_INT_SHIFT 2
    #define MIPS3_INTERRUPT_USBH_INT_MASK 0x00000008
    #define MIPS3_INTERRUPT_USBH_INT_SHIFT 3
    #define MIPS3_INTERRUPT_TSD_INT4_MASK 0x00000010
    #define MIPS3_INTERRUPT_TSD_INT4_SHIFT 4
    #define MIPS3_INTERRUPT_ETH0_INT_MASK 0x00000020
    #define MIPS3_INTERRUPT_ETH0_INT_SHIFT 5
    #define MIPS3_INTERRUPT_ETH1_INT_MASK 0x00000040
    #define MIPS3_INTERRUPT_ETH1_INT_SHIFT 6
    #define MIPS3_INTERRUPT_PPC_INT_MASK 0x00000080
    #define MIPS3_INTERRUPT_PPC_INT_SHIFT 7
    #define MIPS3_INTERRUPT_DMA_INT_MASK 0x00000100
    #define MIPS3_INTERRUPT_DMA_INT_SHIFT 8
    #define MIPS3_INTERRUPT_RBM_INT_MASK 0x00000200
    #define MIPS3_INTERRUPT_RBM_INT_SHIFT 9
    #define MIPS3_INTERRUPT_MPP_INT_MASK 0x00000400
    #define MIPS3_INTERRUPT_MPP_INT_SHIFT 10
    #define MIPS3_INTERRUPT_RSA_INT_MASK 0x00000800
    #define MIPS3_INTERRUPT_RSA_INT_SHIFT 11
    #define MIPS3_INTERRUPT_I2S_INT_MASK 0x00001000
    #define MIPS3_INTERRUPT_I2S_INT_SHIFT 12
    #define MIPS3_INTERRUPT_RMX_INT_MASK 0x00002000
    #define MIPS3_INTERRUPT_RMX_INT_SHIFT 13
    #define MIPS3_INTERRUPT_VHE_INT_MASK 0x00004000
    #define MIPS3_INTERRUPT_VHE_INT_SHIFT 14
    #define MIPS3_INTERRUPT_VFE_INT_MASK 0x00008000
    #define MIPS3_INTERRUPT_VFE_INT_SHIFT 15
    #define MIPS3_INTERRUPT_VNE_INT_MASK 0x00010000
    #define MIPS3_INTERRUPT_VNE_INT_SHIFT 16
    #define MIPS3_INTERRUPT_GVD_INT_MASK 0x00020000
    #define MIPS3_INTERRUPT_GVD_INT_SHIFT 17
    #define MIPS3_INTERRUPT_DVE_INT_MASK 0x00040000
    #define MIPS3_INTERRUPT_DVE_INT_SHIFT 18
    #define MIPS3_INTERRUPT_SATA_INT_MASK 0x00080000
    #define MIPS3_INTERRUPT_SATA_INT_SHIFT 19
    #define MIPS3_INTERRUPT_I2STX_INT_MASK 0x00100000
    #define MIPS3_INTERRUPT_I2STX_INT_SHIFT 20
    #define MIPS3_INTERRUPT_SPDIFRX_INT_MASK 0x00200000
    #define MIPS3_INTERRUPT_SPDIFRX_INT_SHIFT 21
    #define MIPS3_INTERRUPT_SPDIFTX_INT_MASK 0x00400000
    #define MIPS3_INTERRUPT_SPDIFTX_INT_SHIFT 22
    #define MIPS3_INTERRUPT_EDC_INT_MASK 0x00800000
    #define MIPS3_INTERRUPT_EDC_INT_SHIFT 23
    #define MIPS3_INTERRUPT_DSCL_INT_MASK 0x01000000
    #define MIPS3_INTERRUPT_DSCL_INT_SHIFT 24
    #define MIPS3_INTERRUPT_EE_INT_MASK 0x02000000
    #define MIPS3_INTERRUPT_EE_INT_SHIFT 25
    #define MIPS3_INTERRUPT_NFC_INT_MASK 0x04000000
    #define MIPS3_INTERRUPT_NFC_INT_SHIFT 26
#define  MIPS3_INTERRUPT1 0x052C
    #define MIPS3_INTERRUPT1_SMS_INT_MASK 0x00000001
    #define MIPS3_INTERRUPT1_SMS_INT_SHIFT 0
    #define MIPS3_INTERRUPT1_VNH_INT_MASK 0x00000002
    #define MIPS3_INTERRUPT1_VNH_INT_SHIFT 1
    #define MIPS3_INTERRUPT1_DISP_INT_MASK 0x00000004
    #define MIPS3_INTERRUPT1_DISP_INT_SHIFT 2
    #define MIPS3_INTERRUPT1_MAD_INT_MASK 0x00000008
    #define MIPS3_INTERRUPT1_MAD_INT_SHIFT 3
    #define MIPS3_INTERRUPT1_GIC_INT_MASK 0x00000010
    #define MIPS3_INTERRUPT1_GIC_INT_SHIFT 4
    #define MIPS3_INTERRUPT1_FES_INT_MASK 0x00000020
    #define MIPS3_INTERRUPT1_FES_INT_SHIFT 5
    #define MIPS3_INTERRUPT1_G2D_INT_MASK 0x00000040
    #define MIPS3_INTERRUPT1_G2D_INT_SHIFT 6
    #define MIPS3_INTERRUPT1_IRC_INT_MASK 0x00000080
    #define MIPS3_INTERRUPT1_IRC_INT_SHIFT 7
    #define MIPS3_INTERRUPT1_NRFC_INT_MASK 0x00000100
    #define MIPS3_INTERRUPT1_NRFC_INT_SHIFT 8
    #define MIPS3_INTERRUPT1_SMCC_INT_MASK 0x00000200
    #define MIPS3_INTERRUPT1_SMCC_INT_SHIFT 9
    #define MIPS3_INTERRUPT1_MAFE_INT_MASK 0x00000400
    #define MIPS3_INTERRUPT1_MAFE_INT_SHIFT 10
    #define MIPS3_INTERRUPT1_RMX1_INT_MASK 0x00000800
    #define MIPS3_INTERRUPT1_RMX1_INT_SHIFT 11
    #define MIPS3_INTERRUPT1_G3D_INT_MASK 0x00001000
    #define MIPS3_INTERRUPT1_G3D_INT_SHIFT 12
    #define MIPS3_INTERRUPT1_UART0_INT_MASK 0x00002000
    #define MIPS3_INTERRUPT1_UART0_INT_SHIFT 13
    #define MIPS3_INTERRUPT1_UART1_INT_MASK 0x00004000
    #define MIPS3_INTERRUPT1_UART1_INT_SHIFT 14
    #define MIPS3_INTERRUPT1_INT15_MASK 0x00008000
    #define MIPS3_INTERRUPT1_INT15_SHIFT 15
    #define MIPS3_INTERRUPT1_INT16_MASK 0x00010000
    #define MIPS3_INTERRUPT1_INT16_SHIFT 16
    #define MIPS3_INTERRUPT1_INT17_MASK 0x00020000
    #define MIPS3_INTERRUPT1_INT17_SHIFT 17
    #define MIPS3_INTERRUPT1_INT18_MASK 0x00040000
    #define MIPS3_INTERRUPT1_INT18_SHIFT 18
    #define MIPS3_INTERRUPT1_INT19_MASK 0x00080000
    #define MIPS3_INTERRUPT1_INT19_SHIFT 19
    #define MIPS3_INTERRUPT1_INT20_MASK 0x00100000
    #define MIPS3_INTERRUPT1_INT20_SHIFT 20
    #define MIPS3_INTERRUPT1_INT21_MASK 0x00200000
    #define MIPS3_INTERRUPT1_INT21_SHIFT 21
    #define MIPS3_INTERRUPT1_INT22_MASK 0x00400000
    #define MIPS3_INTERRUPT1_INT22_SHIFT 22
    #define MIPS3_INTERRUPT1_INT23_MASK 0x00800000
    #define MIPS3_INTERRUPT1_INT23_SHIFT 23
    #define MIPS3_INTERRUPT1_INT24_MASK 0x01000000
    #define MIPS3_INTERRUPT1_INT24_SHIFT 24
    #define MIPS3_INTERRUPT1_INT25_MASK 0x02000000
    #define MIPS3_INTERRUPT1_INT25_SHIFT 25
    #define MIPS3_INTERRUPT1_INT26_MASK 0x04000000
    #define MIPS3_INTERRUPT1_INT26_SHIFT 26
    #define MIPS3_INTERRUPT1_INT27_MASK 0x08000000
    #define MIPS3_INTERRUPT1_INT27_SHIFT 27
    #define MIPS3_INTERRUPT1_INT28_MASK 0x10000000
    #define MIPS3_INTERRUPT1_INT28_SHIFT 28
    #define MIPS3_INTERRUPT1_INT29_MASK 0x20000000
    #define MIPS3_INTERRUPT1_INT29_SHIFT 29
    #define MIPS3_INTERRUPT1_INT30_MASK 0x40000000
    #define MIPS3_INTERRUPT1_INT30_SHIFT 30
    #define MIPS3_INTERRUPT1_INT31_MASK 0x80000000
    #define MIPS3_INTERRUPT1_INT31_SHIFT 31
#define  MIPS3_INTERRUPT1_MASK 0x0530
    #define MIPS3_INTERRUPT1_MASK_SMS_INT_MASK 0x00000001
    #define MIPS3_INTERRUPT1_MASK_SMS_INT_SHIFT 0
    #define MIPS3_INTERRUPT1_MASK_VNH_INT_MASK 0x00000002
    #define MIPS3_INTERRUPT1_MASK_VNH_INT_SHIFT 1
    #define MIPS3_INTERRUPT1_MASK_DISP_INT_MASK 0x00000004
    #define MIPS3_INTERRUPT1_MASK_DISP_INT_SHIFT 2
    #define MIPS3_INTERRUPT1_MASK_MAD_INT_MASK 0x00000008
    #define MIPS3_INTERRUPT1_MASK_MAD_INT_SHIFT 3
    #define MIPS3_INTERRUPT1_MASK_GIC_INT_MASK 0x00000010
    #define MIPS3_INTERRUPT1_MASK_GIC_INT_SHIFT 4
    #define MIPS3_INTERRUPT1_MASK_FES_INT_MASK 0x00000020
    #define MIPS3_INTERRUPT1_MASK_FES_INT_SHIFT 5
    #define MIPS3_INTERRUPT1_MASK_G2D_INT_MASK 0x00000040
    #define MIPS3_INTERRUPT1_MASK_G2D_INT_SHIFT 6
    #define MIPS3_INTERRUPT1_MASK_IRC_INT_MASK 0x00000080
    #define MIPS3_INTERRUPT1_MASK_IRC_INT_SHIFT 7
    #define MIPS3_INTERRUPT1_MASK_NRFC_INT_MASK 0x00000100
    #define MIPS3_INTERRUPT1_MASK_NRFC_INT_SHIFT 8
    #define MIPS3_INTERRUPT1_MASK_SMCC_INT_MASK 0x00000200
    #define MIPS3_INTERRUPT1_MASK_SMCC_INT_SHIFT 9
    #define MIPS3_INTERRUPT1_MASK_MAFE_INT_MASK 0x00000400
    #define MIPS3_INTERRUPT1_MASK_MAFE_INT_SHIFT 10
    #define MIPS3_INTERRUPT1_MASK_RMX1_INT_MASK 0x00000800
    #define MIPS3_INTERRUPT1_MASK_RMX1_INT_SHIFT 11
    #define MIPS3_INTERRUPT1_MASK_G3D_INT_MASK 0x00001000
    #define MIPS3_INTERRUPT1_MASK_G3D_INT_SHIFT 12
    #define MIPS3_INTERRUPT1_MASK_UART0_INT_MASK 0x00002000
    #define MIPS3_INTERRUPT1_MASK_UART0_INT_SHIFT 13
    #define MIPS3_INTERRUPT1_MASK_UART1_INT_MASK 0x00004000
    #define MIPS3_INTERRUPT1_MASK_UART1_INT_SHIFT 14
    #define MIPS3_INTERRUPT1_MASK_INT15_MASK 0x00008000
    #define MIPS3_INTERRUPT1_MASK_INT15_SHIFT 15
    #define MIPS3_INTERRUPT1_MASK_INT16_MASK 0x00010000
    #define MIPS3_INTERRUPT1_MASK_INT16_SHIFT 16
    #define MIPS3_INTERRUPT1_MASK_INT17_MASK 0x00020000
    #define MIPS3_INTERRUPT1_MASK_INT17_SHIFT 17
    #define MIPS3_INTERRUPT1_MASK_INT18_MASK 0x00040000
    #define MIPS3_INTERRUPT1_MASK_INT18_SHIFT 18
    #define MIPS3_INTERRUPT1_MASK_INT19_MASK 0x00080000
    #define MIPS3_INTERRUPT1_MASK_INT19_SHIFT 19
    #define MIPS3_INTERRUPT1_MASK_INT20_MASK 0x00100000
    #define MIPS3_INTERRUPT1_MASK_INT20_SHIFT 20
    #define MIPS3_INTERRUPT1_MASK_INT21_MASK 0x00200000
    #define MIPS3_INTERRUPT1_MASK_INT21_SHIFT 21
    #define MIPS3_INTERRUPT1_MASK_INT22_MASK 0x00400000
    #define MIPS3_INTERRUPT1_MASK_INT22_SHIFT 22
    #define MIPS3_INTERRUPT1_MASK_INT23_MASK 0x00800000
    #define MIPS3_INTERRUPT1_MASK_INT23_SHIFT 23
    #define MIPS3_INTERRUPT1_MASK_INT24_MASK 0x01000000
    #define MIPS3_INTERRUPT1_MASK_INT24_SHIFT 24
    #define MIPS3_INTERRUPT1_MASK_INT25_MASK 0x02000000
    #define MIPS3_INTERRUPT1_MASK_INT25_SHIFT 25
    #define MIPS3_INTERRUPT1_MASK_INT26_MASK 0x04000000
    #define MIPS3_INTERRUPT1_MASK_INT26_SHIFT 26
    #define MIPS3_INTERRUPT1_MASK_INT27_MASK 0x08000000
    #define MIPS3_INTERRUPT1_MASK_INT27_SHIFT 27
    #define MIPS3_INTERRUPT1_MASK_INT28_MASK 0x10000000
    #define MIPS3_INTERRUPT1_MASK_INT28_SHIFT 28
    #define MIPS3_INTERRUPT1_MASK_INT29_MASK 0x20000000
    #define MIPS3_INTERRUPT1_MASK_INT29_SHIFT 29
    #define MIPS3_INTERRUPT1_MASK_INT30_MASK 0x40000000
    #define MIPS3_INTERRUPT1_MASK_INT30_SHIFT 30
    #define MIPS3_INTERRUPT1_MASK_INT31_MASK 0x80000000
    #define MIPS3_INTERRUPT1_MASK_INT31_SHIFT 31
#define  MIPS3_INTERRUPT_MASK 0x04D4
    #define MIPS3_INTERRUPT_MASK_TSD_INT0_MASK 0x00000001
    #define MIPS3_INTERRUPT_MASK_TSD_INT0_SHIFT 0
    #define MIPS3_INTERRUPT_MASK_TSD_INT1_MASK 0x00000002
    #define MIPS3_INTERRUPT_MASK_TSD_INT1_SHIFT 1
    #define MIPS3_INTERRUPT_MASK_USBD_INT_MASK 0x00000004
    #define MIPS3_INTERRUPT_MASK_USBD_INT_SHIFT 2
    #define MIPS3_INTERRUPT_MASK_USBH_INT_MASK 0x00000008
    #define MIPS3_INTERRUPT_MASK_USBH_INT_SHIFT 3
    #define MIPS3_INTERRUPT_MASK_TSD_INT4_MASK 0x00000010
    #define MIPS3_INTERRUPT_MASK_TSD_INT4_SHIFT 4
    #define MIPS3_INTERRUPT_MASK_ETH0_INT_MASK 0x00000020
    #define MIPS3_INTERRUPT_MASK_ETH0_INT_SHIFT 5
    #define MIPS3_INTERRUPT_MASK_ETH1_INT_MASK 0x00000040
    #define MIPS3_INTERRUPT_MASK_ETH1_INT_SHIFT 6
    #define MIPS3_INTERRUPT_MASK_PPC_INT_MASK 0x00000080
    #define MIPS3_INTERRUPT_MASK_PPC_INT_SHIFT 7
    #define MIPS3_INTERRUPT_MASK_DMA_INT_MASK 0x00000100
    #define MIPS3_INTERRUPT_MASK_DMA_INT_SHIFT 8
    #define MIPS3_INTERRUPT_MASK_RBM_INT_MASK 0x00000200
    #define MIPS3_INTERRUPT_MASK_RBM_INT_SHIFT 9
    #define MIPS3_INTERRUPT_MASK_MPP_INT_MASK 0x00000400
    #define MIPS3_INTERRUPT_MASK_MPP_INT_SHIFT 10
    #define MIPS3_INTERRUPT_MASK_RSA_INT_MASK 0x00000800
    #define MIPS3_INTERRUPT_MASK_RSA_INT_SHIFT 11
    #define MIPS3_INTERRUPT_MASK_I2S_INT_MASK 0x00001000
    #define MIPS3_INTERRUPT_MASK_I2S_INT_SHIFT 12
    #define MIPS3_INTERRUPT_MASK_RMX_INT_MASK 0x00002000
    #define MIPS3_INTERRUPT_MASK_RMX_INT_SHIFT 13
    #define MIPS3_INTERRUPT_MASK_VHE_INT_MASK 0x00004000
    #define MIPS3_INTERRUPT_MASK_VHE_INT_SHIFT 14
    #define MIPS3_INTERRUPT_MASK_VFE_INT_MASK 0x00008000
    #define MIPS3_INTERRUPT_MASK_VFE_INT_SHIFT 15
    #define MIPS3_INTERRUPT_MASK_VNE_INT_MASK 0x00010000
    #define MIPS3_INTERRUPT_MASK_VNE_INT_SHIFT 16
    #define MIPS3_INTERRUPT_MASK_GVD_INT_MASK 0x00020000
    #define MIPS3_INTERRUPT_MASK_GVD_INT_SHIFT 17
    #define MIPS3_INTERRUPT_MASK_DVE_INT_MASK 0x00040000
    #define MIPS3_INTERRUPT_MASK_DVE_INT_SHIFT 18
    #define MIPS3_INTERRUPT_MASK_SATA_INT_MASK 0x00080000
    #define MIPS3_INTERRUPT_MASK_SATA_INT_SHIFT 19
    #define MIPS3_INTERRUPT_MASK_I2STX_INT_MASK 0x00100000
    #define MIPS3_INTERRUPT_MASK_I2STX_INT_SHIFT 20
    #define MIPS3_INTERRUPT_MASK_SPDIFRX_INT_MASK 0x00200000
    #define MIPS3_INTERRUPT_MASK_SPDIFRX_INT_SHIFT 21
    #define MIPS3_INTERRUPT_MASK_SPDIFTX_INT_MASK 0x00400000
    #define MIPS3_INTERRUPT_MASK_SPDIFTX_INT_SHIFT 22
    #define MIPS3_INTERRUPT_MASK_EDC_INT_MASK 0x00800000
    #define MIPS3_INTERRUPT_MASK_EDC_INT_SHIFT 23
    #define MIPS3_INTERRUPT_MASK_DSCL_INT_MASK 0x01000000
    #define MIPS3_INTERRUPT_MASK_DSCL_INT_SHIFT 24
    #define MIPS3_INTERRUPT_MASK_EE_INT_MASK 0x02000000
    #define MIPS3_INTERRUPT_MASK_EE_INT_SHIFT 25
    #define MIPS3_INTERRUPT_MASK_NFC_INT_MASK 0x04000000
    #define MIPS3_INTERRUPT_MASK_NFC_INT_SHIFT 26
#define  MIPS4_INTERRUPT 0x04D8
    #define MIPS4_INTERRUPT_TSD_INT0_MASK 0x00000001
    #define MIPS4_INTERRUPT_TSD_INT0_SHIFT 0
    #define MIPS4_INTERRUPT_TSD_INT1_MASK 0x00000002
    #define MIPS4_INTERRUPT_TSD_INT1_SHIFT 1
    #define MIPS4_INTERRUPT_USBD_INT_MASK 0x00000004
    #define MIPS4_INTERRUPT_USBD_INT_SHIFT 2
    #define MIPS4_INTERRUPT_USBH_INT_MASK 0x00000008
    #define MIPS4_INTERRUPT_USBH_INT_SHIFT 3
    #define MIPS4_INTERRUPT_TSD_INT4_MASK 0x00000010
    #define MIPS4_INTERRUPT_TSD_INT4_SHIFT 4
    #define MIPS4_INTERRUPT_ETH0_INT_MASK 0x00000020
    #define MIPS4_INTERRUPT_ETH0_INT_SHIFT 5
    #define MIPS4_INTERRUPT_ETH1_INT_MASK 0x00000040
    #define MIPS4_INTERRUPT_ETH1_INT_SHIFT 6
    #define MIPS4_INTERRUPT_PPC_INT_MASK 0x00000080
    #define MIPS4_INTERRUPT_PPC_INT_SHIFT 7
    #define MIPS4_INTERRUPT_DMA_INT_MASK 0x00000100
    #define MIPS4_INTERRUPT_DMA_INT_SHIFT 8
    #define MIPS4_INTERRUPT_RBM_INT_MASK 0x00000200
    #define MIPS4_INTERRUPT_RBM_INT_SHIFT 9
    #define MIPS4_INTERRUPT_MPP_INT_MASK 0x00000400
    #define MIPS4_INTERRUPT_MPP_INT_SHIFT 10
    #define MIPS4_INTERRUPT_RSA_INT_MASK 0x00000800
    #define MIPS4_INTERRUPT_RSA_INT_SHIFT 11
    #define MIPS4_INTERRUPT_I2S_INT_MASK 0x00001000
    #define MIPS4_INTERRUPT_I2S_INT_SHIFT 12
    #define MIPS4_INTERRUPT_RMX_INT_MASK 0x00002000
    #define MIPS4_INTERRUPT_RMX_INT_SHIFT 13
    #define MIPS4_INTERRUPT_VHE_INT_MASK 0x00004000
    #define MIPS4_INTERRUPT_VHE_INT_SHIFT 14
    #define MIPS4_INTERRUPT_VFE_INT_MASK 0x00008000
    #define MIPS4_INTERRUPT_VFE_INT_SHIFT 15
    #define MIPS4_INTERRUPT_VNE_INT_MASK 0x00010000
    #define MIPS4_INTERRUPT_VNE_INT_SHIFT 16
    #define MIPS4_INTERRUPT_GVD_INT_MASK 0x00020000
    #define MIPS4_INTERRUPT_GVD_INT_SHIFT 17
    #define MIPS4_INTERRUPT_DVE_INT_MASK 0x00040000
    #define MIPS4_INTERRUPT_DVE_INT_SHIFT 18
    #define MIPS4_INTERRUPT_SATA_INT_MASK 0x00080000
    #define MIPS4_INTERRUPT_SATA_INT_SHIFT 19
    #define MIPS4_INTERRUPT_I2STX_INT_MASK 0x00100000
    #define MIPS4_INTERRUPT_I2STX_INT_SHIFT 20
    #define MIPS4_INTERRUPT_SPDIFRX_INT_MASK 0x00200000
    #define MIPS4_INTERRUPT_SPDIFRX_INT_SHIFT 21
    #define MIPS4_INTERRUPT_SPDIFTX_INT_MASK 0x00400000
    #define MIPS4_INTERRUPT_SPDIFTX_INT_SHIFT 22
    #define MIPS4_INTERRUPT_EDC_INT_MASK 0x00800000
    #define MIPS4_INTERRUPT_EDC_INT_SHIFT 23
    #define MIPS4_INTERRUPT_DSCL_INT_MASK 0x01000000
    #define MIPS4_INTERRUPT_DSCL_INT_SHIFT 24
    #define MIPS4_INTERRUPT_EE_INT_MASK 0x02000000
    #define MIPS4_INTERRUPT_EE_INT_SHIFT 25
    #define MIPS4_INTERRUPT_NFC_INT_MASK 0x04000000
    #define MIPS4_INTERRUPT_NFC_INT_SHIFT 26
#define  MIPS4_INTERRUPT1 0x0534
    #define MIPS4_INTERRUPT1_SMS_INT_MASK 0x00000001
    #define MIPS4_INTERRUPT1_SMS_INT_SHIFT 0
    #define MIPS4_INTERRUPT1_VNH_INT_MASK 0x00000002
    #define MIPS4_INTERRUPT1_VNH_INT_SHIFT 1
    #define MIPS4_INTERRUPT1_DISP_INT_MASK 0x00000004
    #define MIPS4_INTERRUPT1_DISP_INT_SHIFT 2
    #define MIPS4_INTERRUPT1_MAD_INT_MASK 0x00000008
    #define MIPS4_INTERRUPT1_MAD_INT_SHIFT 3
    #define MIPS4_INTERRUPT1_GIC_INT_MASK 0x00000010
    #define MIPS4_INTERRUPT1_GIC_INT_SHIFT 4
    #define MIPS4_INTERRUPT1_FES_INT_MASK 0x00000020
    #define MIPS4_INTERRUPT1_FES_INT_SHIFT 5
    #define MIPS4_INTERRUPT1_G2D_INT_MASK 0x00000040
    #define MIPS4_INTERRUPT1_G2D_INT_SHIFT 6
    #define MIPS4_INTERRUPT1_IRC_INT_MASK 0x00000080
    #define MIPS4_INTERRUPT1_IRC_INT_SHIFT 7
    #define MIPS4_INTERRUPT1_NRFC_INT_MASK 0x00000100
    #define MIPS4_INTERRUPT1_NRFC_INT_SHIFT 8
    #define MIPS4_INTERRUPT1_SMCC_INT_MASK 0x00000200
    #define MIPS4_INTERRUPT1_SMCC_INT_SHIFT 9
    #define MIPS4_INTERRUPT1_MAFE_INT_MASK 0x00000400
    #define MIPS4_INTERRUPT1_MAFE_INT_SHIFT 10
    #define MIPS4_INTERRUPT1_RMX1_INT_MASK 0x00000800
    #define MIPS4_INTERRUPT1_RMX1_INT_SHIFT 11
    #define MIPS4_INTERRUPT1_G3D_INT_MASK 0x00001000
    #define MIPS4_INTERRUPT1_G3D_INT_SHIFT 12
    #define MIPS4_INTERRUPT1_UART0_INT_MASK 0x00002000
    #define MIPS4_INTERRUPT1_UART0_INT_SHIFT 13
    #define MIPS4_INTERRUPT1_UART1_INT_MASK 0x00004000
    #define MIPS4_INTERRUPT1_UART1_INT_SHIFT 14
    #define MIPS4_INTERRUPT1_INT15_MASK 0x00008000
    #define MIPS4_INTERRUPT1_INT15_SHIFT 15
    #define MIPS4_INTERRUPT1_INT16_MASK 0x00010000
    #define MIPS4_INTERRUPT1_INT16_SHIFT 16
    #define MIPS4_INTERRUPT1_INT17_MASK 0x00020000
    #define MIPS4_INTERRUPT1_INT17_SHIFT 17
    #define MIPS4_INTERRUPT1_INT18_MASK 0x00040000
    #define MIPS4_INTERRUPT1_INT18_SHIFT 18
    #define MIPS4_INTERRUPT1_INT19_MASK 0x00080000
    #define MIPS4_INTERRUPT1_INT19_SHIFT 19
    #define MIPS4_INTERRUPT1_INT20_MASK 0x00100000
    #define MIPS4_INTERRUPT1_INT20_SHIFT 20
    #define MIPS4_INTERRUPT1_INT21_MASK 0x00200000
    #define MIPS4_INTERRUPT1_INT21_SHIFT 21
    #define MIPS4_INTERRUPT1_INT22_MASK 0x00400000
    #define MIPS4_INTERRUPT1_INT22_SHIFT 22
    #define MIPS4_INTERRUPT1_INT23_MASK 0x00800000
    #define MIPS4_INTERRUPT1_INT23_SHIFT 23
    #define MIPS4_INTERRUPT1_INT24_MASK 0x01000000
    #define MIPS4_INTERRUPT1_INT24_SHIFT 24
    #define MIPS4_INTERRUPT1_INT25_MASK 0x02000000
    #define MIPS4_INTERRUPT1_INT25_SHIFT 25
    #define MIPS4_INTERRUPT1_INT26_MASK 0x04000000
    #define MIPS4_INTERRUPT1_INT26_SHIFT 26
    #define MIPS4_INTERRUPT1_INT27_MASK 0x08000000
    #define MIPS4_INTERRUPT1_INT27_SHIFT 27
    #define MIPS4_INTERRUPT1_INT28_MASK 0x10000000
    #define MIPS4_INTERRUPT1_INT28_SHIFT 28
    #define MIPS4_INTERRUPT1_INT29_MASK 0x20000000
    #define MIPS4_INTERRUPT1_INT29_SHIFT 29
    #define MIPS4_INTERRUPT1_INT30_MASK 0x40000000
    #define MIPS4_INTERRUPT1_INT30_SHIFT 30
    #define MIPS4_INTERRUPT1_INT31_MASK 0x80000000
    #define MIPS4_INTERRUPT1_INT31_SHIFT 31
#define  MIPS4_INTERRUPT1_MASK 0x0538
    #define MIPS4_INTERRUPT1_MASK_SMS_INT_MASK 0x00000001
    #define MIPS4_INTERRUPT1_MASK_SMS_INT_SHIFT 0
    #define MIPS4_INTERRUPT1_MASK_VNH_INT_MASK 0x00000002
    #define MIPS4_INTERRUPT1_MASK_VNH_INT_SHIFT 1
    #define MIPS4_INTERRUPT1_MASK_DISP_INT_MASK 0x00000004
    #define MIPS4_INTERRUPT1_MASK_DISP_INT_SHIFT 2
    #define MIPS4_INTERRUPT1_MASK_MAD_INT_MASK 0x00000008
    #define MIPS4_INTERRUPT1_MASK_MAD_INT_SHIFT 3
    #define MIPS4_INTERRUPT1_MASK_GIC_INT_MASK 0x00000010
    #define MIPS4_INTERRUPT1_MASK_GIC_INT_SHIFT 4
    #define MIPS4_INTERRUPT1_MASK_FES_INT_MASK 0x00000020
    #define MIPS4_INTERRUPT1_MASK_FES_INT_SHIFT 5
    #define MIPS4_INTERRUPT1_MASK_G2D_INT_MASK 0x00000040
    #define MIPS4_INTERRUPT1_MASK_G2D_INT_SHIFT 6
    #define MIPS4_INTERRUPT1_MASK_IRC_INT_MASK 0x00000080
    #define MIPS4_INTERRUPT1_MASK_IRC_INT_SHIFT 7
    #define MIPS4_INTERRUPT1_MASK_NRFC_INT_MASK 0x00000100
    #define MIPS4_INTERRUPT1_MASK_NRFC_INT_SHIFT 8
    #define MIPS4_INTERRUPT1_MASK_SMCC_INT_MASK 0x00000200
    #define MIPS4_INTERRUPT1_MASK_SMCC_INT_SHIFT 9
    #define MIPS4_INTERRUPT1_MASK_MAFE_INT_MASK 0x00000400
    #define MIPS4_INTERRUPT1_MASK_MAFE_INT_SHIFT 10
    #define MIPS4_INTERRUPT1_MASK_RMX1_INT_MASK 0x00000800
    #define MIPS4_INTERRUPT1_MASK_RMX1_INT_SHIFT 11
    #define MIPS4_INTERRUPT1_MASK_G3D_INT_MASK 0x00001000
    #define MIPS4_INTERRUPT1_MASK_G3D_INT_SHIFT 12
    #define MIPS4_INTERRUPT1_MASK_UART0_INT_MASK 0x00002000
    #define MIPS4_INTERRUPT1_MASK_UART0_INT_SHIFT 13
    #define MIPS4_INTERRUPT1_MASK_UART1_INT_MASK 0x00004000
    #define MIPS4_INTERRUPT1_MASK_UART1_INT_SHIFT 14
    #define MIPS4_INTERRUPT1_MASK_INT15_MASK 0x00008000
    #define MIPS4_INTERRUPT1_MASK_INT15_SHIFT 15
    #define MIPS4_INTERRUPT1_MASK_INT16_MASK 0x00010000
    #define MIPS4_INTERRUPT1_MASK_INT16_SHIFT 16
    #define MIPS4_INTERRUPT1_MASK_INT17_MASK 0x00020000
    #define MIPS4_INTERRUPT1_MASK_INT17_SHIFT 17
    #define MIPS4_INTERRUPT1_MASK_INT18_MASK 0x00040000
    #define MIPS4_INTERRUPT1_MASK_INT18_SHIFT 18
    #define MIPS4_INTERRUPT1_MASK_INT19_MASK 0x00080000
    #define MIPS4_INTERRUPT1_MASK_INT19_SHIFT 19
    #define MIPS4_INTERRUPT1_MASK_INT20_MASK 0x00100000
    #define MIPS4_INTERRUPT1_MASK_INT20_SHIFT 20
    #define MIPS4_INTERRUPT1_MASK_INT21_MASK 0x00200000
    #define MIPS4_INTERRUPT1_MASK_INT21_SHIFT 21
    #define MIPS4_INTERRUPT1_MASK_INT22_MASK 0x00400000
    #define MIPS4_INTERRUPT1_MASK_INT22_SHIFT 22
    #define MIPS4_INTERRUPT1_MASK_INT23_MASK 0x00800000
    #define MIPS4_INTERRUPT1_MASK_INT23_SHIFT 23
    #define MIPS4_INTERRUPT1_MASK_INT24_MASK 0x01000000
    #define MIPS4_INTERRUPT1_MASK_INT24_SHIFT 24
    #define MIPS4_INTERRUPT1_MASK_INT25_MASK 0x02000000
    #define MIPS4_INTERRUPT1_MASK_INT25_SHIFT 25
    #define MIPS4_INTERRUPT1_MASK_INT26_MASK 0x04000000
    #define MIPS4_INTERRUPT1_MASK_INT26_SHIFT 26
    #define MIPS4_INTERRUPT1_MASK_INT27_MASK 0x08000000
    #define MIPS4_INTERRUPT1_MASK_INT27_SHIFT 27
    #define MIPS4_INTERRUPT1_MASK_INT28_MASK 0x10000000
    #define MIPS4_INTERRUPT1_MASK_INT28_SHIFT 28
    #define MIPS4_INTERRUPT1_MASK_INT29_MASK 0x20000000
    #define MIPS4_INTERRUPT1_MASK_INT29_SHIFT 29
    #define MIPS4_INTERRUPT1_MASK_INT30_MASK 0x40000000
    #define MIPS4_INTERRUPT1_MASK_INT30_SHIFT 30
    #define MIPS4_INTERRUPT1_MASK_INT31_MASK 0x80000000
    #define MIPS4_INTERRUPT1_MASK_INT31_SHIFT 31
#define  MIPS4_INTERRUPT_MASK 0x04DC
    #define MIPS4_INTERRUPT_MASK_TSD_INT0_MASK 0x00000001
    #define MIPS4_INTERRUPT_MASK_TSD_INT0_SHIFT 0
    #define MIPS4_INTERRUPT_MASK_TSD_INT1_MASK 0x00000002
    #define MIPS4_INTERRUPT_MASK_TSD_INT1_SHIFT 1
    #define MIPS4_INTERRUPT_MASK_USBD_INT_MASK 0x00000004
    #define MIPS4_INTERRUPT_MASK_USBD_INT_SHIFT 2
    #define MIPS4_INTERRUPT_MASK_USBH_INT_MASK 0x00000008
    #define MIPS4_INTERRUPT_MASK_USBH_INT_SHIFT 3
    #define MIPS4_INTERRUPT_MASK_TSD_INT4_MASK 0x00000010
    #define MIPS4_INTERRUPT_MASK_TSD_INT4_SHIFT 4
    #define MIPS4_INTERRUPT_MASK_ETH0_INT_MASK 0x00000020
    #define MIPS4_INTERRUPT_MASK_ETH0_INT_SHIFT 5
    #define MIPS4_INTERRUPT_MASK_ETH1_INT_MASK 0x00000040
    #define MIPS4_INTERRUPT_MASK_ETH1_INT_SHIFT 6
    #define MIPS4_INTERRUPT_MASK_PPC_INT_MASK 0x00000080
    #define MIPS4_INTERRUPT_MASK_PPC_INT_SHIFT 7
    #define MIPS4_INTERRUPT_MASK_DMA_INT_MASK 0x00000100
    #define MIPS4_INTERRUPT_MASK_DMA_INT_SHIFT 8
    #define MIPS4_INTERRUPT_MASK_RBM_INT_MASK 0x00000200
    #define MIPS4_INTERRUPT_MASK_RBM_INT_SHIFT 9
    #define MIPS4_INTERRUPT_MASK_MPP_INT_MASK 0x00000400
    #define MIPS4_INTERRUPT_MASK_MPP_INT_SHIFT 10
    #define MIPS4_INTERRUPT_MASK_RSA_INT_MASK 0x00000800
    #define MIPS4_INTERRUPT_MASK_RSA_INT_SHIFT 11
    #define MIPS4_INTERRUPT_MASK_I2S_INT_MASK 0x00001000
    #define MIPS4_INTERRUPT_MASK_I2S_INT_SHIFT 12
    #define MIPS4_INTERRUPT_MASK_RMX_INT_MASK 0x00002000
    #define MIPS4_INTERRUPT_MASK_RMX_INT_SHIFT 13
    #define MIPS4_INTERRUPT_MASK_VHE_INT_MASK 0x00004000
    #define MIPS4_INTERRUPT_MASK_VHE_INT_SHIFT 14
    #define MIPS4_INTERRUPT_MASK_VFE_INT_MASK 0x00008000
    #define MIPS4_INTERRUPT_MASK_VFE_INT_SHIFT 15
    #define MIPS4_INTERRUPT_MASK_VNE_INT_MASK 0x00010000
    #define MIPS4_INTERRUPT_MASK_VNE_INT_SHIFT 16
    #define MIPS4_INTERRUPT_MASK_GVD_INT_MASK 0x00020000
    #define MIPS4_INTERRUPT_MASK_GVD_INT_SHIFT 17
    #define MIPS4_INTERRUPT_MASK_DVE_INT_MASK 0x00040000
    #define MIPS4_INTERRUPT_MASK_DVE_INT_SHIFT 18
    #define MIPS4_INTERRUPT_MASK_SATA_INT_MASK 0x00080000
    #define MIPS4_INTERRUPT_MASK_SATA_INT_SHIFT 19
    #define MIPS4_INTERRUPT_MASK_I2STX_INT_MASK 0x00100000
    #define MIPS4_INTERRUPT_MASK_I2STX_INT_SHIFT 20
    #define MIPS4_INTERRUPT_MASK_SPDIFRX_INT_MASK 0x00200000
    #define MIPS4_INTERRUPT_MASK_SPDIFRX_INT_SHIFT 21
    #define MIPS4_INTERRUPT_MASK_SPDIFTX_INT_MASK 0x00400000
    #define MIPS4_INTERRUPT_MASK_SPDIFTX_INT_SHIFT 22
    #define MIPS4_INTERRUPT_MASK_EDC_INT_MASK 0x00800000
    #define MIPS4_INTERRUPT_MASK_EDC_INT_SHIFT 23
    #define MIPS4_INTERRUPT_MASK_DSCL_INT_MASK 0x01000000
    #define MIPS4_INTERRUPT_MASK_DSCL_INT_SHIFT 24
    #define MIPS4_INTERRUPT_MASK_EE_INT_MASK 0x02000000
    #define MIPS4_INTERRUPT_MASK_EE_INT_SHIFT 25
    #define MIPS4_INTERRUPT_MASK_NFC_INT_MASK 0x04000000
    #define MIPS4_INTERRUPT_MASK_NFC_INT_SHIFT 26
#define  MIPS_INTERLOCK0 0x0440
    #define MIPS_INTERLOCK0_ID_MASK 0x000000FF
    #define MIPS_INTERLOCK0_ID_SHIFT 0
    #define MIPS_INTERLOCK0_LOCK_MASK 0x80000000
    #define MIPS_INTERLOCK0_LOCK_SHIFT 31
#define  MIPS_INTERLOCK1 0x0444
    #define MIPS_INTERLOCK1_ID_MASK 0x000000FF
    #define MIPS_INTERLOCK1_ID_SHIFT 0
    #define MIPS_INTERLOCK1_LOCK_MASK 0x80000000
    #define MIPS_INTERLOCK1_LOCK_SHIFT 31
#define  MIPS_INTERLOCK10 0x04B8
    #define MIPS_INTERLOCK10_ID_MASK 0x000000FF
    #define MIPS_INTERLOCK10_ID_SHIFT 0
    #define MIPS_INTERLOCK10_LOCK_MASK 0x80000000
    #define MIPS_INTERLOCK10_LOCK_SHIFT 31
#define  MIPS_INTERLOCK11 0x04BC
    #define MIPS_INTERLOCK11_ID_MASK 0x000000FF
    #define MIPS_INTERLOCK11_ID_SHIFT 0
    #define MIPS_INTERLOCK11_LOCK_MASK 0x80000000
    #define MIPS_INTERLOCK11_LOCK_SHIFT 31
#define  MIPS_INTERLOCK12 0x04C0
    #define MIPS_INTERLOCK12_ID_MASK 0x000000FF
    #define MIPS_INTERLOCK12_ID_SHIFT 0
    #define MIPS_INTERLOCK12_LOCK_MASK 0x80000000
    #define MIPS_INTERLOCK12_LOCK_SHIFT 31
#define  MIPS_INTERLOCK13 0x04C4
    #define MIPS_INTERLOCK13_ID_MASK 0x000000FF
    #define MIPS_INTERLOCK13_ID_SHIFT 0
    #define MIPS_INTERLOCK13_LOCK_MASK 0x80000000
    #define MIPS_INTERLOCK13_LOCK_SHIFT 31
#define  MIPS_INTERLOCK14 0x04C8
    #define MIPS_INTERLOCK14_ID_MASK 0x000000FF
    #define MIPS_INTERLOCK14_ID_SHIFT 0
    #define MIPS_INTERLOCK14_LOCK_MASK 0x80000000
    #define MIPS_INTERLOCK14_LOCK_SHIFT 31
#define  MIPS_INTERLOCK15 0x04CC
    #define MIPS_INTERLOCK15_ID_MASK 0x000000FF
    #define MIPS_INTERLOCK15_ID_SHIFT 0
    #define MIPS_INTERLOCK15_LOCK_MASK 0x80000000
    #define MIPS_INTERLOCK15_LOCK_SHIFT 31
#define  MIPS_INTERLOCK2 0x0448
    #define MIPS_INTERLOCK2_ID_MASK 0x000000FF
    #define MIPS_INTERLOCK2_ID_SHIFT 0
    #define MIPS_INTERLOCK2_LOCK_MASK 0x80000000
    #define MIPS_INTERLOCK2_LOCK_SHIFT 31
#define  MIPS_INTERLOCK3 0x044C
    #define MIPS_INTERLOCK3_ID_MASK 0x000000FF
    #define MIPS_INTERLOCK3_ID_SHIFT 0
    #define MIPS_INTERLOCK3_LOCK_MASK 0x80000000
    #define MIPS_INTERLOCK3_LOCK_SHIFT 31
#define  MIPS_INTERLOCK4 0x0450
    #define MIPS_INTERLOCK4_ID_MASK 0x000000FF
    #define MIPS_INTERLOCK4_ID_SHIFT 0
    #define MIPS_INTERLOCK4_LOCK_MASK 0x80000000
    #define MIPS_INTERLOCK4_LOCK_SHIFT 31
#define  MIPS_INTERLOCK5 0x0454
    #define MIPS_INTERLOCK5_ID_MASK 0x000000FF
    #define MIPS_INTERLOCK5_ID_SHIFT 0
    #define MIPS_INTERLOCK5_LOCK_MASK 0x80000000
    #define MIPS_INTERLOCK5_LOCK_SHIFT 31
#define  MIPS_INTERLOCK6 0x0458
    #define MIPS_INTERLOCK6_ID_MASK 0x000000FF
    #define MIPS_INTERLOCK6_ID_SHIFT 0
    #define MIPS_INTERLOCK6_LOCK_MASK 0x80000000
    #define MIPS_INTERLOCK6_LOCK_SHIFT 31
#define  MIPS_INTERLOCK7 0x045C
    #define MIPS_INTERLOCK7_ID_MASK 0x000000FF
    #define MIPS_INTERLOCK7_ID_SHIFT 0
    #define MIPS_INTERLOCK7_LOCK_MASK 0x80000000
    #define MIPS_INTERLOCK7_LOCK_SHIFT 31
#define  MIPS_INTERLOCK8 0x04B0
    #define MIPS_INTERLOCK8_ID_MASK 0x000000FF
    #define MIPS_INTERLOCK8_ID_SHIFT 0
    #define MIPS_INTERLOCK8_LOCK_MASK 0x80000000
    #define MIPS_INTERLOCK8_LOCK_SHIFT 31
#define  MIPS_INTERLOCK9 0x04B4
    #define MIPS_INTERLOCK9_ID_MASK 0x000000FF
    #define MIPS_INTERLOCK9_ID_SHIFT 0
    #define MIPS_INTERLOCK9_LOCK_MASK 0x80000000
    #define MIPS_INTERLOCK9_LOCK_SHIFT 31
#define  MPP_DMF_CB_BASE 0x7604
    #define MPP_DMF_CB_BASE_ADDR_MASK 0x7FFFFFE0
    #define MPP_DMF_CB_BASE_ADDR_SHIFT 5
#define  MPP_DMF_CR_BASE 0x7608
    #define MPP_DMF_CR_BASE_ADDR_MASK 0x7FFFFFE0
    #define MPP_DMF_CR_BASE_ADDR_SHIFT 5
#define  MPP_DMF_DEBUG 0x7618
    #define INFO_MASK 0xFFFFFFFF
    #define INFO_SHIFT 0
#define  MPP_DMF_DRNG_COEFFS0_PELA 0x7670
    #define MPP_DMF_DRNG_COEFFS0_PELA_CASE0_MASK 0x0000000F
    #define MPP_DMF_DRNG_COEFFS0_PELA_CASE0_SHIFT 0
    #define MPP_DMF_DRNG_COEFFS0_PELA_CASE1_MASK 0x000000F0
    #define MPP_DMF_DRNG_COEFFS0_PELA_CASE1_SHIFT 4
    #define MPP_DMF_DRNG_COEFFS0_PELA_CASE2_MASK 0x00000F00
    #define MPP_DMF_DRNG_COEFFS0_PELA_CASE2_SHIFT 8
    #define MPP_DMF_DRNG_COEFFS0_PELA_CASE3_MASK 0x0000F000
    #define MPP_DMF_DRNG_COEFFS0_PELA_CASE3_SHIFT 12
    #define MPP_DMF_DRNG_COEFFS0_PELA_CASE4_MASK 0x000F0000
    #define MPP_DMF_DRNG_COEFFS0_PELA_CASE4_SHIFT 16
    #define MPP_DMF_DRNG_COEFFS0_PELA_CASE5_MASK 0x00F00000
    #define MPP_DMF_DRNG_COEFFS0_PELA_CASE5_SHIFT 20
    #define MPP_DMF_DRNG_COEFFS0_PELA_CASE6_MASK 0x0F000000
    #define MPP_DMF_DRNG_COEFFS0_PELA_CASE6_SHIFT 24
    #define MPP_DMF_DRNG_COEFFS0_PELA_CASE7_MASK 0xF0000000
    #define MPP_DMF_DRNG_COEFFS0_PELA_CASE7_SHIFT 28
#define  MPP_DMF_DRNG_COEFFS0_PELB 0x7678
    #define MPP_DMF_DRNG_COEFFS0_PELB_CASE0_MASK 0x0000000F
    #define MPP_DMF_DRNG_COEFFS0_PELB_CASE0_SHIFT 0
    #define MPP_DMF_DRNG_COEFFS0_PELB_CASE1_MASK 0x000000F0
    #define MPP_DMF_DRNG_COEFFS0_PELB_CASE1_SHIFT 4
    #define MPP_DMF_DRNG_COEFFS0_PELB_CASE2_MASK 0x00000F00
    #define MPP_DMF_DRNG_COEFFS0_PELB_CASE2_SHIFT 8
    #define MPP_DMF_DRNG_COEFFS0_PELB_CASE3_MASK 0x0000F000
    #define MPP_DMF_DRNG_COEFFS0_PELB_CASE3_SHIFT 12
    #define MPP_DMF_DRNG_COEFFS0_PELB_CASE4_MASK 0x000F0000
    #define MPP_DMF_DRNG_COEFFS0_PELB_CASE4_SHIFT 16
    #define MPP_DMF_DRNG_COEFFS0_PELB_CASE5_MASK 0x00F00000
    #define MPP_DMF_DRNG_COEFFS0_PELB_CASE5_SHIFT 20
    #define MPP_DMF_DRNG_COEFFS0_PELB_CASE6_MASK 0x0F000000
    #define MPP_DMF_DRNG_COEFFS0_PELB_CASE6_SHIFT 24
    #define MPP_DMF_DRNG_COEFFS0_PELB_CASE7_MASK 0xF0000000
    #define MPP_DMF_DRNG_COEFFS0_PELB_CASE7_SHIFT 28
#define  MPP_DMF_DRNG_COEFFS0_PELC 0x7680
    #define MPP_DMF_DRNG_COEFFS0_PELC_CASE0_MASK 0x0000000F
    #define MPP_DMF_DRNG_COEFFS0_PELC_CASE0_SHIFT 0
    #define MPP_DMF_DRNG_COEFFS0_PELC_CASE1_MASK 0x000000F0
    #define MPP_DMF_DRNG_COEFFS0_PELC_CASE1_SHIFT 4
    #define MPP_DMF_DRNG_COEFFS0_PELC_CASE2_MASK 0x00000F00
    #define MPP_DMF_DRNG_COEFFS0_PELC_CASE2_SHIFT 8
    #define MPP_DMF_DRNG_COEFFS0_PELC_CASE3_MASK 0x0000F000
    #define MPP_DMF_DRNG_COEFFS0_PELC_CASE3_SHIFT 12
    #define MPP_DMF_DRNG_COEFFS0_PELC_CASE4_MASK 0x000F0000
    #define MPP_DMF_DRNG_COEFFS0_PELC_CASE4_SHIFT 16
    #define MPP_DMF_DRNG_COEFFS0_PELC_CASE5_MASK 0x00F00000
    #define MPP_DMF_DRNG_COEFFS0_PELC_CASE5_SHIFT 20
    #define MPP_DMF_DRNG_COEFFS0_PELC_CASE6_MASK 0x0F000000
    #define MPP_DMF_DRNG_COEFFS0_PELC_CASE6_SHIFT 24
    #define MPP_DMF_DRNG_COEFFS0_PELC_CASE7_MASK 0xF0000000
    #define MPP_DMF_DRNG_COEFFS0_PELC_CASE7_SHIFT 28
#define  MPP_DMF_DRNG_COEFFS0_PELD 0x7688
    #define MPP_DMF_DRNG_COEFFS0_PELD_CASE0_MASK 0x0000000F
    #define MPP_DMF_DRNG_COEFFS0_PELD_CASE0_SHIFT 0
    #define MPP_DMF_DRNG_COEFFS0_PELD_CASE1_MASK 0x000000F0
    #define MPP_DMF_DRNG_COEFFS0_PELD_CASE1_SHIFT 4
    #define MPP_DMF_DRNG_COEFFS0_PELD_CASE2_MASK 0x00000F00
    #define MPP_DMF_DRNG_COEFFS0_PELD_CASE2_SHIFT 8
    #define MPP_DMF_DRNG_COEFFS0_PELD_CASE3_MASK 0x0000F000
    #define MPP_DMF_DRNG_COEFFS0_PELD_CASE3_SHIFT 12
    #define MPP_DMF_DRNG_COEFFS0_PELD_CASE4_MASK 0x000F0000
    #define MPP_DMF_DRNG_COEFFS0_PELD_CASE4_SHIFT 16
    #define MPP_DMF_DRNG_COEFFS0_PELD_CASE5_MASK 0x00F00000
    #define MPP_DMF_DRNG_COEFFS0_PELD_CASE5_SHIFT 20
    #define MPP_DMF_DRNG_COEFFS0_PELD_CASE6_MASK 0x0F000000
    #define MPP_DMF_DRNG_COEFFS0_PELD_CASE6_SHIFT 24
    #define MPP_DMF_DRNG_COEFFS0_PELD_CASE7_MASK 0xF0000000
    #define MPP_DMF_DRNG_COEFFS0_PELD_CASE7_SHIFT 28
#define  MPP_DMF_DRNG_COEFFS0_PELE 0x7690
    #define MPP_DMF_DRNG_COEFFS0_PELE_CASE0_MASK 0x0000000F
    #define MPP_DMF_DRNG_COEFFS0_PELE_CASE0_SHIFT 0
    #define MPP_DMF_DRNG_COEFFS0_PELE_CASE1_MASK 0x000000F0
    #define MPP_DMF_DRNG_COEFFS0_PELE_CASE1_SHIFT 4
    #define MPP_DMF_DRNG_COEFFS0_PELE_CASE2_MASK 0x00000F00
    #define MPP_DMF_DRNG_COEFFS0_PELE_CASE2_SHIFT 8
    #define MPP_DMF_DRNG_COEFFS0_PELE_CASE3_MASK 0x0000F000
    #define MPP_DMF_DRNG_COEFFS0_PELE_CASE3_SHIFT 12
    #define MPP_DMF_DRNG_COEFFS0_PELE_CASE4_MASK 0x000F0000
    #define MPP_DMF_DRNG_COEFFS0_PELE_CASE4_SHIFT 16
    #define MPP_DMF_DRNG_COEFFS0_PELE_CASE5_MASK 0x00F00000
    #define MPP_DMF_DRNG_COEFFS0_PELE_CASE5_SHIFT 20
    #define MPP_DMF_DRNG_COEFFS0_PELE_CASE6_MASK 0x0F000000
    #define MPP_DMF_DRNG_COEFFS0_PELE_CASE6_SHIFT 24
    #define MPP_DMF_DRNG_COEFFS0_PELE_CASE7_MASK 0xF0000000
    #define MPP_DMF_DRNG_COEFFS0_PELE_CASE7_SHIFT 28
#define  MPP_DMF_DRNG_COEFFS1_PELA 0x7674
    #define MPP_DMF_DRNG_COEFFS1_PELA_CASE8_MASK 0x0000000F
    #define MPP_DMF_DRNG_COEFFS1_PELA_CASE8_SHIFT 0
    #define MPP_DMF_DRNG_COEFFS1_PELA_CASE9_MASK 0x000000F0
    #define MPP_DMF_DRNG_COEFFS1_PELA_CASE9_SHIFT 4
    #define MPP_DMF_DRNG_COEFFS1_PELA_CASE10_MASK 0x00000F00
    #define MPP_DMF_DRNG_COEFFS1_PELA_CASE10_SHIFT 8
    #define MPP_DMF_DRNG_COEFFS1_PELA_CASE11_MASK 0x0000F000
    #define MPP_DMF_DRNG_COEFFS1_PELA_CASE11_SHIFT 12
    #define MPP_DMF_DRNG_COEFFS1_PELA_CASE12_MASK 0x000F0000
    #define MPP_DMF_DRNG_COEFFS1_PELA_CASE12_SHIFT 16
    #define MPP_DMF_DRNG_COEFFS1_PELA_CASE13_MASK 0x00F00000
    #define MPP_DMF_DRNG_COEFFS1_PELA_CASE13_SHIFT 20
    #define MPP_DMF_DRNG_COEFFS1_PELA_CASE14_MASK 0x0F000000
    #define MPP_DMF_DRNG_COEFFS1_PELA_CASE14_SHIFT 24
    #define MPP_DMF_DRNG_COEFFS1_PELA_CASE15_MASK 0xF0000000
    #define MPP_DMF_DRNG_COEFFS1_PELA_CASE15_SHIFT 28
#define  MPP_DMF_DRNG_COEFFS1_PELB 0x767C
    #define MPP_DMF_DRNG_COEFFS1_PELB_CASE8_MASK 0x0000000F
    #define MPP_DMF_DRNG_COEFFS1_PELB_CASE8_SHIFT 0
    #define MPP_DMF_DRNG_COEFFS1_PELB_CASE9_MASK 0x000000F0
    #define MPP_DMF_DRNG_COEFFS1_PELB_CASE9_SHIFT 4
    #define MPP_DMF_DRNG_COEFFS1_PELB_CASE10_MASK 0x00000F00
    #define MPP_DMF_DRNG_COEFFS1_PELB_CASE10_SHIFT 8
    #define MPP_DMF_DRNG_COEFFS1_PELB_CASE11_MASK 0x0000F000
    #define MPP_DMF_DRNG_COEFFS1_PELB_CASE11_SHIFT 12
    #define MPP_DMF_DRNG_COEFFS1_PELB_CASE12_MASK 0x000F0000
    #define MPP_DMF_DRNG_COEFFS1_PELB_CASE12_SHIFT 16
    #define MPP_DMF_DRNG_COEFFS1_PELB_CASE13_MASK 0x00F00000
    #define MPP_DMF_DRNG_COEFFS1_PELB_CASE13_SHIFT 20
    #define MPP_DMF_DRNG_COEFFS1_PELB_CASE14_MASK 0x0F000000
    #define MPP_DMF_DRNG_COEFFS1_PELB_CASE14_SHIFT 24
    #define MPP_DMF_DRNG_COEFFS1_PELB_CASE15_MASK 0xF0000000
    #define MPP_DMF_DRNG_COEFFS1_PELB_CASE15_SHIFT 28
#define  MPP_DMF_DRNG_COEFFS1_PELC 0x7684
    #define MPP_DMF_DRNG_COEFFS1_PELC_CASE8_MASK 0x0000000F
    #define MPP_DMF_DRNG_COEFFS1_PELC_CASE8_SHIFT 0
    #define MPP_DMF_DRNG_COEFFS1_PELC_CASE9_MASK 0x000000F0
    #define MPP_DMF_DRNG_COEFFS1_PELC_CASE9_SHIFT 4
    #define MPP_DMF_DRNG_COEFFS1_PELC_CASE10_MASK 0x00000F00
    #define MPP_DMF_DRNG_COEFFS1_PELC_CASE10_SHIFT 8
    #define MPP_DMF_DRNG_COEFFS1_PELC_CASE11_MASK 0x0000F000
    #define MPP_DMF_DRNG_COEFFS1_PELC_CASE11_SHIFT 12
    #define MPP_DMF_DRNG_COEFFS1_PELC_CASE12_MASK 0x000F0000
    #define MPP_DMF_DRNG_COEFFS1_PELC_CASE12_SHIFT 16
    #define MPP_DMF_DRNG_COEFFS1_PELC_CASE13_MASK 0x00F00000
    #define MPP_DMF_DRNG_COEFFS1_PELC_CASE13_SHIFT 20
    #define MPP_DMF_DRNG_COEFFS1_PELC_CASE14_MASK 0x0F000000
    #define MPP_DMF_DRNG_COEFFS1_PELC_CASE14_SHIFT 24
    #define MPP_DMF_DRNG_COEFFS1_PELC_CASE15_MASK 0xF0000000
    #define MPP_DMF_DRNG_COEFFS1_PELC_CASE15_SHIFT 28
#define  MPP_DMF_DRNG_COEFFS1_PELD 0x768C
    #define MPP_DMF_DRNG_COEFFS1_PELD_CASE8_MASK 0x0000000F
    #define MPP_DMF_DRNG_COEFFS1_PELD_CASE8_SHIFT 0
    #define MPP_DMF_DRNG_COEFFS1_PELD_CASE9_MASK 0x000000F0
    #define MPP_DMF_DRNG_COEFFS1_PELD_CASE9_SHIFT 4
    #define MPP_DMF_DRNG_COEFFS1_PELD_CASE10_MASK 0x00000F00
    #define MPP_DMF_DRNG_COEFFS1_PELD_CASE10_SHIFT 8
    #define MPP_DMF_DRNG_COEFFS1_PELD_CASE11_MASK 0x0000F000
    #define MPP_DMF_DRNG_COEFFS1_PELD_CASE11_SHIFT 12
    #define MPP_DMF_DRNG_COEFFS1_PELD_CASE12_MASK 0x000F0000
    #define MPP_DMF_DRNG_COEFFS1_PELD_CASE12_SHIFT 16
    #define MPP_DMF_DRNG_COEFFS1_PELD_CASE13_MASK 0x00F00000
    #define MPP_DMF_DRNG_COEFFS1_PELD_CASE13_SHIFT 20
    #define MPP_DMF_DRNG_COEFFS1_PELD_CASE14_MASK 0x0F000000
    #define MPP_DMF_DRNG_COEFFS1_PELD_CASE14_SHIFT 24
    #define MPP_DMF_DRNG_COEFFS1_PELD_CASE15_MASK 0xF0000000
    #define MPP_DMF_DRNG_COEFFS1_PELD_CASE15_SHIFT 28
#define  MPP_DMF_DRNG_COEFFS1_PELE 0x7694
    #define MPP_DMF_DRNG_COEFFS1_PELE_CASE8_MASK 0x0000000F
    #define MPP_DMF_DRNG_COEFFS1_PELE_CASE8_SHIFT 0
    #define MPP_DMF_DRNG_COEFFS1_PELE_CASE9_MASK 0x000000F0
    #define MPP_DMF_DRNG_COEFFS1_PELE_CASE9_SHIFT 4
    #define MPP_DMF_DRNG_COEFFS1_PELE_CASE10_MASK 0x00000F00
    #define MPP_DMF_DRNG_COEFFS1_PELE_CASE10_SHIFT 8
    #define MPP_DMF_DRNG_COEFFS1_PELE_CASE11_MASK 0x0000F000
    #define MPP_DMF_DRNG_COEFFS1_PELE_CASE11_SHIFT 12
    #define MPP_DMF_DRNG_COEFFS1_PELE_CASE12_MASK 0x000F0000
    #define MPP_DMF_DRNG_COEFFS1_PELE_CASE12_SHIFT 16
    #define MPP_DMF_DRNG_COEFFS1_PELE_CASE13_MASK 0x00F00000
    #define MPP_DMF_DRNG_COEFFS1_PELE_CASE13_SHIFT 20
    #define MPP_DMF_DRNG_COEFFS1_PELE_CASE14_MASK 0x0F000000
    #define MPP_DMF_DRNG_COEFFS1_PELE_CASE14_SHIFT 24
    #define MPP_DMF_DRNG_COEFFS1_PELE_CASE15_MASK 0xF0000000
    #define MPP_DMF_DRNG_COEFFS1_PELE_CASE15_SHIFT 28
#define  MPP_DMF_DRNG_CONST 0x7698
    #define TC1_MASK 0x000000FF
    #define TC1_SHIFT 0
    #define MC1_MASK 0x0F000000
    #define MC1_SHIFT 24
#define  MPP_DMF_HDBK_COEFFS_P0 0x7620
    #define MPP_DMF_HDBK_COEFFS_P0_CASE1_MASK 0x0000000F
    #define MPP_DMF_HDBK_COEFFS_P0_CASE1_SHIFT 0
    #define MPP_DMF_HDBK_COEFFS_P0_CASE2_MASK 0x000000F0
    #define MPP_DMF_HDBK_COEFFS_P0_CASE2_SHIFT 4
    #define MPP_DMF_HDBK_COEFFS_P0_CASE3_MASK 0x00000F00
    #define MPP_DMF_HDBK_COEFFS_P0_CASE3_SHIFT 8
    #define MPP_DMF_HDBK_COEFFS_P0_CASE4_MASK 0x0000F000
    #define MPP_DMF_HDBK_COEFFS_P0_CASE4_SHIFT 12
    #define MPP_DMF_HDBK_COEFFS_P0_CASE5_MASK 0x000F0000
    #define MPP_DMF_HDBK_COEFFS_P0_CASE5_SHIFT 16
    #define MPP_DMF_HDBK_COEFFS_P0_CASE6_MASK 0x00F00000
    #define MPP_DMF_HDBK_COEFFS_P0_CASE6_SHIFT 20
#define  MPP_DMF_HDBK_COEFFS_P1 0x7624
    #define MPP_DMF_HDBK_COEFFS_P1_CASE1_MASK 0x0000000F
    #define MPP_DMF_HDBK_COEFFS_P1_CASE1_SHIFT 0
    #define MPP_DMF_HDBK_COEFFS_P1_CASE2_MASK 0x000000F0
    #define MPP_DMF_HDBK_COEFFS_P1_CASE2_SHIFT 4
    #define MPP_DMF_HDBK_COEFFS_P1_CASE3_MASK 0x00000F00
    #define MPP_DMF_HDBK_COEFFS_P1_CASE3_SHIFT 8
    #define MPP_DMF_HDBK_COEFFS_P1_CASE4_MASK 0x0000F000
    #define MPP_DMF_HDBK_COEFFS_P1_CASE4_SHIFT 12
    #define MPP_DMF_HDBK_COEFFS_P1_CASE5_MASK 0x000F0000
    #define MPP_DMF_HDBK_COEFFS_P1_CASE5_SHIFT 16
    #define MPP_DMF_HDBK_COEFFS_P1_CASE6_MASK 0x00F00000
    #define MPP_DMF_HDBK_COEFFS_P1_CASE6_SHIFT 20
#define  MPP_DMF_HDBK_COEFFS_P2 0x7628
    #define MPP_DMF_HDBK_COEFFS_P2_CASE1_MASK 0x0000000F
    #define MPP_DMF_HDBK_COEFFS_P2_CASE1_SHIFT 0
    #define MPP_DMF_HDBK_COEFFS_P2_CASE2_MASK 0x000000F0
    #define MPP_DMF_HDBK_COEFFS_P2_CASE2_SHIFT 4
    #define MPP_DMF_HDBK_COEFFS_P2_CASE3_MASK 0x00000F00
    #define MPP_DMF_HDBK_COEFFS_P2_CASE3_SHIFT 8
    #define MPP_DMF_HDBK_COEFFS_P2_CASE4_MASK 0x0000F000
    #define MPP_DMF_HDBK_COEFFS_P2_CASE4_SHIFT 12
    #define MPP_DMF_HDBK_COEFFS_P2_CASE5_MASK 0x000F0000
    #define MPP_DMF_HDBK_COEFFS_P2_CASE5_SHIFT 16
    #define MPP_DMF_HDBK_COEFFS_P2_CASE6_MASK 0x00F00000
    #define MPP_DMF_HDBK_COEFFS_P2_CASE6_SHIFT 20
#define  MPP_DMF_HDBK_COEFFS_P3 0x762C
    #define MPP_DMF_HDBK_COEFFS_P3_CASE1_MASK 0x0000000F
    #define MPP_DMF_HDBK_COEFFS_P3_CASE1_SHIFT 0
    #define MPP_DMF_HDBK_COEFFS_P3_CASE2_MASK 0x000000F0
    #define MPP_DMF_HDBK_COEFFS_P3_CASE2_SHIFT 4
    #define MPP_DMF_HDBK_COEFFS_P3_CASE3_MASK 0x00000F00
    #define MPP_DMF_HDBK_COEFFS_P3_CASE3_SHIFT 8
    #define MPP_DMF_HDBK_COEFFS_P3_CASE4_MASK 0x0000F000
    #define MPP_DMF_HDBK_COEFFS_P3_CASE4_SHIFT 12
    #define MPP_DMF_HDBK_COEFFS_P3_CASE5_MASK 0x000F0000
    #define MPP_DMF_HDBK_COEFFS_P3_CASE5_SHIFT 16
    #define MPP_DMF_HDBK_COEFFS_P3_CASE6_MASK 0x00F00000
    #define MPP_DMF_HDBK_COEFFS_P3_CASE6_SHIFT 20
#define  MPP_DMF_HDBK_CONST 0x7630
    #define TA1_MASK 0x000000FF
    #define TA1_SHIFT 0
    #define TA2_MASK 0x0000FF00
    #define TA2_SHIFT 8
    #define TA3_MASK 0x00FF0000
    #define TA3_SHIFT 16
    #define MA1_MASK 0x0F000000
    #define MA1_SHIFT 24
    #define MA2_MASK 0xF0000000
    #define MA2_SHIFT 28
#define  MPP_DMF_LUMA_BASE 0x7600
    #define MPP_DMF_LUMA_BASE_ADDR_MASK 0x7FFFFFE0
    #define MPP_DMF_LUMA_BASE_ADDR_SHIFT 5
#define  MPP_DMF_MISC 0x7610
    #define MPP_DMF_MISC_SFT_RSTN_MASK 0x00000001
    #define MPP_DMF_MISC_SFT_RSTN_SHIFT 0
    #define DISABLE_MASK 0x00000002
    #define DISABLE_SHIFT 1
    #define MPP_DMF_MISC_CLK_STOP_MASK 0x00000004
    #define MPP_DMF_MISC_CLK_STOP_SHIFT 2
    #define MB_CODING_OVERRIDE_MASK 0x00000100
    #define MB_CODING_OVERRIDE_SHIFT 8
    #define MB_CODING_REG_MASK 0x00000200
    #define MB_CODING_REG_SHIFT 9
    #define CLI0_ARB_TIMER_MASK 0x000F0000
    #define CLI0_ARB_TIMER_SHIFT 16
    #define CLI1_ARB_TIMER_MASK 0x00F00000
    #define CLI1_ARB_TIMER_SHIFT 20
    #define MPP_DMF_MISC_DBG_MUX_SEL_MASK 0x0F000000
    #define MPP_DMF_MISC_DBG_MUX_SEL_SHIFT 24
#define  MPP_DMF_RING_BUF_BASE 0x760C
    #define MPP_DMF_RING_BUF_BASE_ADDR_MASK 0x7FFFFFC0
    #define MPP_DMF_RING_BUF_BASE_ADDR_SHIFT 6
#define  MPP_DMF_TRIG 0x7614
    #define START_FRAME_MASK 0x00000001
    #define START_FRAME_SHIFT 0
#define  MPP_DMF_VDBK_FIELD_COEFFS_P0 0x7654
    #define MPP_DMF_VDBK_FIELD_COEFFS_P0_CASE1_MASK 0x0000000F
    #define MPP_DMF_VDBK_FIELD_COEFFS_P0_CASE1_SHIFT 0
    #define MPP_DMF_VDBK_FIELD_COEFFS_P0_CASE2_MASK 0x000000F0
    #define MPP_DMF_VDBK_FIELD_COEFFS_P0_CASE2_SHIFT 4
    #define MPP_DMF_VDBK_FIELD_COEFFS_P0_CASE3_MASK 0x00000F00
    #define MPP_DMF_VDBK_FIELD_COEFFS_P0_CASE3_SHIFT 8
    #define MPP_DMF_VDBK_FIELD_COEFFS_P0_CASE4_MASK 0x0000F000
    #define MPP_DMF_VDBK_FIELD_COEFFS_P0_CASE4_SHIFT 12
    #define MPP_DMF_VDBK_FIELD_COEFFS_P0_CASE6_MASK 0x000F0000
    #define MPP_DMF_VDBK_FIELD_COEFFS_P0_CASE6_SHIFT 16
#define  MPP_DMF_VDBK_FIELD_COEFFS_P1 0x7658
    #define MPP_DMF_VDBK_FIELD_COEFFS_P1_CASE1_MASK 0x0000000F
    #define MPP_DMF_VDBK_FIELD_COEFFS_P1_CASE1_SHIFT 0
    #define MPP_DMF_VDBK_FIELD_COEFFS_P1_CASE2_MASK 0x000000F0
    #define MPP_DMF_VDBK_FIELD_COEFFS_P1_CASE2_SHIFT 4
    #define MPP_DMF_VDBK_FIELD_COEFFS_P1_CASE3_MASK 0x00000F00
    #define MPP_DMF_VDBK_FIELD_COEFFS_P1_CASE3_SHIFT 8
    #define MPP_DMF_VDBK_FIELD_COEFFS_P1_CASE4_MASK 0x0000F000
    #define MPP_DMF_VDBK_FIELD_COEFFS_P1_CASE4_SHIFT 12
    #define MPP_DMF_VDBK_FIELD_COEFFS_P1_CASE6_MASK 0x000F0000
    #define MPP_DMF_VDBK_FIELD_COEFFS_P1_CASE6_SHIFT 16
#define  MPP_DMF_VDBK_FIELD_COEFFS_P2 0x765C
    #define MPP_DMF_VDBK_FIELD_COEFFS_P2_CASE1_MASK 0x0000000F
    #define MPP_DMF_VDBK_FIELD_COEFFS_P2_CASE1_SHIFT 0
    #define MPP_DMF_VDBK_FIELD_COEFFS_P2_CASE2_MASK 0x000000F0
    #define MPP_DMF_VDBK_FIELD_COEFFS_P2_CASE2_SHIFT 4
    #define MPP_DMF_VDBK_FIELD_COEFFS_P2_CASE3_MASK 0x00000F00
    #define MPP_DMF_VDBK_FIELD_COEFFS_P2_CASE3_SHIFT 8
    #define MPP_DMF_VDBK_FIELD_COEFFS_P2_CASE4_MASK 0x0000F000
    #define MPP_DMF_VDBK_FIELD_COEFFS_P2_CASE4_SHIFT 12
    #define MPP_DMF_VDBK_FIELD_COEFFS_P2_CASE6_MASK 0x000F0000
    #define MPP_DMF_VDBK_FIELD_COEFFS_P2_CASE6_SHIFT 16
#define  MPP_DMF_VDBK_FIELD_COEFFS_P3 0x7660
    #define MPP_DMF_VDBK_FIELD_COEFFS_P3_CASE1_MASK 0x0000000F
    #define MPP_DMF_VDBK_FIELD_COEFFS_P3_CASE1_SHIFT 0
    #define MPP_DMF_VDBK_FIELD_COEFFS_P3_CASE2_MASK 0x000000F0
    #define MPP_DMF_VDBK_FIELD_COEFFS_P3_CASE2_SHIFT 4
    #define MPP_DMF_VDBK_FIELD_COEFFS_P3_CASE3_MASK 0x00000F00
    #define MPP_DMF_VDBK_FIELD_COEFFS_P3_CASE3_SHIFT 8
    #define MPP_DMF_VDBK_FIELD_COEFFS_P3_CASE4_MASK 0x0000F000
    #define MPP_DMF_VDBK_FIELD_COEFFS_P3_CASE4_SHIFT 12
    #define MPP_DMF_VDBK_FIELD_COEFFS_P3_CASE6_MASK 0x000F0000
    #define MPP_DMF_VDBK_FIELD_COEFFS_P3_CASE6_SHIFT 16
#define  MPP_DMF_VDBK_FIELD_CONST 0x7664
    #define MPP_DMF_VDBK_FIELD_CONST_TB1_MASK 0x000000FF
    #define MPP_DMF_VDBK_FIELD_CONST_TB1_SHIFT 0
    #define MPP_DMF_VDBK_FIELD_CONST_TB2_MASK 0x0000FF00
    #define MPP_DMF_VDBK_FIELD_CONST_TB2_SHIFT 8
    #define MPP_DMF_VDBK_FIELD_CONST_TB3_MASK 0x00FF0000
    #define MPP_DMF_VDBK_FIELD_CONST_TB3_SHIFT 16
    #define MPP_DMF_VDBK_FIELD_CONST_MB1_MASK 0x0F000000
    #define MPP_DMF_VDBK_FIELD_CONST_MB1_SHIFT 24
    #define MPP_DMF_VDBK_FIELD_CONST_MB2_MASK 0xF0000000
    #define MPP_DMF_VDBK_FIELD_CONST_MB2_SHIFT 28
#define  MPP_DMF_VDBK_FRAME_COEFFS_P0 0x7640
    #define MPP_DMF_VDBK_FRAME_COEFFS_P0_CASE1_MASK 0x0000000F
    #define MPP_DMF_VDBK_FRAME_COEFFS_P0_CASE1_SHIFT 0
    #define MPP_DMF_VDBK_FRAME_COEFFS_P0_CASE2_MASK 0x000000F0
    #define MPP_DMF_VDBK_FRAME_COEFFS_P0_CASE2_SHIFT 4
    #define MPP_DMF_VDBK_FRAME_COEFFS_P0_CASE3_MASK 0x00000F00
    #define MPP_DMF_VDBK_FRAME_COEFFS_P0_CASE3_SHIFT 8
    #define MPP_DMF_VDBK_FRAME_COEFFS_P0_CASE4_MASK 0x0000F000
    #define MPP_DMF_VDBK_FRAME_COEFFS_P0_CASE4_SHIFT 12
    #define MPP_DMF_VDBK_FRAME_COEFFS_P0_CASE5_MASK 0x000F0000
    #define MPP_DMF_VDBK_FRAME_COEFFS_P0_CASE5_SHIFT 16
    #define MPP_DMF_VDBK_FRAME_COEFFS_P0_CASE6_MASK 0x00F00000
    #define MPP_DMF_VDBK_FRAME_COEFFS_P0_CASE6_SHIFT 20
#define  MPP_DMF_VDBK_FRAME_COEFFS_P1 0x7644
    #define MPP_DMF_VDBK_FRAME_COEFFS_P1_CASE1_MASK 0x0000000F
    #define MPP_DMF_VDBK_FRAME_COEFFS_P1_CASE1_SHIFT 0
    #define MPP_DMF_VDBK_FRAME_COEFFS_P1_CASE2_MASK 0x000000F0
    #define MPP_DMF_VDBK_FRAME_COEFFS_P1_CASE2_SHIFT 4
    #define MPP_DMF_VDBK_FRAME_COEFFS_P1_CASE3_MASK 0x00000F00
    #define MPP_DMF_VDBK_FRAME_COEFFS_P1_CASE3_SHIFT 8
    #define MPP_DMF_VDBK_FRAME_COEFFS_P1_CASE4_MASK 0x0000F000
    #define MPP_DMF_VDBK_FRAME_COEFFS_P1_CASE4_SHIFT 12
    #define MPP_DMF_VDBK_FRAME_COEFFS_P1_CASE5_MASK 0x000F0000
    #define MPP_DMF_VDBK_FRAME_COEFFS_P1_CASE5_SHIFT 16
    #define MPP_DMF_VDBK_FRAME_COEFFS_P1_CASE6_MASK 0x00F00000
    #define MPP_DMF_VDBK_FRAME_COEFFS_P1_CASE6_SHIFT 20
#define  MPP_DMF_VDBK_FRAME_COEFFS_P2 0x7648
    #define MPP_DMF_VDBK_FRAME_COEFFS_P2_CASE1_MASK 0x0000000F
    #define MPP_DMF_VDBK_FRAME_COEFFS_P2_CASE1_SHIFT 0
    #define MPP_DMF_VDBK_FRAME_COEFFS_P2_CASE2_MASK 0x000000F0
    #define MPP_DMF_VDBK_FRAME_COEFFS_P2_CASE2_SHIFT 4
    #define MPP_DMF_VDBK_FRAME_COEFFS_P2_CASE3_MASK 0x00000F00
    #define MPP_DMF_VDBK_FRAME_COEFFS_P2_CASE3_SHIFT 8
    #define MPP_DMF_VDBK_FRAME_COEFFS_P2_CASE4_MASK 0x0000F000
    #define MPP_DMF_VDBK_FRAME_COEFFS_P2_CASE4_SHIFT 12
    #define MPP_DMF_VDBK_FRAME_COEFFS_P2_CASE5_MASK 0x000F0000
    #define MPP_DMF_VDBK_FRAME_COEFFS_P2_CASE5_SHIFT 16
    #define MPP_DMF_VDBK_FRAME_COEFFS_P2_CASE6_MASK 0x00F00000
    #define MPP_DMF_VDBK_FRAME_COEFFS_P2_CASE6_SHIFT 20
#define  MPP_DMF_VDBK_FRAME_COEFFS_P3 0x764C
    #define MPP_DMF_VDBK_FRAME_COEFFS_P3_CASE1_MASK 0x0000000F
    #define MPP_DMF_VDBK_FRAME_COEFFS_P3_CASE1_SHIFT 0
    #define MPP_DMF_VDBK_FRAME_COEFFS_P3_CASE2_MASK 0x000000F0
    #define MPP_DMF_VDBK_FRAME_COEFFS_P3_CASE2_SHIFT 4
    #define MPP_DMF_VDBK_FRAME_COEFFS_P3_CASE3_MASK 0x00000F00
    #define MPP_DMF_VDBK_FRAME_COEFFS_P3_CASE3_SHIFT 8
    #define MPP_DMF_VDBK_FRAME_COEFFS_P3_CASE4_MASK 0x0000F000
    #define MPP_DMF_VDBK_FRAME_COEFFS_P3_CASE4_SHIFT 12
    #define MPP_DMF_VDBK_FRAME_COEFFS_P3_CASE5_MASK 0x000F0000
    #define MPP_DMF_VDBK_FRAME_COEFFS_P3_CASE5_SHIFT 16
    #define MPP_DMF_VDBK_FRAME_COEFFS_P3_CASE6_MASK 0x00F00000
    #define MPP_DMF_VDBK_FRAME_COEFFS_P3_CASE6_SHIFT 20
#define  MPP_DMF_VDBK_FRAME_CONST 0x7650
    #define MPP_DMF_VDBK_FRAME_CONST_TB1_MASK 0x000000FF
    #define MPP_DMF_VDBK_FRAME_CONST_TB1_SHIFT 0
    #define MPP_DMF_VDBK_FRAME_CONST_TB2_MASK 0x0000FF00
    #define MPP_DMF_VDBK_FRAME_CONST_TB2_SHIFT 8
    #define MPP_DMF_VDBK_FRAME_CONST_TB3_MASK 0x00FF0000
    #define MPP_DMF_VDBK_FRAME_CONST_TB3_SHIFT 16
    #define MPP_DMF_VDBK_FRAME_CONST_MB1_MASK 0x0F000000
    #define MPP_DMF_VDBK_FRAME_CONST_MB1_SHIFT 24
    #define MPP_DMF_VDBK_FRAME_CONST_MB2_MASK 0xF0000000
    #define MPP_DMF_VDBK_FRAME_CONST_MB2_SHIFT 28
#define  MPP_INT_TRIG 0x72D0
    #define MPP_INT_TRIG_NODATA_MASK 0x00000001
    #define MPP_INT_TRIG_NODATA_SHIFT 0
#define  MPP_MARB_CTRL 0x729C
    #define MPP_MARB_CTRL_MEM_CNT_RESET_MASK 0x00000001
    #define MPP_MARB_CTRL_MEM_CNT_RESET_SHIFT 0
    #define MPP_MARB_CTRL_MEM_CNT_EN_MASK 0x00000002
    #define MPP_MARB_CTRL_MEM_CNT_EN_SHIFT 1
    #define MPP_MARB_CTRL_MEM_CNT_SEL_MASK 0x00000004
    #define MPP_MARB_CTRL_MEM_CNT_SEL_SHIFT 2
    #define MPP_MARB_CTRL_READ_ACCEL_MASK 0x00000100
    #define MPP_MARB_CTRL_READ_ACCEL_SHIFT 8
    #define MPP_MARB_CTRL_PF_ARB_MASK 0x00000200
    #define MPP_MARB_CTRL_PF_ARB_SHIFT 9
#define  MPP_MEM_CNT 0x72A0
    #define MPP_MEM_CNT_MEM_CNT_MASK 0x00FFFFFF
    #define MPP_MEM_CNT_MEM_CNT_SHIFT 0
#define  MPP_STATUS 0x7260
    #define EVENTBUF_FREECNT_MASK 0x0000001F
    #define EVENTBUF_FREECNT_SHIFT 0
    #define MARB_WRITE_BUSY_MASK 0x00000020
    #define MARB_WRITE_BUSY_SHIFT 5
    #define MARB_READ_BUSY_MASK 0x00000040
    #define MARB_READ_BUSY_SHIFT 6
    #define DZQ_REGBUSY_MASK 0x00000100
    #define DZQ_REGBUSY_SHIFT 8
    #define DZQ_BUSY_MASK 0x00000200
    #define DZQ_BUSY_SHIFT 9
    #define IDCT_REGBUSY_MASK 0x00000400
    #define IDCT_REGBUSY_SHIFT 10
    #define IDCT_BUSY_MASK 0x00000800
    #define IDCT_BUSY_SHIFT 11
    #define MSC_BUSY_MASK 0x00001000
    #define MSC_BUSY_SHIFT 12
    #define SCL_BUSY_MASK 0x00002000
    #define SCL_BUSY_SHIFT 13
    #define DMF_BUSY_MASK 0x00004000
    #define DMF_BUSY_SHIFT 14
    #define MRE_BUSY_MASK 0x00010000
    #define MRE_BUSY_SHIFT 16
    #define DCT_BUSY_MASK 0x00020000
    #define DCT_BUSY_SHIFT 17
    #define EIDCT_BUSY_MASK 0x00040000
    #define EIDCT_BUSY_SHIFT 18
    #define EZQ_BUSY_MASK 0x00080000
    #define EZQ_BUSY_SHIFT 19
    #define OSF_REGBUSY_MASK 0x00100000
    #define OSF_REGBUSY_SHIFT 20
    #define OSF_BUSY_MASK 0x00200000
    #define OSF_BUSY_SHIFT 21
    #define RCB_BUSY_MASK 0x00400000
    #define RCB_BUSY_SHIFT 22
    #define DEC_BUSY_MASK 0x20000000
    #define DEC_BUSY_SHIFT 29
    #define ENC_BUSY_MASK 0x40000000
    #define ENC_BUSY_SHIFT 30
    #define MPP_BUSY_MASK 0x80000000
    #define MPP_BUSY_SHIFT 31
#define  MPP_WAIT_UNTIL 0x7320
    #define DZQ_REGRDY_MASK 0x00000100
    #define DZQ_REGRDY_SHIFT 8
    #define DZQ_IDLE_MASK 0x00000200
    #define DZQ_IDLE_SHIFT 9
    #define IDCT_REGRDY_MASK 0x00000400
    #define IDCT_REGRDY_SHIFT 10
    #define IDCT_IDLE_MASK 0x00000800
    #define IDCT_IDLE_SHIFT 11
    #define MRE_IDLE_MASK 0x00001000
    #define MRE_IDLE_SHIFT 12
    #define SCL_IDLE_MASK 0x00002000
    #define SCL_IDLE_SHIFT 13
    #define MSC_IDLE_MASK 0x00010000
    #define MSC_IDLE_SHIFT 16
    #define DCT_IDLE_MASK 0x00020000
    #define DCT_IDLE_SHIFT 17
    #define EIDCT_IDLE_MASK 0x00040000
    #define EIDCT_IDLE_SHIFT 18
    #define EZQ_IDLE_MASK 0x00080000
    #define EZQ_IDLE_SHIFT 19
    #define OSF_REGRDY_MASK 0x00100000
    #define OSF_REGRDY_SHIFT 20
    #define OSF_IDLE_MASK 0x00200000
    #define OSF_IDLE_SHIFT 21
    #define DEC_IDLE_MASK 0x20000000
    #define DEC_IDLE_SHIFT 29
    #define ENC_IDLE_MASK 0x40000000
    #define ENC_IDLE_SHIFT 30
    #define MPP_IDLE_MASK 0x80000000
    #define MPP_IDLE_SHIFT 31
#define  MRE_CLK_CTRL 0x74C8
    #define MRE_ECLK_GATE_EN_MASK 0x00000001
    #define MRE_ECLK_GATE_EN_SHIFT 0
    #define MRE_MCLK_GATE_EN_MASK 0x00000002
    #define MRE_MCLK_GATE_EN_SHIFT 1
    #define PICT_ECLK_GATE_EN_MASK 0x00000004
    #define PICT_ECLK_GATE_EN_SHIFT 2
    #define PICT_MCLK_GATE_EN_MASK 0x00000008
    #define PICT_MCLK_GATE_EN_SHIFT 3
    #define REF_ECLK_GATE_EN_MASK 0x00000010
    #define REF_ECLK_GATE_EN_SHIFT 4
    #define YCACHE_MCLK_GATE_EN_MASK 0x00000020
    #define YCACHE_MCLK_GATE_EN_SHIFT 5
    #define CCACHE_MCLK_GATE_EN_MASK 0x00000040
    #define CCACHE_MCLK_GATE_EN_SHIFT 6
#define  MRE_CTRL 0x73F4
    #define MRE_CTRL_SRCH_FRM_EN_MASK 0x00000001
    #define MRE_CTRL_SRCH_FRM_EN_SHIFT 0
    #define MRE_CTRL_SRCH_FLD_EN_MASK 0x00000002
    #define MRE_CTRL_SRCH_FLD_EN_SHIFT 1
    #define SRCH_FWD_BWD_EN_MASK 0x0000000C
    #define SRCH_FWD_BWD_EN_SHIFT 2
    #define MV_SCALE_H_EN_MASK 0x00000010
    #define MV_SCALE_H_EN_SHIFT 4
    #define MV_SCALE_V_EN_MASK 0x00000020
    #define MV_SCALE_V_EN_SHIFT 5
    #define INTRA_EN_MASK 0x00000040
    #define INTRA_EN_SHIFT 6
    #define FORCE_FRM_MO_MASK 0x00000080
    #define FORCE_FRM_MO_SHIFT 7
    #define IN_MODE_MASK 0x00000300
    #define IN_MODE_SHIFT 8
    #define MRE_CTRL_MV_BIAS_SHIFT_MASK 0x0000F000
    #define MRE_CTRL_MV_BIAS_SHIFT_SHIFT 12
    #define ENC_STATIONARY_EN_MASK 0x00010000
    #define ENC_STATIONARY_EN_SHIFT 16
    #define FCODE_CLAMP_EN_MASK 0x00020000
    #define FCODE_CLAMP_EN_SHIFT 17
    #define FIRST_PASS_FLAG_MASK 0x00040000
    #define FIRST_PASS_FLAG_SHIFT 18
    #define SECOND_PASS_FLAG_MASK 0x00080000
    #define SECOND_PASS_FLAG_SHIFT 19
    #define MV_SCALE_H_OVERRIDE_EN_MASK 0x00100000
    #define MV_SCALE_H_OVERRIDE_EN_SHIFT 20
    #define MV_SCALE_V_OVERRIDE_EN_MASK 0x00200000
    #define MV_SCALE_V_OVERRIDE_EN_SHIFT 21
    #define READ_8X8_TILE_MASK 0x00400000
    #define READ_8X8_TILE_SHIFT 22
    #define MRE_CTRL_HALF_PEL_REFINE_MASK 0x01000000
    #define MRE_CTRL_HALF_PEL_REFINE_SHIFT 24
    #define READ_LINEAR_MASK 0x10000000
    #define READ_LINEAR_SHIFT 28
#define  MRE_DBG_C_ADR 0x7290
    #define MRE_DBG_C_ADR_BASE_MASK 0x7FFFE000
    #define MRE_DBG_C_ADR_BASE_SHIFT 13
#define  MRE_DBG_Y_ADR 0x728C
    #define MRE_DBG_Y_ADR_BASE_MASK 0x7FFFE000
    #define MRE_DBG_Y_ADR_BASE_SHIFT 13
    #define MRE_DBG_Y_ADR_DEBUG_B_EN_MASK 0x80000000
    #define MRE_DBG_Y_ADR_DEBUG_B_EN_SHIFT 31
#define  MRE_DUMMY_REG 0x72DC
    #define MRE_DUMMY_REG_DUMMY_MASK 0xFFFFFFFF
    #define MRE_DUMMY_REG_DUMMY_SHIFT 0
#define  MRE_REFINE_MODE_SEL 0x74A8
    #define INTRA_THRES_MASK 0x00FFFFFF
    #define INTRA_THRES_SHIFT 0
    #define INTRA_MULT_MASK 0xF0000000
    #define INTRA_MULT_SHIFT 28
#define  MRE_STAT_A 0x727C
    #define MRE_STAT_A_STAT_A_MASK 0xFFFFFFFF
    #define MRE_STAT_A_STAT_A_SHIFT 0
#define  MRE_STAT_B 0x7280
    #define MRE_STAT_B_STAT_B_MASK 0xFFFFFFFF
    #define MRE_STAT_B_STAT_B_SHIFT 0
#define  MRE_STAT_MUX 0x7278
    #define MRE_STAT_MUX_STAT_SEL_A_MASK 0x0000000F
    #define MRE_STAT_MUX_STAT_SEL_A_SHIFT 0
    #define MRE_STAT_MUX_STAT_SEL_B_MASK 0x00000F00
    #define MRE_STAT_MUX_STAT_SEL_B_SHIFT 8
#define  MRE_TRIG 0x7310
    #define MRE_TRIG_MB_CNT_MASK 0x00007FFF
    #define MRE_TRIG_MB_CNT_SHIFT 0
    #define MRE_TRIG_FIELD_SCALE_MASK 0x00010000
    #define MRE_TRIG_FIELD_SCALE_SHIFT 16
    #define RESET_CNT_MASK 0x08000000
    #define RESET_CNT_SHIFT 27
    #define LOCK_CNT_MASK 0x10000000
    #define LOCK_CNT_SHIFT 28
    #define USE_MVI_MASK 0x20000000
    #define USE_MVI_SHIFT 29
    #define MRE_TRIG_TRIG_TYPE_MASK 0x80000000
    #define MRE_TRIG_TRIG_TYPE_SHIFT 31
#define  MSC_BWD_SUBFRM_ADR 0x7488
    #define MSC_BWD_SUBFRM_ADR_BASE_MASK 0x7FFFE000
    #define MSC_BWD_SUBFRM_ADR_BASE_SHIFT 13
#define  MSC_CLK_CTRL 0x74C4
    #define MSC_ECLK_GATE_EN_MASK 0x00000001
    #define MSC_ECLK_GATE_EN_SHIFT 0
    #define MSC_MCLK_GATE_EN_MASK 0x00000002
    #define MSC_MCLK_GATE_EN_SHIFT 1
    #define MSC_CLK_CTRL_XCODE_ECLK_GATE_EN_MASK 0x00000004
    #define MSC_CLK_CTRL_XCODE_ECLK_GATE_EN_SHIFT 2
    #define NCODE_ECLK_GATE_EN_MASK 0x00000008
    #define NCODE_ECLK_GATE_EN_SHIFT 3
    #define PBPICT_ECLK_GATE_EN_MASK 0x00000010
    #define PBPICT_ECLK_GATE_EN_SHIFT 4
    #define PBPICT_MCLK_GATE_EN_MASK 0x00000020
    #define PBPICT_MCLK_GATE_EN_SHIFT 5
#define  MSC_CTRL 0x7460
    #define MSC_CTRL_SRCH_FRM_EN_MASK 0x00000001
    #define MSC_CTRL_SRCH_FRM_EN_SHIFT 0
    #define MSC_CTRL_SRCH_FLD_EN_MASK 0x00000002
    #define MSC_CTRL_SRCH_FLD_EN_SHIFT 1
    #define SRCH_FWD_MV_EN_MASK 0x00000004
    #define SRCH_FWD_MV_EN_SHIFT 2
    #define SRCH_BWD_MV_EN_MASK 0x00000008
    #define SRCH_BWD_MV_EN_SHIFT 3
    #define SRCH_TMPRL_MVA_EN_MASK 0x00000010
    #define SRCH_TMPRL_MVA_EN_SHIFT 4
    #define MSC_CTRL_MV_BIAS_SHIFT_MASK 0x00000F00
    #define MSC_CTRL_MV_BIAS_SHIFT_SHIFT 8
    #define SRCH_MAX_MASK 0x1FFF0000
    #define SRCH_MAX_SHIFT 16
#define  MSC_DBG_C_ADR 0x7288
    #define MSC_DBG_C_ADR_BASE_MASK 0x7FFFE000
    #define MSC_DBG_C_ADR_BASE_SHIFT 13
#define  MSC_DBG_Y_ADR 0x7284
    #define MSC_DBG_Y_ADR_BASE_MASK 0x7FFFE000
    #define MSC_DBG_Y_ADR_BASE_SHIFT 13
    #define MSC_DBG_Y_ADR_DEBUG_B_EN_MASK 0x80000000
    #define MSC_DBG_Y_ADR_DEBUG_B_EN_SHIFT 31
#define  MSC_DUMMY_REG 0x72D8
    #define MSC_DUMMY_REG_DUMMY_MASK 0xFFFFFFFF
    #define MSC_DUMMY_REG_DUMMY_SHIFT 0
#define  MSC_FWD_SUBFRM_ADR 0x7480
    #define MSC_FWD_SUBFRM_ADR_BASE_MASK 0x7FFFE000
    #define MSC_FWD_SUBFRM_ADR_BASE_SHIFT 13
#define  MSC_MVA_TMPRL_ADR 0x7498
    #define MSC_MVA_TMPRL_ADR_BASE_MASK 0x7FFFFC00
    #define MSC_MVA_TMPRL_ADR_BASE_SHIFT 10
#define  MSC_SLICE_CNT 0x721C
    #define MSC_SLICE_CNT_MASK 0x0000007F
    #define MSC_SLICE_CNT_SHIFT 0
#define  MSC_SRCH_FRM_THRES 0x7468
    #define THRES_STATION_MASK 0x00003FFF
    #define THRES_STATION_SHIFT 0
    #define THRES_CANDIDATE_MASK 0x3FFF0000
    #define THRES_CANDIDATE_SHIFT 16
#define  MSC_SRCH_FULL 0x7470
    #define FULL_SPAN_X_MASK 0x000003FE
    #define FULL_SPAN_X_SHIFT 1
    #define FULL_SPAN_Y_MASK 0x03FE0000
    #define FULL_SPAN_Y_SHIFT 17
#define  MSC_SRCH_MAX 0x747C
    #define MAX_SPAN_X_MASK 0x00000FFE
    #define MAX_SPAN_X_SHIFT 1
    #define MAX_SPAN_Y_MASK 0x0FFE0000
    #define MAX_SPAN_Y_SHIFT 17
#define  MSC_SRCH_MV_SCL 0x746C
    #define MV_SCL_FWD_MASK 0x0000FFFF
    #define MV_SCL_FWD_SHIFT 0
    #define MV_SCL_BWD_MASK 0xFFFF0000
    #define MV_SCL_BWD_SHIFT 16
#define  MSC_SRCH_PART 0x7478
    #define PART_SPAN_X_MASK 0x000003FE
    #define PART_SPAN_X_SHIFT 1
    #define PART_SPAN_Y_MASK 0x03FE0000
    #define PART_SPAN_Y_SHIFT 17
#define  MSC_SRCH_SUB_THRES 0x7464
    #define THRES_FULL_MASK 0x00003FFF
    #define THRES_FULL_SHIFT 0
    #define THRES_PART_MASK 0x3FFF0000
    #define THRES_PART_SHIFT 16
#define  MSC_STAT_A 0x7270
    #define MSC_STAT_A_STAT_A_MASK 0xFFFFFFFF
    #define MSC_STAT_A_STAT_A_SHIFT 0
#define  MSC_STAT_B 0x7274
    #define MSC_STAT_B_STAT_B_MASK 0xFFFFFFFF
    #define MSC_STAT_B_STAT_B_SHIFT 0
#define  MSC_STAT_MUX 0x726C
    #define MSC_STAT_MUX_STAT_SEL_A_MASK 0x0000000F
    #define MSC_STAT_MUX_STAT_SEL_A_SHIFT 0
    #define MSC_STAT_MUX_STAT_SEL_B_MASK 0x00000F00
    #define MSC_STAT_MUX_STAT_SEL_B_SHIFT 8
#define  MSC_TRIG 0x7308
    #define MSC_TRIG_MB_CNT_MASK 0x00003FFF
    #define MSC_TRIG_MB_CNT_SHIFT 0
    #define MSC_TRIG_TRIG_TYPE_MASK 0x80000000
    #define MSC_TRIG_TRIG_TYPE_SHIFT 31
#define  MVD0_CTRL 0xA118
    #define MVD0_CTRL_FCODE_FWD_HORI_MASK 0x0000000F
    #define MVD0_CTRL_FCODE_FWD_HORI_SHIFT 0
    #define MVD0_CTRL_FCODE_FWD_VERT_MASK 0x000000F0
    #define MVD0_CTRL_FCODE_FWD_VERT_SHIFT 4
    #define MVD0_CTRL_FCODE_BWD_HORI_MASK 0x00000F00
    #define MVD0_CTRL_FCODE_BWD_HORI_SHIFT 8
    #define MVD0_CTRL_FCODE_BWD_VERT_MASK 0x0000F000
    #define MVD0_CTRL_FCODE_BWD_VERT_SHIFT 12
    #define MVD0_CTRL_FULL_PEL_FWD_MASK 0x00010000
    #define MVD0_CTRL_FULL_PEL_FWD_SHIFT 16
    #define MVD0_CTRL_FULL_PEL_BWD_MASK 0x00020000
    #define MVD0_CTRL_FULL_PEL_BWD_SHIFT 17
#define  MVD0_MV0_BWD 0xA148
    #define MVD0_MV0_BWD_MV_HORI_MASK 0x00001FFF
    #define MVD0_MV0_BWD_MV_HORI_SHIFT 0
    #define MVD0_MV0_BWD_MV_VERT_MASK 0x1FFF0000
    #define MVD0_MV0_BWD_MV_VERT_SHIFT 16
    #define MVD0_MV0_BWD_FLD_SEL_MASK 0x80000000
    #define MVD0_MV0_BWD_FLD_SEL_SHIFT 31
#define  MVD0_MV0_FWD 0xA144
    #define MVD0_MV0_FWD_MV_HORI_MASK 0x00001FFF
    #define MVD0_MV0_FWD_MV_HORI_SHIFT 0
    #define MVD0_MV0_FWD_MV_VERT_MASK 0x1FFF0000
    #define MVD0_MV0_FWD_MV_VERT_SHIFT 16
    #define MVD0_MV0_FWD_FLD_SEL_MASK 0x80000000
    #define MVD0_MV0_FWD_FLD_SEL_SHIFT 31
#define  MVD0_MV1_BWD 0xA150
    #define MVD0_MV1_BWD_MV_HORI_MASK 0x00001FFF
    #define MVD0_MV1_BWD_MV_HORI_SHIFT 0
    #define MVD0_MV1_BWD_MV_VERT_MASK 0x1FFF0000
    #define MVD0_MV1_BWD_MV_VERT_SHIFT 16
    #define MVD0_MV1_BWD_FLD_SEL_MASK 0x80000000
    #define MVD0_MV1_BWD_FLD_SEL_SHIFT 31
#define  MVD0_MV1_FWD 0xA14C
    #define MVD0_MV1_FWD_MV_HORI_MASK 0x00001FFF
    #define MVD0_MV1_FWD_MV_HORI_SHIFT 0
    #define MVD0_MV1_FWD_MV_VERT_MASK 0x1FFF0000
    #define MVD0_MV1_FWD_MV_VERT_SHIFT 16
    #define MVD0_MV1_FWD_FLD_SEL_MASK 0x80000000
    #define MVD0_MV1_FWD_FLD_SEL_SHIFT 31
#define  MVD0_PICT_RES 0xA114
    #define MVD0_PICT_RES_MB_WIDTH_MASK 0x0000007F
    #define MVD0_PICT_RES_MB_WIDTH_SHIFT 0
    #define MVD0_PICT_RES_MB_HEIGHT_MASK 0x007F0000
    #define MVD0_PICT_RES_MB_HEIGHT_SHIFT 16
    #define MVD0_PICT_RES_NO_VERIFY_X_MASK 0x40000000
    #define MVD0_PICT_RES_NO_VERIFY_X_SHIFT 30
    #define MVD0_PICT_RES_NO_VERIFY_Y_MASK 0x80000000
    #define MVD0_PICT_RES_NO_VERIFY_Y_SHIFT 31
#define  MVD0_RESET_PRED 0xA154
    #define MVD0_RESET_PRED_DATA_MASK 0xFFFFFFFF
    #define MVD0_RESET_PRED_DATA_SHIFT 0
#define  MVD0_STATUS 0xA15C
    #define MVD0_STATUS_DONE_MASK 0x00000001
    #define MVD0_STATUS_DONE_SHIFT 0
    #define MVD0_STATUS_MV0_FWD_VALID_MASK 0x00000010
    #define MVD0_STATUS_MV0_FWD_VALID_SHIFT 4
    #define MVD0_STATUS_MV0_BWD_VALID_MASK 0x00000020
    #define MVD0_STATUS_MV0_BWD_VALID_SHIFT 5
    #define MVD0_STATUS_MV1_FWD_VALID_MASK 0x00000040
    #define MVD0_STATUS_MV1_FWD_VALID_SHIFT 6
    #define MVD0_STATUS_MV1_BWD_VALID_MASK 0x00000080
    #define MVD0_STATUS_MV1_BWD_VALID_SHIFT 7
    #define MVD0_STATUS_ERROR_MASK 0xF0000000
    #define MVD0_STATUS_ERROR_SHIFT 28
#define  MVD0_TRIG 0xA158
    #define MVD0_TRIG_MB_TYPE_MASK 0x0000000F
    #define MVD0_TRIG_MB_TYPE_SHIFT 0
    #define MVD0_TRIG_MO_TYPE_MASK 0x00000030
    #define MVD0_TRIG_MO_TYPE_SHIFT 4
    #define MVD0_TRIG_MV_CNT_MASK 0x00000100
    #define MVD0_TRIG_MV_CNT_SHIFT 8
    #define MVD0_TRIG_MB_IDX_X_MASK 0x007F0000
    #define MVD0_TRIG_MB_IDX_X_SHIFT 16
    #define MVD0_TRIG_MB_IDX_Y_MASK 0x7F000000
    #define MVD0_TRIG_MB_IDX_Y_SHIFT 24
#define  MVD1_CTRL 0xA518
    #define MVD1_CTRL_FCODE_FWD_HORI_MASK 0x0000000F
    #define MVD1_CTRL_FCODE_FWD_HORI_SHIFT 0
    #define MVD1_CTRL_FCODE_FWD_VERT_MASK 0x000000F0
    #define MVD1_CTRL_FCODE_FWD_VERT_SHIFT 4
    #define MVD1_CTRL_FCODE_BWD_HORI_MASK 0x00000F00
    #define MVD1_CTRL_FCODE_BWD_HORI_SHIFT 8
    #define MVD1_CTRL_FCODE_BWD_VERT_MASK 0x0000F000
    #define MVD1_CTRL_FCODE_BWD_VERT_SHIFT 12
    #define MVD1_CTRL_FULL_PEL_FWD_MASK 0x00010000
    #define MVD1_CTRL_FULL_PEL_FWD_SHIFT 16
    #define MVD1_CTRL_FULL_PEL_BWD_MASK 0x00020000
    #define MVD1_CTRL_FULL_PEL_BWD_SHIFT 17
#define  MVD1_MV0_BWD 0xA548
    #define MVD1_MV0_BWD_MV_HORI_MASK 0x00001FFF
    #define MVD1_MV0_BWD_MV_HORI_SHIFT 0
    #define MVD1_MV0_BWD_MV_VERT_MASK 0x1FFF0000
    #define MVD1_MV0_BWD_MV_VERT_SHIFT 16
    #define MVD1_MV0_BWD_FLD_SEL_MASK 0x80000000
    #define MVD1_MV0_BWD_FLD_SEL_SHIFT 31
#define  MVD1_MV0_FWD 0xA544
    #define MVD1_MV0_FWD_MV_HORI_MASK 0x00001FFF
    #define MVD1_MV0_FWD_MV_HORI_SHIFT 0
    #define MVD1_MV0_FWD_MV_VERT_MASK 0x1FFF0000
    #define MVD1_MV0_FWD_MV_VERT_SHIFT 16
    #define MVD1_MV0_FWD_FLD_SEL_MASK 0x80000000
    #define MVD1_MV0_FWD_FLD_SEL_SHIFT 31
#define  MVD1_MV1_BWD 0xA550
    #define MVD1_MV1_BWD_MV_HORI_MASK 0x00001FFF
    #define MVD1_MV1_BWD_MV_HORI_SHIFT 0
    #define MVD1_MV1_BWD_MV_VERT_MASK 0x1FFF0000
    #define MVD1_MV1_BWD_MV_VERT_SHIFT 16
    #define MVD1_MV1_BWD_FLD_SEL_MASK 0x80000000
    #define MVD1_MV1_BWD_FLD_SEL_SHIFT 31
#define  MVD1_MV1_FWD 0xA54C
    #define MVD1_MV1_FWD_MV_HORI_MASK 0x00001FFF
    #define MVD1_MV1_FWD_MV_HORI_SHIFT 0
    #define MVD1_MV1_FWD_MV_VERT_MASK 0x1FFF0000
    #define MVD1_MV1_FWD_MV_VERT_SHIFT 16
    #define MVD1_MV1_FWD_FLD_SEL_MASK 0x80000000
    #define MVD1_MV1_FWD_FLD_SEL_SHIFT 31
#define  MVD1_PICT_RES 0xA514
    #define MVD1_PICT_RES_MB_WIDTH_MASK 0x0000007F
    #define MVD1_PICT_RES_MB_WIDTH_SHIFT 0
    #define MVD1_PICT_RES_MB_HEIGHT_MASK 0x007F0000
    #define MVD1_PICT_RES_MB_HEIGHT_SHIFT 16
    #define MVD1_PICT_RES_NO_VERIFY_X_MASK 0x40000000
    #define MVD1_PICT_RES_NO_VERIFY_X_SHIFT 30
    #define MVD1_PICT_RES_NO_VERIFY_Y_MASK 0x80000000
    #define MVD1_PICT_RES_NO_VERIFY_Y_SHIFT 31
#define  MVD1_RESET_PRED 0xA554
    #define MVD1_RESET_PRED_DATA_MASK 0xFFFFFFFF
    #define MVD1_RESET_PRED_DATA_SHIFT 0
#define  MVD1_STATUS 0xA55C
    #define MVD1_STATUS_DONE_MASK 0x00000001
    #define MVD1_STATUS_DONE_SHIFT 0
    #define MVD1_STATUS_MV0_FWD_VALID_MASK 0x00000010
    #define MVD1_STATUS_MV0_FWD_VALID_SHIFT 4
    #define MVD1_STATUS_MV0_BWD_VALID_MASK 0x00000020
    #define MVD1_STATUS_MV0_BWD_VALID_SHIFT 5
    #define MVD1_STATUS_MV1_FWD_VALID_MASK 0x00000040
    #define MVD1_STATUS_MV1_FWD_VALID_SHIFT 6
    #define MVD1_STATUS_MV1_BWD_VALID_MASK 0x00000080
    #define MVD1_STATUS_MV1_BWD_VALID_SHIFT 7
    #define MVD1_STATUS_ERROR_MASK 0xF0000000
    #define MVD1_STATUS_ERROR_SHIFT 28
#define  MVD1_TRIG 0xA558
    #define MVD1_TRIG_MB_TYPE_MASK 0x0000000F
    #define MVD1_TRIG_MB_TYPE_SHIFT 0
    #define MVD1_TRIG_MO_TYPE_MASK 0x00000030
    #define MVD1_TRIG_MO_TYPE_SHIFT 4
    #define MVD1_TRIG_MV_CNT_MASK 0x00000100
    #define MVD1_TRIG_MV_CNT_SHIFT 8
    #define MVD1_TRIG_MB_IDX_X_MASK 0x007F0000
    #define MVD1_TRIG_MB_IDX_X_SHIFT 16
    #define MVD1_TRIG_MB_IDX_Y_MASK 0x7F000000
    #define MVD1_TRIG_MB_IDX_Y_SHIFT 24
#define  NFC_BANK_COL_ADDR 0xE000
    #define NF_COL_ADDR_MASK 0x0000FFFF
    #define NF_COL_ADDR_SHIFT 0
    #define NF_BANK_ADDR_MASK 0xFF000000
    #define NF_BANK_ADDR_SHIFT 24
#define  NFC_BCH_CONTROL 0xE070
    #define BCH_ENABLE_MASK 0x00000001
    #define BCH_ENABLE_SHIFT 0
    #define BCH_CORR_EN_MASK 0x00000002
    #define BCH_CORR_EN_SHIFT 1
    #define BCH_WR_SYNDRM_MASK 0x00000004
    #define BCH_WR_SYNDRM_SHIFT 2
    #define BCH_NBIT_CORR_MASK 0x000000F0
    #define BCH_NBIT_CORR_SHIFT 4
    #define BCH_PARITY_BITS_MASK 0x00007F00
    #define BCH_PARITY_BITS_SHIFT 8
    #define BCH_PARITY_SIZE_MASK 0x000F0000
    #define BCH_PARITY_SIZE_SHIFT 16
#define  NFC_BCH_GEN_POLY0 0xE074
    #define BCH_GEN_POLY0_MASK 0xFFFFFFFF
    #define BCH_GEN_POLY0_SHIFT 0
#define  NFC_BCH_GEN_POLY1 0xE078
    #define BCH_GEN_POLY1_MASK 0xFFFFFFFF
    #define BCH_GEN_POLY1_SHIFT 0
#define  NFC_BCH_GEN_POLY2 0xE07C
    #define BCH_GEN_POLY2_MASK 0xFFFFFFFF
    #define BCH_GEN_POLY2_SHIFT 0
#define  NFC_BCH_GEN_POLY3 0xE080
    #define BCH_GEN_POLY3_MASK 0xFFFFFFFF
    #define BCH_GEN_POLY3_SHIFT 0
#define  NFC_BOOTSTRAP 0xE094
    #define BOOT_CTRL_EN_MASK 0x00000001
    #define BOOT_CTRL_EN_SHIFT 0
    #define BUS_WIDTH_MASK 0x00000002
    #define BUS_WIDTH_SHIFT 1
    #define BLOCK_SIZE_MASK 0x00000004
    #define BLOCK_SIZE_SHIFT 2
    #define PAGE_2_4K_MASK 0x00000008
    #define PAGE_2_4K_SHIFT 3
    #define RADDR_CYC_MASK 0x00000010
    #define RADDR_CYC_SHIFT 4
    #define PAGE_BLOCK_MASK 0x00000020
    #define PAGE_BLOCK_SHIFT 5
    #define SLC_MLC_MODE_MASK 0x00000040
    #define SLC_MLC_MODE_SHIFT 6
    #define BCH_9BIT_CORR_MASK 0x00000080
    #define BCH_9BIT_CORR_SHIFT 7
#define  NFC_BOOTSTRAP_OVRRIDE 0xE098
    #define BOOT_CTRL_EN_OVRRIDE_MASK 0x00000001
    #define BOOT_CTRL_EN_OVRRIDE_SHIFT 0
    #define BUS_WIDTH_OVRRIDE_MASK 0x00000002
    #define BUS_WIDTH_OVRRIDE_SHIFT 1
    #define BLOCK_SIZE_OVRRIDE_MASK 0x00000004
    #define BLOCK_SIZE_OVRRIDE_SHIFT 2
    #define PAGE_2_4K_OVRRIDE_MASK 0x00000008
    #define PAGE_2_4K_OVRRIDE_SHIFT 3
    #define RADDR_CYC_OVRRIDE_MASK 0x00000010
    #define RADDR_CYC_OVRRIDE_SHIFT 4
    #define PAGE_BLOCK_OVRRIDE_MASK 0x00000020
    #define PAGE_BLOCK_OVRRIDE_SHIFT 5
    #define SLC_MLC_MODE_OVRRIDE_MASK 0x00000040
    #define SLC_MLC_MODE_OVRRIDE_SHIFT 6
    #define BCH_9BIT_CORR_OVRRIDE_MASK 0x00000080
    #define BCH_9BIT_CORR_OVRRIDE_SHIFT 7
    #define BOOTSTRAP_OVRRIDE_EN_MASK 0x80000000
    #define BOOTSTRAP_OVRRIDE_EN_SHIFT 31
#define  NFC_BOOT_ADDR 0xE090
    #define BOOT_ADDR_MASK 0xFFFFFFFF
    #define BOOT_ADDR_SHIFT 0
#define  NFC_BOOT_CFG 0xE08C
    #define NFC_BOOT_IDLE_MASK 0x00000010
    #define NFC_BOOT_IDLE_SHIFT 4
    #define NFC_BOOT_ECC_ERR_MASK 0x00000020
    #define NFC_BOOT_ECC_ERR_SHIFT 5
    #define NFC_BOOT_BAD_BLOCK_MASK 0x00000040
    #define NFC_BOOT_BAD_BLOCK_SHIFT 6
#define  NFC_CMD_STATUS 0xE020
    #define NFC_CMD_STATUS_BUSY_MASK 0x00000001
    #define NFC_CMD_STATUS_BUSY_SHIFT 0
    #define DST0FIFO_FILLED_MASK 0x10000000
    #define DST0FIFO_FILLED_SHIFT 28
    #define DST1FIFO_FILLED_MASK 0x20000000
    #define DST1FIFO_FILLED_SHIFT 29
    #define DST2FIFO_FILLED_MASK 0x40000000
    #define DST2FIFO_FILLED_SHIFT 30
#define  NFC_COMMAND 0xE010
    #define CMD_CODE_MASK 0x000000FF
    #define CMD_CODE_SHIFT 0
    #define CMD_PARAM_MASK 0x0FFF0000
    #define CMD_PARAM_SHIFT 16
#define  NFC_CONTROL 0xE068
    #define NFC_CONTROL_RESETN_MASK 0x00000001
    #define NFC_CONTROL_RESETN_SHIFT 0
    #define SEQ_READ_MASK 0x00000100
    #define SEQ_READ_SHIFT 8
    #define STOP_ON_ERR_MASK 0x00010000
    #define STOP_ON_ERR_SHIFT 16
    #define BANK_NUM_MASK 0x03000000
    #define BANK_NUM_SHIFT 24
    #define INTERLEAVE_MASK 0x80000000
    #define INTERLEAVE_SHIFT 31
#define  NFC_DATA_ADDR 0xE008
    #define SRC_DST_ADDR_MASK 0x7FFFFFF0
    #define SRC_DST_ADDR_SHIFT 4
#define  NFC_DEBUG_REG 0xE0AC
    #define NFC_DEBUG_REG_DEBUG_DATA_MASK 0xFFFFFFFF
    #define NFC_DEBUG_REG_DEBUG_DATA_SHIFT 0
#define  NFC_DEV_RB 0xE01C
    #define NF_RB_N_MASK 0x000000FF
    #define NF_RB_N_SHIFT 0
#define  NFC_DEV_STATUS 0xE018
    #define NF_STATUS_MASK 0x000000FF
    #define NF_STATUS_SHIFT 0
#define  NFC_DUMMY_REG 0xE0A8
    #define NFC_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define NFC_DUMMY_REG_DATA_SHIFT 0
#define  NFC_ECC_CONTROL 0xE06C
    #define ECC_1B_DISABLE_MASK 0x00000001
    #define ECC_1B_DISABLE_SHIFT 0
    #define ECC_1B_CORR_MASK 0x00000002
    #define ECC_1B_CORR_SHIFT 1
#define  NFC_ECC_ERR_MAP0 0xE04C
    #define ERR_MAP0_MASK 0xFFFFFFFF
    #define ERR_MAP0_SHIFT 0
#define  NFC_ECC_ERR_MAP1 0xE050
    #define ERR_MAP1_MASK 0xFFFFFFFF
    #define ERR_MAP1_SHIFT 0
#define  NFC_ECC_ERR_MAP2 0xE054
    #define ERR_MAP2_MASK 0xFFFFFFFF
    #define ERR_MAP2_SHIFT 0
#define  NFC_ECC_ERR_MAP3 0xE058
    #define ERR_MAP3_MASK 0xFFFFFFFF
    #define ERR_MAP3_SHIFT 0
#define  NFC_ECC_STAUTS0 0xE02C
    #define ECC_ERR0_MASK 0x00000003
    #define ECC_ERR0_SHIFT 0
    #define ECC_LOC0_MASK 0x000FFF00
    #define ECC_LOC0_SHIFT 8
    #define ECC_PAGE_MASK 0xFF000000
    #define ECC_PAGE_SHIFT 24
#define  NFC_ECC_STAUTS1 0xE030
    #define ECC_ERR1_MASK 0x00000003
    #define ECC_ERR1_SHIFT 0
    #define ECC_LOC1_MASK 0x000FFF00
    #define ECC_LOC1_SHIFT 8
#define  NFC_ECC_STAUTS2 0xE034
    #define ECC_ERR2_MASK 0x00000003
    #define ECC_ERR2_SHIFT 0
    #define ECC_LOC2_MASK 0x000FFF00
    #define ECC_LOC2_SHIFT 8
#define  NFC_ECC_STAUTS3 0xE038
    #define ECC_ERR3_MASK 0x00000003
    #define ECC_ERR3_SHIFT 0
    #define ECC_LOC3_MASK 0x000FFF00
    #define ECC_LOC3_SHIFT 8
#define  NFC_ECC_STAUTS4 0xE03C
    #define ECC_ERR4_MASK 0x00000003
    #define ECC_ERR4_SHIFT 0
    #define ECC_LOC4_MASK 0x000FFF00
    #define ECC_LOC4_SHIFT 8
#define  NFC_ECC_STAUTS5 0xE040
    #define ECC_ERR5_MASK 0x00000003
    #define ECC_ERR5_SHIFT 0
    #define ECC_LOC5_MASK 0x000FFF00
    #define ECC_LOC5_SHIFT 8
#define  NFC_ECC_STAUTS6 0xE044
    #define ECC_ERR6_MASK 0x00000003
    #define ECC_ERR6_SHIFT 0
    #define ECC_LOC6_MASK 0x000FFF00
    #define ECC_LOC6_SHIFT 8
#define  NFC_ECC_STAUTS7 0xE048
    #define ECC_ERR7_MASK 0x00000003
    #define ECC_ERR7_SHIFT 0
    #define ECC_LOC7_MASK 0x000FFF00
    #define ECC_LOC7_SHIFT 8
#define  NFC_EXTENDED_ID 0xE028
    #define ID_REG5_MASK 0x000000FF
    #define ID_REG5_SHIFT 0
#define  NFC_HOST_INT_MASK 0xE060
    #define ECC_1BIT_HOST_MASK_MASK 0x00000001
    #define ECC_1BIT_HOST_MASK_SHIFT 0
    #define ECC_ERR_HOST_MASK_MASK 0x00000002
    #define ECC_ERR_HOST_MASK_SHIFT 1
    #define ECC_VAL_HOST_MASK_MASK 0x00000004
    #define ECC_VAL_HOST_MASK_SHIFT 2
    #define ILLEGAL_ACC_H_MASK_MASK 0x00000008
    #define ILLEGAL_ACC_H_MASK_SHIFT 3
    #define CMD_DONE_HOST_MASK_MASK 0x00000010
    #define CMD_DONE_HOST_MASK_SHIFT 4
#define  NFC_ID 0xE024
    #define ID_REG1_MASK 0x000000FF
    #define ID_REG1_SHIFT 0
    #define ID_REG2_MASK 0x0000FF00
    #define ID_REG2_SHIFT 8
    #define ID_REG3_MASK 0x00FF0000
    #define ID_REG3_SHIFT 16
    #define ID_REG4_MASK 0xFF000000
    #define ID_REG4_SHIFT 24
#define  NFC_INT_STATUS 0xE05C
    #define ECC_1BIT_INT_MASK 0x00000001
    #define ECC_1BIT_INT_SHIFT 0
    #define ECC_ERR_INT_MASK 0x00000002
    #define ECC_ERR_INT_SHIFT 1
    #define ECC_VAL_INT_MASK 0x00000004
    #define ECC_VAL_INT_SHIFT 2
    #define ILLEGAL_ACC_INT_MASK 0x00000008
    #define ILLEGAL_ACC_INT_SHIFT 3
    #define CMD_DONE_INT_MASK 0x00000010
    #define CMD_DONE_INT_SHIFT 4
#define  NFC_IO_TIMING 0xE09C
    #define TCES_MASK 0x00000003
    #define TCES_SHIFT 0
    #define TCED_MASK 0x0000000C
    #define TCED_SHIFT 2
    #define TCEHL_MASK 0x000001F0
    #define TCEHL_SHIFT 4
    #define TCLS_MASK 0x00007000
    #define TCLS_SHIFT 12
    #define TALS_MASK 0x00070000
    #define TALS_SHIFT 16
    #define TCLH_MASK 0x00300000
    #define TCLH_SHIFT 20
    #define TALH_MASK 0x00C00000
    #define TALH_SHIFT 22
    #define TAR_MASK 0x03000000
    #define TAR_SHIFT 24
    #define TADL_MASK 0x7C000000
    #define TADL_SHIFT 26
#define  NFC_IO_TIMING2 0xE0A0
    #define TWP_MASK 0x00000007
    #define TWP_SHIFT 0
    #define TWH_MASK 0x00000030
    #define TWH_SHIFT 4
    #define TWB_MASK 0x000007C0
    #define TWB_SHIFT 6
    #define TWHR_MASK 0x0000F000
    #define TWHR_SHIFT 12
    #define TRP_MASK 0x000F0000
    #define TRP_SHIFT 16
    #define TREH_MASK 0x00300000
    #define TREH_SHIFT 20
    #define TREA_MASK 0x07000000
    #define TREA_SHIFT 24
    #define NFC_IO_TIMING2_TRR_MASK 0x70000000
    #define NFC_IO_TIMING2_TRR_SHIFT 28
#define  NFC_IO_TIMING3 0xE0A4
    #define TBRD_MASK 0x0000001F
    #define TBRD_SHIFT 0
    #define TRRD_MASK 0x00001F00
    #define TRRD_SHIFT 8
    #define TRB_MASK 0x001F0000
    #define TRB_SHIFT 16
    #define TIO_MASK 0x07000000
    #define TIO_SHIFT 24
#define  NFC_MIPS_INT_MASK 0xE064
    #define ECC_1BIT_MIPS_MASK_MASK 0x00000001
    #define ECC_1BIT_MIPS_MASK_SHIFT 0
    #define ECC_ERR_MIPS_MASK_MASK 0x00000002
    #define ECC_ERR_MIPS_MASK_SHIFT 1
    #define ECC_VAL_MIPS_MASK_MASK 0x00000004
    #define ECC_VAL_MIPS_MASK_SHIFT 2
    #define ILLEGAL_ACC_M_MASK_MASK 0x00000008
    #define ILLEGAL_ACC_M_MASK_SHIFT 3
    #define CMD_DONE_MIPS_MASK_MASK 0x00000010
    #define CMD_DONE_MIPS_MASK_SHIFT 4
#define  NFC_NANDF_RDATA 0xE014
    #define NF_RDATA_MASK 0xFFFFFFFF
    #define NF_RDATA_SHIFT 0
#define  NFC_PAGE_ROW_ADDR 0xE004
    #define NANDF_ADDR_MASK 0xFFFFFFFF
    #define NANDF_ADDR_SHIFT 0
#define  NFC_SPARE_ADDR 0xE00C
    #define SPARE_ADDR_MASK 0x7FFFFFF0
    #define SPARE_ADDR_SHIFT 4
#define  NFC_WRITE_PROT 0xE088
    #define NANDF_WP_MASK 0x0000000F
    #define NANDF_WP_SHIFT 0
    #define NFC_WRITE_PROT_LOCK_MASK 0x00000100
    #define NFC_WRITE_PROT_LOCK_SHIFT 8
    #define LOCK_TIGHT_MASK 0x00000200
    #define LOCK_TIGHT_SHIFT 9
#define  OSF_CONST_REG1 0x7314
    #define OSF_CONST_REG1_DATA_MASK 0xFFFFFFFF
    #define OSF_CONST_REG1_DATA_SHIFT 0
#define  OSF_CONST_REG2 0x7318
    #define OSF_CONST_REG2_CNT_MASK 0x0000001F
    #define OSF_CONST_REG2_CNT_SHIFT 0
    #define OSF_CONST_REG2_DATA_MASK 0xFFFFFFE0
    #define OSF_CONST_REG2_DATA_SHIFT 5
#define  OSF_CTRL 0x73F8
    #define PADDING_MASK 0x00000003
    #define PADDING_SHIFT 0
    #define MB_SKIP_EN_MASK 0x00000004
    #define MB_SKIP_EN_SHIFT 2
    #define ENC_FRMPRED_FRMDCT_MASK 0x00000008
    #define ENC_FRMPRED_FRMDCT_SHIFT 3
    #define QSCALE_INITIAL_MASK 0x000007F0
    #define QSCALE_INITIAL_SHIFT 4
    #define OSF_CTRL_PROG_FRM_MASK 0x00000800
    #define OSF_CTRL_PROG_FRM_SHIFT 11
    #define MB_ADR_BITS_MASK 0x0000F000
    #define MB_ADR_BITS_SHIFT 12
    #define FCODE_FW_H_MASK 0x000F0000
    #define FCODE_FW_H_SHIFT 16
    #define FCODE_FW_V_MASK 0x00F00000
    #define FCODE_FW_V_SHIFT 20
    #define FCODE_BW_H_MASK 0x0F000000
    #define FCODE_BW_H_SHIFT 24
    #define FCODE_BW_V_MASK 0xF0000000
    #define FCODE_BW_V_SHIFT 28
#define  OSF_DST_ADR 0x745C
    #define OSF_DST_ADR_BASE_MASK 0x7FFFFC00
    #define OSF_DST_ADR_BASE_SHIFT 10
#define  OSF_MAX_BYTES 0x74D0
    #define MAX_BYTES_VALUE_MASK 0x00FFFFF8
    #define MAX_BYTES_VALUE_SHIFT 3
#define  OSF_OBB_CNT_FREERUN 0x72B0
    #define OBB_CNT_FREERUN_MASK 0x00FFFFFF
    #define OBB_CNT_FREERUN_SHIFT 0
#define  OSF_OBB_CNT_STATIC 0x72B4
    #define OBB_CNT_STATIC_MASK 0x00FFFFFF
    #define OBB_CNT_STATIC_SHIFT 0
#define  OSF_TRIG 0x731C
    #define OSF_TRIG_NODATA_MASK 0x00000001
    #define OSF_TRIG_NODATA_SHIFT 0
#define  PCIE_ASYNC_IF_STATUS 0x1C28
    #define DBI_ACK_MASK 0x00000001
    #define DBI_ACK_SHIFT 0
    #define MSI_GRANT_MASK 0x00000002
    #define MSI_GRANT_SHIFT 1
    #define MSI_EN_MASK 0x00000004
    #define MSI_EN_SHIFT 2
    #define VMI_GRANT_MASK 0x00000008
    #define VMI_GRANT_SHIFT 3
    #define VMI_VALID_MASK 0x00000010
    #define VMI_VALID_SHIFT 4
    #define MSG_REQ_ID_MASK 0xFFFF0000
    #define MSG_REQ_ID_SHIFT 16
#define  PCIE_ASYNC_IF_WDAT_HI 0x1C00
    #define PCIE_ASYNC_IF_WDAT_HI_WDAT_MASK 0xFFFFFFFF
    #define PCIE_ASYNC_IF_WDAT_HI_WDAT_SHIFT 0
#define  PCIE_ASYNC_IF_WDAT_LO 0x1C04
    #define PCIE_ASYNC_IF_WDAT_LO_WDAT_MASK 0xFFFFFFFF
    #define PCIE_ASYNC_IF_WDAT_LO_WDAT_SHIFT 0
#define  PCIE_AUTO_MSI 0x1C18
    #define AUTO_MSI_EN_MASK 0x00000001
    #define AUTO_MSI_EN_SHIFT 0
    #define AUTO_MSI_ASSERT_MASK 0x0000003E
    #define AUTO_MSI_ASSERT_SHIFT 1
    #define AUTO_MSI_DEASSERT_MASK 0x000007C0
    #define AUTO_MSI_DEASSERT_SHIFT 6
#define  PCIE_DBI_ADDR 0x1C08
    #define DBI_ADDR_MASK 0xFFFFFFFF
    #define DBI_ADDR_SHIFT 0
#define  PCIE_DBI_CTRL 0x1C0C
    #define DBI_CS_MASK 0x00000001
    #define DBI_CS_SHIFT 0
    #define DBI_CS2_MASK 0x00000002
    #define DBI_CS2_SHIFT 1
    #define DBI_WR_MASK 0x000000F0
    #define DBI_WR_SHIFT 4
#define  PCIE_DBI_DOUT 0x1C10
    #define DBI_RDAT_MASK 0xFFFFFFFF
    #define DBI_RDAT_SHIFT 0
#define  PCIE_DEBUG 0x1C40
    #define PCIE_DEBUG_DEBUG_DATA_MASK 0x000FFFFF
    #define PCIE_DEBUG_DEBUG_DATA_SHIFT 0
#define  PCIE_DIAGNOSTIC 0x1C3C
    #define DIAGNOSTIC_TD_MASK 0x00000001
    #define DIAGNOSTIC_TD_SHIFT 0
    #define DIAGNOSTIC_EP_MASK 0x00000002
    #define DIAGNOSTIC_EP_SHIFT 1
    #define DIAGNOSTIC_INT_MASK 0x00000004
    #define DIAGNOSTIC_INT_SHIFT 2
    #define DIAGNOSTIC_DMAR_MASK 0x00000008
    #define DIAGNOSTIC_DMAR_SHIFT 3
    #define DIAGNOSTIC_DMAW_MASK 0x00000010
    #define DIAGNOSTIC_DMAW_SHIFT 4
    #define DIAGNOSTIC_LTSSM_EN_MASK 0x00000020
    #define DIAGNOSTIC_LTSSM_EN_SHIFT 5
    #define DIAGNOSTIC_CFG_RETRY_MASK 0x00000040
    #define DIAGNOSTIC_CFG_RETRY_SHIFT 6
    #define DIAG_CTRL_BUS_MASK 0x00000700
    #define DIAG_CTRL_BUS_SHIFT 8
    #define REFCLK_RAMP_TIME_MASK 0xFF000000
    #define REFCLK_RAMP_TIME_SHIFT 24
#define  PCIE_DMA_CFGIO_EN 0x1D00
    #define CFGIO_EN_MASK 0x00000007
    #define CFGIO_EN_SHIFT 0
    #define PCIE_DMA_CFGIO_EN_TLP_TID_LB_MASK 0x000000F8
    #define PCIE_DMA_CFGIO_EN_TLP_TID_LB_SHIFT 3
    #define PCIE_DMA_CFGIO_EN_TLP_TID_UB_MASK 0x00001F00
    #define PCIE_DMA_CFGIO_EN_TLP_TID_UB_SHIFT 8
    #define PCIE_DMA_CFGIO_EN_RETRY_WAIT_CYC_MASK 0x00FF0000
    #define PCIE_DMA_CFGIO_EN_RETRY_WAIT_CYC_SHIFT 16
#define  PCIE_DMA_READ_CFG0 0x1C34
    #define PCIE_DMA_READ_CFG0_MAX_REQ_DW_SZ_MASK 0x000007FF
    #define PCIE_DMA_READ_CFG0_MAX_REQ_DW_SZ_SHIFT 0
    #define PCIE_DMA_READ_CFG0_MAX_REQ_DW_SZ_OVERRIDE_MASK 0x00001000
    #define PCIE_DMA_READ_CFG0_MAX_REQ_DW_SZ_OVERRIDE_SHIFT 12
    #define PCIE_DMA_READ_CFG0_TLP_TID_LB_MASK 0x001F0000
    #define PCIE_DMA_READ_CFG0_TLP_TID_LB_SHIFT 16
    #define PCIE_DMA_READ_CFG0_TLP_TID_UB_MASK 0x1F000000
    #define PCIE_DMA_READ_CFG0_TLP_TID_UB_SHIFT 24
#define  PCIE_DMA_READ_CFG1 0x1C38
    #define PCIE_DMA_READ_CFG1_MTU0_DISABLE_MASK 0x00000001
    #define PCIE_DMA_READ_CFG1_MTU0_DISABLE_SHIFT 0
    #define PCIE_DMA_READ_CFG1_MTU1_DISABLE_MASK 0x00000002
    #define PCIE_DMA_READ_CFG1_MTU1_DISABLE_SHIFT 1
    #define MTU2_DISABLE_MASK 0x00000004
    #define MTU2_DISABLE_SHIFT 2
    #define MTU3_DISABLE_MASK 0x00000008
    #define MTU3_DISABLE_SHIFT 3
    #define PCIE_DMA_READ_CFG1_RETRY_WAIT_CYC_MASK 0x00FF0000
    #define PCIE_DMA_READ_CFG1_RETRY_WAIT_CYC_SHIFT 16
#define  PCIE_DUMMY_REG 0x1C48
    #define PCIE_DUMMY_REG_DUMMY_BITS_MASK 0xFFFFFFFF
    #define PCIE_DUMMY_REG_DUMMY_BITS_SHIFT 0
#define  PCIE_HBRG_ADDR 0x1D04
    #define PCIE_HBRG_ADDR_MASK 0xFFFFFFFF
    #define PCIE_HBRG_ADDR_SHIFT 0
#define  PCIE_HBRG_CMD 0x1D10
    #define PCIE_HBRG_CMD_MASK 0x000000FF
    #define PCIE_HBRG_CMD_SHIFT 0
#define  PCIE_HBRG_RDAT 0x1D0C
    #define PCIE_HBRG_RDAT_MASK 0xFFFFFFFF
    #define PCIE_HBRG_RDAT_SHIFT 0
#define  PCIE_HBRG_STATUS 0x1D14
    #define PCIE_HBRG_DONE_MASK 0x00000001
    #define PCIE_HBRG_DONE_SHIFT 0
#define  PCIE_HBRG_WDAT 0x1D08
    #define PCIE_HBRG_WDAT_MASK 0xFFFFFFFF
    #define PCIE_HBRG_WDAT_SHIFT 0
#define  PCIE_HDMA_READ_CFG0 0x1D38
    #define PCIE_HDMA_READ_CFG0_MAX_REQ_DW_SZ_MASK 0x000007FF
    #define PCIE_HDMA_READ_CFG0_MAX_REQ_DW_SZ_SHIFT 0
    #define PCIE_HDMA_READ_CFG0_MAX_REQ_DW_SZ_OVERRIDE_MASK 0x00001000
    #define PCIE_HDMA_READ_CFG0_MAX_REQ_DW_SZ_OVERRIDE_SHIFT 12
    #define PCIE_HDMA_READ_CFG0_TLP_TID_LB_MASK 0x001F0000
    #define PCIE_HDMA_READ_CFG0_TLP_TID_LB_SHIFT 16
    #define PCIE_HDMA_READ_CFG0_TLP_TID_UB_MASK 0x1F000000
    #define PCIE_HDMA_READ_CFG0_TLP_TID_UB_SHIFT 24
#define  PCIE_HDMA_READ_CFG1 0x1D3C
    #define PCIE_HDMA_READ_CFG1_MTU0_DISABLE_MASK 0x00000001
    #define PCIE_HDMA_READ_CFG1_MTU0_DISABLE_SHIFT 0
    #define PCIE_HDMA_READ_CFG1_MTU1_DISABLE_MASK 0x00000002
    #define PCIE_HDMA_READ_CFG1_MTU1_DISABLE_SHIFT 1
    #define PCIE_HDMA_READ_CFG1_RETRY_WAIT_CYC_MASK 0x00FF0000
    #define PCIE_HDMA_READ_CFG1_RETRY_WAIT_CYC_SHIFT 16
#define  PCIE_IO_ADDR 0x1D30
    #define PCIE_IO_ADDR_MASK 0xFFFFFFFF
    #define PCIE_IO_ADDR_SHIFT 0
#define  PCIE_IO_SIZE 0x1D34
    #define PCIE_IO_SIZE_MASK 0xFFFFFFFF
    #define PCIE_IO_SIZE_SHIFT 0
#define  PCIE_MSI_CTRL 0x1C14
    #define MSI_FUN_NUM_MASK 0x00000007
    #define MSI_FUN_NUM_SHIFT 0
    #define MSI_TC_MASK 0x00000070
    #define MSI_TC_SHIFT 4
    #define MSI_VECTOR_MASK 0x00001F00
    #define MSI_VECTOR_SHIFT 8
#define  PCIE_NP_ADDR 0x1D28
    #define PCIE_NP_ADDR_MASK 0xFFFFFFFF
    #define PCIE_NP_ADDR_SHIFT 0
#define  PCIE_NP_SIZE 0x1D2C
    #define PCIE_NP_SIZE_MASK 0xFFFFFFFF
    #define PCIE_NP_SIZE_SHIFT 0
#define  PCIE_PF_ADDR 0x1D20
    #define PCIE_PF_ADDR_MASK 0xFFFFFFFF
    #define PCIE_PF_ADDR_SHIFT 0
#define  PCIE_PF_SIZE 0x1D24
    #define PCIE_PF_SIZE_MASK 0xFFFFFFFF
    #define PCIE_PF_SIZE_SHIFT 0
#define  PCIE_PF_WATERMARK 0x1D18
    #define PCIE_PF_WATERMARK_MASK 0x0000003F
    #define PCIE_PF_WATERMARK_SHIFT 0
#define  PCIE_PHY_COMMON_CTRL 0x1C54
    #define PCIE_PHY_CTRL_RTUNE_DO_TUNE_MASK 0x00000001
    #define PCIE_PHY_CTRL_RTUNE_DO_TUNE_SHIFT 0
    #define PCIE_PHY_CTRL_TX_LVL_MASK 0x0000003E
    #define PCIE_PHY_CTRL_TX_LVL_SHIFT 1
    #define PCIE_PHY_CTRL_LOS_LVL_MASK 0x000007C0
    #define PCIE_PHY_CTRL_LOS_LVL_SHIFT 6
    #define PCIE_PHY_CTRL_ACJT_LVL_MASK 0x0000F800
    #define PCIE_PHY_CTRL_ACJT_LVL_SHIFT 11
    #define PCIE_PHY_CTRL_RESET_N_MASK 0x00010000
    #define PCIE_PHY_CTRL_RESET_N_SHIFT 16
    #define PCIE_PHY_CTRL_OVERRIDE_CTRL_MASK 0x00020000
    #define PCIE_PHY_CTRL_OVERRIDE_CTRL_SHIFT 17
#define  PCIE_PHY_CR_IN 0x1C5C
    #define PCIE_PHY_CR_IN_DATA_MASK 0x0000FFFF
    #define PCIE_PHY_CR_IN_DATA_SHIFT 0
    #define PCIE_PHY_CR_IN_ACK_MASK 0x00010000
    #define PCIE_PHY_CR_IN_ACK_SHIFT 16
#define  PCIE_PHY_CR_OUT 0x1C58
    #define PCIE_PHY_CR_OUT_DATA_MASK 0x0000FFFF
    #define PCIE_PHY_CR_OUT_DATA_SHIFT 0
    #define PCIE_PHY_CR_OUT_CAP_ADDR_MASK 0x00010000
    #define PCIE_PHY_CR_OUT_CAP_ADDR_SHIFT 16
    #define PCIE_PHY_CR_OUT_CAP_DATA_MASK 0x00020000
    #define PCIE_PHY_CR_OUT_CAP_DATA_SHIFT 17
    #define PCIE_PHY_CR_OUT_WRITE_MASK 0x00040000
    #define PCIE_PHY_CR_OUT_WRITE_SHIFT 18
    #define PCIE_PHY_CR_OUT_READ_MASK 0x00080000
    #define PCIE_PHY_CR_OUT_READ_SHIFT 19
#define  PCIE_PHY_MPLL_CTRL 0x1C50
    #define PCIE_PHY_CTRL_MPLL_CK_OFF_MASK 0x00000001
    #define PCIE_PHY_CTRL_MPLL_CK_OFF_SHIFT 0
    #define PCIE_PHY_CTRL_MPLL_PWRON_MASK 0x00000002
    #define PCIE_PHY_CTRL_MPLL_PWRON_SHIFT 1
    #define PCIE_PHY_CTRL_MPLL_PRESCALE_MASK 0x00000018
    #define PCIE_PHY_CTRL_MPLL_PRESCALE_SHIFT 3
    #define PCIE_PHY_CTRL_MPLL_SS_EN_MASK 0x00000020
    #define PCIE_PHY_CTRL_MPLL_SS_EN_SHIFT 5
    #define PCIE_PHY_CTRL_MPLL_NCY_MASK 0x00000F80
    #define PCIE_PHY_CTRL_MPLL_NCY_SHIFT 7
    #define PCIE_PHY_CTRL_MPLL_NCY5_MASK 0x00003000
    #define PCIE_PHY_CTRL_MPLL_NCY5_SHIFT 12
    #define PCIE_PHY_CTRL_MPLL_INT_CTL_MASK 0x00038000
    #define PCIE_PHY_CTRL_MPLL_INT_CTL_SHIFT 15
    #define PCIE_PHY_CTRL_MPLL_PROP_CTL_MASK 0x00380000
    #define PCIE_PHY_CTRL_MPLL_PROP_CTL_SHIFT 19
    #define PCIE_PHY_CTRL_CKO_WORD_CON_MASK 0x03800000
    #define PCIE_PHY_CTRL_CKO_WORD_CON_SHIFT 23
    #define PCIE_PHY_CTRL_CKO_ALIVE_CON_MASK 0x18000000
    #define PCIE_PHY_CTRL_CKO_ALIVE_CON_SHIFT 27
#define  PCIE_PHY_TXRX_CTRL 0x1C4C
    #define PCIE_PHY_CTRL_TX_EN_MASK 0x00000007
    #define PCIE_PHY_CTRL_TX_EN_SHIFT 0
    #define PCIE_PHY_CTRL_TX_BOOST_MASK 0x000000F0
    #define PCIE_PHY_CTRL_TX_BOOST_SHIFT 4
    #define PCIE_PHY_CTRL_TX_ATTEN_MASK 0x00000700
    #define PCIE_PHY_CTRL_TX_ATTEN_SHIFT 8
    #define PCIE_PHY_CTRL_TX_CLK_ALIGN_MASK 0x00000800
    #define PCIE_PHY_CTRL_TX_CLK_ALIGN_SHIFT 11
    #define PCIE_PHY_CTRL_TX_CKO_EN_MASK 0x00001000
    #define PCIE_PHY_CTRL_TX_CKO_EN_SHIFT 12
    #define PCIE_PHY_CTRL_TX_EDGERATE_MASK 0x00006000
    #define PCIE_PHY_CTRL_TX_EDGERATE_SHIFT 13
    #define PCIE_PHY_CTRL_RX_EN_MASK 0x00008000
    #define PCIE_PHY_CTRL_RX_EN_SHIFT 15
    #define PCIE_PHY_CTRL_RX_PLL_PWRON_MASK 0x00010000
    #define PCIE_PHY_CTRL_RX_PLL_PWRON_SHIFT 16
    #define PCIE_PHY_CTRL_RX_ALIGN_EN_MASK 0x00020000
    #define PCIE_PHY_CTRL_RX_ALIGN_EN_SHIFT 17
    #define PCIE_PHY_CTRL_RX_TERM_EN_MASK 0x00040000
    #define PCIE_PHY_CTRL_RX_TERM_EN_SHIFT 18
    #define PCIE_PHY_CTRL_RX_EQ_VAL_MASK 0x00700000
    #define PCIE_PHY_CTRL_RX_EQ_VAL_SHIFT 20
    #define PCIE_PHY_CTRL_RX_DPLL_MODE_MASK 0x07000000
    #define PCIE_PHY_CTRL_RX_DPLL_MODE_SHIFT 24
    #define PCIE_PHY_CTRL_DPLL_RESET_MASK 0x10000000
    #define PCIE_PHY_CTRL_DPLL_RESET_SHIFT 28
    #define PCIE_PHY_CTRL_RX_LOS_CTL_MASK 0x60000000
    #define PCIE_PHY_CTRL_RX_LOS_CTL_SHIFT 29
#define  PCIE_POWER_MGMT 0x1C60
    #define CLKREQ_N_MASK 0x00000001
    #define CLKREQ_N_SHIFT 0
    #define CLKREQ_SEL_MASK 0x00000002
    #define CLKREQ_SEL_SHIFT 1
#define  PCIE_SFT_RSTN 0x1C44
    #define PCIE_SFT_RSTN_SFT_RSTN_MASK 0x00000001
    #define PCIE_SFT_RSTN_SFT_RSTN_SHIFT 0
#define  PCIE_SII_IDX 0x1C2C
    #define SII_IDX_MASK 0x00000003
    #define SII_IDX_SHIFT 0
    #define DIAG_STATUS_BUS_MUX_MASK 0x000001E0
    #define DIAG_STATUS_BUS_MUX_SHIFT 5
#define  PCIE_SII_INFO 0x1D40
    #define INTA_ASSERTED_MASK 0x00000001
    #define INTA_ASSERTED_SHIFT 0
    #define INTB_ASSERTED_MASK 0x00000002
    #define INTB_ASSERTED_SHIFT 1
    #define INTC_ASSERTED_MASK 0x00000004
    #define INTC_ASSERTED_SHIFT 2
    #define INTD_ASSERTED_MASK 0x00000008
    #define INTD_ASSERTED_SHIFT 3
    #define INTA_DEASSERTED_MASK 0x00000010
    #define INTA_DEASSERTED_SHIFT 4
    #define INTB_DEASSERTED_MASK 0x00000020
    #define INTB_DEASSERTED_SHIFT 5
    #define INTC_DEASSERTED_MASK 0x00000040
    #define INTC_DEASSERTED_SHIFT 6
    #define INTD_DEASSERTED_MASK 0x00000080
    #define INTD_DEASSERTED_SHIFT 7
    #define PM_PME_MSG_MASK 0x00000100
    #define PM_PME_MSG_SHIFT 8
    #define PM_PME_TOACK_MSG_MASK 0x00000200
    #define PM_PME_TOACK_MSG_SHIFT 9
    #define PM_PME_TURNOFF_MSG_MASK 0x00000400
    #define PM_PME_TURNOFF_MSG_SHIFT 10
    #define ERR_CORRECTABLE_MASK 0x00000800
    #define ERR_CORRECTABLE_SHIFT 11
    #define ERR_NONFATAL_MASK 0x00001000
    #define ERR_NONFATAL_SHIFT 12
    #define ERR_FATAL_MASK 0x00002000
    #define ERR_FATAL_SHIFT 13
    #define UNLOCK_MSG_MASK 0x00004000
    #define UNLOCK_MSG_SHIFT 14
#define  PCIE_SII_RDAT 0x1C30
    #define SII_RDAT_MASK 0xFFFFFFFF
    #define SII_RDAT_SHIFT 0
#define  PCIE_VMI_CTRL 0x1C20
    #define VMI_FUN_NUM_MASK 0x00000007
    #define VMI_FUN_NUM_SHIFT 0
    #define VMI_TAG_MASK 0x00000FF0
    #define VMI_TAG_SHIFT 4
    #define VMI_CODE_MASK 0x000FF000
    #define VMI_CODE_SHIFT 12
#define  PCIE_VMI_DOUT 0x1C24
    #define VMI_RDAT_MASK 0xFFFFFFFF
    #define VMI_RDAT_SHIFT 0
#define  PCIE_VMI_PARAM 0x1C1C
    #define VMI_FMT_MASK 0x00000003
    #define VMI_FMT_SHIFT 0
    #define VMI_TYPE_MASK 0x000001F0
    #define VMI_TYPE_SHIFT 4
    #define VMI_TC_MASK 0x00007000
    #define VMI_TC_SHIFT 12
    #define VMI_TD_MASK 0x00010000
    #define VMI_TD_SHIFT 16
    #define VMI_EP_MASK 0x00020000
    #define VMI_EP_SHIFT 17
    #define VMI_ATTR_MASK 0x000C0000
    #define VMI_ATTR_SHIFT 18
    #define VMI_LEN_MASK 0x3FF00000
    #define VMI_LEN_SHIFT 20
#define  PCIH_BR_ADDR 0x1CBC
    #define PCIH_BR_ADDR_MASK 0xFFFFFFFF
    #define PCIH_BR_ADDR_SHIFT 0
#define  PCIH_BR_SIZE 0x1CD0
    #define PCIH_BR_SIZE_MASK 0xFFFFFFFF
    #define PCIH_BR_SIZE_SHIFT 0
#define  PCIH_IO_ADDR 0x1CB4
    #define PCIH_IO_ADDR_MASK 0xFFFFFFFF
    #define PCIH_IO_ADDR_SHIFT 0
#define  PCIH_IO_SIZE 0x1CB8
    #define PCIH_IO_SIZE_MASK 0xFFFFFFFF
    #define PCIH_IO_SIZE_SHIFT 0
#define  PCIH_K_FIX 0x1CF0
    #define BRIDGE_TYPE_MASK 0x00000600
    #define BRIDGE_TYPE_SHIFT 9
#define  PCIH_NP_ADDR 0x1CAC
    #define PCIH_NP_ADDR_MASK 0xFFFFFFFF
    #define PCIH_NP_ADDR_SHIFT 0
#define  PCIH_NP_SIZE 0x1CB0
    #define PCIH_NP_SIZE_MASK 0xFFFFFFFF
    #define PCIH_NP_SIZE_SHIFT 0
#define  PCIH_PF_ADDR 0x1CA4
    #define PCIH_PF_ADDR_MASK 0xFFFFFFFF
    #define PCIH_PF_ADDR_SHIFT 0
#define  PCIH_PF_SIZE 0x1CA8
    #define PCIH_PF_SIZE_MASK 0xFFFFFFFF
    #define PCIH_PF_SIZE_SHIFT 0
#define  PCI_AHB_ARB01_LAT 0x1C9C
    #define AHB_ARB_MSTR0_LAT_MASK 0x00003FFF
    #define AHB_ARB_MSTR0_LAT_SHIFT 0
    #define AHB_ARB_MSTR0_DIS_MASK 0x00008000
    #define AHB_ARB_MSTR0_DIS_SHIFT 15
    #define AHB_ARB_MSTR1_LAT_MASK 0x3FFF0000
    #define AHB_ARB_MSTR1_LAT_SHIFT 16
    #define AHB_ARB_MSTR1_DIS_MASK 0x80000000
    #define AHB_ARB_MSTR1_DIS_SHIFT 31
#define  PCI_AHB_ARB23_LAT 0x1CA0
    #define AHB_ARB_MSTR2_LAT_MASK 0x00003FFF
    #define AHB_ARB_MSTR2_LAT_SHIFT 0
    #define AHB_ARB_MSTR2_DIS_MASK 0x00008000
    #define AHB_ARB_MSTR2_DIS_SHIFT 15
    #define AHB_ARB_MSTR3_LAT_MASK 0x3FFF0000
    #define AHB_ARB_MSTR3_LAT_SHIFT 16
    #define AHB_ARB_MSTR3_DIS_MASK 0x80000000
    #define AHB_ARB_MSTR3_DIS_SHIFT 31
#define  PCI_AHB_WRITE_LAT 0x1C98
    #define AHB_FBW_LAT_MASK 0x000000FF
    #define AHB_FBW_LAT_SHIFT 0
    #define AHB_FBR_PFD_EXPTIME_MASK 0x0000FF00
    #define AHB_FBR_PFD_EXPTIME_SHIFT 8
    #define AHB_DMAW_LAT_MASK 0x00FF0000
    #define AHB_DMAW_LAT_SHIFT 16
#define  PCI_DEBUG 0x1CF8
    #define PCI_DEBUG_DEBUG_DATA_MASK 0xFFFFFFFF
    #define PCI_DEBUG_DEBUG_DATA_SHIFT 0
#define  PCI_DMA_STATUS 0x1CF4
    #define DMAW_DONE_STATUS_MASK 0x00000001
    #define DMAW_DONE_STATUS_SHIFT 0
#define  PCI_HBRG_ADDR 0x1C80
    #define PCI_HBRG_ADDR_MASK 0xFFFFFFFF
    #define PCI_HBRG_ADDR_SHIFT 0
#define  PCI_HBRG_CMD 0x1C8C
    #define PCI_HBRG_CMD_MASK 0x000000FF
    #define PCI_HBRG_CMD_SHIFT 0
#define  PCI_HBRG_RDAT 0x1C88
    #define PCI_HBRG_RDAT_MASK 0xFFFFFFFF
    #define PCI_HBRG_RDAT_SHIFT 0
#define  PCI_HBRG_STATUS 0x1C90
    #define PCI_HBRG_DONE_MASK 0x00000001
    #define PCI_HBRG_DONE_SHIFT 0
#define  PCI_HBRG_WDAT 0x1C84
    #define PCI_HBRG_WDAT_MASK 0xFFFFFFFF
    #define PCI_HBRG_WDAT_SHIFT 0
#define  PCI_MISC_CNTL 0x1C94
    #define PCI_HBRG_DIS_MASK 0x00000001
    #define PCI_HBRG_DIS_SHIFT 0
    #define AHB_ARB_ON_RETRY_MASK 0x000000F0
    #define AHB_ARB_ON_RETRY_SHIFT 4
    #define AHB_DMAR_CROSS_1K_MASK 0x00000200
    #define AHB_DMAR_CROSS_1K_SHIFT 9
    #define AHB_DMAW_CROSS_1K_MASK 0x00000400
    #define AHB_DMAW_CROSS_1K_SHIFT 10
    #define DMA_ERR_DET_DIS_MASK 0x00000800
    #define DMA_ERR_DET_DIS_SHIFT 11
    #define PCI_CLKRUN_GPIO_EN_MASK 0x00010000
    #define PCI_CLKRUN_GPIO_EN_SHIFT 16
    #define PCI_CLKRUN_EN_MASK 0x00020000
    #define PCI_CLKRUN_EN_SHIFT 17
    #define PCI_RBM_BLOCK_MC_MASK 0x00100000
    #define PCI_RBM_BLOCK_MC_SHIFT 20
    #define AHB_R_FLUSH_W_MASK 0x00200000
    #define AHB_R_FLUSH_W_SHIFT 21
    #define PCI_R_FLUSH_W_MASK 0x00400000
    #define PCI_R_FLUSH_W_SHIFT 22
    #define AHB_W_BLOCK_R_MASK 0x00800000
    #define AHB_W_BLOCK_R_SHIFT 23
    #define PCI_W_BLOCK_R_MASK 0x01000000
    #define PCI_W_BLOCK_R_SHIFT 24
#define  PID_TABLE_ADR 0x6040
    #define PID_TABLE_ADR_BASE_MASK 0x0000007F
    #define PID_TABLE_ADR_BASE_SHIFT 0
#define  PID_TABLE_LWDAT 0x6044
    #define PID_MASK 0x00001FFF
    #define PID_SHIFT 0
    #define SID_MASK 0x0000E000
    #define SID_SHIFT 13
    #define PID_RMAP_MASK 0x1FFF0000
    #define PID_RMAP_SHIFT 16
    #define RMAP_EN_MASK 0x20000000
    #define RMAP_EN_SHIFT 29
    #define PTVALID_MASK 0x80000000
    #define PTVALID_SHIFT 31
#define  PID_TABLE_UWDAT 0x6048
    #define RID_MASK 0x0000003F
    #define RID_SHIFT 0
    #define PID_TABLE_UWDAT_MODE_MASK 0x00000300
    #define PID_TABLE_UWDAT_MODE_SHIFT 8
    #define PID_RANGE_MASK 0x0003F000
    #define PID_RANGE_SHIFT 12
    #define TTS_PCR_RTP_CHOOSE_MASK 0x00F00000
    #define TTS_PCR_RTP_CHOOSE_SHIFT 20
    #define PID_RANGE_EN_MASK 0x10000000
    #define PID_RANGE_EN_SHIFT 28
    #define SID_MSB_MASK 0x20000000
    #define SID_MSB_SHIFT 29
    #define TEI_FILTER_MASK 0x40000000
    #define TEI_FILTER_SHIFT 30
#define  PPC_BOOTSTRAP 0x10C4
    #define SPI_RATE_SEL_MASK 0x0000000C
    #define SPI_RATE_SEL_SHIFT 2
    #define I2C_SLAVE_ADDR_SEL_MASK 0x00000010
    #define I2C_SLAVE_ADDR_SEL_SHIFT 4
#define  PPC_CLOCK_CTRL 0x10A0
    #define SCC0_CLOCK_GATE_EN_MASK 0x00000004
    #define SCC0_CLOCK_GATE_EN_SHIFT 2
    #define I2C0_SLAVE_DIS_MASK 0x00000080
    #define I2C0_SLAVE_DIS_SHIFT 7
    #define I2C0_SLAVE_SAMPLE_RATE_MASK 0x00000F00
    #define I2C0_SLAVE_SAMPLE_RATE_SHIFT 8
#define  PPC_DEBUG_DATA 0x10F4
    #define PPC_DEBUG_DATA_DEBUG_DATA_MASK 0x000FFFFF
    #define PPC_DEBUG_DATA_DEBUG_DATA_SHIFT 0
#define  PPC_DUMMY_REG 0x10FC
    #define PPC_DUMMY_REG_DUMMY_REG_MASK 0xFFFFFFFF
    #define PPC_DUMMY_REG_DUMMY_REG_SHIFT 0
#define  PPC_HOST_INT_MASK 0x1098
    #define PPC_HOST_INT_MASK_INT_EN_GPIO_0_INT_MASK 0x00000001
    #define PPC_HOST_INT_MASK_INT_EN_GPIO_0_INT_SHIFT 0
    #define PPC_HOST_INT_MASK_INT_EN_GPIO_1_INT_MASK 0x00000002
    #define PPC_HOST_INT_MASK_INT_EN_GPIO_1_INT_SHIFT 1
    #define PPC_HOST_INT_MASK_INT_EN_GPIO_2_INT_MASK 0x00000004
    #define PPC_HOST_INT_MASK_INT_EN_GPIO_2_INT_SHIFT 2
    #define PPC_HOST_INT_MASK_INT_EN_GPIO_3_INT_MASK 0x00000008
    #define PPC_HOST_INT_MASK_INT_EN_GPIO_3_INT_SHIFT 3
    #define PPC_HOST_INT_MASK_INT_EN_GPIO_4_INT_MASK 0x00000010
    #define PPC_HOST_INT_MASK_INT_EN_GPIO_4_INT_SHIFT 4
    #define PPC_HOST_INT_MASK_INT_EN_I2C0_XFERDONE_MASK 0x00000040
    #define PPC_HOST_INT_MASK_INT_EN_I2C0_XFERDONE_SHIFT 6
    #define PPC_HOST_INT_MASK_INT_EN_I2C1_XFERDONE_MASK 0x00000080
    #define PPC_HOST_INT_MASK_INT_EN_I2C1_XFERDONE_SHIFT 7
    #define PPC_HOST_INT_MASK_INT_EN_SCC0_TXDONE_MASK 0x00000100
    #define PPC_HOST_INT_MASK_INT_EN_SCC0_TXDONE_SHIFT 8
    #define PPC_HOST_INT_MASK_INT_EN_SCC0_PARITY_DET_MASK 0x00000200
    #define PPC_HOST_INT_MASK_INT_EN_SCC0_PARITY_DET_SHIFT 9
    #define PPC_HOST_INT_MASK_INT_EN_SCC0_ERROR_MASK 0x00000400
    #define PPC_HOST_INT_MASK_INT_EN_SCC0_ERROR_SHIFT 10
    #define PPC_HOST_INT_MASK_INT_EN_I2C0_ARB_FAIL_MASK 0x00100000
    #define PPC_HOST_INT_MASK_INT_EN_I2C0_ARB_FAIL_SHIFT 20
    #define PPC_HOST_INT_MASK_INT_EN_I2C0_BUSY_ERROR_MASK 0x00200000
    #define PPC_HOST_INT_MASK_INT_EN_I2C0_BUSY_ERROR_SHIFT 21
    #define PPC_HOST_INT_MASK_INT_EN_CCSPI_RX_PACKET_DONE_MASK 0x00400000
    #define PPC_HOST_INT_MASK_INT_EN_CCSPI_RX_PACKET_DONE_SHIFT 22
    #define PPC_HOST_INT_MASK_INT_EN_CCSPI_TX_PACKET_DONE_MASK 0x00800000
    #define PPC_HOST_INT_MASK_INT_EN_CCSPI_TX_PACKET_DONE_SHIFT 23
    #define PPC_HOST_INT_MASK_INT_EN_SPI_DONE_MASK 0x01000000
    #define PPC_HOST_INT_MASK_INT_EN_SPI_DONE_SHIFT 24
    #define PPC_HOST_INT_MASK_INT_EN_I2C1_ARB_FAIL_MASK 0x02000000
    #define PPC_HOST_INT_MASK_INT_EN_I2C1_ARB_FAIL_SHIFT 25
    #define PPC_HOST_INT_MASK_INT_EN_I2C1_BUSY_ERROR_MASK 0x04000000
    #define PPC_HOST_INT_MASK_INT_EN_I2C1_BUSY_ERROR_SHIFT 26
#define  PPC_INT_STATUS 0x1094
    #define GPIO_0_INT_MASK 0x00000001
    #define GPIO_0_INT_SHIFT 0
    #define GPIO_1_INT_MASK 0x00000002
    #define GPIO_1_INT_SHIFT 1
    #define GPIO_2_INT_MASK 0x00000004
    #define GPIO_2_INT_SHIFT 2
    #define GPIO_3_INT_MASK 0x00000008
    #define GPIO_3_INT_SHIFT 3
    #define GPIO_4_INT_MASK 0x00000010
    #define GPIO_4_INT_SHIFT 4
    #define I2C0_XFERDONE_MASK 0x00000040
    #define I2C0_XFERDONE_SHIFT 6
    #define I2C1_XFERDONE_MASK 0x00000080
    #define I2C1_XFERDONE_SHIFT 7
    #define SCC0_TXDONE_MASK 0x00000100
    #define SCC0_TXDONE_SHIFT 8
    #define SCC0_PARITY_DET_MASK 0x00000200
    #define SCC0_PARITY_DET_SHIFT 9
    #define SCC0_ERROR_MASK 0x00000400
    #define SCC0_ERROR_SHIFT 10
    #define I2C0_ARB_FAIL_MASK 0x00100000
    #define I2C0_ARB_FAIL_SHIFT 20
    #define I2C0_BUSY_ERROR_MASK 0x00200000
    #define I2C0_BUSY_ERROR_SHIFT 21
    #define CCSPI_RX_PACKET_DONE_MASK 0x00400000
    #define CCSPI_RX_PACKET_DONE_SHIFT 22
    #define CCSPI_TX_PACKET_DONE_MASK 0x00800000
    #define CCSPI_TX_PACKET_DONE_SHIFT 23
    #define SPI_DONE_MASK 0x01000000
    #define SPI_DONE_SHIFT 24
    #define I2C1_ARB_FAIL_MASK 0x02000000
    #define I2C1_ARB_FAIL_SHIFT 25
    #define I2C1_BUSY_ERROR_MASK 0x04000000
    #define I2C1_BUSY_ERROR_SHIFT 26
#define  PPC_MIPS_INT_MASK 0x109C
    #define PPC_MIPS_INT_MASK_INT_EN_GPIO_0_INT_MASK 0x00000001
    #define PPC_MIPS_INT_MASK_INT_EN_GPIO_0_INT_SHIFT 0
    #define PPC_MIPS_INT_MASK_INT_EN_GPIO_1_INT_MASK 0x00000002
    #define PPC_MIPS_INT_MASK_INT_EN_GPIO_1_INT_SHIFT 1
    #define PPC_MIPS_INT_MASK_INT_EN_GPIO_2_INT_MASK 0x00000004
    #define PPC_MIPS_INT_MASK_INT_EN_GPIO_2_INT_SHIFT 2
    #define PPC_MIPS_INT_MASK_INT_EN_GPIO_3_INT_MASK 0x00000008
    #define PPC_MIPS_INT_MASK_INT_EN_GPIO_3_INT_SHIFT 3
    #define PPC_MIPS_INT_MASK_INT_EN_GPIO_4_INT_MASK 0x00000010
    #define PPC_MIPS_INT_MASK_INT_EN_GPIO_4_INT_SHIFT 4
    #define PPC_MIPS_INT_MASK_INT_EN_I2C0_XFERDONE_MASK 0x00000040
    #define PPC_MIPS_INT_MASK_INT_EN_I2C0_XFERDONE_SHIFT 6
    #define PPC_MIPS_INT_MASK_INT_EN_I2C1_XFERDONE_MASK 0x00000080
    #define PPC_MIPS_INT_MASK_INT_EN_I2C1_XFERDONE_SHIFT 7
    #define PPC_MIPS_INT_MASK_INT_EN_SCC0_TXDONE_MASK 0x00000100
    #define PPC_MIPS_INT_MASK_INT_EN_SCC0_TXDONE_SHIFT 8
    #define PPC_MIPS_INT_MASK_INT_EN_SCC0_PARITY_DET_MASK 0x00000200
    #define PPC_MIPS_INT_MASK_INT_EN_SCC0_PARITY_DET_SHIFT 9
    #define PPC_MIPS_INT_MASK_INT_EN_SCC0_ERROR_MASK 0x00000400
    #define PPC_MIPS_INT_MASK_INT_EN_SCC0_ERROR_SHIFT 10
    #define PPC_MIPS_INT_MASK_INT_EN_I2C0_ARB_FAIL_MASK 0x00100000
    #define PPC_MIPS_INT_MASK_INT_EN_I2C0_ARB_FAIL_SHIFT 20
    #define PPC_MIPS_INT_MASK_INT_EN_I2C0_BUSY_ERROR_MASK 0x00200000
    #define PPC_MIPS_INT_MASK_INT_EN_I2C0_BUSY_ERROR_SHIFT 21
    #define PPC_MIPS_INT_MASK_INT_EN_CCSPI_RX_PACKET_DONE_MASK 0x00400000
    #define PPC_MIPS_INT_MASK_INT_EN_CCSPI_RX_PACKET_DONE_SHIFT 22
    #define PPC_MIPS_INT_MASK_INT_EN_CCSPI_TX_PACKET_DONE_MASK 0x00800000
    #define PPC_MIPS_INT_MASK_INT_EN_CCSPI_TX_PACKET_DONE_SHIFT 23
    #define PPC_MIPS_INT_MASK_INT_EN_SPI_DONE_MASK 0x01000000
    #define PPC_MIPS_INT_MASK_INT_EN_SPI_DONE_SHIFT 24
    #define PPC_MIPS_INT_MASK_INT_EN_I2C1_ARB_FAIL_MASK 0x02000000
    #define PPC_MIPS_INT_MASK_INT_EN_I2C1_ARB_FAIL_SHIFT 25
    #define PPC_MIPS_INT_MASK_INT_EN_I2C1_BUSY_ERROR_MASK 0x04000000
    #define PPC_MIPS_INT_MASK_INT_EN_I2C1_BUSY_ERROR_SHIFT 26
#define  PPC_PAGING 0x1120
    #define PPC_PAGE_MASK 0x000007FF
    #define PPC_PAGE_SHIFT 0
#define  PPC_SFT_RSTN 0x10A4
    #define PPC_SFT_RSTN_MASK 0x00000001
    #define PPC_SFT_RSTN_SHIFT 0
    #define CCSPI_SFT_RSTN_MASK 0x00000002
    #define CCSPI_SFT_RSTN_SHIFT 1
#define  PROC1_DBG_INBOUND0 0xA460
    #define PROC1_DBG_INBOUND0_DATA_MASK 0xFFFFFFFF
    #define PROC1_DBG_INBOUND0_DATA_SHIFT 0
#define  PROC1_DBG_INBOUND1 0xA4A0
    #define PROC1_DBG_INBOUND1_DATA_MASK 0xFFFFFFFF
    #define PROC1_DBG_INBOUND1_DATA_SHIFT 0
#define  PROC1_DBG_INBOUND2 0xA4A4
    #define PROC1_DBG_INBOUND2_DATA_MASK 0xFFFFFFFF
    #define PROC1_DBG_INBOUND2_DATA_SHIFT 0
#define  PROC1_DBG_INBOUND3 0xA4A8
    #define PROC1_DBG_INBOUND3_DATA_MASK 0xFFFFFFFF
    #define PROC1_DBG_INBOUND3_DATA_SHIFT 0
#define  PROC1_DBG_INBOUND4 0xA4AC
    #define PROC1_DBG_INBOUND4_DATA_MASK 0xFFFFFFFF
    #define PROC1_DBG_INBOUND4_DATA_SHIFT 0
#define  PROC1_DBG_INBOUND5 0xA4D0
    #define PROC1_DBG_INBOUND5_DATA_MASK 0xFFFFFFFF
    #define PROC1_DBG_INBOUND5_DATA_SHIFT 0
#define  PROC1_DBG_INBOUND6 0xA4D4
    #define PROC1_DBG_INBOUND6_DATA_MASK 0xFFFFFFFF
    #define PROC1_DBG_INBOUND6_DATA_SHIFT 0
#define  PROC1_DBG_OUTBOUND 0xA464
    #define PROC1_DBG_OUTBOUND_DATA_MASK 0xFFFFFFFF
    #define PROC1_DBG_OUTBOUND_DATA_SHIFT 0
#define  PROC1_DEBUG_REG1 0xA470
    #define PROC1_DEBUG_REG1_DATA_MASK 0xFFFFFFFF
    #define PROC1_DEBUG_REG1_DATA_SHIFT 0
#define  PROC1_DEBUG_REG2 0xA474
    #define PROC1_DEBUG_REG2_DATA_MASK 0xFFFFFFFF
    #define PROC1_DEBUG_REG2_DATA_SHIFT 0
#define  PROC1_DEBUG_REG3 0xA478
    #define PROC1_DEBUG_REG3_DATA_MASK 0xFFFFFFFF
    #define PROC1_DEBUG_REG3_DATA_SHIFT 0
#define  PROC1_DEBUG_REG4 0xA47C
    #define PROC1_DEBUG_REG4_DATA_MASK 0xFFFFFFFF
    #define PROC1_DEBUG_REG4_DATA_SHIFT 0
#define  PROC1_DEBUG_REG5 0xA488
    #define PROC1_DEBUG_REG5_DATA_MASK 0xFFFFFFFF
    #define PROC1_DEBUG_REG5_DATA_SHIFT 0
#define  PROC1_DEBUG_REG6 0xA48C
    #define PROC1_DEBUG_REG6_DATA_MASK 0xFFFFFFFF
    #define PROC1_DEBUG_REG6_DATA_SHIFT 0
#define  PROC1_DMA_CONFIG 0xA598
    #define PROC1_DMA_CONFIG_LENGTH_MASK 0x000007FF
    #define PROC1_DMA_CONFIG_LENGTH_SHIFT 0
    #define PROC1_DMA_CONFIG_DIRECTION_MASK 0x00010000
    #define PROC1_DMA_CONFIG_DIRECTION_SHIFT 16
    #define PROC1_DMA_CONFIG_QUEUE_WR_EN_MASK 0x01000000
    #define PROC1_DMA_CONFIG_QUEUE_WR_EN_SHIFT 24
    #define PROC1_DMA_CONFIG_DMA_EN_MASK 0x02000000
    #define PROC1_DMA_CONFIG_DMA_EN_SHIFT 25
#define  PROC1_DMA_DCCM 0xA590
    #define PROC1_DMA_DCCM_START_ADR_MASK 0xFFFFFFFC
    #define PROC1_DMA_DCCM_START_ADR_SHIFT 2
#define  PROC1_DMA_FB 0xA594
    #define PROC1_DMA_FB_START_ADR_MASK 0x1FFFFFFC
    #define PROC1_DMA_FB_START_ADR_SHIFT 2
#define  PROC1_DMA_STATUS 0xA59C
    #define PROC1_DMA_STATUS_PENDING_NUM_MASK 0x0000000F
    #define PROC1_DMA_STATUS_PENDING_NUM_SHIFT 0
    #define PROC1_DMA_STATUS_QUEUE_FULL_MASK 0x00000010
    #define PROC1_DMA_STATUS_QUEUE_FULL_SHIFT 4
    #define PROC1_DMA_STATUS_QUEUE_EMPTY_MASK 0x00000020
    #define PROC1_DMA_STATUS_QUEUE_EMPTY_SHIFT 5
#define  PROC1_DUMMY_REG 0xA4FC
    #define PROC1_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define PROC1_DUMMY_REG_DATA_SHIFT 0
#define  PROC1_FB_TOP 0xA404
    #define PROC1_FB_TOP_BASE_MASK 0xFFFF0000
    #define PROC1_FB_TOP_BASE_SHIFT 16
#define  PROC1_HOST_INT_MASK 0xA4E4
    #define PROC1_HOST_INT_MASK_INT_EN_OUTBOUND_CALL0_MASK 0x00000001
    #define PROC1_HOST_INT_MASK_INT_EN_OUTBOUND_CALL0_SHIFT 0
    #define PROC1_HOST_INT_MASK_INT_EN_OUTBOUND_CALL1_MASK 0x00000002
    #define PROC1_HOST_INT_MASK_INT_EN_OUTBOUND_CALL1_SHIFT 1
    #define PROC1_HOST_INT_MASK_INT_EN_OUTBOUND_DBG_MASK 0x00000004
    #define PROC1_HOST_INT_MASK_INT_EN_OUTBOUND_DBG_SHIFT 2
    #define PROC1_HOST_INT_MASK_INT_EN_PROC_HANG_MASK 0x80000000
    #define PROC1_HOST_INT_MASK_INT_EN_PROC_HANG_SHIFT 31
#define  PROC1_HOST_INT_STATUS 0xA4E0
    #define PROC1_HOST_INT_STATUS_OUTBOUND_CALL0_MASK 0x00000001
    #define PROC1_HOST_INT_STATUS_OUTBOUND_CALL0_SHIFT 0
    #define PROC1_HOST_INT_STATUS_OUTBOUND_CALL1_MASK 0x00000002
    #define PROC1_HOST_INT_STATUS_OUTBOUND_CALL1_SHIFT 1
    #define PROC1_HOST_INT_STATUS_OUTBOUND_DBG_MASK 0x00000004
    #define PROC1_HOST_INT_STATUS_OUTBOUND_DBG_SHIFT 2
    #define PROC1_HOST_INT_STATUS_PROC_HANG_MASK 0x80000000
    #define PROC1_HOST_INT_STATUS_PROC_HANG_SHIFT 31
#define  PROC1_INBOUND_CALL_0 0xA420
    #define PROC1_INBOUND_CALL_0_DATA_MASK 0xFFFFFFFF
    #define PROC1_INBOUND_CALL_0_DATA_SHIFT 0
#define  PROC1_INBOUND_CALL_1 0xA424
    #define PROC1_INBOUND_CALL_1_DATA_MASK 0xFFFFFFFF
    #define PROC1_INBOUND_CALL_1_DATA_SHIFT 0
#define  PROC1_IPC_CALL 0xA4F0
    #define PROC1_IPC_CALL_DATA_MASK 0xFFFFFFFF
    #define PROC1_IPC_CALL_DATA_SHIFT 0
#define  PROC1_MBD_EMPTY 0xA4F4
    #define PROC1_MBD_EMPTY_EMPTY_MASK 0x00000001
    #define PROC1_MBD_EMPTY_EMPTY_SHIFT 0
#define  PROC1_MC_ARB 0xA418
    #define PROC1_MC_ARB_ARC_REQ_CNT_LIMIT_MASK 0x0000000F
    #define PROC1_MC_ARB_ARC_REQ_CNT_LIMIT_SHIFT 0
    #define PROC1_MC_ARB_IBB_REQ_CNT_LIMIT_MASK 0x000000F0
    #define PROC1_MC_ARB_IBB_REQ_CNT_LIMIT_SHIFT 4
    #define PROC1_MC_ARB_MBD_REQ_CNT_LIMIT_MASK 0x00000F00
    #define PROC1_MC_ARB_MBD_REQ_CNT_LIMIT_SHIFT 8
    #define PROC1_MC_ARB_DMA_REQ_CNT_LIMIT_MASK 0x0000F000
    #define PROC1_MC_ARB_DMA_REQ_CNT_LIMIT_SHIFT 12
#define  PROC1_MEM_ALIAS 0xA40C
    #define PROC1_MEM_ALIAS_MASK_MASK 0xC0000000
    #define PROC1_MEM_ALIAS_MASK_SHIFT 30
#define  PROC1_MERGED_WRITE_CTL 0xA410
    #define PROC1_MERGED_WRITE_CTL_TIMER_MASK 0x000003FF
    #define PROC1_MERGED_WRITE_CTL_TIMER_SHIFT 0
#define  PROC1_MMREG_APER 0xA408
    #define PROC1_MMREG_APER_BASE_MASK 0x0000FFFF
    #define PROC1_MMREG_APER_BASE_SHIFT 0
    #define PROC1_MMREG_APER_SIZE_MASK 0xFFFF0000
    #define PROC1_MMREG_APER_SIZE_SHIFT 16
#define  PROC1_MSG_DATA_0 0xA430
    #define PROC1_MSG_DATA_0_DATA_MASK 0xFFFFFFFF
    #define PROC1_MSG_DATA_0_DATA_SHIFT 0
#define  PROC1_MSG_DATA_1 0xA434
    #define PROC1_MSG_DATA_1_DATA_MASK 0xFFFFFFFF
    #define PROC1_MSG_DATA_1_DATA_SHIFT 0
#define  PROC1_MSG_DATA_10 0xA458
    #define PROC1_MSG_DATA_10_DATA_MASK 0xFFFFFFFF
    #define PROC1_MSG_DATA_10_DATA_SHIFT 0
#define  PROC1_MSG_DATA_11 0xA45C
    #define PROC1_MSG_DATA_11_DATA_MASK 0xFFFFFFFF
    #define PROC1_MSG_DATA_11_DATA_SHIFT 0
#define  PROC1_MSG_DATA_2 0xA438
    #define PROC1_MSG_DATA_2_DATA_MASK 0xFFFFFFFF
    #define PROC1_MSG_DATA_2_DATA_SHIFT 0
#define  PROC1_MSG_DATA_3 0xA43C
    #define PROC1_MSG_DATA_3_DATA_MASK 0xFFFFFFFF
    #define PROC1_MSG_DATA_3_DATA_SHIFT 0
#define  PROC1_MSG_DATA_4 0xA440
    #define PROC1_MSG_DATA_4_DATA_MASK 0xFFFFFFFF
    #define PROC1_MSG_DATA_4_DATA_SHIFT 0
#define  PROC1_MSG_DATA_5 0xA444
    #define PROC1_MSG_DATA_5_DATA_MASK 0xFFFFFFFF
    #define PROC1_MSG_DATA_5_DATA_SHIFT 0
#define  PROC1_MSG_DATA_6 0xA448
    #define PROC1_MSG_DATA_6_DATA_MASK 0xFFFFFFFF
    #define PROC1_MSG_DATA_6_DATA_SHIFT 0
#define  PROC1_MSG_DATA_7 0xA44C
    #define PROC1_MSG_DATA_7_DATA_MASK 0xFFFFFFFF
    #define PROC1_MSG_DATA_7_DATA_SHIFT 0
#define  PROC1_MSG_DATA_8 0xA450
    #define PROC1_MSG_DATA_8_DATA_MASK 0xFFFFFFFF
    #define PROC1_MSG_DATA_8_DATA_SHIFT 0
#define  PROC1_MSG_DATA_9 0xA454
    #define PROC1_MSG_DATA_9_DATA_MASK 0xFFFFFFFF
    #define PROC1_MSG_DATA_9_DATA_SHIFT 0
#define  PROC1_OUTBOUND_CALL_0 0xA428
    #define PROC1_OUTBOUND_CALL_0_DATA_MASK 0xFFFFFFFF
    #define PROC1_OUTBOUND_CALL_0_DATA_SHIFT 0
#define  PROC1_OUTBOUND_CALL_1 0xA42C
    #define PROC1_OUTBOUND_CALL_1_DATA_MASK 0xFFFFFFFF
    #define PROC1_OUTBOUND_CALL_1_DATA_SHIFT 0
#define  PROC1_PROC_INT_MASK 0xA4EC
    #define PROC1_PROC_INT_MASK_INT_EN_INBOUND_CALL0_MASK 0x00000001
    #define PROC1_PROC_INT_MASK_INT_EN_INBOUND_CALL0_SHIFT 0
    #define PROC1_PROC_INT_MASK_INT_EN_INBOUND_CALL1_MASK 0x00000002
    #define PROC1_PROC_INT_MASK_INT_EN_INBOUND_CALL1_SHIFT 1
    #define PROC1_PROC_INT_MASK_INT_EN_IPC_CALL_MASK 0x00000008
    #define PROC1_PROC_INT_MASK_INT_EN_IPC_CALL_SHIFT 3
    #define PROC1_PROC_INT_MASK_INT_EN_DMA_COMPLETE_MASK 0x00000010
    #define PROC1_PROC_INT_MASK_INT_EN_DMA_COMPLETE_SHIFT 4
    #define PROC1_PROC_INT_MASK_INT_EN_DBG_INBOUND0_MASK 0x00000020
    #define PROC1_PROC_INT_MASK_INT_EN_DBG_INBOUND0_SHIFT 5
    #define PROC1_PROC_INT_MASK_INT_EN_DBG_INBOUND1_MASK 0x00000040
    #define PROC1_PROC_INT_MASK_INT_EN_DBG_INBOUND1_SHIFT 6
    #define PROC1_PROC_INT_MASK_INT_EN_DBG_INBOUND2_MASK 0x00000080
    #define PROC1_PROC_INT_MASK_INT_EN_DBG_INBOUND2_SHIFT 7
    #define PROC1_PROC_INT_MASK_INT_EN_DBG_INBOUND3_MASK 0x00000100
    #define PROC1_PROC_INT_MASK_INT_EN_DBG_INBOUND3_SHIFT 8
    #define PROC1_PROC_INT_MASK_INT_EN_DBG_INBOUND4_MASK 0x00000200
    #define PROC1_PROC_INT_MASK_INT_EN_DBG_INBOUND4_SHIFT 9
    #define PROC1_PROC_INT_MASK_INT_EN_DBG_INBOUND5_MASK 0x00000400
    #define PROC1_PROC_INT_MASK_INT_EN_DBG_INBOUND5_SHIFT 10
    #define PROC1_PROC_INT_MASK_INT_EN_DBG_INBOUND6_MASK 0x00000800
    #define PROC1_PROC_INT_MASK_INT_EN_DBG_INBOUND6_SHIFT 11
#define  PROC1_PROC_INT_STATUS 0xA4E8
    #define PROC1_PROC_INT_STATUS_INBOUND_CALL0_MASK 0x00000001
    #define PROC1_PROC_INT_STATUS_INBOUND_CALL0_SHIFT 0
    #define PROC1_PROC_INT_STATUS_INBOUND_CALL1_MASK 0x00000002
    #define PROC1_PROC_INT_STATUS_INBOUND_CALL1_SHIFT 1
    #define PROC1_PROC_INT_STATUS_IPC_CALL_MASK 0x00000008
    #define PROC1_PROC_INT_STATUS_IPC_CALL_SHIFT 3
    #define PROC1_PROC_INT_STATUS_DMA_COMPLETE_MASK 0x00000010
    #define PROC1_PROC_INT_STATUS_DMA_COMPLETE_SHIFT 4
    #define PROC1_PROC_INT_STATUS_DBG_INBOUND0_MASK 0x00000020
    #define PROC1_PROC_INT_STATUS_DBG_INBOUND0_SHIFT 5
    #define PROC1_PROC_INT_STATUS_DBG_INBOUND1_MASK 0x00000040
    #define PROC1_PROC_INT_STATUS_DBG_INBOUND1_SHIFT 6
    #define PROC1_PROC_INT_STATUS_DBG_INBOUND2_MASK 0x00000080
    #define PROC1_PROC_INT_STATUS_DBG_INBOUND2_SHIFT 7
    #define PROC1_PROC_INT_STATUS_DBG_INBOUND3_MASK 0x00000100
    #define PROC1_PROC_INT_STATUS_DBG_INBOUND3_SHIFT 8
    #define PROC1_PROC_INT_STATUS_DBG_INBOUND4_MASK 0x00000200
    #define PROC1_PROC_INT_STATUS_DBG_INBOUND4_SHIFT 9
    #define PROC1_PROC_INT_STATUS_DBG_INBOUND5_MASK 0x00000400
    #define PROC1_PROC_INT_STATUS_DBG_INBOUND5_SHIFT 10
    #define PROC1_PROC_INT_STATUS_DBG_INBOUND6_MASK 0x00000800
    #define PROC1_PROC_INT_STATUS_DBG_INBOUND6_SHIFT 11
#define  PROC1_RST 0xA414
    #define PROC1_RST_SOFT_RSTN_MASK 0x00000001
    #define PROC1_RST_SOFT_RSTN_SHIFT 0
    #define PROC1_RST_MBD_RSTN_MASK 0x00000004
    #define PROC1_RST_MBD_RSTN_SHIFT 2
    #define PROC1_RST_MBD_FLUSH_MASK 0x80000000
    #define PROC1_RST_MBD_FLUSH_SHIFT 31
#define  PROC1_SHADOW_IBB_CTRL 0xA4B0
    #define PROC1_SHADOW_IBB_CTRL_SHADOW_IBB_CTRL_MASK 0xFFFFFFFF
    #define PROC1_SHADOW_IBB_CTRL_SHADOW_IBB_CTRL_SHIFT 0
#define  PROC1_SHADOW_IBB_RB_ADR 0xA4B8
    #define PROC1_SHADOW_IBB_RB_ADR_SHADOW_IBB_RB_ADR_MASK 0xFFFFFFFF
    #define PROC1_SHADOW_IBB_RB_ADR_SHADOW_IBB_RB_ADR_SHIFT 0
#define  PROC1_SHADOW_IBB_RB_HEAD 0xA4C8
    #define PROC1_SHADOW_IBB_RB_HEAD_SHADOW_IBB_RB_HEAD_MASK 0xFFFFFFFF
    #define PROC1_SHADOW_IBB_RB_HEAD_SHADOW_IBB_RB_HEAD_SHIFT 0
#define  PROC1_SHADOW_IBB_RB_TAIL 0xA4BC
    #define PROC1_SHADOW_IBB_RB_TAIL_SHADOW_IBB_RB_TAIL_MASK 0xFFFFFFFF
    #define PROC1_SHADOW_IBB_RB_TAIL_SHADOW_IBB_RB_TAIL_SHIFT 0
#define  PROC1_SHADOW_IBB_RB_TAIL_READ 0xA4C0
    #define PROC1_SHADOW_IBB_RB_TAIL_READ_SHADOW_IBB_RB_TAIL_READ_MASK 0xFFFFFFFF
    #define PROC1_SHADOW_IBB_RB_TAIL_READ_SHADOW_IBB_RB_TAIL_READ_SHIFT 0
#define  PROC1_SHADOW_IBB_STATUS 0xA4B4
    #define PROC1_SHADOW_IBB_STATUS_SHADOW_IBB_STATUS_MASK 0xFFFFFFFF
    #define PROC1_SHADOW_IBB_STATUS_SHADOW_IBB_STATUS_SHIFT 0
#define  PROC1_WATCHDOG_CNT 0xA480
    #define PROC1_WATCHDOG_CNT_DATA_MASK 0xFFFFFFFF
    #define PROC1_WATCHDOG_CNT_DATA_SHIFT 0
#define  PROC1_WATCHDOG_COMPARE 0xA484
    #define PROC1_WATCHDOG_COMPARE_DATA_MASK 0xFFFFFFFF
    #define PROC1_WATCHDOG_COMPARE_DATA_SHIFT 0
#define  PROC2_DBG_INBOUND0 0xA860
    #define PROC2_DBG_INBOUND0_DATA_MASK 0xFFFFFFFF
    #define PROC2_DBG_INBOUND0_DATA_SHIFT 0
#define  PROC2_DBG_INBOUND1 0xA8A0
    #define PROC2_DBG_INBOUND1_DATA_MASK 0xFFFFFFFF
    #define PROC2_DBG_INBOUND1_DATA_SHIFT 0
#define  PROC2_DBG_INBOUND2 0xA8A4
    #define PROC2_DBG_INBOUND2_DATA_MASK 0xFFFFFFFF
    #define PROC2_DBG_INBOUND2_DATA_SHIFT 0
#define  PROC2_DBG_INBOUND3 0xA8A8
    #define PROC2_DBG_INBOUND3_DATA_MASK 0xFFFFFFFF
    #define PROC2_DBG_INBOUND3_DATA_SHIFT 0
#define  PROC2_DBG_INBOUND4 0xA8AC
    #define PROC2_DBG_INBOUND4_DATA_MASK 0xFFFFFFFF
    #define PROC2_DBG_INBOUND4_DATA_SHIFT 0
#define  PROC2_DBG_INBOUND5 0xA8D0
    #define PROC2_DBG_INBOUND5_DATA_MASK 0xFFFFFFFF
    #define PROC2_DBG_INBOUND5_DATA_SHIFT 0
#define  PROC2_DBG_INBOUND6 0xA8D4
    #define PROC2_DBG_INBOUND6_DATA_MASK 0xFFFFFFFF
    #define PROC2_DBG_INBOUND6_DATA_SHIFT 0
#define  PROC2_DBG_OUTBOUND 0xA864
    #define PROC2_DBG_OUTBOUND_DATA_MASK 0xFFFFFFFF
    #define PROC2_DBG_OUTBOUND_DATA_SHIFT 0
#define  PROC2_DMA_CONFIG 0xA898
    #define PROC2_DMA_CONFIG_LENGTH_MASK 0x000007FF
    #define PROC2_DMA_CONFIG_LENGTH_SHIFT 0
    #define PROC2_DMA_CONFIG_DIRECTION_MASK 0x00010000
    #define PROC2_DMA_CONFIG_DIRECTION_SHIFT 16
    #define PROC2_DMA_CONFIG_QUEUE_WR_EN_MASK 0x01000000
    #define PROC2_DMA_CONFIG_QUEUE_WR_EN_SHIFT 24
    #define PROC2_DMA_CONFIG_DMA_EN_MASK 0x02000000
    #define PROC2_DMA_CONFIG_DMA_EN_SHIFT 25
#define  PROC2_DMA_DCCM 0xA890
    #define PROC2_DMA_DCCM_START_ADR_MASK 0xFFFFFFFC
    #define PROC2_DMA_DCCM_START_ADR_SHIFT 2
#define  PROC2_DMA_FB 0xA894
    #define PROC2_DMA_FB_START_ADR_MASK 0x1FFFFFFC
    #define PROC2_DMA_FB_START_ADR_SHIFT 2
#define  PROC2_DMA_STATUS 0xA89C
    #define PROC2_DMA_STATUS_PENDING_NUM_MASK 0x0000000F
    #define PROC2_DMA_STATUS_PENDING_NUM_SHIFT 0
    #define PROC2_DMA_STATUS_QUEUE_FULL_MASK 0x00000010
    #define PROC2_DMA_STATUS_QUEUE_FULL_SHIFT 4
    #define PROC2_DMA_STATUS_QUEUE_EMPTY_MASK 0x00000020
    #define PROC2_DMA_STATUS_QUEUE_EMPTY_SHIFT 5
#define  PROC2_FB_TOP 0xA804
    #define PROC2_FB_TOP_BASE_MASK 0xFFFF0000
    #define PROC2_FB_TOP_BASE_SHIFT 16
#define  PROC2_HOST_INT_MASK 0xA8E4
    #define PROC2_HOST_INT_MASK_INT_EN_OUTBOUND_CALL0_MASK 0x00000001
    #define PROC2_HOST_INT_MASK_INT_EN_OUTBOUND_CALL0_SHIFT 0
    #define PROC2_HOST_INT_MASK_INT_EN_OUTBOUND_CALL1_MASK 0x00000002
    #define PROC2_HOST_INT_MASK_INT_EN_OUTBOUND_CALL1_SHIFT 1
    #define PROC2_HOST_INT_MASK_INT_EN_OUTBOUND_DBG_MASK 0x00000004
    #define PROC2_HOST_INT_MASK_INT_EN_OUTBOUND_DBG_SHIFT 2
    #define INT_EN_PROC2_HANG_MASK 0x80000000
    #define INT_EN_PROC2_HANG_SHIFT 31
#define  PROC2_HOST_INT_STATUS 0xA8E0
    #define PROC2_HOST_INT_STATUS_OUTBOUND_CALL0_MASK 0x00000001
    #define PROC2_HOST_INT_STATUS_OUTBOUND_CALL0_SHIFT 0
    #define PROC2_HOST_INT_STATUS_OUTBOUND_CALL1_MASK 0x00000002
    #define PROC2_HOST_INT_STATUS_OUTBOUND_CALL1_SHIFT 1
    #define PROC2_HOST_INT_STATUS_OUTBOUND_DBG_MASK 0x00000004
    #define PROC2_HOST_INT_STATUS_OUTBOUND_DBG_SHIFT 2
    #define PROC2_HANG_MASK 0x80000000
    #define PROC2_HANG_SHIFT 31
#define  PROC2_INBOUND_CALL_0 0xA820
    #define PROC2_INBOUND_CALL_0_DATA_MASK 0xFFFFFFFF
    #define PROC2_INBOUND_CALL_0_DATA_SHIFT 0
#define  PROC2_INBOUND_CALL_1 0xA824
    #define PROC2_INBOUND_CALL_1_DATA_MASK 0xFFFFFFFF
    #define PROC2_INBOUND_CALL_1_DATA_SHIFT 0
#define  PROC2_IPC_CALL 0xA8F0
    #define PROC2_IPC_CALL_DATA_MASK 0xFFFFFFFF
    #define PROC2_IPC_CALL_DATA_SHIFT 0
#define  PROC2_MC_ARB 0xA818
    #define PROC2_MC_ARB_ARC_REQ_CNT_LIMIT_MASK 0x0000000F
    #define PROC2_MC_ARB_ARC_REQ_CNT_LIMIT_SHIFT 0
    #define PROC2_MC_ARB_DMA_REQ_CNT_LIMIT_MASK 0x000000F0
    #define PROC2_MC_ARB_DMA_REQ_CNT_LIMIT_SHIFT 4
#define  PROC2_MEM_ALIAS 0xA80C
    #define PROC2_MEM_ALIAS_MASK_MASK 0xC0000000
    #define PROC2_MEM_ALIAS_MASK_SHIFT 30
#define  PROC2_MERGED_WRITE_CTL 0xA810
    #define PROC2_MERGED_WRITE_CTL_TIMER_MASK 0x000003FF
    #define PROC2_MERGED_WRITE_CTL_TIMER_SHIFT 0
#define  PROC2_MMREG_APER 0xA808
    #define PROC2_MMREG_APER_BASE_MASK 0x0000FFFF
    #define PROC2_MMREG_APER_BASE_SHIFT 0
    #define PROC2_MMREG_APER_SIZE_MASK 0xFFFF0000
    #define PROC2_MMREG_APER_SIZE_SHIFT 16
#define  PROC2_MSG_DATA_0 0xA830
    #define PROC2_MSG_DATA_0_DATA_MASK 0xFFFFFFFF
    #define PROC2_MSG_DATA_0_DATA_SHIFT 0
#define  PROC2_MSG_DATA_1 0xA834
    #define PROC2_MSG_DATA_1_DATA_MASK 0xFFFFFFFF
    #define PROC2_MSG_DATA_1_DATA_SHIFT 0
#define  PROC2_MSG_DATA_10 0xA858
    #define PROC2_MSG_DATA_10_DATA_MASK 0xFFFFFFFF
    #define PROC2_MSG_DATA_10_DATA_SHIFT 0
#define  PROC2_MSG_DATA_11 0xA85C
    #define PROC2_MSG_DATA_11_DATA_MASK 0xFFFFFFFF
    #define PROC2_MSG_DATA_11_DATA_SHIFT 0
#define  PROC2_MSG_DATA_2 0xA838
    #define PROC2_MSG_DATA_2_DATA_MASK 0xFFFFFFFF
    #define PROC2_MSG_DATA_2_DATA_SHIFT 0
#define  PROC2_MSG_DATA_3 0xA83C
    #define PROC2_MSG_DATA_3_DATA_MASK 0xFFFFFFFF
    #define PROC2_MSG_DATA_3_DATA_SHIFT 0
#define  PROC2_MSG_DATA_4 0xA840
    #define PROC2_MSG_DATA_4_DATA_MASK 0xFFFFFFFF
    #define PROC2_MSG_DATA_4_DATA_SHIFT 0
#define  PROC2_MSG_DATA_5 0xA844
    #define PROC2_MSG_DATA_5_DATA_MASK 0xFFFFFFFF
    #define PROC2_MSG_DATA_5_DATA_SHIFT 0
#define  PROC2_MSG_DATA_6 0xA848
    #define PROC2_MSG_DATA_6_DATA_MASK 0xFFFFFFFF
    #define PROC2_MSG_DATA_6_DATA_SHIFT 0
#define  PROC2_MSG_DATA_7 0xA84C
    #define PROC2_MSG_DATA_7_DATA_MASK 0xFFFFFFFF
    #define PROC2_MSG_DATA_7_DATA_SHIFT 0
#define  PROC2_MSG_DATA_8 0xA850
    #define PROC2_MSG_DATA_8_DATA_MASK 0xFFFFFFFF
    #define PROC2_MSG_DATA_8_DATA_SHIFT 0
#define  PROC2_MSG_DATA_9 0xA854
    #define PROC2_MSG_DATA_9_DATA_MASK 0xFFFFFFFF
    #define PROC2_MSG_DATA_9_DATA_SHIFT 0
#define  PROC2_OUTBOUND_CALL_0 0xA828
    #define PROC2_OUTBOUND_CALL_0_DATA_MASK 0xFFFFFFFF
    #define PROC2_OUTBOUND_CALL_0_DATA_SHIFT 0
#define  PROC2_OUTBOUND_CALL_1 0xA82C
    #define PROC2_OUTBOUND_CALL_1_DATA_MASK 0xFFFFFFFF
    #define PROC2_OUTBOUND_CALL_1_DATA_SHIFT 0
#define  PROC2_PROC2_INT_MASK 0xA8EC
    #define PROC2_PROC2_INT_MASK_INT_EN_INBOUND_CALL0_MASK 0x00000001
    #define PROC2_PROC2_INT_MASK_INT_EN_INBOUND_CALL0_SHIFT 0
    #define PROC2_PROC2_INT_MASK_INT_EN_INBOUND_CALL1_MASK 0x00000002
    #define PROC2_PROC2_INT_MASK_INT_EN_INBOUND_CALL1_SHIFT 1
    #define PROC2_PROC2_INT_MASK_INT_EN_IPC_CALL_MASK 0x00000008
    #define PROC2_PROC2_INT_MASK_INT_EN_IPC_CALL_SHIFT 3
    #define PROC2_PROC2_INT_MASK_INT_EN_DMA_COMPLETE_MASK 0x00000010
    #define PROC2_PROC2_INT_MASK_INT_EN_DMA_COMPLETE_SHIFT 4
    #define PROC2_PROC2_INT_MASK_INT_EN_DBG_INBOUND0_MASK 0x00000020
    #define PROC2_PROC2_INT_MASK_INT_EN_DBG_INBOUND0_SHIFT 5
    #define PROC2_PROC2_INT_MASK_INT_EN_DBG_INBOUND1_MASK 0x00000040
    #define PROC2_PROC2_INT_MASK_INT_EN_DBG_INBOUND1_SHIFT 6
    #define PROC2_PROC2_INT_MASK_INT_EN_DBG_INBOUND2_MASK 0x00000080
    #define PROC2_PROC2_INT_MASK_INT_EN_DBG_INBOUND2_SHIFT 7
    #define PROC2_PROC2_INT_MASK_INT_EN_DBG_INBOUND3_MASK 0x00000100
    #define PROC2_PROC2_INT_MASK_INT_EN_DBG_INBOUND3_SHIFT 8
    #define PROC2_PROC2_INT_MASK_INT_EN_DBG_INBOUND4_MASK 0x00000200
    #define PROC2_PROC2_INT_MASK_INT_EN_DBG_INBOUND4_SHIFT 9
    #define PROC2_PROC2_INT_MASK_INT_EN_DBG_INBOUND5_MASK 0x00000400
    #define PROC2_PROC2_INT_MASK_INT_EN_DBG_INBOUND5_SHIFT 10
    #define PROC2_PROC2_INT_MASK_INT_EN_DBG_INBOUND6_MASK 0x00000800
    #define PROC2_PROC2_INT_MASK_INT_EN_DBG_INBOUND6_SHIFT 11
#define  PROC2_PROC2_INT_STATUS 0xA8E8
    #define PROC2_PROC2_INT_STATUS_INBOUND_CALL0_MASK 0x00000001
    #define PROC2_PROC2_INT_STATUS_INBOUND_CALL0_SHIFT 0
    #define PROC2_PROC2_INT_STATUS_INBOUND_CALL1_MASK 0x00000002
    #define PROC2_PROC2_INT_STATUS_INBOUND_CALL1_SHIFT 1
    #define PROC2_PROC2_INT_STATUS_IPC_CALL_MASK 0x00000008
    #define PROC2_PROC2_INT_STATUS_IPC_CALL_SHIFT 3
    #define PROC2_PROC2_INT_STATUS_DMA_COMPLETE_MASK 0x00000010
    #define PROC2_PROC2_INT_STATUS_DMA_COMPLETE_SHIFT 4
    #define PROC2_PROC2_INT_STATUS_DBG_INBOUND0_MASK 0x00000020
    #define PROC2_PROC2_INT_STATUS_DBG_INBOUND0_SHIFT 5
    #define PROC2_PROC2_INT_STATUS_DBG_INBOUND1_MASK 0x00000040
    #define PROC2_PROC2_INT_STATUS_DBG_INBOUND1_SHIFT 6
    #define PROC2_PROC2_INT_STATUS_DBG_INBOUND2_MASK 0x00000080
    #define PROC2_PROC2_INT_STATUS_DBG_INBOUND2_SHIFT 7
    #define PROC2_PROC2_INT_STATUS_DBG_INBOUND3_MASK 0x00000100
    #define PROC2_PROC2_INT_STATUS_DBG_INBOUND3_SHIFT 8
    #define PROC2_PROC2_INT_STATUS_DBG_INBOUND4_MASK 0x00000200
    #define PROC2_PROC2_INT_STATUS_DBG_INBOUND4_SHIFT 9
    #define PROC2_PROC2_INT_STATUS_DBG_INBOUND5_MASK 0x00000400
    #define PROC2_PROC2_INT_STATUS_DBG_INBOUND5_SHIFT 10
    #define PROC2_PROC2_INT_STATUS_DBG_INBOUND6_MASK 0x00000800
    #define PROC2_PROC2_INT_STATUS_DBG_INBOUND6_SHIFT 11
#define  PROC2_RST 0xA814
    #define PROC2_RST_SOFT_RSTN_MASK 0x00000001
    #define PROC2_RST_SOFT_RSTN_SHIFT 0
#define  PROC2_SEC_BOOT 0xA81C
    #define SWAP_EN_MASK 0x00000001
    #define SWAP_EN_SHIFT 0
#define  PROC2_WATCHDOG_CNT 0xA880
    #define PROC2_WATCHDOG_CNT_DATA_MASK 0xFFFFFFFF
    #define PROC2_WATCHDOG_CNT_DATA_SHIFT 0
#define  PROC2_WATCHDOG_COMPARE 0xA884
    #define PROC2_WATCHDOG_COMPARE_DATA_MASK 0xFFFFFFFF
    #define PROC2_WATCHDOG_COMPARE_DATA_SHIFT 0
#define  PROC3_DBG_INBOUND0 0xAC60
    #define PROC3_DBG_INBOUND0_DATA_MASK 0xFFFFFFFF
    #define PROC3_DBG_INBOUND0_DATA_SHIFT 0
#define  PROC3_DBG_INBOUND1 0xACA0
    #define PROC3_DBG_INBOUND1_DATA_MASK 0xFFFFFFFF
    #define PROC3_DBG_INBOUND1_DATA_SHIFT 0
#define  PROC3_DBG_INBOUND2 0xACA4
    #define PROC3_DBG_INBOUND2_DATA_MASK 0xFFFFFFFF
    #define PROC3_DBG_INBOUND2_DATA_SHIFT 0
#define  PROC3_DBG_INBOUND3 0xACA8
    #define PROC3_DBG_INBOUND3_DATA_MASK 0xFFFFFFFF
    #define PROC3_DBG_INBOUND3_DATA_SHIFT 0
#define  PROC3_DBG_INBOUND4 0xACAC
    #define PROC3_DBG_INBOUND4_DATA_MASK 0xFFFFFFFF
    #define PROC3_DBG_INBOUND4_DATA_SHIFT 0
#define  PROC3_DBG_INBOUND5 0xACD0
    #define PROC3_DBG_INBOUND5_DATA_MASK 0xFFFFFFFF
    #define PROC3_DBG_INBOUND5_DATA_SHIFT 0
#define  PROC3_DBG_INBOUND6 0xACD4
    #define PROC3_DBG_INBOUND6_DATA_MASK 0xFFFFFFFF
    #define PROC3_DBG_INBOUND6_DATA_SHIFT 0
#define  PROC3_DBG_OUTBOUND 0xAC64
    #define PROC3_DBG_OUTBOUND_DATA_MASK 0xFFFFFFFF
    #define PROC3_DBG_OUTBOUND_DATA_SHIFT 0
#define  PROC3_FB_TOP 0xAC04
    #define PROC3_FB_TOP_BASE_MASK 0xFFFF0000
    #define PROC3_FB_TOP_BASE_SHIFT 16
#define  PROC3_FPB_DBG_DATA0 0xADE0
    #define PROC3_FPB_DBG_DATA0_PCP_MASK 0xFFFFFFFF
    #define PROC3_FPB_DBG_DATA0_PCP_SHIFT 0
#define  PROC3_FPB_DBG_DATA1 0xADE4
    #define PROC3_FPB_DBG_DATA1_PFG_MASK 0xFFFFFFFF
    #define PROC3_FPB_DBG_DATA1_PFG_SHIFT 0
#define  PROC3_FPB_DBG_DATA2 0xADE8
    #define PROC3_FPB_DBG_DATA2_MRC_MASK 0xFFFFFFFF
    #define PROC3_FPB_DBG_DATA2_MRC_SHIFT 0
#define  PROC3_FPB_DBG_DATA3 0xADEC
    #define PROC3_FPB_DBG_DATA3_RDM_MASK 0xFFFFFFFF
    #define PROC3_FPB_DBG_DATA3_RDM_SHIFT 0
#define  PROC3_FPB_DBG_DATA4 0xADF0
    #define PROC3_FPB_DBG_DATA4_PCR_MASK 0xFFFFFFFF
    #define PROC3_FPB_DBG_DATA4_PCR_SHIFT 0
#define  PROC3_HOST_INT_MASK 0xACE4
    #define PROC3_HOST_INT_MASK_INT_EN_OUTBOUND_CALL0_MASK 0x00000001
    #define PROC3_HOST_INT_MASK_INT_EN_OUTBOUND_CALL0_SHIFT 0
    #define PROC3_HOST_INT_MASK_INT_EN_OUTBOUND_CALL1_MASK 0x00000002
    #define PROC3_HOST_INT_MASK_INT_EN_OUTBOUND_CALL1_SHIFT 1
    #define PROC3_HOST_INT_MASK_INT_EN_OUTBOUND_DBG_MASK 0x00000004
    #define PROC3_HOST_INT_MASK_INT_EN_OUTBOUND_DBG_SHIFT 2
    #define INT_EN_PROC3_HANG_MASK 0x80000000
    #define INT_EN_PROC3_HANG_SHIFT 31
#define  PROC3_HOST_INT_STATUS 0xACE0
    #define PROC3_HOST_INT_STATUS_OUTBOUND_CALL0_MASK 0x00000001
    #define PROC3_HOST_INT_STATUS_OUTBOUND_CALL0_SHIFT 0
    #define PROC3_HOST_INT_STATUS_OUTBOUND_CALL1_MASK 0x00000002
    #define PROC3_HOST_INT_STATUS_OUTBOUND_CALL1_SHIFT 1
    #define PROC3_HOST_INT_STATUS_OUTBOUND_DBG_MASK 0x00000004
    #define PROC3_HOST_INT_STATUS_OUTBOUND_DBG_SHIFT 2
    #define PROC3_HANG_MASK 0x80000000
    #define PROC3_HANG_SHIFT 31
#define  PROC3_INBOUND_CALL_0 0xAC20
    #define PROC3_INBOUND_CALL_0_DATA_MASK 0xFFFFFFFF
    #define PROC3_INBOUND_CALL_0_DATA_SHIFT 0
#define  PROC3_INBOUND_CALL_1 0xAC24
    #define PROC3_INBOUND_CALL_1_DATA_MASK 0xFFFFFFFF
    #define PROC3_INBOUND_CALL_1_DATA_SHIFT 0
#define  PROC3_IPC_CALL 0xACF0
    #define PROC3_IPC_CALL_DATA_MASK 0xFFFFFFFF
    #define PROC3_IPC_CALL_DATA_SHIFT 0
#define  PROC3_MEM_ALIAS 0xAC0C
    #define PROC3_MEM_ALIAS_MASK_MASK 0xC0000000
    #define PROC3_MEM_ALIAS_MASK_SHIFT 30
#define  PROC3_MERGED_READ_CTL 0xAC18
    #define PROC3_MERGED_READ_CTL_NONIDC_EN_MASK 0x00000001
    #define PROC3_MERGED_READ_CTL_NONIDC_EN_SHIFT 0
#define  PROC3_MERGED_WRITE_CTL 0xAC10
    #define PROC3_MERGED_WRITE_CTL_TIMER_MASK 0x000003FF
    #define PROC3_MERGED_WRITE_CTL_TIMER_SHIFT 0
#define  PROC3_MMREG_APER 0xAC08
    #define PROC3_MMREG_APER_BASE_MASK 0x0000FFFF
    #define PROC3_MMREG_APER_BASE_SHIFT 0
    #define PROC3_MMREG_APER_SIZE_MASK 0xFFFF0000
    #define PROC3_MMREG_APER_SIZE_SHIFT 16
#define  PROC3_MSG_DATA_0 0xAC30
    #define PROC3_MSG_DATA_0_DATA_MASK 0xFFFFFFFF
    #define PROC3_MSG_DATA_0_DATA_SHIFT 0
#define  PROC3_MSG_DATA_1 0xAC34
    #define PROC3_MSG_DATA_1_DATA_MASK 0xFFFFFFFF
    #define PROC3_MSG_DATA_1_DATA_SHIFT 0
#define  PROC3_MSG_DATA_10 0xAC58
    #define PROC3_MSG_DATA_10_DATA_MASK 0xFFFFFFFF
    #define PROC3_MSG_DATA_10_DATA_SHIFT 0
#define  PROC3_MSG_DATA_11 0xAC5C
    #define PROC3_MSG_DATA_11_DATA_MASK 0xFFFFFFFF
    #define PROC3_MSG_DATA_11_DATA_SHIFT 0
#define  PROC3_MSG_DATA_2 0xAC38
    #define PROC3_MSG_DATA_2_DATA_MASK 0xFFFFFFFF
    #define PROC3_MSG_DATA_2_DATA_SHIFT 0
#define  PROC3_MSG_DATA_3 0xAC3C
    #define PROC3_MSG_DATA_3_DATA_MASK 0xFFFFFFFF
    #define PROC3_MSG_DATA_3_DATA_SHIFT 0
#define  PROC3_MSG_DATA_4 0xAC40
    #define PROC3_MSG_DATA_4_DATA_MASK 0xFFFFFFFF
    #define PROC3_MSG_DATA_4_DATA_SHIFT 0
#define  PROC3_MSG_DATA_5 0xAC44
    #define PROC3_MSG_DATA_5_DATA_MASK 0xFFFFFFFF
    #define PROC3_MSG_DATA_5_DATA_SHIFT 0
#define  PROC3_MSG_DATA_6 0xAC48
    #define PROC3_MSG_DATA_6_DATA_MASK 0xFFFFFFFF
    #define PROC3_MSG_DATA_6_DATA_SHIFT 0
#define  PROC3_MSG_DATA_7 0xAC4C
    #define PROC3_MSG_DATA_7_DATA_MASK 0xFFFFFFFF
    #define PROC3_MSG_DATA_7_DATA_SHIFT 0
#define  PROC3_MSG_DATA_8 0xAC50
    #define PROC3_MSG_DATA_8_DATA_MASK 0xFFFFFFFF
    #define PROC3_MSG_DATA_8_DATA_SHIFT 0
#define  PROC3_MSG_DATA_9 0xAC54
    #define PROC3_MSG_DATA_9_DATA_MASK 0xFFFFFFFF
    #define PROC3_MSG_DATA_9_DATA_SHIFT 0
#define  PROC3_OUTBOUND_CALL_0 0xAC28
    #define PROC3_OUTBOUND_CALL_0_DATA_MASK 0xFFFFFFFF
    #define PROC3_OUTBOUND_CALL_0_DATA_SHIFT 0
#define  PROC3_OUTBOUND_CALL_1 0xAC2C
    #define PROC3_OUTBOUND_CALL_1_DATA_MASK 0xFFFFFFFF
    #define PROC3_OUTBOUND_CALL_1_DATA_SHIFT 0
#define  PROC3_PFB_CFG 0xADA0
    #define PROC3_PFB_CFG_PREFETCH_MODE_MASK 0x00000003
    #define PROC3_PFB_CFG_PREFETCH_MODE_SHIFT 0
    #define PROC3_PFB_CFG_MC_PFB_EN_MASK 0x00000010
    #define PROC3_PFB_CFG_MC_PFB_EN_SHIFT 4
    #define PROC3_PFB_CFG_SEQ_PFB_EN_MASK 0x00000020
    #define PROC3_PFB_CFG_SEQ_PFB_EN_SHIFT 5
    #define PROC3_PFB_CFG_MAX_PREF_LINE_NUM_MASK 0x00000700
    #define PROC3_PFB_CFG_MAX_PREF_LINE_NUM_SHIFT 8
    #define PROC3_PFB_CFG_PFB_INT_EN_MASK 0x00001000
    #define PROC3_PFB_CFG_PFB_INT_EN_SHIFT 12
    #define PROC3_PFB_CFG_BVCI_PLEN_CHK_EN_MASK 0x00010000
    #define PROC3_PFB_CFG_BVCI_PLEN_CHK_EN_SHIFT 16
#define  PROC3_PFB_CL_OFFSET 0xADA4
    #define PROC3_PFB_CL_OFFSET_LINE1_OFFSET_MASK 0x000000FF
    #define PROC3_PFB_CL_OFFSET_LINE1_OFFSET_SHIFT 0
    #define PROC3_PFB_CL_OFFSET_LINE2_OFFSET_MASK 0x0000FF00
    #define PROC3_PFB_CL_OFFSET_LINE2_OFFSET_SHIFT 8
    #define PROC3_PFB_CL_OFFSET_LINE3_OFFSET_MASK 0x00FF0000
    #define PROC3_PFB_CL_OFFSET_LINE3_OFFSET_SHIFT 16
    #define PROC3_PFB_CL_OFFSET_LINE4_OFFSET_MASK 0xFF000000
    #define PROC3_PFB_CL_OFFSET_LINE4_OFFSET_SHIFT 24
#define  PROC3_PFB_DBG_SEL 0xADDC
    #define PROC3_PFB_DBG_SEL_PCP_SEL_MASK 0x0000000F
    #define PROC3_PFB_DBG_SEL_PCP_SEL_SHIFT 0
    #define PROC3_PFB_DBG_SEL_PFG_SEL_MASK 0x000000F0
    #define PROC3_PFB_DBG_SEL_PFG_SEL_SHIFT 4
    #define PROC3_PFB_DBG_SEL_MRC_SEL_MASK 0x00000F00
    #define PROC3_PFB_DBG_SEL_MRC_SEL_SHIFT 8
    #define PROC3_PFB_DBG_SEL_RDM_SEL_MASK 0x0000F000
    #define PROC3_PFB_DBG_SEL_RDM_SEL_SHIFT 12
    #define PROC3_PFB_DBG_SEL_PCR_SEL_MASK 0x000F0000
    #define PROC3_PFB_DBG_SEL_PCR_SEL_SHIFT 16
#define  PROC3_PFB_FLOW_CTL 0xADA8
    #define PROC3_PFB_FLOW_CTL_FEQ_LOW_WATERMARK_MASK 0x000000FF
    #define PROC3_PFB_FLOW_CTL_FEQ_LOW_WATERMARK_SHIFT 0
    #define PROC3_PFB_FLOW_CTL_FCLQ_HIGH_WATERMARK_MASK 0x00000F00
    #define PROC3_PFB_FLOW_CTL_FCLQ_HIGH_WATERMARK_SHIFT 8
    #define PROC3_PFB_FLOW_CTL_CPRQ_HIGH_WATERMARK_MASK 0x000F0000
    #define PROC3_PFB_FLOW_CTL_CPRQ_HIGH_WATERMARK_SHIFT 16
#define  PROC3_PFB_INVALID_ALL 0xADB0
    #define PROC3_PFB_INVALID_ALL_DATA_MASK 0xFFFFFFFF
    #define PROC3_PFB_INVALID_ALL_DATA_SHIFT 0
#define  PROC3_PFB_STAT1 0xADBC
    #define PROC3_PFB_STAT1_CORE_CRD_NUM_MASK 0xFFFFFFFF
    #define PROC3_PFB_STAT1_CORE_CRD_NUM_SHIFT 0
#define  PROC3_PFB_STAT2 0xADC0
    #define PROC3_PFB_STAT2_CORE_CRD_HIT_NUM_MASK 0xFFFFFFFF
    #define PROC3_PFB_STAT2_CORE_CRD_HIT_NUM_SHIFT 0
#define  PROC3_PFB_STAT3 0xADC4
    #define PROC3_PFB_STAT3_PREF_CRD_NUM_MASK 0xFFFFFFFF
    #define PROC3_PFB_STAT3_PREF_CRD_NUM_SHIFT 0
#define  PROC3_PFB_STAT4 0xADC8
    #define PROC3_PFB_STAT4_CORE_CRD_HIT_DATNRDY_NUM_MASK 0xFFFFFFFF
    #define PROC3_PFB_STAT4_CORE_CRD_HIT_DATNRDY_NUM_SHIFT 0
#define  PROC3_PFB_STATUS 0xADB8
    #define PROC3_PFB_STATUS_ERROR_MASK 0x0000001F
    #define PROC3_PFB_STATUS_ERROR_SHIFT 0
    #define PROC3_PFB_STATUS_ERR_CMD_MASK 0x00000F00
    #define PROC3_PFB_STATUS_ERR_CMD_SHIFT 8
#define  PROC3_PFB_TBS_IN 0xADD0
    #define PROC3_PFB_TBS_IN_COMMAND_MASK 0x0000000F
    #define PROC3_PFB_TBS_IN_COMMAND_SHIFT 0
    #define PROC3_PFB_TBS_IN_WAY_PT_MASK 0x00001F00
    #define PROC3_PFB_TBS_IN_WAY_PT_SHIFT 8
    #define PROC3_PFB_TBS_IN_LAST_MASK 0x001F0000
    #define PROC3_PFB_TBS_IN_LAST_SHIFT 16
    #define PROC3_PFB_TBS_IN_NEXT_MASK 0x1F000000
    #define PROC3_PFB_TBS_IN_NEXT_SHIFT 24
    #define PROC3_PFB_TBS_IN_UNLOAD_PD_MASK 0x20000000
    #define PROC3_PFB_TBS_IN_UNLOAD_PD_SHIFT 29
    #define PROC3_PFB_TBS_IN_LOAD_PD_MASK 0x40000000
    #define PROC3_PFB_TBS_IN_LOAD_PD_SHIFT 30
    #define PROC3_PFB_TBS_IN_VALID_MASK 0x80000000
    #define PROC3_PFB_TBS_IN_VALID_SHIFT 31
#define  PROC3_PFB_TBS_IN2 0xADD4
    #define PROC3_PFB_TBS_IN2_ADDR_MASK 0xFFFFFFE0
    #define PROC3_PFB_TBS_IN2_ADDR_SHIFT 5
#define  PROC3_PFB_TBS_OUT 0xADD8
    #define PROC3_PFB_TBS_OUT_TBS_RDY_MASK 0x00000001
    #define PROC3_PFB_TBS_OUT_TBS_RDY_SHIFT 0
    #define PROC3_PFB_TBS_OUT_ADDR_HIT_MASK 0x00000010
    #define PROC3_PFB_TBS_OUT_ADDR_HIT_SHIFT 4
    #define PROC3_PFB_TBS_OUT_WAY_PT_MASK 0x00001F00
    #define PROC3_PFB_TBS_OUT_WAY_PT_SHIFT 8
    #define PROC3_PFB_TBS_OUT_LAST_MASK 0x001F0000
    #define PROC3_PFB_TBS_OUT_LAST_SHIFT 16
    #define PROC3_PFB_TBS_OUT_NEXT_MASK 0x1F000000
    #define PROC3_PFB_TBS_OUT_NEXT_SHIFT 24
    #define PROC3_PFB_TBS_OUT_UNLOAD_PD_MASK 0x20000000
    #define PROC3_PFB_TBS_OUT_UNLOAD_PD_SHIFT 29
    #define PROC3_PFB_TBS_OUT_LOAD_PD_MASK 0x40000000
    #define PROC3_PFB_TBS_OUT_LOAD_PD_SHIFT 30
    #define PROC3_PFB_TBS_OUT_VALID_MASK 0x80000000
    #define PROC3_PFB_TBS_OUT_VALID_SHIFT 31
#define  PROC3_PROC3_INT_MASK 0xACEC
    #define PROC3_PROC3_INT_MASK_INT_EN_INBOUND_CALL0_MASK 0x00000001
    #define PROC3_PROC3_INT_MASK_INT_EN_INBOUND_CALL0_SHIFT 0
    #define PROC3_PROC3_INT_MASK_INT_EN_INBOUND_CALL1_MASK 0x00000002
    #define PROC3_PROC3_INT_MASK_INT_EN_INBOUND_CALL1_SHIFT 1
    #define PROC3_PROC3_INT_MASK_INT_EN_IPC_CALL_MASK 0x00000008
    #define PROC3_PROC3_INT_MASK_INT_EN_IPC_CALL_SHIFT 3
    #define PROC3_PROC3_INT_MASK_INT_EN_DBG_INBOUND0_MASK 0x00000020
    #define PROC3_PROC3_INT_MASK_INT_EN_DBG_INBOUND0_SHIFT 5
    #define PROC3_PROC3_INT_MASK_INT_EN_DBG_INBOUND1_MASK 0x00000040
    #define PROC3_PROC3_INT_MASK_INT_EN_DBG_INBOUND1_SHIFT 6
    #define PROC3_PROC3_INT_MASK_INT_EN_DBG_INBOUND2_MASK 0x00000080
    #define PROC3_PROC3_INT_MASK_INT_EN_DBG_INBOUND2_SHIFT 7
    #define PROC3_PROC3_INT_MASK_INT_EN_DBG_INBOUND3_MASK 0x00000100
    #define PROC3_PROC3_INT_MASK_INT_EN_DBG_INBOUND3_SHIFT 8
    #define PROC3_PROC3_INT_MASK_INT_EN_DBG_INBOUND4_MASK 0x00000200
    #define PROC3_PROC3_INT_MASK_INT_EN_DBG_INBOUND4_SHIFT 9
    #define PROC3_PROC3_INT_MASK_INT_EN_DBG_INBOUND5_MASK 0x00000400
    #define PROC3_PROC3_INT_MASK_INT_EN_DBG_INBOUND5_SHIFT 10
    #define PROC3_PROC3_INT_MASK_INT_EN_DBG_INBOUND6_MASK 0x00000800
    #define PROC3_PROC3_INT_MASK_INT_EN_DBG_INBOUND6_SHIFT 11
#define  PROC3_PROC3_INT_STATUS 0xACE8
    #define PROC3_PROC3_INT_STATUS_INBOUND_CALL0_MASK 0x00000001
    #define PROC3_PROC3_INT_STATUS_INBOUND_CALL0_SHIFT 0
    #define PROC3_PROC3_INT_STATUS_INBOUND_CALL1_MASK 0x00000002
    #define PROC3_PROC3_INT_STATUS_INBOUND_CALL1_SHIFT 1
    #define PROC3_PROC3_INT_STATUS_IPC_CALL_MASK 0x00000008
    #define PROC3_PROC3_INT_STATUS_IPC_CALL_SHIFT 3
    #define PROC3_PROC3_INT_STATUS_DBG_INBOUND0_MASK 0x00000020
    #define PROC3_PROC3_INT_STATUS_DBG_INBOUND0_SHIFT 5
    #define PROC3_PROC3_INT_STATUS_DBG_INBOUND1_MASK 0x00000040
    #define PROC3_PROC3_INT_STATUS_DBG_INBOUND1_SHIFT 6
    #define PROC3_PROC3_INT_STATUS_DBG_INBOUND2_MASK 0x00000080
    #define PROC3_PROC3_INT_STATUS_DBG_INBOUND2_SHIFT 7
    #define PROC3_PROC3_INT_STATUS_DBG_INBOUND3_MASK 0x00000100
    #define PROC3_PROC3_INT_STATUS_DBG_INBOUND3_SHIFT 8
    #define PROC3_PROC3_INT_STATUS_DBG_INBOUND4_MASK 0x00000200
    #define PROC3_PROC3_INT_STATUS_DBG_INBOUND4_SHIFT 9
    #define PROC3_PROC3_INT_STATUS_DBG_INBOUND5_MASK 0x00000400
    #define PROC3_PROC3_INT_STATUS_DBG_INBOUND5_SHIFT 10
    #define PROC3_PROC3_INT_STATUS_DBG_INBOUND6_MASK 0x00000800
    #define PROC3_PROC3_INT_STATUS_DBG_INBOUND6_SHIFT 11
#define  PROC3_RST 0xAC14
    #define PROC3_RST_SOFT_RSTN_MASK 0x00000001
    #define PROC3_RST_SOFT_RSTN_SHIFT 0
#define  PROC3_SEQMC_MAP 0xAC00
    #define PROC3_SEQMC_MAP_CHANNELBIT_MASK 0x0000001F
    #define PROC3_SEQMC_MAP_CHANNELBIT_SHIFT 0
    #define PROC3_SEQMC_MAP_CH0_IS_SEQ_MASK 0x00000100
    #define PROC3_SEQMC_MAP_CH0_IS_SEQ_SHIFT 8
#define  PROC3_WATCHDOG_CNT 0xAC80
    #define PROC3_WATCHDOG_CNT_DATA_MASK 0xFFFFFFFF
    #define PROC3_WATCHDOG_CNT_DATA_SHIFT 0
#define  PROC3_WATCHDOG_COMPARE 0xAC84
    #define PROC3_WATCHDOG_COMPARE_DATA_MASK 0xFFFFFFFF
    #define PROC3_WATCHDOG_COMPARE_DATA_SHIFT 0
#define  PROC4_DBG_INBOUND0 0xB060
    #define PROC4_DBG_INBOUND0_DATA_MASK 0xFFFFFFFF
    #define PROC4_DBG_INBOUND0_DATA_SHIFT 0
#define  PROC4_DBG_INBOUND1 0xB0A0
    #define PROC4_DBG_INBOUND1_DATA_MASK 0xFFFFFFFF
    #define PROC4_DBG_INBOUND1_DATA_SHIFT 0
#define  PROC4_DBG_INBOUND2 0xB0A4
    #define PROC4_DBG_INBOUND2_DATA_MASK 0xFFFFFFFF
    #define PROC4_DBG_INBOUND2_DATA_SHIFT 0
#define  PROC4_DBG_INBOUND3 0xB0A8
    #define PROC4_DBG_INBOUND3_DATA_MASK 0xFFFFFFFF
    #define PROC4_DBG_INBOUND3_DATA_SHIFT 0
#define  PROC4_DBG_INBOUND4 0xB0AC
    #define PROC4_DBG_INBOUND4_DATA_MASK 0xFFFFFFFF
    #define PROC4_DBG_INBOUND4_DATA_SHIFT 0
#define  PROC4_DBG_INBOUND5 0xB0D0
    #define PROC4_DBG_INBOUND5_DATA_MASK 0xFFFFFFFF
    #define PROC4_DBG_INBOUND5_DATA_SHIFT 0
#define  PROC4_DBG_INBOUND6 0xB0D4
    #define PROC4_DBG_INBOUND6_DATA_MASK 0xFFFFFFFF
    #define PROC4_DBG_INBOUND6_DATA_SHIFT 0
#define  PROC4_DBG_OUTBOUND 0xB064
    #define PROC4_DBG_OUTBOUND_DATA_MASK 0xFFFFFFFF
    #define PROC4_DBG_OUTBOUND_DATA_SHIFT 0
#define  PROC4_FB_TOP 0xB004
    #define PROC4_FB_TOP_BASE_MASK 0xFFFF0000
    #define PROC4_FB_TOP_BASE_SHIFT 16
#define  PROC4_FPB_DBG_DATA0 0xB1E0
    #define PROC4_FPB_DBG_DATA0_PCP_MASK 0xFFFFFFFF
    #define PROC4_FPB_DBG_DATA0_PCP_SHIFT 0
#define  PROC4_FPB_DBG_DATA1 0xB1E4
    #define PROC4_FPB_DBG_DATA1_PFG_MASK 0xFFFFFFFF
    #define PROC4_FPB_DBG_DATA1_PFG_SHIFT 0
#define  PROC4_FPB_DBG_DATA2 0xB1E8
    #define PROC4_FPB_DBG_DATA2_MRC_MASK 0xFFFFFFFF
    #define PROC4_FPB_DBG_DATA2_MRC_SHIFT 0
#define  PROC4_FPB_DBG_DATA3 0xB1EC
    #define PROC4_FPB_DBG_DATA3_RDM_MASK 0xFFFFFFFF
    #define PROC4_FPB_DBG_DATA3_RDM_SHIFT 0
#define  PROC4_FPB_DBG_DATA4 0xB1F0
    #define PROC4_FPB_DBG_DATA4_PCR_MASK 0xFFFFFFFF
    #define PROC4_FPB_DBG_DATA4_PCR_SHIFT 0
#define  PROC4_HOST_INT_MASK 0xB0E4
    #define PROC4_HOST_INT_MASK_INT_EN_OUTBOUND_CALL0_MASK 0x00000001
    #define PROC4_HOST_INT_MASK_INT_EN_OUTBOUND_CALL0_SHIFT 0
    #define PROC4_HOST_INT_MASK_INT_EN_OUTBOUND_CALL1_MASK 0x00000002
    #define PROC4_HOST_INT_MASK_INT_EN_OUTBOUND_CALL1_SHIFT 1
    #define PROC4_HOST_INT_MASK_INT_EN_OUTBOUND_DBG_MASK 0x00000004
    #define PROC4_HOST_INT_MASK_INT_EN_OUTBOUND_DBG_SHIFT 2
    #define INT_EN_PROC4_HANG_MASK 0x80000000
    #define INT_EN_PROC4_HANG_SHIFT 31
#define  PROC4_HOST_INT_STATUS 0xB0E0
    #define PROC4_HOST_INT_STATUS_OUTBOUND_CALL0_MASK 0x00000001
    #define PROC4_HOST_INT_STATUS_OUTBOUND_CALL0_SHIFT 0
    #define PROC4_HOST_INT_STATUS_OUTBOUND_CALL1_MASK 0x00000002
    #define PROC4_HOST_INT_STATUS_OUTBOUND_CALL1_SHIFT 1
    #define PROC4_HOST_INT_STATUS_OUTBOUND_DBG_MASK 0x00000004
    #define PROC4_HOST_INT_STATUS_OUTBOUND_DBG_SHIFT 2
    #define PROC4_HANG_MASK 0x80000000
    #define PROC4_HANG_SHIFT 31
#define  PROC4_INBOUND_CALL_0 0xB020
    #define PROC4_INBOUND_CALL_0_DATA_MASK 0xFFFFFFFF
    #define PROC4_INBOUND_CALL_0_DATA_SHIFT 0
#define  PROC4_INBOUND_CALL_1 0xB024
    #define PROC4_INBOUND_CALL_1_DATA_MASK 0xFFFFFFFF
    #define PROC4_INBOUND_CALL_1_DATA_SHIFT 0
#define  PROC4_IPC_CALL 0xB0F0
    #define PROC4_IPC_CALL_DATA_MASK 0xFFFFFFFF
    #define PROC4_IPC_CALL_DATA_SHIFT 0
#define  PROC4_MEM_ALIAS 0xB00C
    #define PROC4_MEM_ALIAS_MASK_MASK 0xC0000000
    #define PROC4_MEM_ALIAS_MASK_SHIFT 30
#define  PROC4_MERGED_READ_CTL 0xB018
    #define PROC4_MERGED_READ_CTL_NONIDC_EN_MASK 0x00000001
    #define PROC4_MERGED_READ_CTL_NONIDC_EN_SHIFT 0
#define  PROC4_MERGED_WRITE_CTL 0xB010
    #define PROC4_MERGED_WRITE_CTL_TIMER_MASK 0x000003FF
    #define PROC4_MERGED_WRITE_CTL_TIMER_SHIFT 0
#define  PROC4_MMREG_APER 0xB008
    #define PROC4_MMREG_APER_BASE_MASK 0x0000FFFF
    #define PROC4_MMREG_APER_BASE_SHIFT 0
    #define PROC4_MMREG_APER_SIZE_MASK 0xFFFF0000
    #define PROC4_MMREG_APER_SIZE_SHIFT 16
#define  PROC4_MSG_DATA_0 0xB030
    #define PROC4_MSG_DATA_0_DATA_MASK 0xFFFFFFFF
    #define PROC4_MSG_DATA_0_DATA_SHIFT 0
#define  PROC4_MSG_DATA_1 0xB034
    #define PROC4_MSG_DATA_1_DATA_MASK 0xFFFFFFFF
    #define PROC4_MSG_DATA_1_DATA_SHIFT 0
#define  PROC4_MSG_DATA_10 0xB058
    #define PROC4_MSG_DATA_10_DATA_MASK 0xFFFFFFFF
    #define PROC4_MSG_DATA_10_DATA_SHIFT 0
#define  PROC4_MSG_DATA_11 0xB05C
    #define PROC4_MSG_DATA_11_DATA_MASK 0xFFFFFFFF
    #define PROC4_MSG_DATA_11_DATA_SHIFT 0
#define  PROC4_MSG_DATA_2 0xB038
    #define PROC4_MSG_DATA_2_DATA_MASK 0xFFFFFFFF
    #define PROC4_MSG_DATA_2_DATA_SHIFT 0
#define  PROC4_MSG_DATA_3 0xB03C
    #define PROC4_MSG_DATA_3_DATA_MASK 0xFFFFFFFF
    #define PROC4_MSG_DATA_3_DATA_SHIFT 0
#define  PROC4_MSG_DATA_4 0xB040
    #define PROC4_MSG_DATA_4_DATA_MASK 0xFFFFFFFF
    #define PROC4_MSG_DATA_4_DATA_SHIFT 0
#define  PROC4_MSG_DATA_5 0xB044
    #define PROC4_MSG_DATA_5_DATA_MASK 0xFFFFFFFF
    #define PROC4_MSG_DATA_5_DATA_SHIFT 0
#define  PROC4_MSG_DATA_6 0xB048
    #define PROC4_MSG_DATA_6_DATA_MASK 0xFFFFFFFF
    #define PROC4_MSG_DATA_6_DATA_SHIFT 0
#define  PROC4_MSG_DATA_7 0xB04C
    #define PROC4_MSG_DATA_7_DATA_MASK 0xFFFFFFFF
    #define PROC4_MSG_DATA_7_DATA_SHIFT 0
#define  PROC4_MSG_DATA_8 0xB050
    #define PROC4_MSG_DATA_8_DATA_MASK 0xFFFFFFFF
    #define PROC4_MSG_DATA_8_DATA_SHIFT 0
#define  PROC4_MSG_DATA_9 0xB054
    #define PROC4_MSG_DATA_9_DATA_MASK 0xFFFFFFFF
    #define PROC4_MSG_DATA_9_DATA_SHIFT 0
#define  PROC4_OUTBOUND_CALL_0 0xB028
    #define PROC4_OUTBOUND_CALL_0_DATA_MASK 0xFFFFFFFF
    #define PROC4_OUTBOUND_CALL_0_DATA_SHIFT 0
#define  PROC4_OUTBOUND_CALL_1 0xB02C
    #define PROC4_OUTBOUND_CALL_1_DATA_MASK 0xFFFFFFFF
    #define PROC4_OUTBOUND_CALL_1_DATA_SHIFT 0
#define  PROC4_PFB_CFG 0xB1A0
    #define PROC4_PFB_CFG_PREFETCH_MODE_MASK 0x00000003
    #define PROC4_PFB_CFG_PREFETCH_MODE_SHIFT 0
    #define PROC4_PFB_CFG_MC_PFB_EN_MASK 0x00000010
    #define PROC4_PFB_CFG_MC_PFB_EN_SHIFT 4
    #define PROC4_PFB_CFG_SEQ_PFB_EN_MASK 0x00000020
    #define PROC4_PFB_CFG_SEQ_PFB_EN_SHIFT 5
    #define PROC4_PFB_CFG_MAX_PREF_LINE_NUM_MASK 0x00000700
    #define PROC4_PFB_CFG_MAX_PREF_LINE_NUM_SHIFT 8
    #define PROC4_PFB_CFG_PFB_INT_EN_MASK 0x00001000
    #define PROC4_PFB_CFG_PFB_INT_EN_SHIFT 12
    #define PROC4_PFB_CFG_BVCI_PLEN_CHK_EN_MASK 0x00010000
    #define PROC4_PFB_CFG_BVCI_PLEN_CHK_EN_SHIFT 16
#define  PROC4_PFB_CL_OFFSET 0xB1A4
    #define PROC4_PFB_CL_OFFSET_LINE1_OFFSET_MASK 0x000000FF
    #define PROC4_PFB_CL_OFFSET_LINE1_OFFSET_SHIFT 0
    #define PROC4_PFB_CL_OFFSET_LINE2_OFFSET_MASK 0x0000FF00
    #define PROC4_PFB_CL_OFFSET_LINE2_OFFSET_SHIFT 8
    #define PROC4_PFB_CL_OFFSET_LINE3_OFFSET_MASK 0x00FF0000
    #define PROC4_PFB_CL_OFFSET_LINE3_OFFSET_SHIFT 16
    #define PROC4_PFB_CL_OFFSET_LINE4_OFFSET_MASK 0xFF000000
    #define PROC4_PFB_CL_OFFSET_LINE4_OFFSET_SHIFT 24
#define  PROC4_PFB_DBG_SEL 0xB1DC
    #define PROC4_PFB_DBG_SEL_PCP_SEL_MASK 0x0000000F
    #define PROC4_PFB_DBG_SEL_PCP_SEL_SHIFT 0
    #define PROC4_PFB_DBG_SEL_PFG_SEL_MASK 0x000000F0
    #define PROC4_PFB_DBG_SEL_PFG_SEL_SHIFT 4
    #define PROC4_PFB_DBG_SEL_MRC_SEL_MASK 0x00000F00
    #define PROC4_PFB_DBG_SEL_MRC_SEL_SHIFT 8
    #define PROC4_PFB_DBG_SEL_RDM_SEL_MASK 0x0000F000
    #define PROC4_PFB_DBG_SEL_RDM_SEL_SHIFT 12
    #define PROC4_PFB_DBG_SEL_PCR_SEL_MASK 0x000F0000
    #define PROC4_PFB_DBG_SEL_PCR_SEL_SHIFT 16
#define  PROC4_PFB_FLOW_CTL 0xB1A8
    #define PROC4_PFB_FLOW_CTL_FEQ_LOW_WATERMARK_MASK 0x000000FF
    #define PROC4_PFB_FLOW_CTL_FEQ_LOW_WATERMARK_SHIFT 0
    #define PROC4_PFB_FLOW_CTL_FCLQ_HIGH_WATERMARK_MASK 0x00000F00
    #define PROC4_PFB_FLOW_CTL_FCLQ_HIGH_WATERMARK_SHIFT 8
    #define PROC4_PFB_FLOW_CTL_CPRQ_HIGH_WATERMARK_MASK 0x000F0000
    #define PROC4_PFB_FLOW_CTL_CPRQ_HIGH_WATERMARK_SHIFT 16
#define  PROC4_PFB_INVALID_ALL 0xB1B0
    #define PROC4_PFB_INVALID_ALL_DATA_MASK 0xFFFFFFFF
    #define PROC4_PFB_INVALID_ALL_DATA_SHIFT 0
#define  PROC4_PFB_STAT1 0xB1BC
    #define PROC4_PFB_STAT1_CORE_CRD_NUM_MASK 0xFFFFFFFF
    #define PROC4_PFB_STAT1_CORE_CRD_NUM_SHIFT 0
#define  PROC4_PFB_STAT2 0xB1C0
    #define PROC4_PFB_STAT2_CORE_CRD_HIT_NUM_MASK 0xFFFFFFFF
    #define PROC4_PFB_STAT2_CORE_CRD_HIT_NUM_SHIFT 0
#define  PROC4_PFB_STAT3 0xB1C4
    #define PROC4_PFB_STAT3_PREF_CRD_NUM_MASK 0xFFFFFFFF
    #define PROC4_PFB_STAT3_PREF_CRD_NUM_SHIFT 0
#define  PROC4_PFB_STAT4 0xB1C8
    #define PROC4_PFB_STAT4_CORE_CRD_HIT_DATNRDY_NUM_MASK 0xFFFFFFFF
    #define PROC4_PFB_STAT4_CORE_CRD_HIT_DATNRDY_NUM_SHIFT 0
#define  PROC4_PFB_STATUS 0xB1B8
    #define PROC4_PFB_STATUS_ERROR_MASK 0x0000001F
    #define PROC4_PFB_STATUS_ERROR_SHIFT 0
    #define PROC4_PFB_STATUS_ERR_CMD_MASK 0x00000F00
    #define PROC4_PFB_STATUS_ERR_CMD_SHIFT 8
#define  PROC4_PFB_TBS_IN 0xB1D0
    #define PROC4_PFB_TBS_IN_COMMAND_MASK 0x0000000F
    #define PROC4_PFB_TBS_IN_COMMAND_SHIFT 0
    #define PROC4_PFB_TBS_IN_WAY_PT_MASK 0x00001F00
    #define PROC4_PFB_TBS_IN_WAY_PT_SHIFT 8
    #define PROC4_PFB_TBS_IN_LAST_MASK 0x001F0000
    #define PROC4_PFB_TBS_IN_LAST_SHIFT 16
    #define PROC4_PFB_TBS_IN_NEXT_MASK 0x1F000000
    #define PROC4_PFB_TBS_IN_NEXT_SHIFT 24
    #define PROC4_PFB_TBS_IN_UNLOAD_PD_MASK 0x20000000
    #define PROC4_PFB_TBS_IN_UNLOAD_PD_SHIFT 29
    #define PROC4_PFB_TBS_IN_LOAD_PD_MASK 0x40000000
    #define PROC4_PFB_TBS_IN_LOAD_PD_SHIFT 30
    #define PROC4_PFB_TBS_IN_VALID_MASK 0x80000000
    #define PROC4_PFB_TBS_IN_VALID_SHIFT 31
#define  PROC4_PFB_TBS_IN2 0xB1D4
    #define PROC4_PFB_TBS_IN2_ADDR_MASK 0xFFFFFFE0
    #define PROC4_PFB_TBS_IN2_ADDR_SHIFT 5
#define  PROC4_PFB_TBS_OUT 0xB1D8
    #define PROC4_PFB_TBS_OUT_TBS_RDY_MASK 0x00000001
    #define PROC4_PFB_TBS_OUT_TBS_RDY_SHIFT 0
    #define PROC4_PFB_TBS_OUT_ADDR_HIT_MASK 0x00000010
    #define PROC4_PFB_TBS_OUT_ADDR_HIT_SHIFT 4
    #define PROC4_PFB_TBS_OUT_WAY_PT_MASK 0x00001F00
    #define PROC4_PFB_TBS_OUT_WAY_PT_SHIFT 8
    #define PROC4_PFB_TBS_OUT_LAST_MASK 0x001F0000
    #define PROC4_PFB_TBS_OUT_LAST_SHIFT 16
    #define PROC4_PFB_TBS_OUT_NEXT_MASK 0x1F000000
    #define PROC4_PFB_TBS_OUT_NEXT_SHIFT 24
    #define PROC4_PFB_TBS_OUT_UNLOAD_PD_MASK 0x20000000
    #define PROC4_PFB_TBS_OUT_UNLOAD_PD_SHIFT 29
    #define PROC4_PFB_TBS_OUT_LOAD_PD_MASK 0x40000000
    #define PROC4_PFB_TBS_OUT_LOAD_PD_SHIFT 30
    #define PROC4_PFB_TBS_OUT_VALID_MASK 0x80000000
    #define PROC4_PFB_TBS_OUT_VALID_SHIFT 31
#define  PROC4_PROC4_INT_MASK 0xB0EC
    #define PROC4_PROC4_INT_MASK_INT_EN_INBOUND_CALL0_MASK 0x00000001
    #define PROC4_PROC4_INT_MASK_INT_EN_INBOUND_CALL0_SHIFT 0
    #define PROC4_PROC4_INT_MASK_INT_EN_INBOUND_CALL1_MASK 0x00000002
    #define PROC4_PROC4_INT_MASK_INT_EN_INBOUND_CALL1_SHIFT 1
    #define PROC4_PROC4_INT_MASK_INT_EN_IPC_CALL_MASK 0x00000008
    #define PROC4_PROC4_INT_MASK_INT_EN_IPC_CALL_SHIFT 3
    #define PROC4_PROC4_INT_MASK_INT_EN_DBG_INBOUND0_MASK 0x00000020
    #define PROC4_PROC4_INT_MASK_INT_EN_DBG_INBOUND0_SHIFT 5
    #define PROC4_PROC4_INT_MASK_INT_EN_DBG_INBOUND1_MASK 0x00000040
    #define PROC4_PROC4_INT_MASK_INT_EN_DBG_INBOUND1_SHIFT 6
    #define PROC4_PROC4_INT_MASK_INT_EN_DBG_INBOUND2_MASK 0x00000080
    #define PROC4_PROC4_INT_MASK_INT_EN_DBG_INBOUND2_SHIFT 7
    #define PROC4_PROC4_INT_MASK_INT_EN_DBG_INBOUND3_MASK 0x00000100
    #define PROC4_PROC4_INT_MASK_INT_EN_DBG_INBOUND3_SHIFT 8
    #define PROC4_PROC4_INT_MASK_INT_EN_DBG_INBOUND4_MASK 0x00000200
    #define PROC4_PROC4_INT_MASK_INT_EN_DBG_INBOUND4_SHIFT 9
    #define PROC4_PROC4_INT_MASK_INT_EN_DBG_INBOUND5_MASK 0x00000400
    #define PROC4_PROC4_INT_MASK_INT_EN_DBG_INBOUND5_SHIFT 10
    #define PROC4_PROC4_INT_MASK_INT_EN_DBG_INBOUND6_MASK 0x00000800
    #define PROC4_PROC4_INT_MASK_INT_EN_DBG_INBOUND6_SHIFT 11
#define  PROC4_PROC4_INT_STATUS 0xB0E8
    #define PROC4_PROC4_INT_STATUS_INBOUND_CALL0_MASK 0x00000001
    #define PROC4_PROC4_INT_STATUS_INBOUND_CALL0_SHIFT 0
    #define PROC4_PROC4_INT_STATUS_INBOUND_CALL1_MASK 0x00000002
    #define PROC4_PROC4_INT_STATUS_INBOUND_CALL1_SHIFT 1
    #define PROC4_PROC4_INT_STATUS_IPC_CALL_MASK 0x00000008
    #define PROC4_PROC4_INT_STATUS_IPC_CALL_SHIFT 3
    #define PROC4_PROC4_INT_STATUS_DBG_INBOUND0_MASK 0x00000020
    #define PROC4_PROC4_INT_STATUS_DBG_INBOUND0_SHIFT 5
    #define PROC4_PROC4_INT_STATUS_DBG_INBOUND1_MASK 0x00000040
    #define PROC4_PROC4_INT_STATUS_DBG_INBOUND1_SHIFT 6
    #define PROC4_PROC4_INT_STATUS_DBG_INBOUND2_MASK 0x00000080
    #define PROC4_PROC4_INT_STATUS_DBG_INBOUND2_SHIFT 7
    #define PROC4_PROC4_INT_STATUS_DBG_INBOUND3_MASK 0x00000100
    #define PROC4_PROC4_INT_STATUS_DBG_INBOUND3_SHIFT 8
    #define PROC4_PROC4_INT_STATUS_DBG_INBOUND4_MASK 0x00000200
    #define PROC4_PROC4_INT_STATUS_DBG_INBOUND4_SHIFT 9
    #define PROC4_PROC4_INT_STATUS_DBG_INBOUND5_MASK 0x00000400
    #define PROC4_PROC4_INT_STATUS_DBG_INBOUND5_SHIFT 10
    #define PROC4_PROC4_INT_STATUS_DBG_INBOUND6_MASK 0x00000800
    #define PROC4_PROC4_INT_STATUS_DBG_INBOUND6_SHIFT 11
#define  PROC4_RST 0xB014
    #define PROC4_RST_SOFT_RSTN_MASK 0x00000001
    #define PROC4_RST_SOFT_RSTN_SHIFT 0
#define  PROC4_SEQMC_MAP 0xB000
    #define PROC4_SEQMC_MAP_CHANNELBIT_MASK 0x0000001F
    #define PROC4_SEQMC_MAP_CHANNELBIT_SHIFT 0
    #define PROC4_SEQMC_MAP_CH0_IS_SEQ_MASK 0x00000100
    #define PROC4_SEQMC_MAP_CH0_IS_SEQ_SHIFT 8
#define  PROC4_WATCHDOG_CNT 0xB080
    #define PROC4_WATCHDOG_CNT_DATA_MASK 0xFFFFFFFF
    #define PROC4_WATCHDOG_CNT_DATA_SHIFT 0
#define  PROC4_WATCHDOG_COMPARE 0xB084
    #define PROC4_WATCHDOG_COMPARE_DATA_MASK 0xFFFFFFFF
    #define PROC4_WATCHDOG_COMPARE_DATA_SHIFT 0
#define  PROC5_DBG_INBOUND0 0xB460
    #define PROC5_DBG_INBOUND0_DATA_MASK 0xFFFFFFFF
    #define PROC5_DBG_INBOUND0_DATA_SHIFT 0
#define  PROC5_DBG_INBOUND1 0xB4A0
    #define PROC5_DBG_INBOUND1_DATA_MASK 0xFFFFFFFF
    #define PROC5_DBG_INBOUND1_DATA_SHIFT 0
#define  PROC5_DBG_INBOUND2 0xB4A4
    #define PROC5_DBG_INBOUND2_DATA_MASK 0xFFFFFFFF
    #define PROC5_DBG_INBOUND2_DATA_SHIFT 0
#define  PROC5_DBG_INBOUND3 0xB4A8
    #define PROC5_DBG_INBOUND3_DATA_MASK 0xFFFFFFFF
    #define PROC5_DBG_INBOUND3_DATA_SHIFT 0
#define  PROC5_DBG_INBOUND4 0xB4AC
    #define PROC5_DBG_INBOUND4_DATA_MASK 0xFFFFFFFF
    #define PROC5_DBG_INBOUND4_DATA_SHIFT 0
#define  PROC5_DBG_INBOUND5 0xB4D0
    #define PROC5_DBG_INBOUND5_DATA_MASK 0xFFFFFFFF
    #define PROC5_DBG_INBOUND5_DATA_SHIFT 0
#define  PROC5_DBG_OUTBOUND 0xB464
    #define PROC5_DBG_OUTBOUND_DATA_MASK 0xFFFFFFFF
    #define PROC5_DBG_OUTBOUND_DATA_SHIFT 0
#define  PROC5_FB_TOP 0xB404
    #define PROC5_FB_TOP_BASE_MASK 0xFFFF0000
    #define PROC5_FB_TOP_BASE_SHIFT 16
#define  PROC5_FPB_DBG_DATA0 0xB5E0
    #define PROC5_FPB_DBG_DATA0_PCP_MASK 0xFFFFFFFF
    #define PROC5_FPB_DBG_DATA0_PCP_SHIFT 0
#define  PROC5_FPB_DBG_DATA1 0xB5E4
    #define PROC5_FPB_DBG_DATA1_PFG_MASK 0xFFFFFFFF
    #define PROC5_FPB_DBG_DATA1_PFG_SHIFT 0
#define  PROC5_FPB_DBG_DATA2 0xB5E8
    #define PROC5_FPB_DBG_DATA2_MRC_MASK 0xFFFFFFFF
    #define PROC5_FPB_DBG_DATA2_MRC_SHIFT 0
#define  PROC5_FPB_DBG_DATA3 0xB5EC
    #define PROC5_FPB_DBG_DATA3_RDM_MASK 0xFFFFFFFF
    #define PROC5_FPB_DBG_DATA3_RDM_SHIFT 0
#define  PROC5_FPB_DBG_DATA4 0xB5F0
    #define PROC5_FPB_DBG_DATA4_PCR_MASK 0xFFFFFFFF
    #define PROC5_FPB_DBG_DATA4_PCR_SHIFT 0
#define  PROC5_HOST_INT_MASK 0xB4E4
    #define PROC5_HOST_INT_MASK_INT_EN_OUTBOUND_CALL0_MASK 0x00000001
    #define PROC5_HOST_INT_MASK_INT_EN_OUTBOUND_CALL0_SHIFT 0
    #define PROC5_HOST_INT_MASK_INT_EN_OUTBOUND_CALL1_MASK 0x00000002
    #define PROC5_HOST_INT_MASK_INT_EN_OUTBOUND_CALL1_SHIFT 1
    #define PROC5_HOST_INT_MASK_INT_EN_OUTBOUND_DBG_MASK 0x00000004
    #define PROC5_HOST_INT_MASK_INT_EN_OUTBOUND_DBG_SHIFT 2
    #define INT_EN_PROC5_HANG_MASK 0x80000000
    #define INT_EN_PROC5_HANG_SHIFT 31
#define  PROC5_HOST_INT_STATUS 0xB4E0
    #define PROC5_HOST_INT_STATUS_OUTBOUND_CALL0_MASK 0x00000001
    #define PROC5_HOST_INT_STATUS_OUTBOUND_CALL0_SHIFT 0
    #define PROC5_HOST_INT_STATUS_OUTBOUND_CALL1_MASK 0x00000002
    #define PROC5_HOST_INT_STATUS_OUTBOUND_CALL1_SHIFT 1
    #define PROC5_HOST_INT_STATUS_OUTBOUND_DBG_MASK 0x00000004
    #define PROC5_HOST_INT_STATUS_OUTBOUND_DBG_SHIFT 2
    #define PROC5_HANG_MASK 0x80000000
    #define PROC5_HANG_SHIFT 31
#define  PROC5_INBOUND_CALL_0 0xB420
    #define PROC5_INBOUND_CALL_0_DATA_MASK 0xFFFFFFFF
    #define PROC5_INBOUND_CALL_0_DATA_SHIFT 0
#define  PROC5_INBOUND_CALL_1 0xB424
    #define PROC5_INBOUND_CALL_1_DATA_MASK 0xFFFFFFFF
    #define PROC5_INBOUND_CALL_1_DATA_SHIFT 0
#define  PROC5_IPC_CALL 0xB4F0
    #define PROC5_IPC_CALL_DATA_MASK 0xFFFFFFFF
    #define PROC5_IPC_CALL_DATA_SHIFT 0
#define  PROC5_MEM_ALIAS 0xB40C
    #define PROC5_MEM_ALIAS_MASK_MASK 0xC0000000
    #define PROC5_MEM_ALIAS_MASK_SHIFT 30
#define  PROC5_MERGED_READ_CTL 0xB418
    #define PROC5_MERGED_READ_CTL_NONIDC_EN_MASK 0x00000001
    #define PROC5_MERGED_READ_CTL_NONIDC_EN_SHIFT 0
#define  PROC5_MERGED_WRITE_CTL 0xB410
    #define PROC5_MERGED_WRITE_CTL_TIMER_MASK 0x000003FF
    #define PROC5_MERGED_WRITE_CTL_TIMER_SHIFT 0
#define  PROC5_MMREG_APER 0xB408
    #define PROC5_MMREG_APER_BASE_MASK 0x0000FFFF
    #define PROC5_MMREG_APER_BASE_SHIFT 0
    #define PROC5_MMREG_APER_SIZE_MASK 0xFFFF0000
    #define PROC5_MMREG_APER_SIZE_SHIFT 16
#define  PROC5_MSG_DATA_0 0xB430
    #define PROC5_MSG_DATA_0_DATA_MASK 0xFFFFFFFF
    #define PROC5_MSG_DATA_0_DATA_SHIFT 0
#define  PROC5_MSG_DATA_1 0xB434
    #define PROC5_MSG_DATA_1_DATA_MASK 0xFFFFFFFF
    #define PROC5_MSG_DATA_1_DATA_SHIFT 0
#define  PROC5_MSG_DATA_10 0xB458
    #define PROC5_MSG_DATA_10_DATA_MASK 0xFFFFFFFF
    #define PROC5_MSG_DATA_10_DATA_SHIFT 0
#define  PROC5_MSG_DATA_11 0xB45C
    #define PROC5_MSG_DATA_11_DATA_MASK 0xFFFFFFFF
    #define PROC5_MSG_DATA_11_DATA_SHIFT 0
#define  PROC5_MSG_DATA_2 0xB438
    #define PROC5_MSG_DATA_2_DATA_MASK 0xFFFFFFFF
    #define PROC5_MSG_DATA_2_DATA_SHIFT 0
#define  PROC5_MSG_DATA_3 0xB43C
    #define PROC5_MSG_DATA_3_DATA_MASK 0xFFFFFFFF
    #define PROC5_MSG_DATA_3_DATA_SHIFT 0
#define  PROC5_MSG_DATA_4 0xB440
    #define PROC5_MSG_DATA_4_DATA_MASK 0xFFFFFFFF
    #define PROC5_MSG_DATA_4_DATA_SHIFT 0
#define  PROC5_MSG_DATA_5 0xB444
    #define PROC5_MSG_DATA_5_DATA_MASK 0xFFFFFFFF
    #define PROC5_MSG_DATA_5_DATA_SHIFT 0
#define  PROC5_MSG_DATA_6 0xB448
    #define PROC5_MSG_DATA_6_DATA_MASK 0xFFFFFFFF
    #define PROC5_MSG_DATA_6_DATA_SHIFT 0
#define  PROC5_MSG_DATA_7 0xB44C
    #define PROC5_MSG_DATA_7_DATA_MASK 0xFFFFFFFF
    #define PROC5_MSG_DATA_7_DATA_SHIFT 0
#define  PROC5_MSG_DATA_8 0xB450
    #define PROC5_MSG_DATA_8_DATA_MASK 0xFFFFFFFF
    #define PROC5_MSG_DATA_8_DATA_SHIFT 0
#define  PROC5_MSG_DATA_9 0xB454
    #define PROC5_MSG_DATA_9_DATA_MASK 0xFFFFFFFF
    #define PROC5_MSG_DATA_9_DATA_SHIFT 0
#define  PROC5_OUTBOUND_CALL_0 0xB428
    #define PROC5_OUTBOUND_CALL_0_DATA_MASK 0xFFFFFFFF
    #define PROC5_OUTBOUND_CALL_0_DATA_SHIFT 0
#define  PROC5_OUTBOUND_CALL_1 0xB42C
    #define PROC5_OUTBOUND_CALL_1_DATA_MASK 0xFFFFFFFF
    #define PROC5_OUTBOUND_CALL_1_DATA_SHIFT 0
#define  PROC5_PFB_CFG 0xB5A0
    #define PROC5_PFB_CFG_PREFETCH_MODE_MASK 0x00000003
    #define PROC5_PFB_CFG_PREFETCH_MODE_SHIFT 0
    #define PROC5_PFB_CFG_MC_PFB_EN_MASK 0x00000010
    #define PROC5_PFB_CFG_MC_PFB_EN_SHIFT 4
    #define PROC5_PFB_CFG_SEQ_PFB_EN_MASK 0x00000020
    #define PROC5_PFB_CFG_SEQ_PFB_EN_SHIFT 5
    #define PROC5_PFB_CFG_MAX_PREF_LINE_NUM_MASK 0x00000700
    #define PROC5_PFB_CFG_MAX_PREF_LINE_NUM_SHIFT 8
    #define PROC5_PFB_CFG_BVCI_PLEN_CHK_EN_MASK 0x00010000
    #define PROC5_PFB_CFG_BVCI_PLEN_CHK_EN_SHIFT 16
#define  PROC5_PFB_CL_OFFSET 0xB5A4
    #define PROC5_PFB_CL_OFFSET_LINE1_OFFSET_MASK 0x000000FF
    #define PROC5_PFB_CL_OFFSET_LINE1_OFFSET_SHIFT 0
    #define PROC5_PFB_CL_OFFSET_LINE2_OFFSET_MASK 0x0000FF00
    #define PROC5_PFB_CL_OFFSET_LINE2_OFFSET_SHIFT 8
    #define PROC5_PFB_CL_OFFSET_LINE3_OFFSET_MASK 0x00FF0000
    #define PROC5_PFB_CL_OFFSET_LINE3_OFFSET_SHIFT 16
    #define PROC5_PFB_CL_OFFSET_LINE4_OFFSET_MASK 0xFF000000
    #define PROC5_PFB_CL_OFFSET_LINE4_OFFSET_SHIFT 24
#define  PROC5_PFB_DBG_SEL 0xB5DC
    #define PROC5_PFB_DBG_SEL_PCP_SEL_MASK 0x0000000F
    #define PROC5_PFB_DBG_SEL_PCP_SEL_SHIFT 0
    #define PROC5_PFB_DBG_SEL_PFG_SEL_MASK 0x000000F0
    #define PROC5_PFB_DBG_SEL_PFG_SEL_SHIFT 4
    #define PROC5_PFB_DBG_SEL_MRC_SEL_MASK 0x00000F00
    #define PROC5_PFB_DBG_SEL_MRC_SEL_SHIFT 8
    #define PROC5_PFB_DBG_SEL_RDM_SEL_MASK 0x0000F000
    #define PROC5_PFB_DBG_SEL_RDM_SEL_SHIFT 12
    #define PROC5_PFB_DBG_SEL_PCR_SEL_MASK 0x000F0000
    #define PROC5_PFB_DBG_SEL_PCR_SEL_SHIFT 16
#define  PROC5_PFB_FLOW_CTL 0xB5A8
    #define PROC5_PFB_FLOW_CTL_FEQ_LOW_WATERMARK_MASK 0x000000FF
    #define PROC5_PFB_FLOW_CTL_FEQ_LOW_WATERMARK_SHIFT 0
    #define PROC5_PFB_FLOW_CTL_FCLQ_HIGH_WATERMARK_MASK 0x00000F00
    #define PROC5_PFB_FLOW_CTL_FCLQ_HIGH_WATERMARK_SHIFT 8
    #define PROC5_PFB_FLOW_CTL_CPRQ_HIGH_WATERMARK_MASK 0x000F0000
    #define PROC5_PFB_FLOW_CTL_CPRQ_HIGH_WATERMARK_SHIFT 16
#define  PROC5_PFB_INVALID_ALL 0xB5B0
    #define PROC5_PFB_INVALID_ALL_DATA_MASK 0xFFFFFFFF
    #define PROC5_PFB_INVALID_ALL_DATA_SHIFT 0
#define  PROC5_PFB_STAT1 0xB5BC
    #define PROC5_PFB_STAT1_CORE_CRD_NUM_MASK 0xFFFFFFFF
    #define PROC5_PFB_STAT1_CORE_CRD_NUM_SHIFT 0
#define  PROC5_PFB_STAT2 0xB5C0
    #define PROC5_PFB_STAT2_CORE_CRD_HIT_NUM_MASK 0xFFFFFFFF
    #define PROC5_PFB_STAT2_CORE_CRD_HIT_NUM_SHIFT 0
#define  PROC5_PFB_STAT3 0xB5C4
    #define PROC5_PFB_STAT3_PREF_CRD_NUM_MASK 0xFFFFFFFF
    #define PROC5_PFB_STAT3_PREF_CRD_NUM_SHIFT 0
#define  PROC5_PFB_STAT4 0xB5C8
    #define PROC5_PFB_STAT4_CORE_CRD_HIT_DATNRDY_NUM_MASK 0xFFFFFFFF
    #define PROC5_PFB_STAT4_CORE_CRD_HIT_DATNRDY_NUM_SHIFT 0
#define  PROC5_PFB_STATUS 0xB5B8
    #define PROC5_PFB_STATUS_ERROR_MASK 0x0000001F
    #define PROC5_PFB_STATUS_ERROR_SHIFT 0
    #define PROC5_PFB_STATUS_ERR_CMD_MASK 0x00000F00
    #define PROC5_PFB_STATUS_ERR_CMD_SHIFT 8
#define  PROC5_PFB_TBS_IN 0xB5D0
    #define PROC5_PFB_TBS_IN_COMMAND_MASK 0x0000000F
    #define PROC5_PFB_TBS_IN_COMMAND_SHIFT 0
    #define PROC5_PFB_TBS_IN_WAY_PT_MASK 0x00001F00
    #define PROC5_PFB_TBS_IN_WAY_PT_SHIFT 8
    #define PROC5_PFB_TBS_IN_LAST_MASK 0x001F0000
    #define PROC5_PFB_TBS_IN_LAST_SHIFT 16
    #define PROC5_PFB_TBS_IN_NEXT_MASK 0x1F000000
    #define PROC5_PFB_TBS_IN_NEXT_SHIFT 24
    #define PROC5_PFB_TBS_IN_UNLOAD_PD_MASK 0x20000000
    #define PROC5_PFB_TBS_IN_UNLOAD_PD_SHIFT 29
    #define PROC5_PFB_TBS_IN_LOAD_PD_MASK 0x40000000
    #define PROC5_PFB_TBS_IN_LOAD_PD_SHIFT 30
    #define PROC5_PFB_TBS_IN_VALID_MASK 0x80000000
    #define PROC5_PFB_TBS_IN_VALID_SHIFT 31
#define  PROC5_PFB_TBS_IN2 0xB5D4
    #define PROC5_PFB_TBS_IN2_ADDR_MASK 0xFFFFFFE0
    #define PROC5_PFB_TBS_IN2_ADDR_SHIFT 5
#define  PROC5_PFB_TBS_OUT 0xB5D8
    #define PROC5_PFB_TBS_OUT_TBS_RDY_MASK 0x00000001
    #define PROC5_PFB_TBS_OUT_TBS_RDY_SHIFT 0
    #define PROC5_PFB_TBS_OUT_ADDR_HIT_MASK 0x00000010
    #define PROC5_PFB_TBS_OUT_ADDR_HIT_SHIFT 4
    #define PROC5_PFB_TBS_OUT_WAY_PT_MASK 0x00001F00
    #define PROC5_PFB_TBS_OUT_WAY_PT_SHIFT 8
    #define PROC5_PFB_TBS_OUT_LAST_MASK 0x001F0000
    #define PROC5_PFB_TBS_OUT_LAST_SHIFT 16
    #define PROC5_PFB_TBS_OUT_NEXT_MASK 0x1F000000
    #define PROC5_PFB_TBS_OUT_NEXT_SHIFT 24
    #define PROC5_PFB_TBS_OUT_UNLOAD_PD_MASK 0x20000000
    #define PROC5_PFB_TBS_OUT_UNLOAD_PD_SHIFT 29
    #define PROC5_PFB_TBS_OUT_LOAD_PD_MASK 0x40000000
    #define PROC5_PFB_TBS_OUT_LOAD_PD_SHIFT 30
    #define PROC5_PFB_TBS_OUT_VALID_MASK 0x80000000
    #define PROC5_PFB_TBS_OUT_VALID_SHIFT 31
#define  PROC5_PROC5_INT_MASK 0xB4EC
    #define PROC5_PROC5_INT_MASK_INT_EN_INBOUND_CALL0_MASK 0x00000001
    #define PROC5_PROC5_INT_MASK_INT_EN_INBOUND_CALL0_SHIFT 0
    #define PROC5_PROC5_INT_MASK_INT_EN_INBOUND_CALL1_MASK 0x00000002
    #define PROC5_PROC5_INT_MASK_INT_EN_INBOUND_CALL1_SHIFT 1
    #define PROC5_PROC5_INT_MASK_INT_EN_IPC_CALL_MASK 0x00000008
    #define PROC5_PROC5_INT_MASK_INT_EN_IPC_CALL_SHIFT 3
    #define PROC5_PROC5_INT_MASK_INT_EN_DBG_INBOUND0_MASK 0x00000020
    #define PROC5_PROC5_INT_MASK_INT_EN_DBG_INBOUND0_SHIFT 5
    #define PROC5_PROC5_INT_MASK_INT_EN_DBG_INBOUND1_MASK 0x00000040
    #define PROC5_PROC5_INT_MASK_INT_EN_DBG_INBOUND1_SHIFT 6
    #define PROC5_PROC5_INT_MASK_INT_EN_DBG_INBOUND2_MASK 0x00000080
    #define PROC5_PROC5_INT_MASK_INT_EN_DBG_INBOUND2_SHIFT 7
    #define PROC5_PROC5_INT_MASK_INT_EN_DBG_INBOUND3_MASK 0x00000100
    #define PROC5_PROC5_INT_MASK_INT_EN_DBG_INBOUND3_SHIFT 8
    #define PROC5_PROC5_INT_MASK_INT_EN_DBG_INBOUND4_MASK 0x00000200
    #define PROC5_PROC5_INT_MASK_INT_EN_DBG_INBOUND4_SHIFT 9
    #define PROC5_PROC5_INT_MASK_INT_EN_DBG_INBOUND5_MASK 0x00000400
    #define PROC5_PROC5_INT_MASK_INT_EN_DBG_INBOUND5_SHIFT 10
#define  PROC5_PROC5_INT_STATUS 0xB4E8
    #define PROC5_PROC5_INT_STATUS_INBOUND_CALL0_MASK 0x00000001
    #define PROC5_PROC5_INT_STATUS_INBOUND_CALL0_SHIFT 0
    #define PROC5_PROC5_INT_STATUS_INBOUND_CALL1_MASK 0x00000002
    #define PROC5_PROC5_INT_STATUS_INBOUND_CALL1_SHIFT 1
    #define PROC5_PROC5_INT_STATUS_IPC_CALL_MASK 0x00000008
    #define PROC5_PROC5_INT_STATUS_IPC_CALL_SHIFT 3
    #define PROC5_PROC5_INT_STATUS_DBG_INBOUND0_MASK 0x00000020
    #define PROC5_PROC5_INT_STATUS_DBG_INBOUND0_SHIFT 5
    #define PROC5_PROC5_INT_STATUS_DBG_INBOUND1_MASK 0x00000040
    #define PROC5_PROC5_INT_STATUS_DBG_INBOUND1_SHIFT 6
    #define PROC5_PROC5_INT_STATUS_DBG_INBOUND2_MASK 0x00000080
    #define PROC5_PROC5_INT_STATUS_DBG_INBOUND2_SHIFT 7
    #define PROC5_PROC5_INT_STATUS_DBG_INBOUND3_MASK 0x00000100
    #define PROC5_PROC5_INT_STATUS_DBG_INBOUND3_SHIFT 8
    #define PROC5_PROC5_INT_STATUS_DBG_INBOUND4_MASK 0x00000200
    #define PROC5_PROC5_INT_STATUS_DBG_INBOUND4_SHIFT 9
    #define PROC5_PROC5_INT_STATUS_DBG_INBOUND5_MASK 0x00000400
    #define PROC5_PROC5_INT_STATUS_DBG_INBOUND5_SHIFT 10
#define  PROC5_RST 0xB414
    #define PROC5_RST_SOFT_RSTN_MASK 0x00000001
    #define PROC5_RST_SOFT_RSTN_SHIFT 0
#define  PROC5_SEQMC_MAP 0xB400
    #define PROC5_SEQMC_MAP_CHANNELBIT_MASK 0x0000001F
    #define PROC5_SEQMC_MAP_CHANNELBIT_SHIFT 0
    #define PROC5_SEQMC_MAP_CH0_IS_SEQ_MASK 0x00000100
    #define PROC5_SEQMC_MAP_CH0_IS_SEQ_SHIFT 8
#define  PROC5_WATCHDOG_CNT 0xB480
    #define PROC5_WATCHDOG_CNT_DATA_MASK 0xFFFFFFFF
    #define PROC5_WATCHDOG_CNT_DATA_SHIFT 0
#define  PROC5_WATCHDOG_COMPARE 0xB484
    #define PROC5_WATCHDOG_COMPARE_DATA_MASK 0xFFFFFFFF
    #define PROC5_WATCHDOG_COMPARE_DATA_SHIFT 0
#define  PROC6_DBG_INBOUND0 0xB860
    #define PROC6_DBG_INBOUND0_DATA_MASK 0xFFFFFFFF
    #define PROC6_DBG_INBOUND0_DATA_SHIFT 0
#define  PROC6_DBG_INBOUND1 0xB8A0
    #define PROC6_DBG_INBOUND1_DATA_MASK 0xFFFFFFFF
    #define PROC6_DBG_INBOUND1_DATA_SHIFT 0
#define  PROC6_DBG_INBOUND2 0xB8A4
    #define PROC6_DBG_INBOUND2_DATA_MASK 0xFFFFFFFF
    #define PROC6_DBG_INBOUND2_DATA_SHIFT 0
#define  PROC6_DBG_INBOUND3 0xB8A8
    #define PROC6_DBG_INBOUND3_DATA_MASK 0xFFFFFFFF
    #define PROC6_DBG_INBOUND3_DATA_SHIFT 0
#define  PROC6_DBG_INBOUND4 0xB8AC
    #define PROC6_DBG_INBOUND4_DATA_MASK 0xFFFFFFFF
    #define PROC6_DBG_INBOUND4_DATA_SHIFT 0
#define  PROC6_DBG_INBOUND5 0xB8D0
    #define PROC6_DBG_INBOUND5_DATA_MASK 0xFFFFFFFF
    #define PROC6_DBG_INBOUND5_DATA_SHIFT 0
#define  PROC6_DBG_INBOUND6 0xB8D4
    #define PROC6_DBG_INBOUND6_DATA_MASK 0xFFFFFFFF
    #define PROC6_DBG_INBOUND6_DATA_SHIFT 0
#define  PROC6_DBG_OUTBOUND 0xB864
    #define PROC6_DBG_OUTBOUND_DATA_MASK 0xFFFFFFFF
    #define PROC6_DBG_OUTBOUND_DATA_SHIFT 0
#define  PROC6_DMA_CONFIG 0xB898
    #define PROC6_DMA_CONFIG_LENGTH_MASK 0x000007FF
    #define PROC6_DMA_CONFIG_LENGTH_SHIFT 0
    #define PROC6_DMA_CONFIG_DIRECTION_MASK 0x00010000
    #define PROC6_DMA_CONFIG_DIRECTION_SHIFT 16
    #define PROC6_DMA_CONFIG_QUEUE_WR_EN_MASK 0x01000000
    #define PROC6_DMA_CONFIG_QUEUE_WR_EN_SHIFT 24
    #define PROC6_DMA_CONFIG_DMA_EN_MASK 0x02000000
    #define PROC6_DMA_CONFIG_DMA_EN_SHIFT 25
#define  PROC6_DMA_DCCM 0xB890
    #define PROC6_DMA_DCCM_START_ADR_MASK 0xFFFFFFFC
    #define PROC6_DMA_DCCM_START_ADR_SHIFT 2
#define  PROC6_DMA_FB 0xB894
    #define PROC6_DMA_FB_START_ADR_MASK 0x1FFFFFFC
    #define PROC6_DMA_FB_START_ADR_SHIFT 2
#define  PROC6_DMA_STATUS 0xB89C
    #define PROC6_DMA_STATUS_PENDING_NUM_MASK 0x0000000F
    #define PROC6_DMA_STATUS_PENDING_NUM_SHIFT 0
    #define PROC6_DMA_STATUS_QUEUE_FULL_MASK 0x00000010
    #define PROC6_DMA_STATUS_QUEUE_FULL_SHIFT 4
    #define PROC6_DMA_STATUS_QUEUE_EMPTY_MASK 0x00000020
    #define PROC6_DMA_STATUS_QUEUE_EMPTY_SHIFT 5
#define  PROC6_FB_TOP 0xB804
    #define PROC6_FB_TOP_BASE_MASK 0xFFFF0000
    #define PROC6_FB_TOP_BASE_SHIFT 16
#define  PROC6_FPB_DBG_DATA0 0xB9E0
    #define PROC6_FPB_DBG_DATA0_PCP_MASK 0xFFFFFFFF
    #define PROC6_FPB_DBG_DATA0_PCP_SHIFT 0
#define  PROC6_FPB_DBG_DATA1 0xB9E4
    #define PROC6_FPB_DBG_DATA1_PFG_MASK 0xFFFFFFFF
    #define PROC6_FPB_DBG_DATA1_PFG_SHIFT 0
#define  PROC6_FPB_DBG_DATA2 0xB9E8
    #define PROC6_FPB_DBG_DATA2_MRC_MASK 0xFFFFFFFF
    #define PROC6_FPB_DBG_DATA2_MRC_SHIFT 0
#define  PROC6_FPB_DBG_DATA3 0xB9EC
    #define PROC6_FPB_DBG_DATA3_RDM_MASK 0xFFFFFFFF
    #define PROC6_FPB_DBG_DATA3_RDM_SHIFT 0
#define  PROC6_FPB_DBG_DATA4 0xB9F0
    #define PROC6_FPB_DBG_DATA4_PCR_MASK 0xFFFFFFFF
    #define PROC6_FPB_DBG_DATA4_PCR_SHIFT 0
#define  PROC6_HOST_INT_MASK 0xB8E4
    #define PROC6_HOST_INT_MASK_INT_EN_OUTBOUND_CALL0_MASK 0x00000001
    #define PROC6_HOST_INT_MASK_INT_EN_OUTBOUND_CALL0_SHIFT 0
    #define PROC6_HOST_INT_MASK_INT_EN_OUTBOUND_CALL1_MASK 0x00000002
    #define PROC6_HOST_INT_MASK_INT_EN_OUTBOUND_CALL1_SHIFT 1
    #define PROC6_HOST_INT_MASK_INT_EN_OUTBOUND_DBG_MASK 0x00000004
    #define PROC6_HOST_INT_MASK_INT_EN_OUTBOUND_DBG_SHIFT 2
    #define INT_EN_PROC6_HANG_MASK 0x80000000
    #define INT_EN_PROC6_HANG_SHIFT 31
#define  PROC6_HOST_INT_STATUS 0xB8E0
    #define PROC6_HOST_INT_STATUS_OUTBOUND_CALL0_MASK 0x00000001
    #define PROC6_HOST_INT_STATUS_OUTBOUND_CALL0_SHIFT 0
    #define PROC6_HOST_INT_STATUS_OUTBOUND_CALL1_MASK 0x00000002
    #define PROC6_HOST_INT_STATUS_OUTBOUND_CALL1_SHIFT 1
    #define PROC6_HOST_INT_STATUS_OUTBOUND_DBG_MASK 0x00000004
    #define PROC6_HOST_INT_STATUS_OUTBOUND_DBG_SHIFT 2
    #define PROC6_HANG_MASK 0x80000000
    #define PROC6_HANG_SHIFT 31
#define  PROC6_INBOUND_CALL_0 0xB820
    #define PROC6_INBOUND_CALL_0_DATA_MASK 0xFFFFFFFF
    #define PROC6_INBOUND_CALL_0_DATA_SHIFT 0
#define  PROC6_INBOUND_CALL_1 0xB824
    #define PROC6_INBOUND_CALL_1_DATA_MASK 0xFFFFFFFF
    #define PROC6_INBOUND_CALL_1_DATA_SHIFT 0
#define  PROC6_IPC_CALL 0xB8F0
    #define PROC6_IPC_CALL_DATA_MASK 0xFFFFFFFF
    #define PROC6_IPC_CALL_DATA_SHIFT 0
#define  PROC6_MEM_ALIAS 0xB80C
    #define PROC6_MEM_ALIAS_MASK_MASK 0xC0000000
    #define PROC6_MEM_ALIAS_MASK_SHIFT 30
#define  PROC6_MERGED_READ_CTL 0xB818
    #define PROC6_MERGED_READ_CTL_NONIDC_EN_MASK 0x00000001
    #define PROC6_MERGED_READ_CTL_NONIDC_EN_SHIFT 0
#define  PROC6_MERGED_WRITE_CTL 0xB810
    #define PROC6_MERGED_WRITE_CTL_TIMER_MASK 0x000003FF
    #define PROC6_MERGED_WRITE_CTL_TIMER_SHIFT 0
#define  PROC6_MMREG_APER 0xB808
    #define PROC6_MMREG_APER_BASE_MASK 0x0000FFFF
    #define PROC6_MMREG_APER_BASE_SHIFT 0
    #define PROC6_MMREG_APER_SIZE_MASK 0xFFFF0000
    #define PROC6_MMREG_APER_SIZE_SHIFT 16
#define  PROC6_MSG_DATA_0 0xB830
    #define PROC6_MSG_DATA_0_DATA_MASK 0xFFFFFFFF
    #define PROC6_MSG_DATA_0_DATA_SHIFT 0
#define  PROC6_MSG_DATA_1 0xB834
    #define PROC6_MSG_DATA_1_DATA_MASK 0xFFFFFFFF
    #define PROC6_MSG_DATA_1_DATA_SHIFT 0
#define  PROC6_MSG_DATA_10 0xB858
    #define PROC6_MSG_DATA_10_DATA_MASK 0xFFFFFFFF
    #define PROC6_MSG_DATA_10_DATA_SHIFT 0
#define  PROC6_MSG_DATA_11 0xB85C
    #define PROC6_MSG_DATA_11_DATA_MASK 0xFFFFFFFF
    #define PROC6_MSG_DATA_11_DATA_SHIFT 0
#define  PROC6_MSG_DATA_2 0xB838
    #define PROC6_MSG_DATA_2_DATA_MASK 0xFFFFFFFF
    #define PROC6_MSG_DATA_2_DATA_SHIFT 0
#define  PROC6_MSG_DATA_3 0xB83C
    #define PROC6_MSG_DATA_3_DATA_MASK 0xFFFFFFFF
    #define PROC6_MSG_DATA_3_DATA_SHIFT 0
#define  PROC6_MSG_DATA_4 0xB840
    #define PROC6_MSG_DATA_4_DATA_MASK 0xFFFFFFFF
    #define PROC6_MSG_DATA_4_DATA_SHIFT 0
#define  PROC6_MSG_DATA_5 0xB844
    #define PROC6_MSG_DATA_5_DATA_MASK 0xFFFFFFFF
    #define PROC6_MSG_DATA_5_DATA_SHIFT 0
#define  PROC6_MSG_DATA_6 0xB848
    #define PROC6_MSG_DATA_6_DATA_MASK 0xFFFFFFFF
    #define PROC6_MSG_DATA_6_DATA_SHIFT 0
#define  PROC6_MSG_DATA_7 0xB84C
    #define PROC6_MSG_DATA_7_DATA_MASK 0xFFFFFFFF
    #define PROC6_MSG_DATA_7_DATA_SHIFT 0
#define  PROC6_MSG_DATA_8 0xB850
    #define PROC6_MSG_DATA_8_DATA_MASK 0xFFFFFFFF
    #define PROC6_MSG_DATA_8_DATA_SHIFT 0
#define  PROC6_MSG_DATA_9 0xB854
    #define PROC6_MSG_DATA_9_DATA_MASK 0xFFFFFFFF
    #define PROC6_MSG_DATA_9_DATA_SHIFT 0
#define  PROC6_OUTBOUND_CALL_0 0xB828
    #define PROC6_OUTBOUND_CALL_0_DATA_MASK 0xFFFFFFFF
    #define PROC6_OUTBOUND_CALL_0_DATA_SHIFT 0
#define  PROC6_OUTBOUND_CALL_1 0xB82C
    #define PROC6_OUTBOUND_CALL_1_DATA_MASK 0xFFFFFFFF
    #define PROC6_OUTBOUND_CALL_1_DATA_SHIFT 0
#define  PROC6_PFB_CFG 0xB9A0
    #define PROC6_PFB_CFG_PREFETCH_MODE_MASK 0x00000003
    #define PROC6_PFB_CFG_PREFETCH_MODE_SHIFT 0
    #define PROC6_PFB_CFG_MC_PFB_EN_MASK 0x00000010
    #define PROC6_PFB_CFG_MC_PFB_EN_SHIFT 4
    #define PROC6_PFB_CFG_SEQ_PFB_EN_MASK 0x00000020
    #define PROC6_PFB_CFG_SEQ_PFB_EN_SHIFT 5
    #define PROC6_PFB_CFG_MAX_PREF_LINE_NUM_MASK 0x00000700
    #define PROC6_PFB_CFG_MAX_PREF_LINE_NUM_SHIFT 8
    #define PROC6_PFB_CFG_BVCI_PLEN_CHK_EN_MASK 0x00010000
    #define PROC6_PFB_CFG_BVCI_PLEN_CHK_EN_SHIFT 16
#define  PROC6_PFB_CL_OFFSET 0xB9A4
    #define PROC6_PFB_CL_OFFSET_LINE1_OFFSET_MASK 0x000000FF
    #define PROC6_PFB_CL_OFFSET_LINE1_OFFSET_SHIFT 0
    #define PROC6_PFB_CL_OFFSET_LINE2_OFFSET_MASK 0x0000FF00
    #define PROC6_PFB_CL_OFFSET_LINE2_OFFSET_SHIFT 8
    #define PROC6_PFB_CL_OFFSET_LINE3_OFFSET_MASK 0x00FF0000
    #define PROC6_PFB_CL_OFFSET_LINE3_OFFSET_SHIFT 16
    #define PROC6_PFB_CL_OFFSET_LINE4_OFFSET_MASK 0xFF000000
    #define PROC6_PFB_CL_OFFSET_LINE4_OFFSET_SHIFT 24
#define  PROC6_PFB_DBG_SEL 0xB9DC
    #define PROC6_PFB_DBG_SEL_PCP_SEL_MASK 0x0000000F
    #define PROC6_PFB_DBG_SEL_PCP_SEL_SHIFT 0
    #define PROC6_PFB_DBG_SEL_PFG_SEL_MASK 0x000000F0
    #define PROC6_PFB_DBG_SEL_PFG_SEL_SHIFT 4
    #define PROC6_PFB_DBG_SEL_MRC_SEL_MASK 0x00000F00
    #define PROC6_PFB_DBG_SEL_MRC_SEL_SHIFT 8
    #define PROC6_PFB_DBG_SEL_RDM_SEL_MASK 0x0000F000
    #define PROC6_PFB_DBG_SEL_RDM_SEL_SHIFT 12
    #define PROC6_PFB_DBG_SEL_PCR_SEL_MASK 0x000F0000
    #define PROC6_PFB_DBG_SEL_PCR_SEL_SHIFT 16
#define  PROC6_PFB_FLOW_CTL 0xB9A8
    #define PROC6_PFB_FLOW_CTL_FEQ_LOW_WATERMARK_MASK 0x000000FF
    #define PROC6_PFB_FLOW_CTL_FEQ_LOW_WATERMARK_SHIFT 0
    #define PROC6_PFB_FLOW_CTL_FCLQ_HIGH_WATERMARK_MASK 0x00000F00
    #define PROC6_PFB_FLOW_CTL_FCLQ_HIGH_WATERMARK_SHIFT 8
    #define PROC6_PFB_FLOW_CTL_CPRQ_HIGH_WATERMARK_MASK 0x000F0000
    #define PROC6_PFB_FLOW_CTL_CPRQ_HIGH_WATERMARK_SHIFT 16
#define  PROC6_PFB_INVALID_ALL 0xB9B0
    #define PROC6_PFB_INVALID_ALL_DATA_MASK 0xFFFFFFFF
    #define PROC6_PFB_INVALID_ALL_DATA_SHIFT 0
#define  PROC6_PFB_STAT1 0xB9BC
    #define PROC6_PFB_STAT1_CORE_CRD_NUM_MASK 0xFFFFFFFF
    #define PROC6_PFB_STAT1_CORE_CRD_NUM_SHIFT 0
#define  PROC6_PFB_STAT2 0xB9C0
    #define PROC6_PFB_STAT2_CORE_CRD_HIT_NUM_MASK 0xFFFFFFFF
    #define PROC6_PFB_STAT2_CORE_CRD_HIT_NUM_SHIFT 0
#define  PROC6_PFB_STAT3 0xB9C4
    #define PROC6_PFB_STAT3_PREF_CRD_NUM_MASK 0xFFFFFFFF
    #define PROC6_PFB_STAT3_PREF_CRD_NUM_SHIFT 0
#define  PROC6_PFB_STAT4 0xB9C8
    #define PROC6_PFB_STAT4_CORE_CRD_HIT_DATNRDY_NUM_MASK 0xFFFFFFFF
    #define PROC6_PFB_STAT4_CORE_CRD_HIT_DATNRDY_NUM_SHIFT 0
#define  PROC6_PFB_STATUS 0xB9B8
    #define PROC6_PFB_STATUS_ERROR_MASK 0x0000001F
    #define PROC6_PFB_STATUS_ERROR_SHIFT 0
    #define PROC6_PFB_STATUS_ERR_CMD_MASK 0x00000F00
    #define PROC6_PFB_STATUS_ERR_CMD_SHIFT 8
#define  PROC6_PFB_TBS_IN 0xB9D0
    #define PROC6_PFB_TBS_IN_COMMAND_MASK 0x0000000F
    #define PROC6_PFB_TBS_IN_COMMAND_SHIFT 0
    #define PROC6_PFB_TBS_IN_WAY_PT_MASK 0x00001F00
    #define PROC6_PFB_TBS_IN_WAY_PT_SHIFT 8
    #define PROC6_PFB_TBS_IN_LAST_MASK 0x001F0000
    #define PROC6_PFB_TBS_IN_LAST_SHIFT 16
    #define PROC6_PFB_TBS_IN_NEXT_MASK 0x1F000000
    #define PROC6_PFB_TBS_IN_NEXT_SHIFT 24
    #define PROC6_PFB_TBS_IN_UNLOAD_PD_MASK 0x20000000
    #define PROC6_PFB_TBS_IN_UNLOAD_PD_SHIFT 29
    #define PROC6_PFB_TBS_IN_LOAD_PD_MASK 0x40000000
    #define PROC6_PFB_TBS_IN_LOAD_PD_SHIFT 30
    #define PROC6_PFB_TBS_IN_VALID_MASK 0x80000000
    #define PROC6_PFB_TBS_IN_VALID_SHIFT 31
#define  PROC6_PFB_TBS_IN2 0xB9D4
    #define PROC6_PFB_TBS_IN2_ADDR_MASK 0xFFFFFFE0
    #define PROC6_PFB_TBS_IN2_ADDR_SHIFT 5
#define  PROC6_PFB_TBS_OUT 0xB9D8
    #define PROC6_PFB_TBS_OUT_TBS_RDY_MASK 0x00000001
    #define PROC6_PFB_TBS_OUT_TBS_RDY_SHIFT 0
    #define PROC6_PFB_TBS_OUT_ADDR_HIT_MASK 0x00000010
    #define PROC6_PFB_TBS_OUT_ADDR_HIT_SHIFT 4
    #define PROC6_PFB_TBS_OUT_WAY_PT_MASK 0x00001F00
    #define PROC6_PFB_TBS_OUT_WAY_PT_SHIFT 8
    #define PROC6_PFB_TBS_OUT_LAST_MASK 0x001F0000
    #define PROC6_PFB_TBS_OUT_LAST_SHIFT 16
    #define PROC6_PFB_TBS_OUT_NEXT_MASK 0x1F000000
    #define PROC6_PFB_TBS_OUT_NEXT_SHIFT 24
    #define PROC6_PFB_TBS_OUT_UNLOAD_PD_MASK 0x20000000
    #define PROC6_PFB_TBS_OUT_UNLOAD_PD_SHIFT 29
    #define PROC6_PFB_TBS_OUT_LOAD_PD_MASK 0x40000000
    #define PROC6_PFB_TBS_OUT_LOAD_PD_SHIFT 30
    #define PROC6_PFB_TBS_OUT_VALID_MASK 0x80000000
    #define PROC6_PFB_TBS_OUT_VALID_SHIFT 31
#define  PROC6_PROC6_INT_MASK 0xB8EC
    #define PROC6_PROC6_INT_MASK_INT_EN_INBOUND_CALL0_MASK 0x00000001
    #define PROC6_PROC6_INT_MASK_INT_EN_INBOUND_CALL0_SHIFT 0
    #define PROC6_PROC6_INT_MASK_INT_EN_INBOUND_CALL1_MASK 0x00000002
    #define PROC6_PROC6_INT_MASK_INT_EN_INBOUND_CALL1_SHIFT 1
    #define PROC6_PROC6_INT_MASK_INT_EN_IPC_CALL_MASK 0x00000008
    #define PROC6_PROC6_INT_MASK_INT_EN_IPC_CALL_SHIFT 3
    #define PROC6_PROC6_INT_MASK_INT_EN_DMA_COMPLETE_MASK 0x00000010
    #define PROC6_PROC6_INT_MASK_INT_EN_DMA_COMPLETE_SHIFT 4
    #define PROC6_PROC6_INT_MASK_INT_EN_DBG_INBOUND0_MASK 0x00000020
    #define PROC6_PROC6_INT_MASK_INT_EN_DBG_INBOUND0_SHIFT 5
    #define PROC6_PROC6_INT_MASK_INT_EN_DBG_INBOUND1_MASK 0x00000040
    #define PROC6_PROC6_INT_MASK_INT_EN_DBG_INBOUND1_SHIFT 6
    #define PROC6_PROC6_INT_MASK_INT_EN_DBG_INBOUND2_MASK 0x00000080
    #define PROC6_PROC6_INT_MASK_INT_EN_DBG_INBOUND2_SHIFT 7
    #define PROC6_PROC6_INT_MASK_INT_EN_DBG_INBOUND3_MASK 0x00000100
    #define PROC6_PROC6_INT_MASK_INT_EN_DBG_INBOUND3_SHIFT 8
    #define PROC6_PROC6_INT_MASK_INT_EN_DBG_INBOUND4_MASK 0x00000200
    #define PROC6_PROC6_INT_MASK_INT_EN_DBG_INBOUND4_SHIFT 9
    #define PROC6_PROC6_INT_MASK_INT_EN_DBG_INBOUND5_MASK 0x00000400
    #define PROC6_PROC6_INT_MASK_INT_EN_DBG_INBOUND5_SHIFT 10
    #define PROC6_PROC6_INT_MASK_INT_EN_DBG_INBOUND6_MASK 0x00000800
    #define PROC6_PROC6_INT_MASK_INT_EN_DBG_INBOUND6_SHIFT 11
#define  PROC6_PROC6_INT_STATUS 0xB8E8
    #define PROC6_PROC6_INT_STATUS_INBOUND_CALL0_MASK 0x00000001
    #define PROC6_PROC6_INT_STATUS_INBOUND_CALL0_SHIFT 0
    #define PROC6_PROC6_INT_STATUS_INBOUND_CALL1_MASK 0x00000002
    #define PROC6_PROC6_INT_STATUS_INBOUND_CALL1_SHIFT 1
    #define PROC6_PROC6_INT_STATUS_IPC_CALL_MASK 0x00000008
    #define PROC6_PROC6_INT_STATUS_IPC_CALL_SHIFT 3
    #define PROC6_PROC6_INT_STATUS_DMA_COMPLETE_MASK 0x00000010
    #define PROC6_PROC6_INT_STATUS_DMA_COMPLETE_SHIFT 4
    #define PROC6_PROC6_INT_STATUS_DBG_INBOUND0_MASK 0x00000020
    #define PROC6_PROC6_INT_STATUS_DBG_INBOUND0_SHIFT 5
    #define PROC6_PROC6_INT_STATUS_DBG_INBOUND1_MASK 0x00000040
    #define PROC6_PROC6_INT_STATUS_DBG_INBOUND1_SHIFT 6
    #define PROC6_PROC6_INT_STATUS_DBG_INBOUND2_MASK 0x00000080
    #define PROC6_PROC6_INT_STATUS_DBG_INBOUND2_SHIFT 7
    #define PROC6_PROC6_INT_STATUS_DBG_INBOUND3_MASK 0x00000100
    #define PROC6_PROC6_INT_STATUS_DBG_INBOUND3_SHIFT 8
    #define PROC6_PROC6_INT_STATUS_DBG_INBOUND4_MASK 0x00000200
    #define PROC6_PROC6_INT_STATUS_DBG_INBOUND4_SHIFT 9
    #define PROC6_PROC6_INT_STATUS_DBG_INBOUND5_MASK 0x00000400
    #define PROC6_PROC6_INT_STATUS_DBG_INBOUND5_SHIFT 10
    #define PROC6_PROC6_INT_STATUS_DBG_INBOUND6_MASK 0x00000800
    #define PROC6_PROC6_INT_STATUS_DBG_INBOUND6_SHIFT 11
#define  PROC6_RST 0xB814
    #define PROC6_RST_SOFT_RSTN_MASK 0x00000001
    #define PROC6_RST_SOFT_RSTN_SHIFT 0
#define  PROC6_SEQMC_MAP 0xB800
    #define PROC6_SEQMC_MAP_CHANNELBIT_MASK 0x0000001F
    #define PROC6_SEQMC_MAP_CHANNELBIT_SHIFT 0
    #define PROC6_SEQMC_MAP_CH0_IS_SEQ_MASK 0x00000100
    #define PROC6_SEQMC_MAP_CH0_IS_SEQ_SHIFT 8
#define  PROC6_WATCHDOG_CNT 0xB880
    #define PROC6_WATCHDOG_CNT_DATA_MASK 0xFFFFFFFF
    #define PROC6_WATCHDOG_CNT_DATA_SHIFT 0
#define  PROC6_WATCHDOG_COMPARE 0xB884
    #define PROC6_WATCHDOG_COMPARE_DATA_MASK 0xFFFFFFFF
    #define PROC6_WATCHDOG_COMPARE_DATA_SHIFT 0
#define  PROC_DBG_INBOUND0 0xA060
    #define PROC_DBG_INBOUND0_DATA_MASK 0xFFFFFFFF
    #define PROC_DBG_INBOUND0_DATA_SHIFT 0
#define  PROC_DBG_INBOUND1 0xA0A0
    #define PROC_DBG_INBOUND1_DATA_MASK 0xFFFFFFFF
    #define PROC_DBG_INBOUND1_DATA_SHIFT 0
#define  PROC_DBG_INBOUND2 0xA0A4
    #define PROC_DBG_INBOUND2_DATA_MASK 0xFFFFFFFF
    #define PROC_DBG_INBOUND2_DATA_SHIFT 0
#define  PROC_DBG_INBOUND3 0xA0A8
    #define PROC_DBG_INBOUND3_DATA_MASK 0xFFFFFFFF
    #define PROC_DBG_INBOUND3_DATA_SHIFT 0
#define  PROC_DBG_INBOUND4 0xA0AC
    #define PROC_DBG_INBOUND4_DATA_MASK 0xFFFFFFFF
    #define PROC_DBG_INBOUND4_DATA_SHIFT 0
#define  PROC_DBG_INBOUND5 0xA0D0
    #define PROC_DBG_INBOUND5_DATA_MASK 0xFFFFFFFF
    #define PROC_DBG_INBOUND5_DATA_SHIFT 0
#define  PROC_DBG_INBOUND6 0xA0D4
    #define PROC_DBG_INBOUND6_DATA_MASK 0xFFFFFFFF
    #define PROC_DBG_INBOUND6_DATA_SHIFT 0
#define  PROC_DBG_OUTBOUND 0xA064
    #define PROC_DBG_OUTBOUND_DATA_MASK 0xFFFFFFFF
    #define PROC_DBG_OUTBOUND_DATA_SHIFT 0
#define  PROC_DEBUG_REG1 0xA070
    #define PROC_DEBUG_REG1_DATA_MASK 0xFFFFFFFF
    #define PROC_DEBUG_REG1_DATA_SHIFT 0
#define  PROC_DEBUG_REG2 0xA074
    #define PROC_DEBUG_REG2_DATA_MASK 0xFFFFFFFF
    #define PROC_DEBUG_REG2_DATA_SHIFT 0
#define  PROC_DEBUG_REG3 0xA078
    #define PROC_DEBUG_REG3_DATA_MASK 0xFFFFFFFF
    #define PROC_DEBUG_REG3_DATA_SHIFT 0
#define  PROC_DEBUG_REG4 0xA07C
    #define PROC_DEBUG_REG4_DATA_MASK 0xFFFFFFFF
    #define PROC_DEBUG_REG4_DATA_SHIFT 0
#define  PROC_DEBUG_REG5 0xA088
    #define PROC_DEBUG_REG5_DATA_MASK 0xFFFFFFFF
    #define PROC_DEBUG_REG5_DATA_SHIFT 0
#define  PROC_DEBUG_REG6 0xA08C
    #define PROC_DEBUG_REG6_DATA_MASK 0xFFFFFFFF
    #define PROC_DEBUG_REG6_DATA_SHIFT 0
#define  PROC_DMA_CONFIG 0xA198
    #define PROC_DMA_CONFIG_LENGTH_MASK 0x000007FF
    #define PROC_DMA_CONFIG_LENGTH_SHIFT 0
    #define PROC_DMA_CONFIG_DIRECTION_MASK 0x00010000
    #define PROC_DMA_CONFIG_DIRECTION_SHIFT 16
    #define PROC_DMA_CONFIG_QUEUE_WR_EN_MASK 0x01000000
    #define PROC_DMA_CONFIG_QUEUE_WR_EN_SHIFT 24
    #define PROC_DMA_CONFIG_DMA_EN_MASK 0x02000000
    #define PROC_DMA_CONFIG_DMA_EN_SHIFT 25
#define  PROC_DMA_DCCM 0xA190
    #define PROC_DMA_DCCM_START_ADR_MASK 0xFFFFFFFC
    #define PROC_DMA_DCCM_START_ADR_SHIFT 2
#define  PROC_DMA_FB 0xA194
    #define PROC_DMA_FB_START_ADR_MASK 0x1FFFFFFC
    #define PROC_DMA_FB_START_ADR_SHIFT 2
#define  PROC_DMA_STATUS 0xA19C
    #define PROC_DMA_STATUS_PENDING_NUM_MASK 0x0000000F
    #define PROC_DMA_STATUS_PENDING_NUM_SHIFT 0
    #define PROC_DMA_STATUS_QUEUE_FULL_MASK 0x00000010
    #define PROC_DMA_STATUS_QUEUE_FULL_SHIFT 4
    #define PROC_DMA_STATUS_QUEUE_EMPTY_MASK 0x00000020
    #define PROC_DMA_STATUS_QUEUE_EMPTY_SHIFT 5
#define  PROC_DUMMY_REG 0xA0FC
    #define PROC_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define PROC_DUMMY_REG_DATA_SHIFT 0
#define  PROC_FB_TOP 0xA004
    #define PROC_FB_TOP_BASE_MASK 0xFFFF0000
    #define PROC_FB_TOP_BASE_SHIFT 16
#define  PROC_HOST_INT_MASK 0xA0E4
    #define PROC_HOST_INT_MASK_INT_EN_OUTBOUND_CALL0_MASK 0x00000001
    #define PROC_HOST_INT_MASK_INT_EN_OUTBOUND_CALL0_SHIFT 0
    #define PROC_HOST_INT_MASK_INT_EN_OUTBOUND_CALL1_MASK 0x00000002
    #define PROC_HOST_INT_MASK_INT_EN_OUTBOUND_CALL1_SHIFT 1
    #define PROC_HOST_INT_MASK_INT_EN_OUTBOUND_DBG_MASK 0x00000004
    #define PROC_HOST_INT_MASK_INT_EN_OUTBOUND_DBG_SHIFT 2
    #define PROC_HOST_INT_MASK_INT_EN_PROC_HANG_MASK 0x80000000
    #define PROC_HOST_INT_MASK_INT_EN_PROC_HANG_SHIFT 31
#define  PROC_HOST_INT_STATUS 0xA0E0
    #define PROC_HOST_INT_STATUS_OUTBOUND_CALL0_MASK 0x00000001
    #define PROC_HOST_INT_STATUS_OUTBOUND_CALL0_SHIFT 0
    #define PROC_HOST_INT_STATUS_OUTBOUND_CALL1_MASK 0x00000002
    #define PROC_HOST_INT_STATUS_OUTBOUND_CALL1_SHIFT 1
    #define PROC_HOST_INT_STATUS_OUTBOUND_DBG_MASK 0x00000004
    #define PROC_HOST_INT_STATUS_OUTBOUND_DBG_SHIFT 2
    #define PROC_HOST_INT_STATUS_PROC_HANG_MASK 0x80000000
    #define PROC_HOST_INT_STATUS_PROC_HANG_SHIFT 31
#define  PROC_INBOUND_CALL_0 0xA020
    #define PROC_INBOUND_CALL_0_DATA_MASK 0xFFFFFFFF
    #define PROC_INBOUND_CALL_0_DATA_SHIFT 0
#define  PROC_INBOUND_CALL_1 0xA024
    #define PROC_INBOUND_CALL_1_DATA_MASK 0xFFFFFFFF
    #define PROC_INBOUND_CALL_1_DATA_SHIFT 0
#define  PROC_IPC_CALL 0xA0F0
    #define PROC_IPC_CALL_DATA_MASK 0xFFFFFFFF
    #define PROC_IPC_CALL_DATA_SHIFT 0
#define  PROC_MBD_EMPTY 0xA0F4
    #define PROC_MBD_EMPTY_EMPTY_MASK 0x00000001
    #define PROC_MBD_EMPTY_EMPTY_SHIFT 0
#define  PROC_MC_ARB 0xA018
    #define PROC_MC_ARB_ARC_REQ_CNT_LIMIT_MASK 0x0000000F
    #define PROC_MC_ARB_ARC_REQ_CNT_LIMIT_SHIFT 0
    #define PROC_MC_ARB_IBB_REQ_CNT_LIMIT_MASK 0x000000F0
    #define PROC_MC_ARB_IBB_REQ_CNT_LIMIT_SHIFT 4
    #define PROC_MC_ARB_MBD_REQ_CNT_LIMIT_MASK 0x00000F00
    #define PROC_MC_ARB_MBD_REQ_CNT_LIMIT_SHIFT 8
    #define PROC_MC_ARB_DMA_REQ_CNT_LIMIT_MASK 0x0000F000
    #define PROC_MC_ARB_DMA_REQ_CNT_LIMIT_SHIFT 12
#define  PROC_MEM_ALIAS 0xA00C
    #define PROC_MEM_ALIAS_MASK_MASK 0xC0000000
    #define PROC_MEM_ALIAS_MASK_SHIFT 30
#define  PROC_MERGED_WRITE_CTL 0xA010
    #define PROC_MERGED_WRITE_CTL_TIMER_MASK 0x000003FF
    #define PROC_MERGED_WRITE_CTL_TIMER_SHIFT 0
#define  PROC_MMREG_APER 0xA008
    #define PROC_MMREG_APER_BASE_MASK 0x0000FFFF
    #define PROC_MMREG_APER_BASE_SHIFT 0
    #define PROC_MMREG_APER_SIZE_MASK 0xFFFF0000
    #define PROC_MMREG_APER_SIZE_SHIFT 16
#define  PROC_MSG_DATA_0 0xA030
    #define PROC_MSG_DATA_0_DATA_MASK 0xFFFFFFFF
    #define PROC_MSG_DATA_0_DATA_SHIFT 0
#define  PROC_MSG_DATA_1 0xA034
    #define PROC_MSG_DATA_1_DATA_MASK 0xFFFFFFFF
    #define PROC_MSG_DATA_1_DATA_SHIFT 0
#define  PROC_MSG_DATA_10 0xA058
    #define PROC_MSG_DATA_10_DATA_MASK 0xFFFFFFFF
    #define PROC_MSG_DATA_10_DATA_SHIFT 0
#define  PROC_MSG_DATA_11 0xA05C
    #define PROC_MSG_DATA_11_DATA_MASK 0xFFFFFFFF
    #define PROC_MSG_DATA_11_DATA_SHIFT 0
#define  PROC_MSG_DATA_2 0xA038
    #define PROC_MSG_DATA_2_DATA_MASK 0xFFFFFFFF
    #define PROC_MSG_DATA_2_DATA_SHIFT 0
#define  PROC_MSG_DATA_3 0xA03C
    #define PROC_MSG_DATA_3_DATA_MASK 0xFFFFFFFF
    #define PROC_MSG_DATA_3_DATA_SHIFT 0
#define  PROC_MSG_DATA_4 0xA040
    #define PROC_MSG_DATA_4_DATA_MASK 0xFFFFFFFF
    #define PROC_MSG_DATA_4_DATA_SHIFT 0
#define  PROC_MSG_DATA_5 0xA044
    #define PROC_MSG_DATA_5_DATA_MASK 0xFFFFFFFF
    #define PROC_MSG_DATA_5_DATA_SHIFT 0
#define  PROC_MSG_DATA_6 0xA048
    #define PROC_MSG_DATA_6_DATA_MASK 0xFFFFFFFF
    #define PROC_MSG_DATA_6_DATA_SHIFT 0
#define  PROC_MSG_DATA_7 0xA04C
    #define PROC_MSG_DATA_7_DATA_MASK 0xFFFFFFFF
    #define PROC_MSG_DATA_7_DATA_SHIFT 0
#define  PROC_MSG_DATA_8 0xA050
    #define PROC_MSG_DATA_8_DATA_MASK 0xFFFFFFFF
    #define PROC_MSG_DATA_8_DATA_SHIFT 0
#define  PROC_MSG_DATA_9 0xA054
    #define PROC_MSG_DATA_9_DATA_MASK 0xFFFFFFFF
    #define PROC_MSG_DATA_9_DATA_SHIFT 0
#define  PROC_OUTBOUND_CALL_0 0xA028
    #define PROC_OUTBOUND_CALL_0_DATA_MASK 0xFFFFFFFF
    #define PROC_OUTBOUND_CALL_0_DATA_SHIFT 0
#define  PROC_OUTBOUND_CALL_1 0xA02C
    #define PROC_OUTBOUND_CALL_1_DATA_MASK 0xFFFFFFFF
    #define PROC_OUTBOUND_CALL_1_DATA_SHIFT 0
#define  PROC_PROC_INT_MASK 0xA0EC
    #define PROC_PROC_INT_MASK_INT_EN_INBOUND_CALL0_MASK 0x00000001
    #define PROC_PROC_INT_MASK_INT_EN_INBOUND_CALL0_SHIFT 0
    #define PROC_PROC_INT_MASK_INT_EN_INBOUND_CALL1_MASK 0x00000002
    #define PROC_PROC_INT_MASK_INT_EN_INBOUND_CALL1_SHIFT 1
    #define PROC_PROC_INT_MASK_INT_EN_IPC_CALL_MASK 0x00000008
    #define PROC_PROC_INT_MASK_INT_EN_IPC_CALL_SHIFT 3
    #define PROC_PROC_INT_MASK_INT_EN_DMA_COMPLETE_MASK 0x00000010
    #define PROC_PROC_INT_MASK_INT_EN_DMA_COMPLETE_SHIFT 4
    #define PROC_PROC_INT_MASK_INT_EN_DBG_INBOUND0_MASK 0x00000020
    #define PROC_PROC_INT_MASK_INT_EN_DBG_INBOUND0_SHIFT 5
    #define PROC_PROC_INT_MASK_INT_EN_DBG_INBOUND1_MASK 0x00000040
    #define PROC_PROC_INT_MASK_INT_EN_DBG_INBOUND1_SHIFT 6
    #define PROC_PROC_INT_MASK_INT_EN_DBG_INBOUND2_MASK 0x00000080
    #define PROC_PROC_INT_MASK_INT_EN_DBG_INBOUND2_SHIFT 7
    #define PROC_PROC_INT_MASK_INT_EN_DBG_INBOUND3_MASK 0x00000100
    #define PROC_PROC_INT_MASK_INT_EN_DBG_INBOUND3_SHIFT 8
    #define PROC_PROC_INT_MASK_INT_EN_DBG_INBOUND4_MASK 0x00000200
    #define PROC_PROC_INT_MASK_INT_EN_DBG_INBOUND4_SHIFT 9
    #define PROC_PROC_INT_MASK_INT_EN_DBG_INBOUND5_MASK 0x00000400
    #define PROC_PROC_INT_MASK_INT_EN_DBG_INBOUND5_SHIFT 10
    #define PROC_PROC_INT_MASK_INT_EN_DBG_INBOUND6_MASK 0x00000800
    #define PROC_PROC_INT_MASK_INT_EN_DBG_INBOUND6_SHIFT 11
#define  PROC_PROC_INT_STATUS 0xA0E8
    #define PROC_PROC_INT_STATUS_INBOUND_CALL0_MASK 0x00000001
    #define PROC_PROC_INT_STATUS_INBOUND_CALL0_SHIFT 0
    #define PROC_PROC_INT_STATUS_INBOUND_CALL1_MASK 0x00000002
    #define PROC_PROC_INT_STATUS_INBOUND_CALL1_SHIFT 1
    #define PROC_PROC_INT_STATUS_IPC_CALL_MASK 0x00000008
    #define PROC_PROC_INT_STATUS_IPC_CALL_SHIFT 3
    #define PROC_PROC_INT_STATUS_DMA_COMPLETE_MASK 0x00000010
    #define PROC_PROC_INT_STATUS_DMA_COMPLETE_SHIFT 4
    #define PROC_PROC_INT_STATUS_DBG_INBOUND0_MASK 0x00000020
    #define PROC_PROC_INT_STATUS_DBG_INBOUND0_SHIFT 5
    #define PROC_PROC_INT_STATUS_DBG_INBOUND1_MASK 0x00000040
    #define PROC_PROC_INT_STATUS_DBG_INBOUND1_SHIFT 6
    #define PROC_PROC_INT_STATUS_DBG_INBOUND2_MASK 0x00000080
    #define PROC_PROC_INT_STATUS_DBG_INBOUND2_SHIFT 7
    #define PROC_PROC_INT_STATUS_DBG_INBOUND3_MASK 0x00000100
    #define PROC_PROC_INT_STATUS_DBG_INBOUND3_SHIFT 8
    #define PROC_PROC_INT_STATUS_DBG_INBOUND4_MASK 0x00000200
    #define PROC_PROC_INT_STATUS_DBG_INBOUND4_SHIFT 9
    #define PROC_PROC_INT_STATUS_DBG_INBOUND5_MASK 0x00000400
    #define PROC_PROC_INT_STATUS_DBG_INBOUND5_SHIFT 10
    #define PROC_PROC_INT_STATUS_DBG_INBOUND6_MASK 0x00000800
    #define PROC_PROC_INT_STATUS_DBG_INBOUND6_SHIFT 11
#define  PROC_RST 0xA014
    #define PROC_RST_SOFT_RSTN_MASK 0x00000001
    #define PROC_RST_SOFT_RSTN_SHIFT 0
    #define PROC_RST_MBD_RSTN_MASK 0x00000004
    #define PROC_RST_MBD_RSTN_SHIFT 2
    #define PROC_RST_MBD_FLUSH_MASK 0x80000000
    #define PROC_RST_MBD_FLUSH_SHIFT 31
#define  PROC_SHADOW_IBB_CTRL 0xA0B0
    #define PROC_SHADOW_IBB_CTRL_SHADOW_IBB_CTRL_MASK 0xFFFFFFFF
    #define PROC_SHADOW_IBB_CTRL_SHADOW_IBB_CTRL_SHIFT 0
#define  PROC_SHADOW_IBB_RB_ADR 0xA0B8
    #define PROC_SHADOW_IBB_RB_ADR_SHADOW_IBB_RB_ADR_MASK 0xFFFFFFFF
    #define PROC_SHADOW_IBB_RB_ADR_SHADOW_IBB_RB_ADR_SHIFT 0
#define  PROC_SHADOW_IBB_RB_HEAD 0xA0C8
    #define PROC_SHADOW_IBB_RB_HEAD_SHADOW_IBB_RB_HEAD_MASK 0xFFFFFFFF
    #define PROC_SHADOW_IBB_RB_HEAD_SHADOW_IBB_RB_HEAD_SHIFT 0
#define  PROC_SHADOW_IBB_RB_TAIL 0xA0BC
    #define PROC_SHADOW_IBB_RB_TAIL_SHADOW_IBB_RB_TAIL_MASK 0xFFFFFFFF
    #define PROC_SHADOW_IBB_RB_TAIL_SHADOW_IBB_RB_TAIL_SHIFT 0
#define  PROC_SHADOW_IBB_RB_TAIL_READ 0xA0C0
    #define PROC_SHADOW_IBB_RB_TAIL_READ_SHADOW_IBB_RB_TAIL_READ_MASK 0xFFFFFFFF
    #define PROC_SHADOW_IBB_RB_TAIL_READ_SHADOW_IBB_RB_TAIL_READ_SHIFT 0
#define  PROC_SHADOW_IBB_STATUS 0xA0B4
    #define PROC_SHADOW_IBB_STATUS_SHADOW_IBB_STATUS_MASK 0xFFFFFFFF
    #define PROC_SHADOW_IBB_STATUS_SHADOW_IBB_STATUS_SHIFT 0
#define  PROC_WATCHDOG_CNT 0xA080
    #define PROC_WATCHDOG_CNT_DATA_MASK 0xFFFFFFFF
    #define PROC_WATCHDOG_CNT_DATA_SHIFT 0
#define  PROC_WATCHDOG_COMPARE 0xA084
    #define PROC_WATCHDOG_COMPARE_DATA_MASK 0xFFFFFFFF
    #define PROC_WATCHDOG_COMPARE_DATA_SHIFT 0
#define  RBM_BIST_CTRL 0x04F0
    #define BIST_MODE_MASK 0x0000003F
    #define BIST_MODE_SHIFT 0
    #define BIST_WDAT_MASK 0x00000100
    #define BIST_WDAT_SHIFT 8
    #define BIST_RDAT_MASK 0x00000200
    #define BIST_RDAT_SHIFT 9
    #define REPR_WDAT_MASK 0x00000400
    #define REPR_WDAT_SHIFT 10
    #define REPR_RDAT_MASK 0x00000800
    #define REPR_RDAT_SHIFT 11
    #define BIST_LOAD_EN_MASK 0x00001000
    #define BIST_LOAD_EN_SHIFT 12
    #define BIST_SHIFT_CLK_SEL_MASK 0x00002000
    #define BIST_SHIFT_CLK_SEL_SHIFT 13
    #define BIST_LPBK_EN_MASK 0x00004000
    #define BIST_LPBK_EN_SHIFT 14
    #define BIST_SHIFT_CLK_MASK 0x00008000
    #define BIST_SHIFT_CLK_SHIFT 15
    #define BIST_TCLK_SEL_MASK 0x00010000
    #define BIST_TCLK_SEL_SHIFT 16
#define  RBM_BOARD_ID 0x0478
    #define BOARD_ID_MASK 0x000000FF
    #define BOARD_ID_SHIFT 0
    #define TECH_ID_MASK 0x0000FF00
    #define TECH_ID_SHIFT 8
    #define REV_ID_MASK 0x00FF0000
    #define REV_ID_SHIFT 16
    #define STRAP_EXTBOOT_MASK 0x01000000
    #define STRAP_EXTBOOT_SHIFT 24
    #define STRAP_NVBOOT_MASK 0x02000000
    #define STRAP_NVBOOT_SHIFT 25
    #define STRAP_BOOTROM_MASK 0x04000000
    #define STRAP_BOOTROM_SHIFT 26
    #define STRAP_SECURE_MODE_MASK 0x08000000
    #define STRAP_SECURE_MODE_SHIFT 27
#define  RBM_DMA_STICKY_BITS_HI_HI 0x04EC
    #define RBM_DMA_STICKY_BITS_HI_HI_MASK 0xFFFFFFFF
    #define RBM_DMA_STICKY_BITS_HI_HI_SHIFT 0
#define  RBM_DMA_STICKY_BITS_HI_LO 0x04E8
    #define RBM_DMA_STICKY_BITS_HI_LO_MASK 0xFFFFFFFF
    #define RBM_DMA_STICKY_BITS_HI_LO_SHIFT 0
#define  RBM_DMA_STICKY_BITS_LO_HI 0x04E4
    #define RBM_DMA_STICKY_BITS_LO_HI_MASK 0xFFFFFFFF
    #define RBM_DMA_STICKY_BITS_LO_HI_SHIFT 0
#define  RBM_DMA_STICKY_BITS_LO_LO 0x04E0
    #define RBM_DMA_STICKY_BITS_LO_LO_MASK 0xFFFFFFFF
    #define RBM_DMA_STICKY_BITS_LO_LO_SHIFT 0
#define  RBM_DUMMY_REG 0x047C
    #define RBM_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define RBM_DUMMY_REG_DATA_SHIFT 0
#define  RBM_FE_FILTER_HI 0x0490
    #define RBM_FE_FILTER_HI_FILTER_MASK 0xFFFFFFFF
    #define RBM_FE_FILTER_HI_FILTER_SHIFT 0
#define  RBM_FE_FILTER_LO 0x048C
    #define RBM_FE_FILTER_LO_FILTER_MASK 0xFFFFFFFF
    #define RBM_FE_FILTER_LO_FILTER_SHIFT 0
#define  RBM_FILTER_STICKY 0x04A0
    #define FILTER_STICKY_MASK 0x0000007F
    #define FILTER_STICKY_SHIFT 0
#define  RBM_HOST_INT_MASK 0x0408
    #define RBM_HOST_INT_MASK_CLI_TIMEOUT_MASK 0x0000007F
    #define RBM_HOST_INT_MASK_CLI_TIMEOUT_SHIFT 0
    #define RBM_HOST_INT_MASK_WDT_TIMER_MASK 0x00030000
    #define RBM_HOST_INT_MASK_WDT_TIMER_SHIFT 16
    #define RBM_HOST_INT_MASK_WDT_RESET_MASK 0x80000000
    #define RBM_HOST_INT_MASK_WDT_RESET_SHIFT 31
#define  RBM_INT_STATUS 0x0404
    #define RBM_INT_STATUS_CLI_TIMEOUT_MASK 0x0000007F
    #define RBM_INT_STATUS_CLI_TIMEOUT_SHIFT 0
    #define RBM_INT_STATUS_WDT_TIMER_MASK 0x00030000
    #define RBM_INT_STATUS_WDT_TIMER_SHIFT 16
    #define RBM_INT_STATUS_WDT_RESET_MASK 0x80000000
    #define RBM_INT_STATUS_WDT_RESET_SHIFT 31
#define  RBM_MIPS_INT_MASK 0x0410
    #define RBM_MIPS_INT_MASK_CLI_TIMEOUT_MASK 0x0000007F
    #define RBM_MIPS_INT_MASK_CLI_TIMEOUT_SHIFT 0
    #define RBM_MIPS_INT_MASK_WDT_TIMER_MASK 0x00030000
    #define RBM_MIPS_INT_MASK_WDT_TIMER_SHIFT 16
    #define RBM_MIPS_INT_MASK_WDT_RESET_MASK 0x80000000
    #define RBM_MIPS_INT_MASK_WDT_RESET_SHIFT 31
#define  RBM_PADU_CTRL 0x04A8
    #define PADU_CTRL_UART_MASK 0x00000003
    #define PADU_CTRL_UART_SHIFT 0
    #define PADU_CTRL_FLASH_MASK 0x00000010
    #define PADU_CTRL_FLASH_SHIFT 4
    #define PADU_CTRL_ETH0_MASK 0x00000100
    #define PADU_CTRL_ETH0_SHIFT 8
    #define PADU_CTRL_TEST_CLK_MASK 0x00001000
    #define PADU_CTRL_TEST_CLK_SHIFT 12
    #define PADU_CTRL_TSI_I2C_MASK 0x00010000
    #define PADU_CTRL_TSI_I2C_SHIFT 16
#define  RBM_PCI_CFG 0x0484
    #define PCI_CFG_MASK 0xFFFFFFFF
    #define PCI_CFG_SHIFT 0
#define  RBM_PCI_DEV_ID 0x0474
    #define PCI_DEV_ID_MASK 0x000000FF
    #define PCI_DEV_ID_SHIFT 0
#define  RBM_PCI_SUB_CFG 0x0480
    #define PCI_SUB_CFG_MASK 0xFFFFFFFF
    #define PCI_SUB_CFG_SHIFT 0
#define  RBM_STICKY_BITS 0x0488
    #define STICKY_BIT_MASK 0x000000FF
    #define STICKY_BIT_SHIFT 0
#define  RBM_SWAP 0x043C
    #define BYTE_SWAP_MASK 0x00000007
    #define BYTE_SWAP_SHIFT 0
    #define ALT_SWAP_MASK 0x000000F0
    #define ALT_SWAP_SHIFT 4
    #define RBM_SWAP_BIT_SWAP_MASK 0x0000FF00
    #define RBM_SWAP_BIT_SWAP_SHIFT 8
    #define REQ_HELD_LOW_MASK 0x00010000
    #define REQ_HELD_LOW_SHIFT 16
    #define MC_INIT_MASK 0x00020000
    #define MC_INIT_SHIFT 17
#define  RBM_TIMEOUT_CTRL 0x04A4
    #define SETTLE_TIME_MASK 0x0000003F
    #define SETTLE_TIME_SHIFT 0
    #define TIMEOUT_TIME_MASK 0x0003FF00
    #define TIMEOUT_TIME_SHIFT 8
    #define TIMEOUT_DISABLE_MASK 0x80000000
    #define TIMEOUT_DISABLE_SHIFT 31
#define  RCB_ACT_TOTAL 0x70B0
    #define ACT_TOTAL_MASK 0x000FFFFF
    #define ACT_TOTAL_SHIFT 0
#define  RCB_ADR 0x70BC
    #define RCB_ADR_BASE_MASK 0x7FFFFFC0
    #define RCB_ADR_BASE_SHIFT 6
#define  RCB_BITCOUNT_ADR 0x70C0
    #define RCB_BITCOUNT_ADR_BASE_MASK 0x7FFFFFC0
    #define RCB_BITCOUNT_ADR_BASE_SHIFT 6
#define  RCB_CTRL 0x70A0
    #define QUANT_SRC_MASK 0x00000003
    #define QUANT_SRC_SHIFT 0
    #define QUANT_TYPE_MASK 0x00000004
    #define QUANT_TYPE_SHIFT 2
    #define ZERO_ERR_MASK 0x00000008
    #define ZERO_ERR_SHIFT 3
    #define DELAY_MASK 0x00000070
    #define DELAY_SHIFT 4
    #define USE_FRM_DCT_MASK 0x00000080
    #define USE_FRM_DCT_SHIFT 7
    #define QUANT_VALUE_MASK 0x00007F00
    #define QUANT_VALUE_SHIFT 8
    #define FORCE_QUANT_MASK 0x00008000
    #define FORCE_QUANT_SHIFT 15
    #define RCB_CTRL_MB_CNT_MASK 0x3FFF0000
    #define RCB_CTRL_MB_CNT_SHIFT 16
    #define BITCNT_EN_MASK 0x80000000
    #define BITCNT_EN_SHIFT 31
#define  RCB_QPARAM 0x70A4
    #define QIPB_MASK 0x0000003F
    #define QIPB_SHIFT 0
    #define QMAX_MASK 0x00007F00
    #define QMAX_SHIFT 8
    #define QMIN_MASK 0x007F0000
    #define QMIN_SHIFT 16
#define  RCB_QSUM 0x70B4
    #define QSUM_MASK 0x00FFFFFF
    #define QSUM_SHIFT 0
#define  RCB_REACT 0x70A8
    #define REACT_MASK 0x000FFFFF
    #define REACT_SHIFT 0
#define  RCB_TIPB 0x70AC
    #define TIPB_MASK 0x00FFFFFF
    #define TIPB_SHIFT 0
#define  RCB_XSUM 0x70B8
    #define XSUM_MASK 0x7FFFFFFF
    #define XSUM_SHIFT 0
#define  RMX0_LIST_A 0x6190
    #define RMX0_LIST_A_ADDR_MASK 0x7FFFFFF0
    #define RMX0_LIST_A_ADDR_SHIFT 4
#define  RMX0_LIST_B 0x6194
    #define RMX0_LIST_B_ADDR_MASK 0x7FFFFFF0
    #define RMX0_LIST_B_ADDR_SHIFT 4
#define  RMX0_STATUS 0x6250
    #define RMX0_STATUS_SYNC0_ERR_MASK 0x00000001
    #define RMX0_STATUS_SYNC0_ERR_SHIFT 0
    #define RMX0_STATUS_LENGTH0_ERR_MASK 0x00000002
    #define RMX0_STATUS_LENGTH0_ERR_SHIFT 1
    #define RMX0_STATUS_PESID0_ERR_MASK 0x00000004
    #define RMX0_STATUS_PESID0_ERR_SHIFT 2
    #define RMX0_STATUS_PTSFLAG0_ERR_MASK 0x00000008
    #define RMX0_STATUS_PTSFLAG0_ERR_SHIFT 3
    #define RMX0_STATUS_CC0_MASK 0x000000F0
    #define RMX0_STATUS_CC0_SHIFT 4
    #define RMX0_STATUS_SYNC1_ERR_MASK 0x00000100
    #define RMX0_STATUS_SYNC1_ERR_SHIFT 8
    #define RMX0_STATUS_LENGTH1_ERR_MASK 0x00000200
    #define RMX0_STATUS_LENGTH1_ERR_SHIFT 9
    #define RMX0_STATUS_PESID1_ERR_MASK 0x00000400
    #define RMX0_STATUS_PESID1_ERR_SHIFT 10
    #define RMX0_STATUS_PTSFLAG1_ERR_MASK 0x00000800
    #define RMX0_STATUS_PTSFLAG1_ERR_SHIFT 11
    #define RMX0_STATUS_CC1_MASK 0x0000F000
    #define RMX0_STATUS_CC1_SHIFT 12
    #define RMX0_STATUS_SYNC2_ERR_MASK 0x00010000
    #define RMX0_STATUS_SYNC2_ERR_SHIFT 16
    #define RMX0_STATUS_LENGTH2_ERR_MASK 0x00020000
    #define RMX0_STATUS_LENGTH2_ERR_SHIFT 17
    #define RMX0_STATUS_PESID2_ERR_MASK 0x00040000
    #define RMX0_STATUS_PESID2_ERR_SHIFT 18
    #define RMX0_STATUS_PTSFLAG2_ERR_MASK 0x00080000
    #define RMX0_STATUS_PTSFLAG2_ERR_SHIFT 19
    #define RMX0_STATUS_CC2_MASK 0x00F00000
    #define RMX0_STATUS_CC2_SHIFT 20
    #define RMX0_STATUS_SYNC3_ERR_MASK 0x01000000
    #define RMX0_STATUS_SYNC3_ERR_SHIFT 24
    #define RMX0_STATUS_LENGTH3_ERR_MASK 0x02000000
    #define RMX0_STATUS_LENGTH3_ERR_SHIFT 25
    #define RMX0_STATUS_PESID3_ERR_MASK 0x04000000
    #define RMX0_STATUS_PESID3_ERR_SHIFT 26
    #define RMX0_STATUS_PTSFLAG3_ERR_MASK 0x08000000
    #define RMX0_STATUS_PTSFLAG3_ERR_SHIFT 27
    #define RMX0_STATUS_CC3_MASK 0xF0000000
    #define RMX0_STATUS_CC3_SHIFT 28
#define  RMX0_VBV 0x6210
    #define RMX0_VBV_OFFSET_MASK 0xFFFFFFFF
    #define RMX0_VBV_OFFSET_SHIFT 0
#define  RMX1_0_LIST_A 0x6304
    #define RMX1_0_LIST_A_ADDR_MASK 0x7FFFFFF0
    #define RMX1_0_LIST_A_ADDR_SHIFT 4
#define  RMX1_0_LIST_B 0x6308
    #define RMX1_0_LIST_B_ADDR_MASK 0x7FFFFFF0
    #define RMX1_0_LIST_B_ADDR_SHIFT 4
#define  RMX1_0_STATUS 0x6364
    #define RMX1_0_STATUS_SYNC0_ERR_MASK 0x00000001
    #define RMX1_0_STATUS_SYNC0_ERR_SHIFT 0
    #define RMX1_0_STATUS_LENGTH0_ERR_MASK 0x00000002
    #define RMX1_0_STATUS_LENGTH0_ERR_SHIFT 1
    #define RMX1_0_STATUS_PESID0_ERR_MASK 0x00000004
    #define RMX1_0_STATUS_PESID0_ERR_SHIFT 2
    #define RMX1_0_STATUS_PTSFLAG0_ERR_MASK 0x00000008
    #define RMX1_0_STATUS_PTSFLAG0_ERR_SHIFT 3
    #define RMX1_0_STATUS_CC0_MASK 0x000000F0
    #define RMX1_0_STATUS_CC0_SHIFT 4
    #define RMX1_0_STATUS_SYNC1_ERR_MASK 0x00000100
    #define RMX1_0_STATUS_SYNC1_ERR_SHIFT 8
    #define RMX1_0_STATUS_LENGTH1_ERR_MASK 0x00000200
    #define RMX1_0_STATUS_LENGTH1_ERR_SHIFT 9
    #define RMX1_0_STATUS_PESID1_ERR_MASK 0x00000400
    #define RMX1_0_STATUS_PESID1_ERR_SHIFT 10
    #define RMX1_0_STATUS_PTSFLAG1_ERR_MASK 0x00000800
    #define RMX1_0_STATUS_PTSFLAG1_ERR_SHIFT 11
    #define RMX1_0_STATUS_CC1_MASK 0x0000F000
    #define RMX1_0_STATUS_CC1_SHIFT 12
    #define RMX1_0_STATUS_SYNC2_ERR_MASK 0x00010000
    #define RMX1_0_STATUS_SYNC2_ERR_SHIFT 16
    #define RMX1_0_STATUS_LENGTH2_ERR_MASK 0x00020000
    #define RMX1_0_STATUS_LENGTH2_ERR_SHIFT 17
    #define RMX1_0_STATUS_PESID2_ERR_MASK 0x00040000
    #define RMX1_0_STATUS_PESID2_ERR_SHIFT 18
    #define RMX1_0_STATUS_PTSFLAG2_ERR_MASK 0x00080000
    #define RMX1_0_STATUS_PTSFLAG2_ERR_SHIFT 19
    #define RMX1_0_STATUS_CC2_MASK 0x00F00000
    #define RMX1_0_STATUS_CC2_SHIFT 20
    #define RMX1_0_STATUS_SYNC3_ERR_MASK 0x01000000
    #define RMX1_0_STATUS_SYNC3_ERR_SHIFT 24
    #define RMX1_0_STATUS_LENGTH3_ERR_MASK 0x02000000
    #define RMX1_0_STATUS_LENGTH3_ERR_SHIFT 25
    #define RMX1_0_STATUS_PESID3_ERR_MASK 0x04000000
    #define RMX1_0_STATUS_PESID3_ERR_SHIFT 26
    #define RMX1_0_STATUS_PTSFLAG3_ERR_MASK 0x08000000
    #define RMX1_0_STATUS_PTSFLAG3_ERR_SHIFT 27
    #define RMX1_0_STATUS_CC3_MASK 0xF0000000
    #define RMX1_0_STATUS_CC3_SHIFT 28
#define  RMX1_0_VBV 0x6344
    #define RMX1_0_VBV_OFFSET_MASK 0xFFFFFFFF
    #define RMX1_0_VBV_OFFSET_SHIFT 0
#define  RMX1_1_LIST_A 0x630C
    #define RMX1_1_LIST_A_ADDR_MASK 0x7FFFFFF0
    #define RMX1_1_LIST_A_ADDR_SHIFT 4
#define  RMX1_1_LIST_B 0x6310
    #define RMX1_1_LIST_B_ADDR_MASK 0x7FFFFFF0
    #define RMX1_1_LIST_B_ADDR_SHIFT 4
#define  RMX1_1_VBV 0x6348
    #define RMX1_1_VBV_OFFSET_MASK 0xFFFFFFFF
    #define RMX1_1_VBV_OFFSET_SHIFT 0
#define  RMX1_2_LIST_A 0x6314
    #define RMX1_2_LIST_A_ADDR_MASK 0x7FFFFFF0
    #define RMX1_2_LIST_A_ADDR_SHIFT 4
#define  RMX1_2_LIST_B 0x6318
    #define RMX1_2_LIST_B_ADDR_MASK 0x7FFFFFF0
    #define RMX1_2_LIST_B_ADDR_SHIFT 4
#define  RMX1_2_VBV 0x634C
    #define RMX1_2_VBV_OFFSET_MASK 0xFFFFFFFF
    #define RMX1_2_VBV_OFFSET_SHIFT 0
#define  RMX1_3_LIST_A 0x631C
    #define RMX1_3_LIST_A_ADDR_MASK 0x7FFFFFF0
    #define RMX1_3_LIST_A_ADDR_SHIFT 4
#define  RMX1_3_LIST_B 0x6320
    #define RMX1_3_LIST_B_ADDR_MASK 0x7FFFFFF0
    #define RMX1_3_LIST_B_ADDR_SHIFT 4
#define  RMX1_3_VBV 0x6350
    #define RMX1_3_VBV_OFFSET_MASK 0xFFFFFFFF
    #define RMX1_3_VBV_OFFSET_SHIFT 0
#define  RMX1_4_LIST_A 0x6324
    #define RMX1_4_LIST_A_ADDR_MASK 0x7FFFFFF0
    #define RMX1_4_LIST_A_ADDR_SHIFT 4
#define  RMX1_4_LIST_B 0x6328
    #define RMX1_4_LIST_B_ADDR_MASK 0x7FFFFFF0
    #define RMX1_4_LIST_B_ADDR_SHIFT 4
#define  RMX1_4_STATUS 0x6368
    #define RMX1_4_STATUS_SYNC4_ERR_MASK 0x00000001
    #define RMX1_4_STATUS_SYNC4_ERR_SHIFT 0
    #define RMX1_4_STATUS_LENGTH4_ERR_MASK 0x00000002
    #define RMX1_4_STATUS_LENGTH4_ERR_SHIFT 1
    #define RMX1_4_STATUS_PESID4_ERR_MASK 0x00000004
    #define RMX1_4_STATUS_PESID4_ERR_SHIFT 2
    #define RMX1_4_STATUS_PTSFLAG4_ERR_MASK 0x00000008
    #define RMX1_4_STATUS_PTSFLAG4_ERR_SHIFT 3
    #define RMX1_4_STATUS_CC4_MASK 0x000000F0
    #define RMX1_4_STATUS_CC4_SHIFT 4
    #define RMX1_4_STATUS_SYNC5_ERR_MASK 0x00000100
    #define RMX1_4_STATUS_SYNC5_ERR_SHIFT 8
    #define RMX1_4_STATUS_LENGTH5_ERR_MASK 0x00000200
    #define RMX1_4_STATUS_LENGTH5_ERR_SHIFT 9
    #define RMX1_4_STATUS_PESID5_ERR_MASK 0x00000400
    #define RMX1_4_STATUS_PESID5_ERR_SHIFT 10
    #define RMX1_4_STATUS_PTSFLAG5_ERR_MASK 0x00000800
    #define RMX1_4_STATUS_PTSFLAG5_ERR_SHIFT 11
    #define RMX1_4_STATUS_CC5_MASK 0x0000F000
    #define RMX1_4_STATUS_CC5_SHIFT 12
    #define RMX1_4_STATUS_SYNC6_ERR_MASK 0x00010000
    #define RMX1_4_STATUS_SYNC6_ERR_SHIFT 16
    #define RMX1_4_STATUS_LENGTH6_ERR_MASK 0x00020000
    #define RMX1_4_STATUS_LENGTH6_ERR_SHIFT 17
    #define RMX1_4_STATUS_PESID6_ERR_MASK 0x00040000
    #define RMX1_4_STATUS_PESID6_ERR_SHIFT 18
    #define RMX1_4_STATUS_PTSFLAG6_ERR_MASK 0x00080000
    #define RMX1_4_STATUS_PTSFLAG6_ERR_SHIFT 19
    #define RMX1_4_STATUS_CC6_MASK 0x00F00000
    #define RMX1_4_STATUS_CC6_SHIFT 20
    #define RMX1_4_STATUS_SYNC7_ERR_MASK 0x01000000
    #define RMX1_4_STATUS_SYNC7_ERR_SHIFT 24
    #define RMX1_4_STATUS_LENGTH7_ERR_MASK 0x02000000
    #define RMX1_4_STATUS_LENGTH7_ERR_SHIFT 25
    #define RMX1_4_STATUS_PESID7_ERR_MASK 0x04000000
    #define RMX1_4_STATUS_PESID7_ERR_SHIFT 26
    #define RMX1_4_STATUS_PTSFLAG7_ERR_MASK 0x08000000
    #define RMX1_4_STATUS_PTSFLAG7_ERR_SHIFT 27
    #define RMX1_4_STATUS_CC7_MASK 0xF0000000
    #define RMX1_4_STATUS_CC7_SHIFT 28
#define  RMX1_4_VBV 0x6354
    #define RMX1_4_VBV_OFFSET_MASK 0xFFFFFFFF
    #define RMX1_4_VBV_OFFSET_SHIFT 0
#define  RMX1_5_LIST_A 0x632C
    #define RMX1_5_LIST_A_ADDR_MASK 0x7FFFFFF0
    #define RMX1_5_LIST_A_ADDR_SHIFT 4
#define  RMX1_5_LIST_B 0x6330
    #define RMX1_5_LIST_B_ADDR_MASK 0x7FFFFFF0
    #define RMX1_5_LIST_B_ADDR_SHIFT 4
#define  RMX1_5_VBV 0x6358
    #define RMX1_5_VBV_OFFSET_MASK 0xFFFFFFFF
    #define RMX1_5_VBV_OFFSET_SHIFT 0
#define  RMX1_6_LIST_A 0x6334
    #define RMX1_6_LIST_A_ADDR_MASK 0x7FFFFFF0
    #define RMX1_6_LIST_A_ADDR_SHIFT 4
#define  RMX1_6_LIST_B 0x6338
    #define RMX1_6_LIST_B_ADDR_MASK 0x7FFFFFF0
    #define RMX1_6_LIST_B_ADDR_SHIFT 4
#define  RMX1_6_VBV 0x635C
    #define RMX1_6_VBV_OFFSET_MASK 0xFFFFFFFF
    #define RMX1_6_VBV_OFFSET_SHIFT 0
#define  RMX1_7_LIST_A 0x633C
    #define RMX1_7_LIST_A_ADDR_MASK 0x7FFFFFF0
    #define RMX1_7_LIST_A_ADDR_SHIFT 4
#define  RMX1_7_LIST_B 0x6340
    #define RMX1_7_LIST_B_ADDR_MASK 0x7FFFFFF0
    #define RMX1_7_LIST_B_ADDR_SHIFT 4
#define  RMX1_7_VBV 0x6360
    #define RMX1_7_VBV_OFFSET_MASK 0xFFFFFFFF
    #define RMX1_7_VBV_OFFSET_SHIFT 0
#define  RMX1_CTRL 0x6300
    #define RMX1_CTRL_SRC_0_MASK 0x00000001
    #define RMX1_CTRL_SRC_0_SHIFT 0
    #define RMX1_CTRL_SRC_1_MASK 0x00000002
    #define RMX1_CTRL_SRC_1_SHIFT 1
    #define RMX1_CTRL_SRC_2_MASK 0x00000004
    #define RMX1_CTRL_SRC_2_SHIFT 2
    #define RMX1_CTRL_SRC_3_MASK 0x00000008
    #define RMX1_CTRL_SRC_3_SHIFT 3
    #define RMX1_CTRL_SRC_4_MASK 0x00000010
    #define RMX1_CTRL_SRC_4_SHIFT 4
    #define RMX1_CTRL_SRC_5_MASK 0x00000020
    #define RMX1_CTRL_SRC_5_SHIFT 5
    #define RMX1_CTRL_SRC_6_MASK 0x00000040
    #define RMX1_CTRL_SRC_6_SHIFT 6
    #define RMX1_CTRL_SRC_7_MASK 0x00000080
    #define RMX1_CTRL_SRC_7_SHIFT 7
    #define RMX1_CTRL_RMX_PARTIAL_TS_MASK 0x00010000
    #define RMX1_CTRL_RMX_PARTIAL_TS_SHIFT 16
    #define RMX1_CTRL_OP_RATE_EN_MASK 0x00100000
    #define RMX1_CTRL_OP_RATE_EN_SHIFT 20
    #define RMX1_CTRL_OP_RATE_MASK 0xFF000000
    #define RMX1_CTRL_OP_RATE_SHIFT 24
#define  RMX1_HOST_INT_MASK 0x62F8
    #define RMX1_HOST_INT_MASK_INT_EN_LIST0_A_DONE_MASK 0x00000001
    #define RMX1_HOST_INT_MASK_INT_EN_LIST0_A_DONE_SHIFT 0
    #define RMX1_HOST_INT_MASK_INT_EN_LIST1_A_DONE_MASK 0x00000002
    #define RMX1_HOST_INT_MASK_INT_EN_LIST1_A_DONE_SHIFT 1
    #define RMX1_HOST_INT_MASK_INT_EN_LIST2_A_DONE_MASK 0x00000004
    #define RMX1_HOST_INT_MASK_INT_EN_LIST2_A_DONE_SHIFT 2
    #define RMX1_HOST_INT_MASK_INT_EN_LIST3_A_DONE_MASK 0x00000008
    #define RMX1_HOST_INT_MASK_INT_EN_LIST3_A_DONE_SHIFT 3
    #define RMX1_HOST_INT_MASK_INT_EN_LIST4_A_DONE_MASK 0x00000010
    #define RMX1_HOST_INT_MASK_INT_EN_LIST4_A_DONE_SHIFT 4
    #define RMX1_HOST_INT_MASK_INT_EN_LIST5_A_DONE_MASK 0x00000020
    #define RMX1_HOST_INT_MASK_INT_EN_LIST5_A_DONE_SHIFT 5
    #define RMX1_HOST_INT_MASK_INT_EN_LIST6_A_DONE_MASK 0x00000040
    #define RMX1_HOST_INT_MASK_INT_EN_LIST6_A_DONE_SHIFT 6
    #define RMX1_HOST_INT_MASK_INT_EN_LIST7_A_DONE_MASK 0x00000080
    #define RMX1_HOST_INT_MASK_INT_EN_LIST7_A_DONE_SHIFT 7
    #define RMX1_HOST_INT_MASK_INT_EN_LIST0_B_DONE_MASK 0x00000100
    #define RMX1_HOST_INT_MASK_INT_EN_LIST0_B_DONE_SHIFT 8
    #define RMX1_HOST_INT_MASK_INT_EN_LIST1_B_DONE_MASK 0x00000200
    #define RMX1_HOST_INT_MASK_INT_EN_LIST1_B_DONE_SHIFT 9
    #define RMX1_HOST_INT_MASK_INT_EN_LIST2_B_DONE_MASK 0x00000400
    #define RMX1_HOST_INT_MASK_INT_EN_LIST2_B_DONE_SHIFT 10
    #define RMX1_HOST_INT_MASK_INT_EN_LIST3_B_DONE_MASK 0x00000800
    #define RMX1_HOST_INT_MASK_INT_EN_LIST3_B_DONE_SHIFT 11
    #define RMX1_HOST_INT_MASK_INT_EN_LIST4_B_DONE_MASK 0x00001000
    #define RMX1_HOST_INT_MASK_INT_EN_LIST4_B_DONE_SHIFT 12
    #define RMX1_HOST_INT_MASK_INT_EN_LIST5_B_DONE_MASK 0x00002000
    #define RMX1_HOST_INT_MASK_INT_EN_LIST5_B_DONE_SHIFT 13
    #define RMX1_HOST_INT_MASK_INT_EN_LIST6_B_DONE_MASK 0x00004000
    #define RMX1_HOST_INT_MASK_INT_EN_LIST6_B_DONE_SHIFT 14
    #define RMX1_HOST_INT_MASK_INT_EN_LIST7_B_DONE_MASK 0x00008000
    #define RMX1_HOST_INT_MASK_INT_EN_LIST7_B_DONE_SHIFT 15
#define  RMX1_INT_STATUS 0x62F4
    #define RMX1_INT_STATUS_LIST0_A_DONE_MASK 0x00000001
    #define RMX1_INT_STATUS_LIST0_A_DONE_SHIFT 0
    #define RMX1_INT_STATUS_LIST1_A_DONE_MASK 0x00000002
    #define RMX1_INT_STATUS_LIST1_A_DONE_SHIFT 1
    #define RMX1_INT_STATUS_LIST2_A_DONE_MASK 0x00000004
    #define RMX1_INT_STATUS_LIST2_A_DONE_SHIFT 2
    #define RMX1_INT_STATUS_LIST3_A_DONE_MASK 0x00000008
    #define RMX1_INT_STATUS_LIST3_A_DONE_SHIFT 3
    #define RMX1_INT_STATUS_LIST4_A_DONE_MASK 0x00000010
    #define RMX1_INT_STATUS_LIST4_A_DONE_SHIFT 4
    #define RMX1_INT_STATUS_LIST5_A_DONE_MASK 0x00000020
    #define RMX1_INT_STATUS_LIST5_A_DONE_SHIFT 5
    #define RMX1_INT_STATUS_LIST6_A_DONE_MASK 0x00000040
    #define RMX1_INT_STATUS_LIST6_A_DONE_SHIFT 6
    #define RMX1_INT_STATUS_LIST7_A_DONE_MASK 0x00000080
    #define RMX1_INT_STATUS_LIST7_A_DONE_SHIFT 7
    #define RMX1_INT_STATUS_LIST0_B_DONE_MASK 0x00000100
    #define RMX1_INT_STATUS_LIST0_B_DONE_SHIFT 8
    #define RMX1_INT_STATUS_LIST1_B_DONE_MASK 0x00000200
    #define RMX1_INT_STATUS_LIST1_B_DONE_SHIFT 9
    #define RMX1_INT_STATUS_LIST2_B_DONE_MASK 0x00000400
    #define RMX1_INT_STATUS_LIST2_B_DONE_SHIFT 10
    #define RMX1_INT_STATUS_LIST3_B_DONE_MASK 0x00000800
    #define RMX1_INT_STATUS_LIST3_B_DONE_SHIFT 11
    #define RMX1_INT_STATUS_LIST4_B_DONE_MASK 0x00001000
    #define RMX1_INT_STATUS_LIST4_B_DONE_SHIFT 12
    #define RMX1_INT_STATUS_LIST5_B_DONE_MASK 0x00002000
    #define RMX1_INT_STATUS_LIST5_B_DONE_SHIFT 13
    #define RMX1_INT_STATUS_LIST6_B_DONE_MASK 0x00004000
    #define RMX1_INT_STATUS_LIST6_B_DONE_SHIFT 14
    #define RMX1_INT_STATUS_LIST7_B_DONE_MASK 0x00008000
    #define RMX1_INT_STATUS_LIST7_B_DONE_SHIFT 15
#define  RMX1_LIST_A 0x6198
    #define RMX1_LIST_A_ADDR_MASK 0x7FFFFFF0
    #define RMX1_LIST_A_ADDR_SHIFT 4
#define  RMX1_LIST_B 0x619C
    #define RMX1_LIST_B_ADDR_MASK 0x7FFFFFF0
    #define RMX1_LIST_B_ADDR_SHIFT 4
#define  RMX1_MIPS_INT_MASK 0x62FC
    #define RMX1_MIPS_INT_MASK_INT_EN_LIST0_A_DONE_MASK 0x00000001
    #define RMX1_MIPS_INT_MASK_INT_EN_LIST0_A_DONE_SHIFT 0
    #define RMX1_MIPS_INT_MASK_INT_EN_LIST1_A_DONE_MASK 0x00000002
    #define RMX1_MIPS_INT_MASK_INT_EN_LIST1_A_DONE_SHIFT 1
    #define RMX1_MIPS_INT_MASK_INT_EN_LIST2_A_DONE_MASK 0x00000004
    #define RMX1_MIPS_INT_MASK_INT_EN_LIST2_A_DONE_SHIFT 2
    #define RMX1_MIPS_INT_MASK_INT_EN_LIST3_A_DONE_MASK 0x00000008
    #define RMX1_MIPS_INT_MASK_INT_EN_LIST3_A_DONE_SHIFT 3
    #define RMX1_MIPS_INT_MASK_INT_EN_LIST4_A_DONE_MASK 0x00000010
    #define RMX1_MIPS_INT_MASK_INT_EN_LIST4_A_DONE_SHIFT 4
    #define RMX1_MIPS_INT_MASK_INT_EN_LIST5_A_DONE_MASK 0x00000020
    #define RMX1_MIPS_INT_MASK_INT_EN_LIST5_A_DONE_SHIFT 5
    #define RMX1_MIPS_INT_MASK_INT_EN_LIST6_A_DONE_MASK 0x00000040
    #define RMX1_MIPS_INT_MASK_INT_EN_LIST6_A_DONE_SHIFT 6
    #define RMX1_MIPS_INT_MASK_INT_EN_LIST7_A_DONE_MASK 0x00000080
    #define RMX1_MIPS_INT_MASK_INT_EN_LIST7_A_DONE_SHIFT 7
    #define RMX1_MIPS_INT_MASK_INT_EN_LIST0_B_DONE_MASK 0x00000100
    #define RMX1_MIPS_INT_MASK_INT_EN_LIST0_B_DONE_SHIFT 8
    #define RMX1_MIPS_INT_MASK_INT_EN_LIST1_B_DONE_MASK 0x00000200
    #define RMX1_MIPS_INT_MASK_INT_EN_LIST1_B_DONE_SHIFT 9
    #define RMX1_MIPS_INT_MASK_INT_EN_LIST2_B_DONE_MASK 0x00000400
    #define RMX1_MIPS_INT_MASK_INT_EN_LIST2_B_DONE_SHIFT 10
    #define RMX1_MIPS_INT_MASK_INT_EN_LIST3_B_DONE_MASK 0x00000800
    #define RMX1_MIPS_INT_MASK_INT_EN_LIST3_B_DONE_SHIFT 11
    #define RMX1_MIPS_INT_MASK_INT_EN_LIST4_B_DONE_MASK 0x00001000
    #define RMX1_MIPS_INT_MASK_INT_EN_LIST4_B_DONE_SHIFT 12
    #define RMX1_MIPS_INT_MASK_INT_EN_LIST5_B_DONE_MASK 0x00002000
    #define RMX1_MIPS_INT_MASK_INT_EN_LIST5_B_DONE_SHIFT 13
    #define RMX1_MIPS_INT_MASK_INT_EN_LIST6_B_DONE_MASK 0x00004000
    #define RMX1_MIPS_INT_MASK_INT_EN_LIST6_B_DONE_SHIFT 14
    #define RMX1_MIPS_INT_MASK_INT_EN_LIST7_B_DONE_MASK 0x00008000
    #define RMX1_MIPS_INT_MASK_INT_EN_LIST7_B_DONE_SHIFT 15
#define  RMX1_STATE_A 0x636C
    #define RMX1_STATE_A_STATE_A_MASK 0x000007FF
    #define RMX1_STATE_A_STATE_A_SHIFT 0
#define  RMX1_STATE_L 0x6374
    #define RMX1_STATE_L_STATE_L_MASK 0xFFFFFFFF
    #define RMX1_STATE_L_STATE_L_SHIFT 0
#define  RMX1_STATE_U 0x6370
    #define RMX1_STATE_U_STATE_U_MASK 0xFFFFFFFF
    #define RMX1_STATE_U_STATE_U_SHIFT 0
#define  RMX1_VBV 0x6214
    #define RMX1_VBV_OFFSET_MASK 0xFFFFFFFF
    #define RMX1_VBV_OFFSET_SHIFT 0
#define  RMX2_LIST_A 0x61A0
    #define RMX2_LIST_A_ADDR_MASK 0x7FFFFFF0
    #define RMX2_LIST_A_ADDR_SHIFT 4
#define  RMX2_LIST_B 0x61A4
    #define RMX2_LIST_B_ADDR_MASK 0x7FFFFFF0
    #define RMX2_LIST_B_ADDR_SHIFT 4
#define  RMX2_VBV 0x6218
    #define RMX2_VBV_OFFSET_MASK 0xFFFFFFFF
    #define RMX2_VBV_OFFSET_SHIFT 0
#define  RMX3_LIST_A 0x61A8
    #define RMX3_LIST_A_ADDR_MASK 0x7FFFFFF0
    #define RMX3_LIST_A_ADDR_SHIFT 4
#define  RMX3_LIST_B 0x61AC
    #define RMX3_LIST_B_ADDR_MASK 0x7FFFFFF0
    #define RMX3_LIST_B_ADDR_SHIFT 4
#define  RMX3_VBV 0x621C
    #define RMX3_VBV_OFFSET_MASK 0xFFFFFFFF
    #define RMX3_VBV_OFFSET_SHIFT 0
#define  RMX4_LIST_A 0x61B0
    #define RMX4_LIST_A_ADDR_MASK 0x7FFFFFF0
    #define RMX4_LIST_A_ADDR_SHIFT 4
#define  RMX4_LIST_B 0x61B4
    #define RMX4_LIST_B_ADDR_MASK 0x7FFFFFF0
    #define RMX4_LIST_B_ADDR_SHIFT 4
#define  RMX4_STATUS 0x6254
    #define RMX4_STATUS_SYNC4_ERR_MASK 0x00000001
    #define RMX4_STATUS_SYNC4_ERR_SHIFT 0
    #define RMX4_STATUS_LENGTH4_ERR_MASK 0x00000002
    #define RMX4_STATUS_LENGTH4_ERR_SHIFT 1
    #define RMX4_STATUS_PESID4_ERR_MASK 0x00000004
    #define RMX4_STATUS_PESID4_ERR_SHIFT 2
    #define RMX4_STATUS_PTSFLAG4_ERR_MASK 0x00000008
    #define RMX4_STATUS_PTSFLAG4_ERR_SHIFT 3
    #define RMX4_STATUS_CC4_MASK 0x000000F0
    #define RMX4_STATUS_CC4_SHIFT 4
    #define RMX4_STATUS_SYNC5_ERR_MASK 0x00000100
    #define RMX4_STATUS_SYNC5_ERR_SHIFT 8
    #define RMX4_STATUS_LENGTH5_ERR_MASK 0x00000200
    #define RMX4_STATUS_LENGTH5_ERR_SHIFT 9
    #define RMX4_STATUS_PESID5_ERR_MASK 0x00000400
    #define RMX4_STATUS_PESID5_ERR_SHIFT 10
    #define RMX4_STATUS_PTSFLAG5_ERR_MASK 0x00000800
    #define RMX4_STATUS_PTSFLAG5_ERR_SHIFT 11
    #define RMX4_STATUS_CC5_MASK 0x0000F000
    #define RMX4_STATUS_CC5_SHIFT 12
    #define RMX4_STATUS_SYNC6_ERR_MASK 0x00010000
    #define RMX4_STATUS_SYNC6_ERR_SHIFT 16
    #define RMX4_STATUS_LENGTH6_ERR_MASK 0x00020000
    #define RMX4_STATUS_LENGTH6_ERR_SHIFT 17
    #define RMX4_STATUS_PESID6_ERR_MASK 0x00040000
    #define RMX4_STATUS_PESID6_ERR_SHIFT 18
    #define RMX4_STATUS_PTSFLAG6_ERR_MASK 0x00080000
    #define RMX4_STATUS_PTSFLAG6_ERR_SHIFT 19
    #define RMX4_STATUS_CC6_MASK 0x00F00000
    #define RMX4_STATUS_CC6_SHIFT 20
    #define RMX4_STATUS_SYNC7_ERR_MASK 0x01000000
    #define RMX4_STATUS_SYNC7_ERR_SHIFT 24
    #define RMX4_STATUS_LENGTH7_ERR_MASK 0x02000000
    #define RMX4_STATUS_LENGTH7_ERR_SHIFT 25
    #define RMX4_STATUS_PESID7_ERR_MASK 0x04000000
    #define RMX4_STATUS_PESID7_ERR_SHIFT 26
    #define RMX4_STATUS_PTSFLAG7_ERR_MASK 0x08000000
    #define RMX4_STATUS_PTSFLAG7_ERR_SHIFT 27
    #define RMX4_STATUS_CC7_MASK 0xF0000000
    #define RMX4_STATUS_CC7_SHIFT 28
#define  RMX4_VBV 0x6220
    #define RMX4_VBV_OFFSET_MASK 0xFFFFFFFF
    #define RMX4_VBV_OFFSET_SHIFT 0
#define  RMX5_LIST_A 0x61B8
    #define RMX5_LIST_A_ADDR_MASK 0x7FFFFFF0
    #define RMX5_LIST_A_ADDR_SHIFT 4
#define  RMX5_LIST_B 0x61BC
    #define RMX5_LIST_B_ADDR_MASK 0x7FFFFFF0
    #define RMX5_LIST_B_ADDR_SHIFT 4
#define  RMX5_VBV 0x6224
    #define RMX5_VBV_OFFSET_MASK 0xFFFFFFFF
    #define RMX5_VBV_OFFSET_SHIFT 0
#define  RMX6_LIST_A 0x61C0
    #define RMX6_LIST_A_ADDR_MASK 0x7FFFFFF0
    #define RMX6_LIST_A_ADDR_SHIFT 4
#define  RMX6_LIST_B 0x61C4
    #define RMX6_LIST_B_ADDR_MASK 0x7FFFFFF0
    #define RMX6_LIST_B_ADDR_SHIFT 4
#define  RMX6_VBV 0x6228
    #define RMX6_VBV_OFFSET_MASK 0xFFFFFFFF
    #define RMX6_VBV_OFFSET_SHIFT 0
#define  RMX7_LIST_A 0x61C8
    #define RMX7_LIST_A_ADDR_MASK 0x7FFFFFF0
    #define RMX7_LIST_A_ADDR_SHIFT 4
#define  RMX7_LIST_B 0x61CC
    #define RMX7_LIST_B_ADDR_MASK 0x7FFFFFF0
    #define RMX7_LIST_B_ADDR_SHIFT 4
#define  RMX7_VBV 0x622C
    #define RMX7_VBV_OFFSET_MASK 0xFFFFFFFF
    #define RMX7_VBV_OFFSET_SHIFT 0
#define  RMX_CTRL 0x6180
    #define RMX_CTRL_SRC_0_MASK 0x00000001
    #define RMX_CTRL_SRC_0_SHIFT 0
    #define RMX_CTRL_SRC_1_MASK 0x00000002
    #define RMX_CTRL_SRC_1_SHIFT 1
    #define RMX_CTRL_SRC_2_MASK 0x00000004
    #define RMX_CTRL_SRC_2_SHIFT 2
    #define RMX_CTRL_SRC_3_MASK 0x00000008
    #define RMX_CTRL_SRC_3_SHIFT 3
    #define RMX_CTRL_SRC_4_MASK 0x00000010
    #define RMX_CTRL_SRC_4_SHIFT 4
    #define RMX_CTRL_SRC_5_MASK 0x00000020
    #define RMX_CTRL_SRC_5_SHIFT 5
    #define RMX_CTRL_SRC_6_MASK 0x00000040
    #define RMX_CTRL_SRC_6_SHIFT 6
    #define RMX_CTRL_SRC_7_MASK 0x00000080
    #define RMX_CTRL_SRC_7_SHIFT 7
    #define RMX_CTRL_RMX_PARTIAL_TS_MASK 0x00010000
    #define RMX_CTRL_RMX_PARTIAL_TS_SHIFT 16
    #define RMX_CTRL_OP_RATE_EN_MASK 0x00100000
    #define RMX_CTRL_OP_RATE_EN_SHIFT 20
    #define RMX_CTRL_OP_RATE_MASK 0xFF000000
    #define RMX_CTRL_OP_RATE_SHIFT 24
#define  RMX_HOST_INT_MASK 0x6174
    #define RMX_HOST_INT_MASK_INT_EN_LIST0_A_DONE_MASK 0x00000001
    #define RMX_HOST_INT_MASK_INT_EN_LIST0_A_DONE_SHIFT 0
    #define RMX_HOST_INT_MASK_INT_EN_LIST1_A_DONE_MASK 0x00000002
    #define RMX_HOST_INT_MASK_INT_EN_LIST1_A_DONE_SHIFT 1
    #define RMX_HOST_INT_MASK_INT_EN_LIST2_A_DONE_MASK 0x00000004
    #define RMX_HOST_INT_MASK_INT_EN_LIST2_A_DONE_SHIFT 2
    #define RMX_HOST_INT_MASK_INT_EN_LIST3_A_DONE_MASK 0x00000008
    #define RMX_HOST_INT_MASK_INT_EN_LIST3_A_DONE_SHIFT 3
    #define RMX_HOST_INT_MASK_INT_EN_LIST4_A_DONE_MASK 0x00000010
    #define RMX_HOST_INT_MASK_INT_EN_LIST4_A_DONE_SHIFT 4
    #define RMX_HOST_INT_MASK_INT_EN_LIST5_A_DONE_MASK 0x00000020
    #define RMX_HOST_INT_MASK_INT_EN_LIST5_A_DONE_SHIFT 5
    #define RMX_HOST_INT_MASK_INT_EN_LIST6_A_DONE_MASK 0x00000040
    #define RMX_HOST_INT_MASK_INT_EN_LIST6_A_DONE_SHIFT 6
    #define RMX_HOST_INT_MASK_INT_EN_LIST7_A_DONE_MASK 0x00000080
    #define RMX_HOST_INT_MASK_INT_EN_LIST7_A_DONE_SHIFT 7
    #define RMX_HOST_INT_MASK_INT_EN_LIST0_B_DONE_MASK 0x00000100
    #define RMX_HOST_INT_MASK_INT_EN_LIST0_B_DONE_SHIFT 8
    #define RMX_HOST_INT_MASK_INT_EN_LIST1_B_DONE_MASK 0x00000200
    #define RMX_HOST_INT_MASK_INT_EN_LIST1_B_DONE_SHIFT 9
    #define RMX_HOST_INT_MASK_INT_EN_LIST2_B_DONE_MASK 0x00000400
    #define RMX_HOST_INT_MASK_INT_EN_LIST2_B_DONE_SHIFT 10
    #define RMX_HOST_INT_MASK_INT_EN_LIST3_B_DONE_MASK 0x00000800
    #define RMX_HOST_INT_MASK_INT_EN_LIST3_B_DONE_SHIFT 11
    #define RMX_HOST_INT_MASK_INT_EN_LIST4_B_DONE_MASK 0x00001000
    #define RMX_HOST_INT_MASK_INT_EN_LIST4_B_DONE_SHIFT 12
    #define RMX_HOST_INT_MASK_INT_EN_LIST5_B_DONE_MASK 0x00002000
    #define RMX_HOST_INT_MASK_INT_EN_LIST5_B_DONE_SHIFT 13
    #define RMX_HOST_INT_MASK_INT_EN_LIST6_B_DONE_MASK 0x00004000
    #define RMX_HOST_INT_MASK_INT_EN_LIST6_B_DONE_SHIFT 14
    #define RMX_HOST_INT_MASK_INT_EN_LIST7_B_DONE_MASK 0x00008000
    #define RMX_HOST_INT_MASK_INT_EN_LIST7_B_DONE_SHIFT 15
    #define RMX_HOST_INT_MASK_INT_EN_FRM_CNT_ZERO_MASK 0x00010000
    #define RMX_HOST_INT_MASK_INT_EN_FRM_CNT_ZERO_SHIFT 16
#define  RMX_INT_STATUS 0x6170
    #define RMX_INT_STATUS_LIST0_A_DONE_MASK 0x00000001
    #define RMX_INT_STATUS_LIST0_A_DONE_SHIFT 0
    #define RMX_INT_STATUS_LIST1_A_DONE_MASK 0x00000002
    #define RMX_INT_STATUS_LIST1_A_DONE_SHIFT 1
    #define RMX_INT_STATUS_LIST2_A_DONE_MASK 0x00000004
    #define RMX_INT_STATUS_LIST2_A_DONE_SHIFT 2
    #define RMX_INT_STATUS_LIST3_A_DONE_MASK 0x00000008
    #define RMX_INT_STATUS_LIST3_A_DONE_SHIFT 3
    #define RMX_INT_STATUS_LIST4_A_DONE_MASK 0x00000010
    #define RMX_INT_STATUS_LIST4_A_DONE_SHIFT 4
    #define RMX_INT_STATUS_LIST5_A_DONE_MASK 0x00000020
    #define RMX_INT_STATUS_LIST5_A_DONE_SHIFT 5
    #define RMX_INT_STATUS_LIST6_A_DONE_MASK 0x00000040
    #define RMX_INT_STATUS_LIST6_A_DONE_SHIFT 6
    #define RMX_INT_STATUS_LIST7_A_DONE_MASK 0x00000080
    #define RMX_INT_STATUS_LIST7_A_DONE_SHIFT 7
    #define RMX_INT_STATUS_LIST0_B_DONE_MASK 0x00000100
    #define RMX_INT_STATUS_LIST0_B_DONE_SHIFT 8
    #define RMX_INT_STATUS_LIST1_B_DONE_MASK 0x00000200
    #define RMX_INT_STATUS_LIST1_B_DONE_SHIFT 9
    #define RMX_INT_STATUS_LIST2_B_DONE_MASK 0x00000400
    #define RMX_INT_STATUS_LIST2_B_DONE_SHIFT 10
    #define RMX_INT_STATUS_LIST3_B_DONE_MASK 0x00000800
    #define RMX_INT_STATUS_LIST3_B_DONE_SHIFT 11
    #define RMX_INT_STATUS_LIST4_B_DONE_MASK 0x00001000
    #define RMX_INT_STATUS_LIST4_B_DONE_SHIFT 12
    #define RMX_INT_STATUS_LIST5_B_DONE_MASK 0x00002000
    #define RMX_INT_STATUS_LIST5_B_DONE_SHIFT 13
    #define RMX_INT_STATUS_LIST6_B_DONE_MASK 0x00004000
    #define RMX_INT_STATUS_LIST6_B_DONE_SHIFT 14
    #define RMX_INT_STATUS_LIST7_B_DONE_MASK 0x00008000
    #define RMX_INT_STATUS_LIST7_B_DONE_SHIFT 15
    #define FRM_CNT_ZERO_INT_MASK 0x00010000
    #define FRM_CNT_ZERO_INT_SHIFT 16
#define  RMX_MIPS_INT_MASK 0x6178
    #define RMX_MIPS_INT_MASK_INT_EN_LIST0_A_DONE_MASK 0x00000001
    #define RMX_MIPS_INT_MASK_INT_EN_LIST0_A_DONE_SHIFT 0
    #define RMX_MIPS_INT_MASK_INT_EN_LIST1_A_DONE_MASK 0x00000002
    #define RMX_MIPS_INT_MASK_INT_EN_LIST1_A_DONE_SHIFT 1
    #define RMX_MIPS_INT_MASK_INT_EN_LIST2_A_DONE_MASK 0x00000004
    #define RMX_MIPS_INT_MASK_INT_EN_LIST2_A_DONE_SHIFT 2
    #define RMX_MIPS_INT_MASK_INT_EN_LIST3_A_DONE_MASK 0x00000008
    #define RMX_MIPS_INT_MASK_INT_EN_LIST3_A_DONE_SHIFT 3
    #define RMX_MIPS_INT_MASK_INT_EN_LIST4_A_DONE_MASK 0x00000010
    #define RMX_MIPS_INT_MASK_INT_EN_LIST4_A_DONE_SHIFT 4
    #define RMX_MIPS_INT_MASK_INT_EN_LIST5_A_DONE_MASK 0x00000020
    #define RMX_MIPS_INT_MASK_INT_EN_LIST5_A_DONE_SHIFT 5
    #define RMX_MIPS_INT_MASK_INT_EN_LIST6_A_DONE_MASK 0x00000040
    #define RMX_MIPS_INT_MASK_INT_EN_LIST6_A_DONE_SHIFT 6
    #define RMX_MIPS_INT_MASK_INT_EN_LIST7_A_DONE_MASK 0x00000080
    #define RMX_MIPS_INT_MASK_INT_EN_LIST7_A_DONE_SHIFT 7
    #define RMX_MIPS_INT_MASK_INT_EN_LIST0_B_DONE_MASK 0x00000100
    #define RMX_MIPS_INT_MASK_INT_EN_LIST0_B_DONE_SHIFT 8
    #define RMX_MIPS_INT_MASK_INT_EN_LIST1_B_DONE_MASK 0x00000200
    #define RMX_MIPS_INT_MASK_INT_EN_LIST1_B_DONE_SHIFT 9
    #define RMX_MIPS_INT_MASK_INT_EN_LIST2_B_DONE_MASK 0x00000400
    #define RMX_MIPS_INT_MASK_INT_EN_LIST2_B_DONE_SHIFT 10
    #define RMX_MIPS_INT_MASK_INT_EN_LIST3_B_DONE_MASK 0x00000800
    #define RMX_MIPS_INT_MASK_INT_EN_LIST3_B_DONE_SHIFT 11
    #define RMX_MIPS_INT_MASK_INT_EN_LIST4_B_DONE_MASK 0x00001000
    #define RMX_MIPS_INT_MASK_INT_EN_LIST4_B_DONE_SHIFT 12
    #define RMX_MIPS_INT_MASK_INT_EN_LIST5_B_DONE_MASK 0x00002000
    #define RMX_MIPS_INT_MASK_INT_EN_LIST5_B_DONE_SHIFT 13
    #define RMX_MIPS_INT_MASK_INT_EN_LIST6_B_DONE_MASK 0x00004000
    #define RMX_MIPS_INT_MASK_INT_EN_LIST6_B_DONE_SHIFT 14
    #define RMX_MIPS_INT_MASK_INT_EN_LIST7_B_DONE_MASK 0x00008000
    #define RMX_MIPS_INT_MASK_INT_EN_LIST7_B_DONE_SHIFT 15
    #define RMX_MIPS_INT_MASK_INT_EN_FRM_CNT_ZERO_MASK 0x00010000
    #define RMX_MIPS_INT_MASK_INT_EN_FRM_CNT_ZERO_SHIFT 16
#define  RMX_STATE_A 0x625C
    #define RMX_STATE_A_STATE_A_MASK 0x000007FF
    #define RMX_STATE_A_STATE_A_SHIFT 0
#define  RMX_STATE_L 0x6264
    #define RMX_STATE_L_STATE_L_MASK 0xFFFFFFFF
    #define RMX_STATE_L_STATE_L_SHIFT 0
#define  RMX_STATE_U 0x6260
    #define RMX_STATE_U_STATE_U_MASK 0xFFFFFFFF
    #define RMX_STATE_U_STATE_U_SHIFT 0
#define  ROUTING_INFO_ADR 0x6080
    #define ROUTING_INFO_BASE_MASK 0x0000003F
    #define ROUTING_INFO_BASE_SHIFT 0
#define  ROUTING_INFO_LWDAT 0x6230
    #define VECTOR_IDX_MASK 0x0000007F
    #define VECTOR_IDX_SHIFT 0
    #define CW_IDX01_MASK 0x00007F00
    #define CW_IDX01_SHIFT 8
    #define CW_IDX10_MASK 0x007F0000
    #define CW_IDX10_SHIFT 16
    #define CW_IDX11_MASK 0x7F000000
    #define CW_IDX11_SHIFT 24
#define  ROUTING_INFO_WDAT 0x6084
    #define DECRYPT_MODE_MASK 0x00000007
    #define DECRYPT_MODE_SHIFT 0
    #define DES_CTRL_S0_MASK 0x00000008
    #define DES_CTRL_S0_SHIFT 3
    #define DES_CTRL_S1_MASK 0x00000010
    #define DES_CTRL_S1_SHIFT 4
    #define DES_CTRL_S2_MASK 0x00000020
    #define DES_CTRL_S2_SHIFT 5
    #define DES_MODE_MASK 0x00000040
    #define DES_MODE_SHIFT 6
    #define DES_OC_MASK 0x00000080
    #define DES_OC_SHIFT 7
#define  RSA_ARRAY_CTRL 0x182C
    #define ARRAY_DIR_WADR_MASK 0x0000007F
    #define ARRAY_DIR_WADR_SHIFT 0
    #define RSA_ARRAY_CTRL_IDLE_MASK 0x00000080
    #define RSA_ARRAY_CTRL_IDLE_SHIFT 7
    #define DIRECT_RAND_MASK 0x00000100
    #define DIRECT_RAND_SHIFT 8
#define  RSA_ARRAY_WDAT_H 0x1828
    #define RSA_ARRAY_WDAT_H_WDAT_MASK 0xFFFFFFFF
    #define RSA_ARRAY_WDAT_H_WDAT_SHIFT 0
#define  RSA_ARRAY_WDAT_L 0x1824
    #define RSA_ARRAY_WDAT_L_WDAT_MASK 0xFFFFFFFF
    #define RSA_ARRAY_WDAT_L_WDAT_SHIFT 0
#define  RSA_CLIENT_CTRL 0x1800
    #define MOD_WEN_MASK 0x00000001
    #define MOD_WEN_SHIFT 0
    #define EXP_WEN_MASK 0x00000002
    #define EXP_WEN_SHIFT 1
    #define DAT_WEN_MASK 0x00000004
    #define DAT_WEN_SHIFT 2
    #define REG_IDX_MASK 0x000003F0
    #define REG_IDX_SHIFT 4
#define  RSA_CLIENT_READ 0x1808
    #define RSA_CLIENT_READ_DATA_MASK 0xFFFFFFFF
    #define RSA_CLIENT_READ_DATA_SHIFT 0
#define  RSA_CLIENT_WRITE 0x1804
    #define RSA_CLIENT_WRITE_DATA_MASK 0xFFFFFFFF
    #define RSA_CLIENT_WRITE_DATA_SHIFT 0
#define  RSA_COPY_CTRL 0x1820
    #define COPY_START_ADR_MASK 0x0000007F
    #define COPY_START_ADR_SHIFT 0
    #define COPY_NUM_MASK 0x00000F80
    #define COPY_NUM_SHIFT 7
    #define RSA_COPY_CTRL_IDLE_MASK 0x00001000
    #define RSA_COPY_CTRL_IDLE_SHIFT 12
#define  RSA_DEBUG 0x1900
    #define RSA_DEBUG_DEBUG_DATA_MASK 0x000FFFFF
    #define RSA_DEBUG_DEBUG_DATA_SHIFT 0
#define  RSA_DUMMY_REG 0x1868
    #define RSA_DUMMY_REG_DUMMY_BITS_MASK 0xFFFFFFFF
    #define RSA_DUMMY_REG_DUMMY_BITS_SHIFT 0
#define  RSA_ECC_CTRL 0x1870
    #define ECC_ENABLE_MASK 0x00000001
    #define ECC_ENABLE_SHIFT 0
    #define ECC_EEA_DEBUG_MASK 0x00000002
    #define ECC_EEA_DEBUG_SHIFT 1
    #define ECC_DIV_DEBUG_MASK 0x00000004
    #define ECC_DIV_DEBUG_SHIFT 2
    #define ECC_MULT_DEBUG_MASK 0x00000008
    #define ECC_MULT_DEBUG_SHIFT 3
    #define ECC_DST_MASK 0x00000010
    #define ECC_DST_SHIFT 4
    #define ECC_KS_WADR_MASK 0x00007F00
    #define ECC_KS_WADR_SHIFT 8
    #define ECC_NUM_WRITES_MASK 0x00070000
    #define ECC_NUM_WRITES_SHIFT 16
    #define ECC_MOD_SIZE_MASK 0x0FF00000
    #define ECC_MOD_SIZE_SHIFT 20
#define  RSA_ECC_OPT 0x186C
    #define ECC_OPT_MASK 0x000007FF
    #define ECC_OPT_SHIFT 0
#define  RSA_ENGINE_CTRL 0x1814
    #define DST_MASK 0x00000001
    #define DST_SHIFT 0
    #define RSA_ENGINE_CTRL_SRC_MASK 0x00000002
    #define RSA_ENGINE_CTRL_SRC_SHIFT 1
    #define ITERATE_MASK 0x00000004
    #define ITERATE_SHIFT 2
    #define RSA_ENGINE_CTRL_BUSY_MASK 0x00000008
    #define RSA_ENGINE_CTRL_BUSY_SHIFT 3
    #define ARRAY_WADR_MASK 0x000007F0
    #define ARRAY_WADR_SHIFT 4
    #define NUM_WRITES_MASK 0x0001F000
    #define NUM_WRITES_SHIFT 12
    #define MOD_SIZE_MASK 0x7FF00000
    #define MOD_SIZE_SHIFT 20
#define  RSA_I2C_ADDR 0x1890
    #define I2C_ADDR_MASK 0x0000007F
    #define I2C_ADDR_SHIFT 0
#define  RSA_INT_MASK 0x1818
    #define RSA_ERR_INT_EN_MASK 0x00000001
    #define RSA_ERR_INT_EN_SHIFT 0
    #define RSA_DONE_INT_EN_MASK 0x00000002
    #define RSA_DONE_INT_EN_SHIFT 1
    #define ECC_ERR_INT_EN_MASK 0x00000004
    #define ECC_ERR_INT_EN_SHIFT 2
    #define ECC_DONE_INT_EN_MASK 0x00000008
    #define ECC_DONE_INT_EN_SHIFT 3
#define  RSA_INT_STATUS 0x181C
    #define RSA_ERR_MASK 0x00000001
    #define RSA_ERR_SHIFT 0
    #define RSA_DONE_MASK 0x00000002
    #define RSA_DONE_SHIFT 1
    #define ECC_ERR_MASK 0x00000004
    #define ECC_ERR_SHIFT 2
    #define ECC_DONE_MASK 0x00000008
    #define ECC_DONE_SHIFT 3
#define  RSA_MAGIC 0x1878
    #define MAGIC_MASK 0xFFFFFFFF
    #define MAGIC_SHIFT 0
#define  RSA_NVM_CONFIG0 0x1840
    #define TPP_MASK 0x0000FFFF
    #define TPP_SHIFT 0
    #define TPR_MASK 0x00FF0000
    #define TPR_SHIFT 16
    #define TPCP_MASK 0x0F000000
    #define TPCP_SHIFT 24
#define  RSA_NVM_CONFIG1 0x1844
    #define TVPPS_MASK 0x0000FFFF
    #define TVPPS_SHIFT 0
    #define TPUR_MASK 0x00FF0000
    #define TPUR_SHIFT 16
#define  RSA_NVM_CONFIG2 0x1848
    #define TVPPH_MASK 0xFFFFFFFF
    #define TVPPH_SHIFT 0
#define  RSA_NVM_CONFIG3 0x184C
    #define TRCYC_MASK 0x0000000F
    #define TRCYC_SHIFT 0
    #define RSA_NVM_CONFIG3_TRR_MASK 0x000000F0
    #define RSA_NVM_CONFIG3_TRR_SHIFT 4
    #define TWCYC_MASK 0x00000F00
    #define TWCYC_SHIFT 8
    #define TWR_MASK 0x0000F000
    #define TWR_SHIFT 12
#define  RSA_NVM_CONFIG4 0x1850
    #define MAX_PGM_NUM_MASK 0x000000FF
    #define MAX_PGM_NUM_SHIFT 0
    #define PWR_DOWN_MASK 0x00000100
    #define PWR_DOWN_SHIFT 8
#define  RSA_NVM_CONFIG5 0x1854
    #define TUCYC_MASK 0x00000FFF
    #define TUCYC_SHIFT 0
    #define TUSTR_MASK 0x007FF000
    #define TUSTR_SHIFT 12
    #define TUEND_MASK 0xFF800000
    #define TUEND_SHIFT 23
#define  RSA_NVM_CTRL 0x1834
    #define NVM_DATA_MASK 0x0000FFFF
    #define NVM_DATA_SHIFT 0
    #define NVM_ADDR_MASK 0x0FFF0000
    #define NVM_ADDR_SHIFT 16
    #define NVM_RD_MASK 0x10000000
    #define NVM_RD_SHIFT 28
    #define NVM_WR_MASK 0x20000000
    #define NVM_WR_SHIFT 29
    #define NVM_STRT_PUMP_MASK 0x40000000
    #define NVM_STRT_PUMP_SHIFT 30
    #define NVM_STOP_PUMP_MASK 0x80000000
    #define NVM_STOP_PUMP_SHIFT 31
#define  RSA_NVM_PASSWD 0x1858
    #define NVM_PASSWD_MASK 0xFFFFFFFF
    #define NVM_PASSWD_SHIFT 0
#define  RSA_NVM_SKU0 0x1880
    #define NVM_SKU0_MASK 0xFFFFFFFF
    #define NVM_SKU0_SHIFT 0
#define  RSA_NVM_SKU1 0x1884
    #define NVM_SKU1_MASK 0xFFFFFFFF
    #define NVM_SKU1_SHIFT 0
#define  RSA_NVM_STATUS 0x1838
    #define NVM_BOOTED_MASK 0x00000001
    #define NVM_BOOTED_SHIFT 0
    #define NVM_RDY_MASK 0x00000002
    #define NVM_RDY_SHIFT 1
    #define NVM_PASS_MASK 0x00000004
    #define NVM_PASS_SHIFT 2
    #define NVM_LOCKED_MASK 0x00000008
    #define NVM_LOCKED_SHIFT 3
#define  RSA_NVM_TEST 0x183C
    #define NVM_TEST_DATA_MASK 0x0000FFFF
    #define NVM_TEST_DATA_SHIFT 0
    #define NVM_MR_WR_MASK 0x00010000
    #define NVM_MR_WR_SHIFT 16
    #define NVM_MRA_WR_MASK 0x00020000
    #define NVM_MRA_WR_SHIFT 17
    #define NVM_MRB_WR_MASK 0x00040000
    #define NVM_MRB_WR_SHIFT 18
    #define NVM_MR_RST_MASK 0x00080000
    #define NVM_MR_RST_SHIFT 19
    #define NVM_BIST_ENB_MASK 0x00100000
    #define NVM_BIST_ENB_SHIFT 20
    #define NVM_BIST_DONE_MASK 0x00200000
    #define NVM_BIST_DONE_SHIFT 21
    #define NVM_BIST_ERR_MASK 0x00400000
    #define NVM_BIST_ERR_SHIFT 22
#define  RSA_SFT_RSTN 0x1830
    #define RSA_SFT_RSTN_SFT_RSTN_MASK 0x00000001
    #define RSA_SFT_RSTN_SFT_RSTN_SHIFT 0
    #define NVM_RSTN_MASK 0x00000002
    #define NVM_RSTN_SHIFT 1
#define  RSA_UNIQUE_ID0 0x1888
    #define UNIQUE_ID0_MASK 0xFFFFFFFF
    #define UNIQUE_ID0_SHIFT 0
#define  RSA_UNIQUE_ID1 0x188C
    #define UNIQUE_ID1_MASK 0xFFFFFFFF
    #define UNIQUE_ID1_SHIFT 0
#define  SATA0_HOST_SERR 0xD054
    #define SERR_MASK 0xFFFFFFFF
    #define SERR_SHIFT 0
#define  SATA0_HOST_SSTAT 0xD058
    #define SSTS_MASK 0x00000FFF
    #define SSTS_SHIFT 0
    #define INTSTAT_MASK 0xFFFF8000
    #define INTSTAT_SHIFT 15
#define  SATA0_PHY_TXRX_CTRL 0xD03C
    #define SATA0_PHY_TX_BOOST_MASK 0x0000000F
    #define SATA0_PHY_TX_BOOST_SHIFT 0
    #define SATA0_PHY_TX_ATTEN_MASK 0x00000070
    #define SATA0_PHY_TX_ATTEN_SHIFT 4
    #define SATA0_PHY_TX_EDGERATE_MASK 0x00000300
    #define SATA0_PHY_TX_EDGERATE_SHIFT 8
    #define SATA0_PHY_TX_CLK_ALIGN_MASK 0x00001000
    #define SATA0_PHY_TX_CLK_ALIGN_SHIFT 12
    #define SATA0_PHY_TX_CKO_ENABLE_MASK 0x00004000
    #define SATA0_PHY_TX_CKO_ENABLE_SHIFT 14
    #define SATA0_PHY_RX_EQ_VAL_MASK 0x00070000
    #define SATA0_PHY_RX_EQ_VAL_SHIFT 16
    #define SATA0_PHY_RX_DPLL_MODE_MASK 0x00700000
    #define SATA0_PHY_RX_DPLL_MODE_SHIFT 20
    #define SATA0_PHY_RX_ALIGN_EN_MASK 0x01000000
    #define SATA0_PHY_RX_ALIGN_EN_SHIFT 24
    #define SATA0_PHY_RX_TERM_EN_MASK 0x02000000
    #define SATA0_PHY_RX_TERM_EN_SHIFT 25
    #define SATA0_PHY_RX_PLL_PWRON_MASK 0x04000000
    #define SATA0_PHY_RX_PLL_PWRON_SHIFT 26
    #define SATA0_PHY_RX_EN_MASK 0x08000000
    #define SATA0_PHY_RX_EN_SHIFT 27
    #define SATA0_PHY_LOS_CTL_MASK 0x30000000
    #define SATA0_PHY_LOS_CTL_SHIFT 28
#define  SATA1_PHY_TXRX_CTRL 0xD040
    #define SATA1_PHY_TX_BOOST_MASK 0x0000000F
    #define SATA1_PHY_TX_BOOST_SHIFT 0
    #define SATA1_PHY_TX_ATTEN_MASK 0x00000070
    #define SATA1_PHY_TX_ATTEN_SHIFT 4
    #define SATA1_PHY_TX_EDGERATE_MASK 0x00000300
    #define SATA1_PHY_TX_EDGERATE_SHIFT 8
    #define SATA1_PHY_TX_CLK_ALIGN_MASK 0x00001000
    #define SATA1_PHY_TX_CLK_ALIGN_SHIFT 12
    #define SATA1_PHY_TX_CKO_ENABLE_MASK 0x00004000
    #define SATA1_PHY_TX_CKO_ENABLE_SHIFT 14
    #define SATA1_PHY_RX_EQ_VAL_MASK 0x00070000
    #define SATA1_PHY_RX_EQ_VAL_SHIFT 16
    #define SATA1_PHY_RX_DPLL_MODE_MASK 0x00700000
    #define SATA1_PHY_RX_DPLL_MODE_SHIFT 20
    #define SATA1_PHY_RX_ALIGN_EN_MASK 0x01000000
    #define SATA1_PHY_RX_ALIGN_EN_SHIFT 24
    #define SATA1_PHY_RX_TERM_EN_MASK 0x02000000
    #define SATA1_PHY_RX_TERM_EN_SHIFT 25
    #define SATA1_PHY_RX_PLL_PWRON_MASK 0x04000000
    #define SATA1_PHY_RX_PLL_PWRON_SHIFT 26
    #define SATA1_PHY_RX_EN_MASK 0x08000000
    #define SATA1_PHY_RX_EN_SHIFT 27
    #define SATA1_PHY_LOS_CTL_MASK 0x30000000
    #define SATA1_PHY_LOS_CTL_SHIFT 28
#define  SATA_AHB_REG_CTRL 0xD000
    #define SATA_REG_ADDR_MASK 0x0000FFFF
    #define SATA_REG_ADDR_SHIFT 0
    #define SATA0_HSEL_MASK 0x00010000
    #define SATA0_HSEL_SHIFT 16
    #define BUS_SIZE_MASK 0x00300000
    #define BUS_SIZE_SHIFT 20
    #define SATA_AHB_REG_CTRL_WOP_MASK 0x80000000
    #define SATA_AHB_REG_CTRL_WOP_SHIFT 31
#define  SATA_AHB_REG_RDAT 0xD00C
    #define SATA_AHB_REG_RDAT_DATA_MASK 0xFFFFFFFF
    #define SATA_AHB_REG_RDAT_DATA_SHIFT 0
#define  SATA_AHB_REG_STATUS 0xD004
    #define SATA_CSR_BUSY_MASK 0x00000001
    #define SATA_CSR_BUSY_SHIFT 0
    #define SATA_CSR_ERR_MASK 0x00000002
    #define SATA_CSR_ERR_SHIFT 1
#define  SATA_AHB_REG_WDAT 0xD008
    #define SATA_AHB_REG_WDAT_DATA_MASK 0xFFFFFFFF
    #define SATA_AHB_REG_WDAT_DATA_SHIFT 0
#define  SATA_CONTROL 0xD014
    #define SATA0_AHBM_MODE_MASK 0x00000001
    #define SATA0_AHBM_MODE_SHIFT 0
    #define SATA0_LPBK_ENABLE_MASK 0x00000002
    #define SATA0_LPBK_ENABLE_SHIFT 1
    #define SATA0_LOCAL_CLK_GATE_MASK 0x00000004
    #define SATA0_LOCAL_CLK_GATE_SHIFT 2
    #define SATA0_PHY_CALIBRATED_MASK 0x00000008
    #define SATA0_PHY_CALIBRATED_SHIFT 3
    #define SATA0_PHY_SPDMODE_MASK 0x00000010
    #define SATA0_PHY_SPDMODE_SHIFT 4
    #define SATA0_AGR_PWM_MASK 0x00000020
    #define SATA0_AGR_PWM_SHIFT 5
    #define SATA0_CONTROL_MASK 0x000000C0
    #define SATA0_CONTROL_SHIFT 6
    #define SATA_RESET_MODE_MASK 0x80000000
    #define SATA_RESET_MODE_SHIFT 31
#define  SATA_HOST_INT_MASK 0xD020
    #define SATA_HOST_INT_MASK_SATA0_AHB_S_MASK 0x00000001
    #define SATA_HOST_INT_MASK_SATA0_AHB_S_SHIFT 0
    #define SATA_HOST_INT_MASK_SATA0_AHB_M_BLOCK_MASK 0x00000002
    #define SATA_HOST_INT_MASK_SATA0_AHB_M_BLOCK_SHIFT 1
    #define SATA_HOST_INT_MASK_SATA0_AHB_M_XFR_MASK 0x00000004
    #define SATA_HOST_INT_MASK_SATA0_AHB_M_XFR_SHIFT 2
    #define SATA_HOST_INT_MASK_SATA0_MASK 0x00000008
    #define SATA_HOST_INT_MASK_SATA0_SHIFT 3
    #define SATA_HOST_INT_MASK_SATA0_SPECIAL_MASK 0x00000010
    #define SATA_HOST_INT_MASK_SATA0_SPECIAL_SHIFT 4
#define  SATA_INT_STATUS 0xD018
    #define SATA_INT_STATUS_SATA0_AHB_S_MASK 0x00000001
    #define SATA_INT_STATUS_SATA0_AHB_S_SHIFT 0
    #define SATA_INT_STATUS_SATA0_AHB_M_BLOCK_MASK 0x00000002
    #define SATA_INT_STATUS_SATA0_AHB_M_BLOCK_SHIFT 1
    #define SATA_INT_STATUS_SATA0_AHB_M_XFR_MASK 0x00000004
    #define SATA_INT_STATUS_SATA0_AHB_M_XFR_SHIFT 2
    #define SATA_INT_STATUS_SATA0_MASK 0x00000008
    #define SATA_INT_STATUS_SATA0_SHIFT 3
    #define SATA_INT_STATUS_SATA0_SPECIAL_MASK 0x00000010
    #define SATA_INT_STATUS_SATA0_SPECIAL_SHIFT 4
#define  SATA_MIPS_INT_MASK 0xD01C
    #define SATA_MIPS_INT_MASK_SATA0_AHB_S_MASK 0x00000001
    #define SATA_MIPS_INT_MASK_SATA0_AHB_S_SHIFT 0
    #define SATA_MIPS_INT_MASK_SATA0_AHB_M_BLOCK_MASK 0x00000002
    #define SATA_MIPS_INT_MASK_SATA0_AHB_M_BLOCK_SHIFT 1
    #define SATA_MIPS_INT_MASK_SATA0_AHB_M_XFR_MASK 0x00000004
    #define SATA_MIPS_INT_MASK_SATA0_AHB_M_XFR_SHIFT 2
    #define SATA_MIPS_INT_MASK_SATA0_MASK 0x00000008
    #define SATA_MIPS_INT_MASK_SATA0_SHIFT 3
    #define SATA_MIPS_INT_MASK_SATA0_SPECIAL_MASK 0x00000010
    #define SATA_MIPS_INT_MASK_SATA0_SPECIAL_SHIFT 4
#define  SATA_PHY_ANALOG_CTRL 0xD048
    #define SATA_PHY_TX_LVL_MASK 0x0000001F
    #define SATA_PHY_TX_LVL_SHIFT 0
    #define SATA_PHY_TEST_BYP_MODE_MASK 0x00000020
    #define SATA_PHY_TEST_BYP_MODE_SHIFT 5
    #define SATA_PHY_TEST_BURNIN_MODE_MASK 0x00000040
    #define SATA_PHY_TEST_BURNIN_MODE_SHIFT 6
    #define SATA_PHY_TEST_PDDQ_MASK 0x00000080
    #define SATA_PHY_TEST_PDDQ_SHIFT 7
    #define SATA_PHY_LOS_LVL_MASK 0x00001F00
    #define SATA_PHY_LOS_LVL_SHIFT 8
    #define SATA_PHY_ACJT_LVL_MASK 0x001F0000
    #define SATA_PHY_ACJT_LVL_SHIFT 16
    #define SATA_PHY_CKO_WORD_CON_MASK 0x07000000
    #define SATA_PHY_CKO_WORD_CON_SHIFT 24
    #define SATA_PHY_CKO_ALIVE_CON_MASK 0x30000000
    #define SATA_PHY_CKO_ALIVE_CON_SHIFT 28
    #define SATA_PHY_WIDE_XFACE_MASK 0x40000000
    #define SATA_PHY_WIDE_XFACE_SHIFT 30
    #define SATA_PHY_RTUNE_DO_TUNE_MASK 0x80000000
    #define SATA_PHY_RTUNE_DO_TUNE_SHIFT 31
#define  SATA_PHY_COMMON_STATUS 0xD034
    #define PHY_SATA0_RX_PLL_STATE_MASK 0x00000001
    #define PHY_SATA0_RX_PLL_STATE_SHIFT 0
    #define PHY_SATA0_RX_VALID_MASK 0x00000002
    #define PHY_SATA0_RX_VALID_SHIFT 1
    #define PHY_SATA0_TXDONE_MASK 0x00000004
    #define PHY_SATA0_TXDONE_SHIFT 2
    #define SATA0_PHY_NEARAFELB_MASK 0x00000008
    #define SATA0_PHY_NEARAFELB_SHIFT 3
    #define SATA0_PHY_FARAFELB_MASK 0x00000010
    #define SATA0_PHY_FARAFELB_SHIFT 4
    #define SATA0_PHY_PARTIAL_MASK 0x00000020
    #define SATA0_PHY_PARTIAL_SHIFT 5
    #define SATA0_PHY_SLUMBER_MASK 0x00000040
    #define SATA0_PHY_SLUMBER_SHIFT 6
    #define SATA0_PHY_ACT_LED_MASK 0x00000080
    #define SATA0_PHY_ACT_LED_SHIFT 7
    #define SATA0_PHY_RX_EN_STAT_MASK 0x00000100
    #define SATA0_PHY_RX_EN_STAT_SHIFT 8
    #define PHY_SATA_DTB_OUT_MASK 0x30000000
    #define PHY_SATA_DTB_OUT_SHIFT 28
    #define PHY_SATA_OP_DONE_MASK 0x40000000
    #define PHY_SATA_OP_DONE_SHIFT 30
    #define PHY_SATA_POWER_GOOD_MASK 0x80000000
    #define PHY_SATA_POWER_GOOD_SHIFT 31
#define  SATA_PHY_CR_IN 0xD050
    #define SATA_PHY_CR_IN_DATA_MASK 0x0000FFFF
    #define SATA_PHY_CR_IN_DATA_SHIFT 0
    #define SATA_PHY_CR_IN_ACK_MASK 0x00010000
    #define SATA_PHY_CR_IN_ACK_SHIFT 16
#define  SATA_PHY_CR_OUT 0xD04C
    #define SATA_PHY_CR_OUT_DATA_MASK 0x0000FFFF
    #define SATA_PHY_CR_OUT_DATA_SHIFT 0
    #define SATA_PHY_CR_OUT_CAP_ADDR_MASK 0x00010000
    #define SATA_PHY_CR_OUT_CAP_ADDR_SHIFT 16
    #define SATA_PHY_CR_OUT_CAP_DATA_MASK 0x00020000
    #define SATA_PHY_CR_OUT_CAP_DATA_SHIFT 17
    #define SATA_PHY_CR_OUT_WRITE_MASK 0x00040000
    #define SATA_PHY_CR_OUT_WRITE_SHIFT 18
    #define SATA_PHY_CR_OUT_READ_MASK 0x00080000
    #define SATA_PHY_CR_OUT_READ_SHIFT 19
#define  SATA_PHY_MPLL_CTRL 0xD044
    #define SATA_PHY_MPLL_PWRON_MASK 0x00000001
    #define SATA_PHY_MPLL_PWRON_SHIFT 0
    #define SATA_PHY_MPLL_PRESCALE_MASK 0x00000006
    #define SATA_PHY_MPLL_PRESCALE_SHIFT 1
    #define SATA_PHY_MPLL_SS_EN_MASK 0x00000008
    #define SATA_PHY_MPLL_SS_EN_SHIFT 3
    #define SATA_PHY_MPLL_NCY_MASK 0x000001F0
    #define SATA_PHY_MPLL_NCY_SHIFT 4
    #define SATA_PHY_MPLL_NCY5_MASK 0x00000600
    #define SATA_PHY_MPLL_NCY5_SHIFT 9
    #define SATA_PHY_MPLL_CK_OFF_MASK 0x00001000
    #define SATA_PHY_MPLL_CK_OFF_SHIFT 12
    #define SATA_PHY_USE_REFCLK_ALT_MASK 0x00002000
    #define SATA_PHY_USE_REFCLK_ALT_SHIFT 13
    #define SATA_PHY_MPLL_INT_CTL_MASK 0x00070000
    #define SATA_PHY_MPLL_INT_CTL_SHIFT 16
    #define SATA_PHY_MPLL_PROP_CTL_MASK 0x00700000
    #define SATA_PHY_MPLL_PROP_CTL_SHIFT 20
#define  SATA_SFT_RESETS 0xD010
    #define PHY_SFT_RSTN_MASK 0x00000001
    #define PHY_SFT_RSTN_SHIFT 0
    #define AHB_SLAVE_SFT_RSTN_MASK 0x00000002
    #define AHB_SLAVE_SFT_RSTN_SHIFT 1
    #define MEM_BUS_SFT_RSTN_MASK 0x00000004
    #define MEM_BUS_SFT_RSTN_SHIFT 2
    #define SATA0_SFT_RSTN_MASK 0x00000010
    #define SATA0_SFT_RSTN_SHIFT 4
    #define SATA0_AHB_MSTR_SFT_RSTN_MASK 0x00000020
    #define SATA0_AHB_MSTR_SFT_RSTN_SHIFT 5
    #define SATA0_AHB_MSTR_SIGDET_SFT_RSTN_EN_MASK 0x40000000
    #define SATA0_AHB_MSTR_SIGDET_SFT_RSTN_EN_SHIFT 30
#define  SBC_BOOT_CTRL 0x058C
    #define SBC_EXTBOOT_MASK 0x00000001
    #define SBC_EXTBOOT_SHIFT 0
    #define SBC_BOOTROM_MASK 0x00000002
    #define SBC_BOOTROM_SHIFT 1
    #define SBC_FLASH_SEL_MASK 0x00000004
    #define SBC_FLASH_SEL_SHIFT 2
#define  SBC_CMD 0x0580
    #define SBC_GO_MASK 0x00000001
    #define SBC_GO_SHIFT 0
    #define SBC_DONE_MASK 0x00000002
    #define SBC_DONE_SHIFT 1
    #define SBC_DIE_MASK 0x00000004
    #define SBC_DIE_SHIFT 2
#define  SBC_CTRL 0x0584
    #define SBC_SIZE_MASK 0x0000FFFF
    #define SBC_SIZE_SHIFT 0
    #define SBC_OFFSET_MASK 0xFFFF0000
    #define SBC_OFFSET_SHIFT 16
#define  SBC_DIAG 0x059C
    #define SBC_STATE_MASK 0x0000000F
    #define SBC_STATE_SHIFT 0
    #define SBC_WDT_FAIL_MASK 0x00000010
    #define SBC_WDT_FAIL_SHIFT 4
#define  SBC_WATCHDOG 0x0588
    #define SBC_WATCHDOG_TIME_MASK 0xFFFFFFFF
    #define SBC_WATCHDOG_TIME_SHIFT 0
#define  SCC0_COMMAND 0x1030
    #define SCC0_COMMAND_COMMAND_MASK 0x00000003
    #define SCC0_COMMAND_COMMAND_SHIFT 0
    #define READ_BYTECNT_MASK 0x00007F00
    #define READ_BYTECNT_SHIFT 8
    #define INT_EN_RDDONE_MASK 0x00008000
    #define INT_EN_RDDONE_SHIFT 15
    #define SCC0_COMMAND_BYTECNT_MASK 0x007F0000
    #define SCC0_COMMAND_BYTECNT_SHIFT 16
    #define INT_EN_WRDONE_MASK 0x00800000
    #define INT_EN_WRDONE_SHIFT 23
    #define READ_BYTECNT_HIGH_MASK 0x03000000
    #define READ_BYTECNT_HIGH_SHIFT 24
    #define BYTECNT_HIGH_MASK 0x30000000
    #define BYTECNT_HIGH_SHIFT 28
#define  SCC0_CONFIG0 0x1020
    #define ETU_VALUE_MASK 0x0000FFFF
    #define ETU_VALUE_SHIFT 0
    #define TPRH_MASK 0xFFFF0000
    #define TPRH_SHIFT 16
#define  SCC0_CONFIG1 0x1024
    #define RX_RETRYCNT_MASK 0x00000003
    #define RX_RETRYCNT_SHIFT 0
    #define TX_RETRYCNT_MASK 0x0000000C
    #define TX_RETRYCNT_SHIFT 2
    #define RX_RETRYEN_MASK 0x00000010
    #define RX_RETRYEN_SHIFT 4
    #define TX_RETRYEN_MASK 0x00000020
    #define TX_RETRYEN_SHIFT 5
    #define TS_MASK 0x00000040
    #define TS_SHIFT 6
    #define SCC0_CONFIG1_PARITY_EN_MASK 0x00000080
    #define SCC0_CONFIG1_PARITY_EN_SHIFT 7
    #define TGUARD_MASK 0x0000FF00
    #define TGUARD_SHIFT 8
    #define CARD_READER_MODE_MASK 0x00030000
    #define CARD_READER_MODE_SHIFT 16
    #define SCC_CHANNEL_MASK 0xC0000000
    #define SCC_CHANNEL_SHIFT 30
#define  SCC0_DATA_LOAD 0x1028
    #define DATA_LOAD_MASK 0x000000FF
    #define DATA_LOAD_SHIFT 0
#define  SCC0_DATA_READ 0x102C
    #define DATA_READ_MASK 0x000000FF
    #define DATA_READ_SHIFT 0
#define  SCC0_STATUS 0x1034
    #define BYTEXFERED_MASK 0x0000007F
    #define BYTEXFERED_SHIFT 0
    #define CARD_PRESENT_MASK 0x00000100
    #define CARD_PRESENT_SHIFT 8
    #define SCC0_STATUS_ACTIVE_MASK 0x00000200
    #define SCC0_STATUS_ACTIVE_SHIFT 9
    #define BYTEXFERED_HIGH_MASK 0x00003000
    #define BYTEXFERED_HIGH_SHIFT 12
#define  SCC_CLOCK_CTRL 0x1080
    #define HIGH_DUR_MASK 0x000000FF
    #define HIGH_DUR_SHIFT 0
    #define LOW_DUR_MASK 0x00FF0000
    #define LOW_DUR_SHIFT 16
    #define STOP_MASK 0x80000000
    #define STOP_SHIFT 31
#define  SCL_BOT_CR_WR_ADR 0x73A8
    #define SCL_BOT_CR_WR_ADR_BASE_MASK 0x7FFFFFC0
    #define SCL_BOT_CR_WR_ADR_BASE_SHIFT 6
#define  SCL_BOT_C_WR_ADR 0x73A4
    #define SCL_BOT_C_WR_ADR_BASE_MASK 0x7FFFFFC0
    #define SCL_BOT_C_WR_ADR_BASE_SHIFT 6
#define  SCL_BOT_Y_WR_ADR 0x73A0
    #define SCL_BOT_Y_WR_ADR_BASE_MASK 0x7FFFFFC0
    #define SCL_BOT_Y_WR_ADR_BASE_SHIFT 6
#define  SCL_CR_RD_ADR 0x739C
    #define SCL_CR_RD_ADR_BASE_MASK 0x7FFFFFC0
    #define SCL_CR_RD_ADR_BASE_SHIFT 6
#define  SCL_CR_WR_ADR 0x7398
    #define SCL_CR_WR_ADR_BASE_MASK 0x7FFFFFC0
    #define SCL_CR_WR_ADR_BASE_SHIFT 6
#define  SCL_C_RD_ADR 0x7394
    #define SCL_C_RD_ADR_BASE_MASK 0x7FFFFFC0
    #define SCL_C_RD_ADR_BASE_SHIFT 6
#define  SCL_C_WR_ADR 0x738C
    #define SCL_C_WR_ADR_BASE_MASK 0x7FFFFFC0
    #define SCL_C_WR_ADR_BASE_SHIFT 6
#define  SCL_HORI_CTRL 0x736C
    #define SCL_HORI_CTRL_SCALE_EN_MASK 0x00000001
    #define SCL_HORI_CTRL_SCALE_EN_SHIFT 0
    #define SCL_HORI_CTRL_UCODE_VCNT_MASK 0x0000007E
    #define SCL_HORI_CTRL_UCODE_VCNT_SHIFT 1
    #define SCL_HORI_CTRL_INV_DIV_MASK 0xFFFF0000
    #define SCL_HORI_CTRL_INV_DIV_SHIFT 16
#define  SCL_HORI_UCODE 0x7204
    #define SCL_HORI_UCODE_HORI0_UCODE_MASK 0x000000FF
    #define SCL_HORI_UCODE_HORI0_UCODE_SHIFT 0
    #define SCL_HORI_UCODE_HORI1_UCODE_MASK 0x0000FF00
    #define SCL_HORI_UCODE_HORI1_UCODE_SHIFT 8
    #define SCL_HORI_UCODE_HORI2_UCODE_MASK 0x00FF0000
    #define SCL_HORI_UCODE_HORI2_UCODE_SHIFT 16
    #define SCL_HORI_UCODE_HORI3_UCODE_MASK 0xFF000000
    #define SCL_HORI_UCODE_HORI3_UCODE_SHIFT 24
#define  SCL_INT 0x74DC
    #define SCL_INTERRUPT_MASK 0x00000001
    #define SCL_INTERRUPT_SHIFT 0
#define  SCL_INT_CTRL 0x74E0
    #define SCL_INT_MIPS_EN_MASK 0x00000001
    #define SCL_INT_MIPS_EN_SHIFT 0
    #define SCL_INT_HOST_EN_MASK 0x00000002
    #define SCL_INT_HOST_EN_SHIFT 1
#define  SCL_PICT_RD_SIZE 0x7360
    #define SCL_PICT_RD_SIZE_SLICE_RD_SIZE_MASK 0x0000007F
    #define SCL_PICT_RD_SIZE_SLICE_RD_SIZE_SHIFT 0
    #define SCL_PICT_RD_SIZE_SLICE_RD_CNT_MASK 0x00007F00
    #define SCL_PICT_RD_SIZE_SLICE_RD_CNT_SHIFT 8
#define  SCL_PICT_WR_SIZE 0x7364
    #define SCL_PICT_WR_SIZE_SLICE_WR_SIZE_MASK 0x0000007F
    #define SCL_PICT_WR_SIZE_SLICE_WR_SIZE_SHIFT 0
    #define SCL_PICT_WR_SIZE_SLICE_WR_CNT_MASK 0x00007F00
    #define SCL_PICT_WR_SIZE_SLICE_WR_CNT_SHIFT 8
#define  SCL_SLICE_CNT 0x7218
    #define TOP_FIELD_MASK 0x000000FF
    #define TOP_FIELD_SHIFT 0
    #define BOT_FIELD_MASK 0x0000FF00
    #define BOT_FIELD_SHIFT 8
    #define SCL_SLICE_CNT_FIELD_SCALE_MASK 0x80000000
    #define SCL_SLICE_CNT_FIELD_SCALE_SHIFT 31
#define  SCL_SURF_RD_SIZE 0x73DC
    #define SCL_RD_PITCH_MASK 0x00000FC0
    #define SCL_RD_PITCH_SHIFT 6
#define  SCL_SURF_WR_SIZE 0x7368
    #define SCL_WR_PITCH_MASK 0x00000FC0
    #define SCL_WR_PITCH_SHIFT 6
#define  SCL_TRIG 0x730C
    #define SCL_TRIG_COLBITS_OVERRIDE_MASK 0x00000001
    #define SCL_TRIG_COLBITS_OVERRIDE_SHIFT 0
    #define SCL_TRIG_COLBITS_RD_VALUE_MASK 0x000000F0
    #define SCL_TRIG_COLBITS_RD_VALUE_SHIFT 4
    #define SCL_TRIG_COLBITS_WR_VALUE_MASK 0x00000F00
    #define SCL_TRIG_COLBITS_WR_VALUE_SHIFT 8
    #define SCL_TRIG_FORCE_RD_ONLY_MASK 0x00010000
    #define SCL_TRIG_FORCE_RD_ONLY_SHIFT 16
    #define SCL_TRIG_FIELD_SCALE_MASK 0x00100000
    #define SCL_TRIG_FIELD_SCALE_SHIFT 20
    #define COMBINE_FIELDS_MASK 0x00200000
    #define COMBINE_FIELDS_SHIFT 21
    #define SCL_TRIG_RD_8X8_MASK 0x00800000
    #define SCL_TRIG_RD_8X8_SHIFT 23
    #define SCL_TRIG_RD_LINEAR_MASK 0x01000000
    #define SCL_TRIG_RD_LINEAR_SHIFT 24
    #define SCL_TRIG_WR_LINEAR_MASK 0x02000000
    #define SCL_TRIG_WR_LINEAR_SHIFT 25
    #define SCL_RD_EN_MASK 0x08000000
    #define SCL_RD_EN_SHIFT 27
    #define SCL_TRIG_SCL_EN_MASK 0x10000000
    #define SCL_TRIG_SCL_EN_SHIFT 28
    #define OUT_MODE_MASK 0x20000000
    #define OUT_MODE_SHIFT 29
    #define SCL_TRIG_SKIP_FLD_EN_MASK 0x40000000
    #define SCL_TRIG_SKIP_FLD_EN_SHIFT 30
    #define SCL_TRIG_FLD_SEL_MASK 0x80000000
    #define SCL_TRIG_FLD_SEL_SHIFT 31
#define  SCL_UCODE_IDX 0x7200
    #define SCL_UCODE_IDX_HORI_IDX_MASK 0x0000000F
    #define SCL_UCODE_IDX_HORI_IDX_SHIFT 0
    #define SCL_UCODE_IDX_VERT_IDX_MASK 0x000F0000
    #define SCL_UCODE_IDX_VERT_IDX_SHIFT 16
    #define SCL_UCODE_IDX_VERT_BOT_IDX_MASK 0x00F00000
    #define SCL_UCODE_IDX_VERT_BOT_IDX_SHIFT 20
#define  SCL_VAR_ADR 0x7214
    #define SCL_VAR_ADR_BASE_MASK 0x7FFFFFC0
    #define SCL_VAR_ADR_BASE_SHIFT 6
#define  SCL_VAR_CTRL 0x7210
    #define SCL_VAR_EN_MASK 0x00000001
    #define SCL_VAR_EN_SHIFT 0
    #define SCL_VAR_FLD_DIS_MASK 0x00000002
    #define SCL_VAR_FLD_DIS_SHIFT 1
#define  SCL_VERT_BOT_CTRL 0x73AC
    #define SCL_VERT_BOT_CTRL_SCALE_EN_MASK 0x00000001
    #define SCL_VERT_BOT_CTRL_SCALE_EN_SHIFT 0
    #define SCL_VERT_BOT_CTRL_UCODE_VCNT_MASK 0x0000007E
    #define SCL_VERT_BOT_CTRL_UCODE_VCNT_SHIFT 1
    #define SCL_VERT_BOT_CTRL_INV_DIV_MASK 0xFFFF0000
    #define SCL_VERT_BOT_CTRL_INV_DIV_SHIFT 16
#define  SCL_VERT_BOT_UCODE 0x720C
    #define SCL_VERT_BOT_UCODE_VERT0_BOT_UCODE_MASK 0x000000FF
    #define SCL_VERT_BOT_UCODE_VERT0_BOT_UCODE_SHIFT 0
    #define SCL_VERT_BOT_UCODE_VERT1_BOT_UCODE_MASK 0x0000FF00
    #define SCL_VERT_BOT_UCODE_VERT1_BOT_UCODE_SHIFT 8
    #define SCL_VERT_BOT_UCODE_VERT2_BOT_UCODE_MASK 0x00FF0000
    #define SCL_VERT_BOT_UCODE_VERT2_BOT_UCODE_SHIFT 16
    #define SCL_VERT_BOT_UCODE_VERT3_BOT_UCODE_MASK 0xFF000000
    #define SCL_VERT_BOT_UCODE_VERT3_BOT_UCODE_SHIFT 24
#define  SCL_VERT_CTRL 0x7370
    #define SCL_VERT_CTRL_SCALE_EN_MASK 0x00000001
    #define SCL_VERT_CTRL_SCALE_EN_SHIFT 0
    #define SCL_VERT_CTRL_UCODE_VCNT_MASK 0x0000007E
    #define SCL_VERT_CTRL_UCODE_VCNT_SHIFT 1
    #define SCL_VERT_CTRL_INV_DIV_MASK 0xFFFF0000
    #define SCL_VERT_CTRL_INV_DIV_SHIFT 16
#define  SCL_VERT_UCODE 0x7208
    #define SCL_VERT_UCODE_VERT0_UCODE_MASK 0x000000FF
    #define SCL_VERT_UCODE_VERT0_UCODE_SHIFT 0
    #define SCL_VERT_UCODE_VERT1_UCODE_MASK 0x0000FF00
    #define SCL_VERT_UCODE_VERT1_UCODE_SHIFT 8
    #define SCL_VERT_UCODE_VERT2_UCODE_MASK 0x00FF0000
    #define SCL_VERT_UCODE_VERT2_UCODE_SHIFT 16
    #define SCL_VERT_UCODE_VERT3_UCODE_MASK 0xFF000000
    #define SCL_VERT_UCODE_VERT3_UCODE_SHIFT 24
#define  SCL_Y_RD_ADR 0x7390
    #define SCL_Y_RD_ADR_BASE_MASK 0x7FFFFFC0
    #define SCL_Y_RD_ADR_BASE_SHIFT 6
#define  SCL_Y_WR_ADR 0x7388
    #define SCL_Y_WR_ADR_BASE_MASK 0x7FFFFFC0
    #define SCL_Y_WR_ADR_BASE_SHIFT 6
#define  SCR_APB_CTRL 0x112C
    #define SCR_APB_IDLE_MASK 0x00000001
    #define SCR_APB_IDLE_SHIFT 0
    #define SCR_APB_WOP_MASK 0x00000002
    #define SCR_APB_WOP_SHIFT 1
    #define SCR_APB_ADDR_MASK 0x000003FC
    #define SCR_APB_ADDR_SHIFT 2
#define  SCR_APB_RDATA 0x1128
    #define SCR_APB_RDATA_MASK 0x0000FFFF
    #define SCR_APB_RDATA_SHIFT 0
#define  SCR_APB_WDATA 0x1124
    #define SCR_APB_WDATA_MASK 0x0000FFFF
    #define SCR_APB_WDATA_SHIFT 0
#define  SCS0_FIND_START_CODE 0xA100
    #define SCS0_FIND_START_CODE_DONE_MASK 0x00000001
    #define SCS0_FIND_START_CODE_DONE_SHIFT 0
    #define SCS0_FIND_START_CODE_ERROR_MASK 0x00000002
    #define SCS0_FIND_START_CODE_ERROR_SHIFT 1
#define  SCS1_FIND_START_CODE 0xA500
    #define SCS1_FIND_START_CODE_DONE_MASK 0x00000001
    #define SCS1_FIND_START_CODE_DONE_SHIFT 0
    #define SCS1_FIND_START_CODE_ERROR_MASK 0x00000002
    #define SCS1_FIND_START_CODE_ERROR_SHIFT 1
#define  SEQ_CH0_ACTIVE_CNT 0xC034
    #define SEQ_CH0_ACTIVE_CNT_REG_MASK 0xFFFFFFFF
    #define SEQ_CH0_ACTIVE_CNT_REG_SHIFT 0
#define  SEQ_CH0_ADDRMAP0 0xC060
    #define SEQ_CH0_ADDRMAP0_BANK_B0_MASK 0x0000000F
    #define SEQ_CH0_ADDRMAP0_BANK_B0_SHIFT 0
    #define SEQ_CH0_ADDRMAP0_BANK_B1_MASK 0x000000F0
    #define SEQ_CH0_ADDRMAP0_BANK_B1_SHIFT 4
    #define SEQ_CH0_ADDRMAP0_BANK_B2_MASK 0x00000F00
    #define SEQ_CH0_ADDRMAP0_BANK_B2_SHIFT 8
#define  SEQ_CH0_ADDRMAP1 0xC064
    #define SEQ_CH0_ADDRMAP1_COL_B2_MASK 0x0000000F
    #define SEQ_CH0_ADDRMAP1_COL_B2_SHIFT 0
    #define SEQ_CH0_ADDRMAP1_COL_B3_MASK 0x000000F0
    #define SEQ_CH0_ADDRMAP1_COL_B3_SHIFT 4
    #define SEQ_CH0_ADDRMAP1_COL_B4_6_MASK 0x00000F00
    #define SEQ_CH0_ADDRMAP1_COL_B4_6_SHIFT 8
    #define SEQ_CH0_ADDRMAP1_COL_B7_MASK 0x0000F000
    #define SEQ_CH0_ADDRMAP1_COL_B7_SHIFT 12
    #define SEQ_CH0_ADDRMAP1_COL_B8_MASK 0x000F0000
    #define SEQ_CH0_ADDRMAP1_COL_B8_SHIFT 16
    #define SEQ_CH0_ADDRMAP1_COL_B9_MASK 0x00F00000
    #define SEQ_CH0_ADDRMAP1_COL_B9_SHIFT 20
    #define SEQ_CH0_ADDRMAP1_COL_B10_MASK 0x0F000000
    #define SEQ_CH0_ADDRMAP1_COL_B10_SHIFT 24
    #define SEQ_CH0_ADDRMAP1_COL_B11_MASK 0xF0000000
    #define SEQ_CH0_ADDRMAP1_COL_B11_SHIFT 28
#define  SEQ_CH0_ADDRMAP2 0xC068
    #define SEQ_CH0_ADDRMAP2_ROW_B0_MASK 0x0000000F
    #define SEQ_CH0_ADDRMAP2_ROW_B0_SHIFT 0
    #define SEQ_CH0_ADDRMAP2_ROW_B1_MASK 0x000000F0
    #define SEQ_CH0_ADDRMAP2_ROW_B1_SHIFT 4
    #define SEQ_CH0_ADDRMAP2_ROW_B2_11_MASK 0x00000F00
    #define SEQ_CH0_ADDRMAP2_ROW_B2_11_SHIFT 8
    #define SEQ_CH0_ADDRMAP2_ROW_B12_MASK 0x0000F000
    #define SEQ_CH0_ADDRMAP2_ROW_B12_SHIFT 12
    #define SEQ_CH0_ADDRMAP2_ROW_B13_MASK 0x000F0000
    #define SEQ_CH0_ADDRMAP2_ROW_B13_SHIFT 16
    #define SEQ_CH0_ADDRMAP2_ROW_B14_MASK 0x00F00000
    #define SEQ_CH0_ADDRMAP2_ROW_B14_SHIFT 20
    #define SEQ_CH0_ADDRMAP2_ROW_B15_MASK 0x0F000000
    #define SEQ_CH0_ADDRMAP2_ROW_B15_SHIFT 24
#define  SEQ_CH0_CYCLE_CNT 0xC030
    #define SEQ_CH0_CYCLE_CNT_REG_MASK 0xFFFFFFFF
    #define SEQ_CH0_CYCLE_CNT_REG_SHIFT 0
#define  SEQ_CH0_DEBUG_BUS 0xC00C
    #define SEQ_CH0_DEBUG_BUS_REG_MASK 0xFFFFFFFF
    #define SEQ_CH0_DEBUG_BUS_REG_SHIFT 0
#define  SEQ_CH0_DIRECTIF_UNLOCK_RANGE 0xC040
    #define SEQ_CH0_DIRECTIF_UNLOCK_RANGE_START_ADDR_MASK 0x000007FF
    #define SEQ_CH0_DIRECTIF_UNLOCK_RANGE_START_ADDR_SHIFT 0
    #define SEQ_CH0_DIRECTIF_UNLOCK_RANGE_END_ADDR_MASK 0x07FF0000
    #define SEQ_CH0_DIRECTIF_UNLOCK_RANGE_END_ADDR_SHIFT 16
#define  SEQ_CH0_DLL 0xC0A8
    #define SEQ_CH0_DLL_CALIB_MIN_X1024_MASK 0x000000FF
    #define SEQ_CH0_DLL_CALIB_MIN_X1024_SHIFT 0
    #define SEQ_CH0_DLL_CALIB_MAX_X1024_MASK 0x0000FF00
    #define SEQ_CH0_DLL_CALIB_MAX_X1024_SHIFT 8
    #define SEQ_CH0_DLL_DIS_DLL_CALIB_MASK 0x40000000
    #define SEQ_CH0_DLL_DIS_DLL_CALIB_SHIFT 30
    #define SEQ_CH0_DLL_DO_CALIB_MASK 0x80000000
    #define SEQ_CH0_DLL_DO_CALIB_SHIFT 31
#define  SEQ_CH0_DRAM_BIST 0xC010
    #define SEQ_CH0_DRAM_BIST_REQ_SIZE_MASK 0x00000003
    #define SEQ_CH0_DRAM_BIST_REQ_SIZE_SHIFT 0
    #define SEQ_CH0_DRAM_BIST_REQ_WOP_MASK 0x0000000C
    #define SEQ_CH0_DRAM_BIST_REQ_WOP_SHIFT 2
    #define SEQ_CH0_DRAM_BIST_REQ_COUNT_MASK 0x000003F0
    #define SEQ_CH0_DRAM_BIST_REQ_COUNT_SHIFT 4
    #define SEQ_CH0_DRAM_BIST_REQ_ADR_MASK 0x00001000
    #define SEQ_CH0_DRAM_BIST_REQ_ADR_SHIFT 12
    #define SEQ_CH0_DRAM_BIST_RNDM_DAT_MASK 0x00002000
    #define SEQ_CH0_DRAM_BIST_RNDM_DAT_SHIFT 13
    #define SEQ_CH0_DRAM_BIST_RNDM_DAT_CNTR_MASK 0x00004000
    #define SEQ_CH0_DRAM_BIST_RNDM_DAT_CNTR_SHIFT 14
    #define SEQ_CH0_DRAM_BIST_RNDM_WBE_MASK 0x00008000
    #define SEQ_CH0_DRAM_BIST_RNDM_WBE_SHIFT 15
    #define SEQ_CH0_DRAM_BIST_DBIST_STOP_MASK 0x00010000
    #define SEQ_CH0_DRAM_BIST_DBIST_STOP_SHIFT 16
    #define SEQ_CH0_DRAM_BIST_DUMP_ERR_DAT_MASK 0x00020000
    #define SEQ_CH0_DRAM_BIST_DUMP_ERR_DAT_SHIFT 17
#define  SEQ_CH0_DUMMY_REG 0xC000
    #define SEQ_CH0_DUMMY_REG_REG_MASK 0xFFFFFFFF
    #define SEQ_CH0_DUMMY_REG_REG_SHIFT 0
#define  SEQ_CH0_FPGA_CTRL 0xC300
    #define SEQ_CH0_FPGA_CTRL_EN_SCRAMBLE_MASK 0x00000001
    #define SEQ_CH0_FPGA_CTRL_EN_SCRAMBLE_SHIFT 0
    #define SEQ_CH0_FPGA_CTRL_SBC_ACTIVE_MASK 0x00000002
    #define SEQ_CH0_FPGA_CTRL_SBC_ACTIVE_SHIFT 1
#define  SEQ_CH0_INIT0 0xC07C
    #define SEQ_CH0_INIT0_PRE_CKE_X1024_MASK 0x000000FF
    #define SEQ_CH0_INIT0_PRE_CKE_X1024_SHIFT 0
    #define SEQ_CH0_INIT0_POST_CKE_X1024_MASK 0x0000FF00
    #define SEQ_CH0_INIT0_POST_CKE_X1024_SHIFT 8
    #define SEQ_CH0_INIT0_PRE_OCD_X32_MASK 0x000F0000
    #define SEQ_CH0_INIT0_PRE_OCD_X32_SHIFT 16
    #define SEQ_CH0_INIT0_FINAL_WAIT_X32_MASK 0x07F00000
    #define SEQ_CH0_INIT0_FINAL_WAIT_X32_SHIFT 20
    #define SEQ_CH0_INIT0_SKIP_OCD_INIT_MASK 0x80000000
    #define SEQ_CH0_INIT0_SKIP_OCD_INIT_SHIFT 31
#define  SEQ_CH0_INIT1 0xC080
    #define SEQ_CH0_INIT1_DRAM_RSTN_X1024_MASK 0x000000FF
    #define SEQ_CH0_INIT1_DRAM_RSTN_X1024_SHIFT 0
#define  SEQ_CH0_INIT2 0xC084
    #define SEQ_CH0_INIT2_MR_MASK 0x0000FFFF
    #define SEQ_CH0_INIT2_MR_SHIFT 0
    #define SEQ_CH0_INIT2_EMR_MASK 0xFFFF0000
    #define SEQ_CH0_INIT2_EMR_SHIFT 16
#define  SEQ_CH0_INIT3 0xC088
    #define SEQ_CH0_INIT3_EMR2_MASK 0x0000FFFF
    #define SEQ_CH0_INIT3_EMR2_SHIFT 0
    #define SEQ_CH0_INIT3_EMR3_MASK 0xFFFF0000
    #define SEQ_CH0_INIT3_EMR3_SHIFT 16
#define  SEQ_CH0_IOCALIB_CTRL 0xC260
    #define SEQ_CH0_IOCALIB_CTRL_CUSTOM_PCAL150_MASK 0x0000000F
    #define SEQ_CH0_IOCALIB_CTRL_CUSTOM_PCAL150_SHIFT 0
    #define SEQ_CH0_IOCALIB_CTRL_CUSTOM_NCAL150_MASK 0x000000F0
    #define SEQ_CH0_IOCALIB_CTRL_CUSTOM_NCAL150_SHIFT 4
    #define SEQ_CH0_IOCALIB_CTRL_CUSTOM_PCAL240_MASK 0x00000F00
    #define SEQ_CH0_IOCALIB_CTRL_CUSTOM_PCAL240_SHIFT 8
    #define SEQ_CH0_IOCALIB_CTRL_CUSTOM_NCAL240_MASK 0x0000F000
    #define SEQ_CH0_IOCALIB_CTRL_CUSTOM_NCAL240_SHIFT 12
    #define SEQ_CH0_IOCALIB_CTRL_CUSTOM_CALIB_MASK 0x00010000
    #define SEQ_CH0_IOCALIB_CTRL_CUSTOM_CALIB_SHIFT 16
    #define SEQ_CH0_IOCALIB_CTRL_START_CALIB_MASK 0x00020000
    #define SEQ_CH0_IOCALIB_CTRL_START_CALIB_SHIFT 17
    #define SEQ_CH0_IOCALIB_CTRL_DDR2_MODE_MASK 0x00040000
    #define SEQ_CH0_IOCALIB_CTRL_DDR2_MODE_SHIFT 18
    #define SEQ_CH0_IOCALIB_CTRL_POWERDOWN_MODE_MASK 0x00080000
    #define SEQ_CH0_IOCALIB_CTRL_POWERDOWN_MODE_SHIFT 19
    #define SEQ_CH0_IOCALIB_CTRL_CODE_MOD_EN_MASK 0x00100000
    #define SEQ_CH0_IOCALIB_CTRL_CODE_MOD_EN_SHIFT 20
    #define SEQ_CH0_IOCALIB_CTRL_CODE_MOD_VAL_MASK 0x00600000
    #define SEQ_CH0_IOCALIB_CTRL_CODE_MOD_VAL_SHIFT 21
#define  SEQ_CH0_IOCALIB_STATUS 0xC264
    #define SEQ_CH0_IOCALIB_STATUS_CALIB_VAL_PCAL150_MASK 0x0000000F
    #define SEQ_CH0_IOCALIB_STATUS_CALIB_VAL_PCAL150_SHIFT 0
    #define SEQ_CH0_IOCALIB_STATUS_CALIB_VAL_NCAL150_MASK 0x000000F0
    #define SEQ_CH0_IOCALIB_STATUS_CALIB_VAL_NCAL150_SHIFT 4
    #define SEQ_CH0_IOCALIB_STATUS_CALIB_VAL_PCAL240_MASK 0x00000F00
    #define SEQ_CH0_IOCALIB_STATUS_CALIB_VAL_PCAL240_SHIFT 8
    #define SEQ_CH0_IOCALIB_STATUS_CALIB_VAL_NCAL240_MASK 0x0000F000
    #define SEQ_CH0_IOCALIB_STATUS_CALIB_VAL_NCAL240_SHIFT 12
    #define SEQ_CH0_IOCALIB_STATUS_DETECT_CNT_PCAL150_MASK 0x000F0000
    #define SEQ_CH0_IOCALIB_STATUS_DETECT_CNT_PCAL150_SHIFT 16
    #define SEQ_CH0_IOCALIB_STATUS_DETECT_CNT_NCAL150_MASK 0x00F00000
    #define SEQ_CH0_IOCALIB_STATUS_DETECT_CNT_NCAL150_SHIFT 20
    #define SEQ_CH0_IOCALIB_STATUS_DETECT_CNT_PCAL240_MASK 0x0F000000
    #define SEQ_CH0_IOCALIB_STATUS_DETECT_CNT_PCAL240_SHIFT 24
    #define SEQ_CH0_IOCALIB_STATUS_DETECT_CNT_NCAL240_MASK 0xF0000000
    #define SEQ_CH0_IOCALIB_STATUS_DETECT_CNT_NCAL240_SHIFT 28
#define  SEQ_CH0_IO_ADR_A 0xC240
    #define SEQ_CH0_IO_ADR_A_DDR2_MODE_MASK 0x00000001
    #define SEQ_CH0_IO_ADR_A_DDR2_MODE_SHIFT 0
    #define SEQ_CH0_IO_ADR_A_RD_ODT_VAL_MASK 0x0000000E
    #define SEQ_CH0_IO_ADR_A_RD_ODT_VAL_SHIFT 1
    #define SEQ_CH0_IO_ADR_A_DRV_STRENGTH_MASK 0x00000070
    #define SEQ_CH0_IO_ADR_A_DRV_STRENGTH_SHIFT 4
    #define SEQ_CH0_IO_ADR_A_DRVR_DLAY_MASK 0x00000700
    #define SEQ_CH0_IO_ADR_A_DRVR_DLAY_SHIFT 8
    #define SEQ_CH0_IO_ADR_A_DRVR_DUTY_MASK 0x00007000
    #define SEQ_CH0_IO_ADR_A_DRVR_DUTY_SHIFT 12
    #define SEQ_CH0_IO_ADR_A_RCVR_DUTY_MASK 0x00070000
    #define SEQ_CH0_IO_ADR_A_RCVR_DUTY_SHIFT 16
    #define SEQ_CH0_IO_ADR_A_RCVR_DIFEN_MASK 0x00F00000
    #define SEQ_CH0_IO_ADR_A_RCVR_DIFEN_SHIFT 20
    #define SEQ_CH0_IO_ADR_A_RCVR_DIFFDDR2_MASK 0x01000000
    #define SEQ_CH0_IO_ADR_A_RCVR_DIFFDDR2_SHIFT 24
    #define SEQ_CH0_IO_ADR_A_VREF_MUX_MASK 0x06000000
    #define SEQ_CH0_IO_ADR_A_VREF_MUX_SHIFT 25
    #define SEQ_CH0_IO_ADR_A_DODT_EN_MASK 0x10000000
    #define SEQ_CH0_IO_ADR_A_DODT_EN_SHIFT 28
    #define SEQ_CH0_IO_ADR_A_DODT_VAL_MASK 0x60000000
    #define SEQ_CH0_IO_ADR_A_DODT_VAL_SHIFT 29
#define  SEQ_CH0_IO_ADR_B 0xC244
    #define SEQ_CH0_IO_ADR_B_DRVR_SR_EN_MASK 0x0000001F
    #define SEQ_CH0_IO_ADR_B_DRVR_SR_EN_SHIFT 0
    #define SEQ_CH0_IO_ADR_B_DRVR_PEMPH_EN_MASK 0x00000F00
    #define SEQ_CH0_IO_ADR_B_DRVR_PEMPH_EN_SHIFT 8
    #define SEQ_CH0_IO_ADR_B_TRANSMIT_EN_MASK 0x00001000
    #define SEQ_CH0_IO_ADR_B_TRANSMIT_EN_SHIFT 12
    #define SEQ_CH0_IO_ADR_B_RCVR_CMOS_EN_MASK 0x00002000
    #define SEQ_CH0_IO_ADR_B_RCVR_CMOS_EN_SHIFT 13
    #define SEQ_CH0_IO_ADR_B_RCVR_TEN_MASK 0x00004000
    #define SEQ_CH0_IO_ADR_B_RCVR_TEN_SHIFT 14
#define  SEQ_CH0_IO_CLK_A 0xC250
    #define SEQ_CH0_IO_CLK_A_DDR2_MODE_MASK 0x00000001
    #define SEQ_CH0_IO_CLK_A_DDR2_MODE_SHIFT 0
    #define SEQ_CH0_IO_CLK_A_RD_ODT_VAL_MASK 0x0000000E
    #define SEQ_CH0_IO_CLK_A_RD_ODT_VAL_SHIFT 1
    #define SEQ_CH0_IO_CLK_A_DRV_STRENGTH_MASK 0x00000070
    #define SEQ_CH0_IO_CLK_A_DRV_STRENGTH_SHIFT 4
    #define SEQ_CH0_IO_CLK_A_DRVR_DLAY_MASK 0x00000700
    #define SEQ_CH0_IO_CLK_A_DRVR_DLAY_SHIFT 8
    #define SEQ_CH0_IO_CLK_A_DRVR_DUTY_MASK 0x00007000
    #define SEQ_CH0_IO_CLK_A_DRVR_DUTY_SHIFT 12
    #define SEQ_CH0_IO_CLK_A_RCVR_DUTY_MASK 0x00070000
    #define SEQ_CH0_IO_CLK_A_RCVR_DUTY_SHIFT 16
    #define SEQ_CH0_IO_CLK_A_RCVR_DIFEN_MASK 0x00F00000
    #define SEQ_CH0_IO_CLK_A_RCVR_DIFEN_SHIFT 20
    #define SEQ_CH0_IO_CLK_A_RCVR_DIFFDDR2_MASK 0x01000000
    #define SEQ_CH0_IO_CLK_A_RCVR_DIFFDDR2_SHIFT 24
    #define SEQ_CH0_IO_CLK_A_VREF_MUX_MASK 0x06000000
    #define SEQ_CH0_IO_CLK_A_VREF_MUX_SHIFT 25
    #define SEQ_CH0_IO_CLK_A_DODT_EN_MASK 0x10000000
    #define SEQ_CH0_IO_CLK_A_DODT_EN_SHIFT 28
    #define SEQ_CH0_IO_CLK_A_DODT_VAL_MASK 0x60000000
    #define SEQ_CH0_IO_CLK_A_DODT_VAL_SHIFT 29
#define  SEQ_CH0_IO_CLK_B 0xC254
    #define SEQ_CH0_IO_CLK_B_DRVR_SR_EN_MASK 0x0000001F
    #define SEQ_CH0_IO_CLK_B_DRVR_SR_EN_SHIFT 0
    #define SEQ_CH0_IO_CLK_B_DRVR_PEMPH_EN_MASK 0x00000F00
    #define SEQ_CH0_IO_CLK_B_DRVR_PEMPH_EN_SHIFT 8
    #define SEQ_CH0_IO_CLK_B_TRANSMIT_EN_MASK 0x00001000
    #define SEQ_CH0_IO_CLK_B_TRANSMIT_EN_SHIFT 12
    #define SEQ_CH0_IO_CLK_B_RCVR_CMOS_EN_MASK 0x00002000
    #define SEQ_CH0_IO_CLK_B_RCVR_CMOS_EN_SHIFT 13
#define  SEQ_CH0_IO_CMD_A 0xC248
    #define SEQ_CH0_IO_CMD_A_DDR2_MODE_MASK 0x00000001
    #define SEQ_CH0_IO_CMD_A_DDR2_MODE_SHIFT 0
    #define SEQ_CH0_IO_CMD_A_RD_ODT_VAL_MASK 0x0000000E
    #define SEQ_CH0_IO_CMD_A_RD_ODT_VAL_SHIFT 1
    #define SEQ_CH0_IO_CMD_A_DRV_STRENGTH_MASK 0x00000070
    #define SEQ_CH0_IO_CMD_A_DRV_STRENGTH_SHIFT 4
    #define SEQ_CH0_IO_CMD_A_DRVR_DLAY_MASK 0x00000700
    #define SEQ_CH0_IO_CMD_A_DRVR_DLAY_SHIFT 8
    #define SEQ_CH0_IO_CMD_A_DRVR_DUTY_MASK 0x00007000
    #define SEQ_CH0_IO_CMD_A_DRVR_DUTY_SHIFT 12
    #define SEQ_CH0_IO_CMD_A_RCVR_DUTY_MASK 0x00070000
    #define SEQ_CH0_IO_CMD_A_RCVR_DUTY_SHIFT 16
    #define SEQ_CH0_IO_CMD_A_RCVR_DIFEN_MASK 0x00F00000
    #define SEQ_CH0_IO_CMD_A_RCVR_DIFEN_SHIFT 20
    #define SEQ_CH0_IO_CMD_A_RCVR_DIFFDDR2_MASK 0x01000000
    #define SEQ_CH0_IO_CMD_A_RCVR_DIFFDDR2_SHIFT 24
    #define SEQ_CH0_IO_CMD_A_VREF_MUX_MASK 0x06000000
    #define SEQ_CH0_IO_CMD_A_VREF_MUX_SHIFT 25
    #define SEQ_CH0_IO_CMD_A_DODT_EN_MASK 0x10000000
    #define SEQ_CH0_IO_CMD_A_DODT_EN_SHIFT 28
    #define SEQ_CH0_IO_CMD_A_DODT_VAL_MASK 0x60000000
    #define SEQ_CH0_IO_CMD_A_DODT_VAL_SHIFT 29
#define  SEQ_CH0_IO_CMD_B 0xC24C
    #define SEQ_CH0_IO_CMD_B_DRVR_SR_EN_MASK 0x0000001F
    #define SEQ_CH0_IO_CMD_B_DRVR_SR_EN_SHIFT 0
    #define SEQ_CH0_IO_CMD_B_DRVR_PEMPH_EN_MASK 0x00000F00
    #define SEQ_CH0_IO_CMD_B_DRVR_PEMPH_EN_SHIFT 8
    #define SEQ_CH0_IO_CMD_B_TRANSMIT_EN_MASK 0x00001000
    #define SEQ_CH0_IO_CMD_B_TRANSMIT_EN_SHIFT 12
    #define SEQ_CH0_IO_CMD_B_RCVR_CMOS_EN_MASK 0x00002000
    #define SEQ_CH0_IO_CMD_B_RCVR_CMOS_EN_SHIFT 13
    #define SEQ_CH0_IO_CMD_B_RCVR_TEN_MASK 0x00004000
    #define SEQ_CH0_IO_CMD_B_RCVR_TEN_SHIFT 14
#define  SEQ_CH0_IO_DQS_BYTE0_A 0xC208
    #define SEQ_CH0_IO_DQS_BYTE0_A_DDR2_MODE_MASK 0x00000001
    #define SEQ_CH0_IO_DQS_BYTE0_A_DDR2_MODE_SHIFT 0
    #define SEQ_CH0_IO_DQS_BYTE0_A_RD_ODT_VAL_MASK 0x0000000E
    #define SEQ_CH0_IO_DQS_BYTE0_A_RD_ODT_VAL_SHIFT 1
    #define SEQ_CH0_IO_DQS_BYTE0_A_DRV_STRENGTH_MASK 0x00000070
    #define SEQ_CH0_IO_DQS_BYTE0_A_DRV_STRENGTH_SHIFT 4
    #define SEQ_CH0_IO_DQS_BYTE0_A_DRVR_DLAY_MASK 0x00000700
    #define SEQ_CH0_IO_DQS_BYTE0_A_DRVR_DLAY_SHIFT 8
    #define SEQ_CH0_IO_DQS_BYTE0_A_DRVR_DUTY_MASK 0x00007000
    #define SEQ_CH0_IO_DQS_BYTE0_A_DRVR_DUTY_SHIFT 12
    #define SEQ_CH0_IO_DQS_BYTE0_A_RCVR_DUTY_MASK 0x00070000
    #define SEQ_CH0_IO_DQS_BYTE0_A_RCVR_DUTY_SHIFT 16
    #define SEQ_CH0_IO_DQS_BYTE0_A_RCVR_DIFEN_MASK 0x00F00000
    #define SEQ_CH0_IO_DQS_BYTE0_A_RCVR_DIFEN_SHIFT 20
    #define SEQ_CH0_IO_DQS_BYTE0_A_RCVR_DIFFDDR2_MASK 0x01000000
    #define SEQ_CH0_IO_DQS_BYTE0_A_RCVR_DIFFDDR2_SHIFT 24
    #define SEQ_CH0_IO_DQS_BYTE0_A_VREF_MUX_MASK 0x06000000
    #define SEQ_CH0_IO_DQS_BYTE0_A_VREF_MUX_SHIFT 25
    #define SEQ_CH0_IO_DQS_BYTE0_A_DODT_EN_MASK 0x10000000
    #define SEQ_CH0_IO_DQS_BYTE0_A_DODT_EN_SHIFT 28
    #define SEQ_CH0_IO_DQS_BYTE0_A_DODT_VAL_MASK 0x60000000
    #define SEQ_CH0_IO_DQS_BYTE0_A_DODT_VAL_SHIFT 29
#define  SEQ_CH0_IO_DQS_BYTE0_B 0xC20C
    #define SEQ_CH0_IO_DQS_BYTE0_B_DRVR_SR_EN_MASK 0x0000001F
    #define SEQ_CH0_IO_DQS_BYTE0_B_DRVR_SR_EN_SHIFT 0
    #define SEQ_CH0_IO_DQS_BYTE0_B_DRVR_PEMPH_EN_MASK 0x00000F00
    #define SEQ_CH0_IO_DQS_BYTE0_B_DRVR_PEMPH_EN_SHIFT 8
    #define SEQ_CH0_IO_DQS_BYTE0_B_RCVR_CMOS_EN_MASK 0x00002000
    #define SEQ_CH0_IO_DQS_BYTE0_B_RCVR_CMOS_EN_SHIFT 13
    #define SEQ_CH0_IO_DQS_BYTE0_B_RCVR_DIFFERENTIAL_MASK 0x00008000
    #define SEQ_CH0_IO_DQS_BYTE0_B_RCVR_DIFFERENTIAL_SHIFT 15
#define  SEQ_CH0_IO_DQS_BYTE1_A 0xC218
    #define SEQ_CH0_IO_DQS_BYTE1_A_DDR2_MODE_MASK 0x00000001
    #define SEQ_CH0_IO_DQS_BYTE1_A_DDR2_MODE_SHIFT 0
    #define SEQ_CH0_IO_DQS_BYTE1_A_RD_ODT_VAL_MASK 0x0000000E
    #define SEQ_CH0_IO_DQS_BYTE1_A_RD_ODT_VAL_SHIFT 1
    #define SEQ_CH0_IO_DQS_BYTE1_A_DRV_STRENGTH_MASK 0x00000070
    #define SEQ_CH0_IO_DQS_BYTE1_A_DRV_STRENGTH_SHIFT 4
    #define SEQ_CH0_IO_DQS_BYTE1_A_DRVR_DLAY_MASK 0x00000700
    #define SEQ_CH0_IO_DQS_BYTE1_A_DRVR_DLAY_SHIFT 8
    #define SEQ_CH0_IO_DQS_BYTE1_A_DRVR_DUTY_MASK 0x00007000
    #define SEQ_CH0_IO_DQS_BYTE1_A_DRVR_DUTY_SHIFT 12
    #define SEQ_CH0_IO_DQS_BYTE1_A_RCVR_DUTY_MASK 0x00070000
    #define SEQ_CH0_IO_DQS_BYTE1_A_RCVR_DUTY_SHIFT 16
    #define SEQ_CH0_IO_DQS_BYTE1_A_RCVR_DIFEN_MASK 0x00F00000
    #define SEQ_CH0_IO_DQS_BYTE1_A_RCVR_DIFEN_SHIFT 20
    #define SEQ_CH0_IO_DQS_BYTE1_A_RCVR_DIFFDDR2_MASK 0x01000000
    #define SEQ_CH0_IO_DQS_BYTE1_A_RCVR_DIFFDDR2_SHIFT 24
    #define SEQ_CH0_IO_DQS_BYTE1_A_VREF_MUX_MASK 0x06000000
    #define SEQ_CH0_IO_DQS_BYTE1_A_VREF_MUX_SHIFT 25
    #define SEQ_CH0_IO_DQS_BYTE1_A_DODT_EN_MASK 0x10000000
    #define SEQ_CH0_IO_DQS_BYTE1_A_DODT_EN_SHIFT 28
    #define SEQ_CH0_IO_DQS_BYTE1_A_DODT_VAL_MASK 0x60000000
    #define SEQ_CH0_IO_DQS_BYTE1_A_DODT_VAL_SHIFT 29
#define  SEQ_CH0_IO_DQS_BYTE1_B 0xC21C
    #define SEQ_CH0_IO_DQS_BYTE1_B_DRVR_SR_EN_MASK 0x0000001F
    #define SEQ_CH0_IO_DQS_BYTE1_B_DRVR_SR_EN_SHIFT 0
    #define SEQ_CH0_IO_DQS_BYTE1_B_DRVR_PEMPH_EN_MASK 0x00000F00
    #define SEQ_CH0_IO_DQS_BYTE1_B_DRVR_PEMPH_EN_SHIFT 8
    #define SEQ_CH0_IO_DQS_BYTE1_B_RCVR_CMOS_EN_MASK 0x00002000
    #define SEQ_CH0_IO_DQS_BYTE1_B_RCVR_CMOS_EN_SHIFT 13
    #define SEQ_CH0_IO_DQS_BYTE1_B_RCVR_DIFFERENTIAL_MASK 0x00008000
    #define SEQ_CH0_IO_DQS_BYTE1_B_RCVR_DIFFERENTIAL_SHIFT 15
#define  SEQ_CH0_IO_DQS_BYTE2_A 0xC228
    #define SEQ_CH0_IO_DQS_BYTE2_A_DDR2_MODE_MASK 0x00000001
    #define SEQ_CH0_IO_DQS_BYTE2_A_DDR2_MODE_SHIFT 0
    #define SEQ_CH0_IO_DQS_BYTE2_A_RD_ODT_VAL_MASK 0x0000000E
    #define SEQ_CH0_IO_DQS_BYTE2_A_RD_ODT_VAL_SHIFT 1
    #define SEQ_CH0_IO_DQS_BYTE2_A_DRV_STRENGTH_MASK 0x00000070
    #define SEQ_CH0_IO_DQS_BYTE2_A_DRV_STRENGTH_SHIFT 4
    #define SEQ_CH0_IO_DQS_BYTE2_A_DRVR_DLAY_MASK 0x00000700
    #define SEQ_CH0_IO_DQS_BYTE2_A_DRVR_DLAY_SHIFT 8
    #define SEQ_CH0_IO_DQS_BYTE2_A_DRVR_DUTY_MASK 0x00007000
    #define SEQ_CH0_IO_DQS_BYTE2_A_DRVR_DUTY_SHIFT 12
    #define SEQ_CH0_IO_DQS_BYTE2_A_RCVR_DUTY_MASK 0x00070000
    #define SEQ_CH0_IO_DQS_BYTE2_A_RCVR_DUTY_SHIFT 16
    #define SEQ_CH0_IO_DQS_BYTE2_A_RCVR_DIFEN_MASK 0x00F00000
    #define SEQ_CH0_IO_DQS_BYTE2_A_RCVR_DIFEN_SHIFT 20
    #define SEQ_CH0_IO_DQS_BYTE2_A_RCVR_DIFFDDR2_MASK 0x01000000
    #define SEQ_CH0_IO_DQS_BYTE2_A_RCVR_DIFFDDR2_SHIFT 24
    #define SEQ_CH0_IO_DQS_BYTE2_A_VREF_MUX_MASK 0x06000000
    #define SEQ_CH0_IO_DQS_BYTE2_A_VREF_MUX_SHIFT 25
    #define SEQ_CH0_IO_DQS_BYTE2_A_DODT_EN_MASK 0x10000000
    #define SEQ_CH0_IO_DQS_BYTE2_A_DODT_EN_SHIFT 28
    #define SEQ_CH0_IO_DQS_BYTE2_A_DODT_VAL_MASK 0x60000000
    #define SEQ_CH0_IO_DQS_BYTE2_A_DODT_VAL_SHIFT 29
#define  SEQ_CH0_IO_DQS_BYTE2_B 0xC22C
    #define SEQ_CH0_IO_DQS_BYTE2_B_DRVR_SR_EN_MASK 0x0000001F
    #define SEQ_CH0_IO_DQS_BYTE2_B_DRVR_SR_EN_SHIFT 0
    #define SEQ_CH0_IO_DQS_BYTE2_B_DRVR_PEMPH_EN_MASK 0x00000F00
    #define SEQ_CH0_IO_DQS_BYTE2_B_DRVR_PEMPH_EN_SHIFT 8
    #define SEQ_CH0_IO_DQS_BYTE2_B_RCVR_CMOS_EN_MASK 0x00002000
    #define SEQ_CH0_IO_DQS_BYTE2_B_RCVR_CMOS_EN_SHIFT 13
    #define SEQ_CH0_IO_DQS_BYTE2_B_RCVR_DIFFERENTIAL_MASK 0x00008000
    #define SEQ_CH0_IO_DQS_BYTE2_B_RCVR_DIFFERENTIAL_SHIFT 15
#define  SEQ_CH0_IO_DQS_BYTE3_A 0xC238
    #define SEQ_CH0_IO_DQS_BYTE3_A_DDR2_MODE_MASK 0x00000001
    #define SEQ_CH0_IO_DQS_BYTE3_A_DDR2_MODE_SHIFT 0
    #define SEQ_CH0_IO_DQS_BYTE3_A_RD_ODT_VAL_MASK 0x0000000E
    #define SEQ_CH0_IO_DQS_BYTE3_A_RD_ODT_VAL_SHIFT 1
    #define SEQ_CH0_IO_DQS_BYTE3_A_DRV_STRENGTH_MASK 0x00000070
    #define SEQ_CH0_IO_DQS_BYTE3_A_DRV_STRENGTH_SHIFT 4
    #define SEQ_CH0_IO_DQS_BYTE3_A_DRVR_DLAY_MASK 0x00000700
    #define SEQ_CH0_IO_DQS_BYTE3_A_DRVR_DLAY_SHIFT 8
    #define SEQ_CH0_IO_DQS_BYTE3_A_DRVR_DUTY_MASK 0x00007000
    #define SEQ_CH0_IO_DQS_BYTE3_A_DRVR_DUTY_SHIFT 12
    #define SEQ_CH0_IO_DQS_BYTE3_A_RCVR_DUTY_MASK 0x00070000
    #define SEQ_CH0_IO_DQS_BYTE3_A_RCVR_DUTY_SHIFT 16
    #define SEQ_CH0_IO_DQS_BYTE3_A_RCVR_DIFEN_MASK 0x00F00000
    #define SEQ_CH0_IO_DQS_BYTE3_A_RCVR_DIFEN_SHIFT 20
    #define SEQ_CH0_IO_DQS_BYTE3_A_RCVR_DIFFDDR2_MASK 0x01000000
    #define SEQ_CH0_IO_DQS_BYTE3_A_RCVR_DIFFDDR2_SHIFT 24
    #define SEQ_CH0_IO_DQS_BYTE3_A_VREF_MUX_MASK 0x06000000
    #define SEQ_CH0_IO_DQS_BYTE3_A_VREF_MUX_SHIFT 25
    #define SEQ_CH0_IO_DQS_BYTE3_A_DODT_EN_MASK 0x10000000
    #define SEQ_CH0_IO_DQS_BYTE3_A_DODT_EN_SHIFT 28
    #define SEQ_CH0_IO_DQS_BYTE3_A_DODT_VAL_MASK 0x60000000
    #define SEQ_CH0_IO_DQS_BYTE3_A_DODT_VAL_SHIFT 29
#define  SEQ_CH0_IO_DQS_BYTE3_B 0xC23C
    #define SEQ_CH0_IO_DQS_BYTE3_B_DRVR_SR_EN_MASK 0x0000001F
    #define SEQ_CH0_IO_DQS_BYTE3_B_DRVR_SR_EN_SHIFT 0
    #define SEQ_CH0_IO_DQS_BYTE3_B_DRVR_PEMPH_EN_MASK 0x00000F00
    #define SEQ_CH0_IO_DQS_BYTE3_B_DRVR_PEMPH_EN_SHIFT 8
    #define SEQ_CH0_IO_DQS_BYTE3_B_RCVR_CMOS_EN_MASK 0x00002000
    #define SEQ_CH0_IO_DQS_BYTE3_B_RCVR_CMOS_EN_SHIFT 13
    #define SEQ_CH0_IO_DQS_BYTE3_B_RCVR_DIFFERENTIAL_MASK 0x00008000
    #define SEQ_CH0_IO_DQS_BYTE3_B_RCVR_DIFFERENTIAL_SHIFT 15
#define  SEQ_CH0_IO_DQ_BYTE0_A 0xC200
    #define SEQ_CH0_IO_DQ_BYTE0_A_DDR2_MODE_MASK 0x00000001
    #define SEQ_CH0_IO_DQ_BYTE0_A_DDR2_MODE_SHIFT 0
    #define SEQ_CH0_IO_DQ_BYTE0_A_RD_ODT_VAL_MASK 0x0000000E
    #define SEQ_CH0_IO_DQ_BYTE0_A_RD_ODT_VAL_SHIFT 1
    #define SEQ_CH0_IO_DQ_BYTE0_A_DRV_STRENGTH_MASK 0x00000070
    #define SEQ_CH0_IO_DQ_BYTE0_A_DRV_STRENGTH_SHIFT 4
    #define SEQ_CH0_IO_DQ_BYTE0_A_DRVR_DLAY_MASK 0x00000700
    #define SEQ_CH0_IO_DQ_BYTE0_A_DRVR_DLAY_SHIFT 8
    #define SEQ_CH0_IO_DQ_BYTE0_A_DRVR_DUTY_MASK 0x00007000
    #define SEQ_CH0_IO_DQ_BYTE0_A_DRVR_DUTY_SHIFT 12
    #define SEQ_CH0_IO_DQ_BYTE0_A_RCVR_DUTY_MASK 0x00070000
    #define SEQ_CH0_IO_DQ_BYTE0_A_RCVR_DUTY_SHIFT 16
    #define SEQ_CH0_IO_DQ_BYTE0_A_RCVR_DIFEN_MASK 0x00F00000
    #define SEQ_CH0_IO_DQ_BYTE0_A_RCVR_DIFEN_SHIFT 20
    #define SEQ_CH0_IO_DQ_BYTE0_A_RCVR_DIFFDDR2_MASK 0x01000000
    #define SEQ_CH0_IO_DQ_BYTE0_A_RCVR_DIFFDDR2_SHIFT 24
    #define SEQ_CH0_IO_DQ_BYTE0_A_VREF_MUX_MASK 0x06000000
    #define SEQ_CH0_IO_DQ_BYTE0_A_VREF_MUX_SHIFT 25
    #define SEQ_CH0_IO_DQ_BYTE0_A_DODT_EN_MASK 0x10000000
    #define SEQ_CH0_IO_DQ_BYTE0_A_DODT_EN_SHIFT 28
    #define SEQ_CH0_IO_DQ_BYTE0_A_DODT_VAL_MASK 0x60000000
    #define SEQ_CH0_IO_DQ_BYTE0_A_DODT_VAL_SHIFT 29
#define  SEQ_CH0_IO_DQ_BYTE0_B 0xC204
    #define SEQ_CH0_IO_DQ_BYTE0_B_DRVR_SR_EN_MASK 0x0000001F
    #define SEQ_CH0_IO_DQ_BYTE0_B_DRVR_SR_EN_SHIFT 0
    #define SEQ_CH0_IO_DQ_BYTE0_B_DRVR_PEMPH_EN_MASK 0x00000F00
    #define SEQ_CH0_IO_DQ_BYTE0_B_DRVR_PEMPH_EN_SHIFT 8
    #define SEQ_CH0_IO_DQ_BYTE0_B_TRANSMIT_EN_MASK 0x00001000
    #define SEQ_CH0_IO_DQ_BYTE0_B_TRANSMIT_EN_SHIFT 12
    #define SEQ_CH0_IO_DQ_BYTE0_B_RCVR_CMOS_EN_MASK 0x00002000
    #define SEQ_CH0_IO_DQ_BYTE0_B_RCVR_CMOS_EN_SHIFT 13
    #define SEQ_CH0_IO_DQ_BYTE0_B_RCVR_TEN_MASK 0x00004000
    #define SEQ_CH0_IO_DQ_BYTE0_B_RCVR_TEN_SHIFT 14
#define  SEQ_CH0_IO_DQ_BYTE1_A 0xC210
    #define SEQ_CH0_IO_DQ_BYTE1_A_DDR2_MODE_MASK 0x00000001
    #define SEQ_CH0_IO_DQ_BYTE1_A_DDR2_MODE_SHIFT 0
    #define SEQ_CH0_IO_DQ_BYTE1_A_RD_ODT_VAL_MASK 0x0000000E
    #define SEQ_CH0_IO_DQ_BYTE1_A_RD_ODT_VAL_SHIFT 1
    #define SEQ_CH0_IO_DQ_BYTE1_A_DRV_STRENGTH_MASK 0x00000070
    #define SEQ_CH0_IO_DQ_BYTE1_A_DRV_STRENGTH_SHIFT 4
    #define SEQ_CH0_IO_DQ_BYTE1_A_DRVR_DLAY_MASK 0x00000700
    #define SEQ_CH0_IO_DQ_BYTE1_A_DRVR_DLAY_SHIFT 8
    #define SEQ_CH0_IO_DQ_BYTE1_A_DRVR_DUTY_MASK 0x00007000
    #define SEQ_CH0_IO_DQ_BYTE1_A_DRVR_DUTY_SHIFT 12
    #define SEQ_CH0_IO_DQ_BYTE1_A_RCVR_DUTY_MASK 0x00070000
    #define SEQ_CH0_IO_DQ_BYTE1_A_RCVR_DUTY_SHIFT 16
    #define SEQ_CH0_IO_DQ_BYTE1_A_RCVR_DIFEN_MASK 0x00F00000
    #define SEQ_CH0_IO_DQ_BYTE1_A_RCVR_DIFEN_SHIFT 20
    #define SEQ_CH0_IO_DQ_BYTE1_A_RCVR_DIFFDDR2_MASK 0x01000000
    #define SEQ_CH0_IO_DQ_BYTE1_A_RCVR_DIFFDDR2_SHIFT 24
    #define SEQ_CH0_IO_DQ_BYTE1_A_VREF_MUX_MASK 0x06000000
    #define SEQ_CH0_IO_DQ_BYTE1_A_VREF_MUX_SHIFT 25
    #define SEQ_CH0_IO_DQ_BYTE1_A_DODT_EN_MASK 0x10000000
    #define SEQ_CH0_IO_DQ_BYTE1_A_DODT_EN_SHIFT 28
    #define SEQ_CH0_IO_DQ_BYTE1_A_DODT_VAL_MASK 0x60000000
    #define SEQ_CH0_IO_DQ_BYTE1_A_DODT_VAL_SHIFT 29
#define  SEQ_CH0_IO_DQ_BYTE1_B 0xC214
    #define SEQ_CH0_IO_DQ_BYTE1_B_DRVR_SR_EN_MASK 0x0000001F
    #define SEQ_CH0_IO_DQ_BYTE1_B_DRVR_SR_EN_SHIFT 0
    #define SEQ_CH0_IO_DQ_BYTE1_B_DRVR_PEMPH_EN_MASK 0x00000F00
    #define SEQ_CH0_IO_DQ_BYTE1_B_DRVR_PEMPH_EN_SHIFT 8
    #define SEQ_CH0_IO_DQ_BYTE1_B_TRANSMIT_EN_MASK 0x00001000
    #define SEQ_CH0_IO_DQ_BYTE1_B_TRANSMIT_EN_SHIFT 12
    #define SEQ_CH0_IO_DQ_BYTE1_B_RCVR_CMOS_EN_MASK 0x00002000
    #define SEQ_CH0_IO_DQ_BYTE1_B_RCVR_CMOS_EN_SHIFT 13
    #define SEQ_CH0_IO_DQ_BYTE1_B_RCVR_TEN_MASK 0x00004000
    #define SEQ_CH0_IO_DQ_BYTE1_B_RCVR_TEN_SHIFT 14
#define  SEQ_CH0_IO_DQ_BYTE2_A 0xC220
    #define SEQ_CH0_IO_DQ_BYTE2_A_DDR2_MODE_MASK 0x00000001
    #define SEQ_CH0_IO_DQ_BYTE2_A_DDR2_MODE_SHIFT 0
    #define SEQ_CH0_IO_DQ_BYTE2_A_RD_ODT_VAL_MASK 0x0000000E
    #define SEQ_CH0_IO_DQ_BYTE2_A_RD_ODT_VAL_SHIFT 1
    #define SEQ_CH0_IO_DQ_BYTE2_A_DRV_STRENGTH_MASK 0x00000070
    #define SEQ_CH0_IO_DQ_BYTE2_A_DRV_STRENGTH_SHIFT 4
    #define SEQ_CH0_IO_DQ_BYTE2_A_DRVR_DLAY_MASK 0x00000700
    #define SEQ_CH0_IO_DQ_BYTE2_A_DRVR_DLAY_SHIFT 8
    #define SEQ_CH0_IO_DQ_BYTE2_A_DRVR_DUTY_MASK 0x00007000
    #define SEQ_CH0_IO_DQ_BYTE2_A_DRVR_DUTY_SHIFT 12
    #define SEQ_CH0_IO_DQ_BYTE2_A_RCVR_DUTY_MASK 0x00070000
    #define SEQ_CH0_IO_DQ_BYTE2_A_RCVR_DUTY_SHIFT 16
    #define SEQ_CH0_IO_DQ_BYTE2_A_RCVR_DIFEN_MASK 0x00F00000
    #define SEQ_CH0_IO_DQ_BYTE2_A_RCVR_DIFEN_SHIFT 20
    #define SEQ_CH0_IO_DQ_BYTE2_A_RCVR_DIFFDDR2_MASK 0x01000000
    #define SEQ_CH0_IO_DQ_BYTE2_A_RCVR_DIFFDDR2_SHIFT 24
    #define SEQ_CH0_IO_DQ_BYTE2_A_VREF_MUX_MASK 0x06000000
    #define SEQ_CH0_IO_DQ_BYTE2_A_VREF_MUX_SHIFT 25
    #define SEQ_CH0_IO_DQ_BYTE2_A_DODT_EN_MASK 0x10000000
    #define SEQ_CH0_IO_DQ_BYTE2_A_DODT_EN_SHIFT 28
    #define SEQ_CH0_IO_DQ_BYTE2_A_DODT_VAL_MASK 0x60000000
    #define SEQ_CH0_IO_DQ_BYTE2_A_DODT_VAL_SHIFT 29
#define  SEQ_CH0_IO_DQ_BYTE2_B 0xC224
    #define SEQ_CH0_IO_DQ_BYTE2_B_DRVR_SR_EN_MASK 0x0000001F
    #define SEQ_CH0_IO_DQ_BYTE2_B_DRVR_SR_EN_SHIFT 0
    #define SEQ_CH0_IO_DQ_BYTE2_B_DRVR_PEMPH_EN_MASK 0x00000F00
    #define SEQ_CH0_IO_DQ_BYTE2_B_DRVR_PEMPH_EN_SHIFT 8
    #define SEQ_CH0_IO_DQ_BYTE2_B_TRANSMIT_EN_MASK 0x00001000
    #define SEQ_CH0_IO_DQ_BYTE2_B_TRANSMIT_EN_SHIFT 12
    #define SEQ_CH0_IO_DQ_BYTE2_B_RCVR_CMOS_EN_MASK 0x00002000
    #define SEQ_CH0_IO_DQ_BYTE2_B_RCVR_CMOS_EN_SHIFT 13
    #define SEQ_CH0_IO_DQ_BYTE2_B_RCVR_TEN_MASK 0x00004000
    #define SEQ_CH0_IO_DQ_BYTE2_B_RCVR_TEN_SHIFT 14
#define  SEQ_CH0_IO_DQ_BYTE3_A 0xC230
    #define SEQ_CH0_IO_DQ_BYTE3_A_DDR2_MODE_MASK 0x00000001
    #define SEQ_CH0_IO_DQ_BYTE3_A_DDR2_MODE_SHIFT 0
    #define SEQ_CH0_IO_DQ_BYTE3_A_RD_ODT_VAL_MASK 0x0000000E
    #define SEQ_CH0_IO_DQ_BYTE3_A_RD_ODT_VAL_SHIFT 1
    #define SEQ_CH0_IO_DQ_BYTE3_A_DRV_STRENGTH_MASK 0x00000070
    #define SEQ_CH0_IO_DQ_BYTE3_A_DRV_STRENGTH_SHIFT 4
    #define SEQ_CH0_IO_DQ_BYTE3_A_DRVR_DLAY_MASK 0x00000700
    #define SEQ_CH0_IO_DQ_BYTE3_A_DRVR_DLAY_SHIFT 8
    #define SEQ_CH0_IO_DQ_BYTE3_A_DRVR_DUTY_MASK 0x00007000
    #define SEQ_CH0_IO_DQ_BYTE3_A_DRVR_DUTY_SHIFT 12
    #define SEQ_CH0_IO_DQ_BYTE3_A_RCVR_DUTY_MASK 0x00070000
    #define SEQ_CH0_IO_DQ_BYTE3_A_RCVR_DUTY_SHIFT 16
    #define SEQ_CH0_IO_DQ_BYTE3_A_RCVR_DIFEN_MASK 0x00F00000
    #define SEQ_CH0_IO_DQ_BYTE3_A_RCVR_DIFEN_SHIFT 20
    #define SEQ_CH0_IO_DQ_BYTE3_A_RCVR_DIFFDDR2_MASK 0x01000000
    #define SEQ_CH0_IO_DQ_BYTE3_A_RCVR_DIFFDDR2_SHIFT 24
    #define SEQ_CH0_IO_DQ_BYTE3_A_VREF_MUX_MASK 0x06000000
    #define SEQ_CH0_IO_DQ_BYTE3_A_VREF_MUX_SHIFT 25
    #define SEQ_CH0_IO_DQ_BYTE3_A_DODT_EN_MASK 0x10000000
    #define SEQ_CH0_IO_DQ_BYTE3_A_DODT_EN_SHIFT 28
    #define SEQ_CH0_IO_DQ_BYTE3_A_DODT_VAL_MASK 0x60000000
    #define SEQ_CH0_IO_DQ_BYTE3_A_DODT_VAL_SHIFT 29
#define  SEQ_CH0_IO_DQ_BYTE3_B 0xC234
    #define SEQ_CH0_IO_DQ_BYTE3_B_DRVR_SR_EN_MASK 0x0000001F
    #define SEQ_CH0_IO_DQ_BYTE3_B_DRVR_SR_EN_SHIFT 0
    #define SEQ_CH0_IO_DQ_BYTE3_B_DRVR_PEMPH_EN_MASK 0x00000F00
    #define SEQ_CH0_IO_DQ_BYTE3_B_DRVR_PEMPH_EN_SHIFT 8
    #define SEQ_CH0_IO_DQ_BYTE3_B_TRANSMIT_EN_MASK 0x00001000
    #define SEQ_CH0_IO_DQ_BYTE3_B_TRANSMIT_EN_SHIFT 12
    #define SEQ_CH0_IO_DQ_BYTE3_B_RCVR_CMOS_EN_MASK 0x00002000
    #define SEQ_CH0_IO_DQ_BYTE3_B_RCVR_CMOS_EN_SHIFT 13
    #define SEQ_CH0_IO_DQ_BYTE3_B_RCVR_TEN_MASK 0x00004000
    #define SEQ_CH0_IO_DQ_BYTE3_B_RCVR_TEN_SHIFT 14
#define  SEQ_CH0_IO_MISC 0xC258
    #define SEQ_CH0_IO_MISC_VREF_ADJ_MASK 0x0000000F
    #define SEQ_CH0_IO_MISC_VREF_ADJ_SHIFT 0
    #define SEQ_CH0_IO_MISC_VREF_PD_BUF_MASK 0x00000010
    #define SEQ_CH0_IO_MISC_VREF_PD_BUF_SHIFT 4
    #define SEQ_CH0_IO_MISC_VREF_PD_REF_MASK 0x00000020
    #define SEQ_CH0_IO_MISC_VREF_PD_REF_SHIFT 5
    #define SEQ_CH0_IO_MISC_ZQ_PD_MASK 0x00000040
    #define SEQ_CH0_IO_MISC_ZQ_PD_SHIFT 6
    #define SEQ_CH0_IO_MISC_ZQ_PS_MASK 0x00000080
    #define SEQ_CH0_IO_MISC_ZQ_PS_SHIFT 7
    #define SEQ_CH0_IO_MISC_CLK_TIME2_MASK 0x00000200
    #define SEQ_CH0_IO_MISC_CLK_TIME2_SHIFT 9
    #define SEQ_CH0_IO_MISC_DBG_NDQSIN_MASK 0x00000400
    #define SEQ_CH0_IO_MISC_DBG_NDQSIN_SHIFT 10
    #define SEQ_CH0_IO_MISC_DBG_FFWEIN_EN_MASK 0x00000800
    #define SEQ_CH0_IO_MISC_DBG_FFWEIN_EN_SHIFT 11
    #define SEQ_CH0_IO_MISC_DBG_FFWEIN_DAT_MASK 0x00001000
    #define SEQ_CH0_IO_MISC_DBG_FFWEIN_DAT_SHIFT 12
#define  SEQ_CH0_ITM_CTRL 0xC02C
    #define SEQ_CH0_ITM_CTRL_MDLL_RSTN_MASK 0x00000001
    #define SEQ_CH0_ITM_CTRL_MDLL_RSTN_SHIFT 0
    #define SEQ_CH0_ITM_CTRL_MSDLL0_RSTN_MASK 0x00000002
    #define SEQ_CH0_ITM_CTRL_MSDLL0_RSTN_SHIFT 1
    #define SEQ_CH0_ITM_CTRL_MSDLL1_RSTN_MASK 0x00000004
    #define SEQ_CH0_ITM_CTRL_MSDLL1_RSTN_SHIFT 2
    #define SEQ_CH0_ITM_CTRL_MSDLL2_RSTN_MASK 0x00000008
    #define SEQ_CH0_ITM_CTRL_MSDLL2_RSTN_SHIFT 3
    #define SEQ_CH0_ITM_CTRL_MSDLL3_RSTN_MASK 0x00000010
    #define SEQ_CH0_ITM_CTRL_MSDLL3_RSTN_SHIFT 4
    #define SEQ_CH0_ITM_CTRL_DTP_OUT_MASK 0x00000700
    #define SEQ_CH0_ITM_CTRL_DTP_OUT_SHIFT 8
#define  SEQ_CH0_LOOPBACK 0xC0B8
    #define SEQ_CH0_LOOPBACK_ADDR_MASK 0x7FFFFFFF
    #define SEQ_CH0_LOOPBACK_ADDR_SHIFT 0
#define  SEQ_CH0_MISC_REG 0xC024
    #define SEQ_CH0_MISC_REG_MSDCFG_RSTN_MASK 0x00000001
    #define SEQ_CH0_MISC_REG_MSDCFG_RSTN_SHIFT 0
    #define SEQ_CH0_MISC_REG_MSDSEQ_RSTN_MASK 0x00000002
    #define SEQ_CH0_MISC_REG_MSDSEQ_RSTN_SHIFT 1
    #define SEQ_CH0_MISC_REG_M2XLOGIC_RSTN_MASK 0x00000004
    #define SEQ_CH0_MISC_REG_M2XLOGIC_RSTN_SHIFT 2
    #define SEQ_CH0_MISC_REG_MDLOGIC_RSTN_MASK 0x00000008
    #define SEQ_CH0_MISC_REG_MDLOGIC_RSTN_SHIFT 3
    #define SEQ_CH0_MISC_REG_CTRLWRAP_RSTN_MASK 0x00000010
    #define SEQ_CH0_MISC_REG_CTRLWRAP_RSTN_SHIFT 4
    #define SEQ_CH0_MISC_REG_TEST_MODE_MASK 0x00000300
    #define SEQ_CH0_MISC_REG_TEST_MODE_SHIFT 8
    #define SEQ_CH0_MISC_REG_DLL_BYPASS_MASK 0x00000400
    #define SEQ_CH0_MISC_REG_DLL_BYPASS_SHIFT 10
    #define SEQ_CH0_MISC_REG_INIT_BYPASS_MASK 0x00000800
    #define SEQ_CH0_MISC_REG_INIT_BYPASS_SHIFT 11
    #define SEQ_CH0_MISC_REG_SSTL18_PADS_MASK 0x00010000
    #define SEQ_CH0_MISC_REG_SSTL18_PADS_SHIFT 16
    #define SEQ_CH0_MISC_REG_BSTLENGTH_MASK 0x00020000
    #define SEQ_CH0_MISC_REG_BSTLENGTH_SHIFT 17
#define  SEQ_CH0_MISC_REG_0 0xC004
    #define SEQ_CH0_MISC_REG_0_MRCLK_RSTN_MASK 0x00000001
    #define SEQ_CH0_MISC_REG_0_MRCLK_RSTN_SHIFT 0
    #define SEQ_CH0_MISC_REG_0_MCLK_RSTN_MASK 0x00000002
    #define SEQ_CH0_MISC_REG_0_MCLK_RSTN_SHIFT 1
    #define SEQ_CH0_MISC_REG_0_SEQCLK_RSTN_MASK 0x00000004
    #define SEQ_CH0_MISC_REG_0_SEQCLK_RSTN_SHIFT 2
    #define SEQ_CH0_MISC_REG_0_CTRLWRAP_RSTN_MASK 0x00000010
    #define SEQ_CH0_MISC_REG_0_CTRLWRAP_RSTN_SHIFT 4
    #define SEQ_CH0_MISC_REG_0_IPWRAP_RSTN_MASK 0x00000020
    #define SEQ_CH0_MISC_REG_0_IPWRAP_RSTN_SHIFT 5
    #define SEQ_CH0_MISC_REG_0_SOFT_IP_RSTN_MASK 0x00000040
    #define SEQ_CH0_MISC_REG_0_SOFT_IP_RSTN_SHIFT 6
    #define SEQ_CH0_MISC_REG_0_DBIST_RSTN_MASK 0x00000080
    #define SEQ_CH0_MISC_REG_0_DBIST_RSTN_SHIFT 7
    #define SEQ_CH0_MISC_REG_0_PHY_SEQCLK_RSTN_MASK 0x00000100
    #define SEQ_CH0_MISC_REG_0_PHY_SEQCLK_RSTN_SHIFT 8
    #define SEQ_CH0_MISC_REG_0_PHY_SEQ2XCLK_RSTN_MASK 0x00000200
    #define SEQ_CH0_MISC_REG_0_PHY_SEQ2XCLK_RSTN_SHIFT 9
    #define SEQ_CH0_MISC_REG_0_PHY_CALIBCLK_RSTN_MASK 0x00000400
    #define SEQ_CH0_MISC_REG_0_PHY_CALIBCLK_RSTN_SHIFT 10
    #define SEQ_CH0_MISC_REG_0_IO_ASYNC_RSTN_MASK 0x00000800
    #define SEQ_CH0_MISC_REG_0_IO_ASYNC_RSTN_SHIFT 11
    #define SEQ_CH0_MISC_REG_0_BSTLENGTH_MASK 0x00010000
    #define SEQ_CH0_MISC_REG_0_BSTLENGTH_SHIFT 16
    #define SEQ_CH0_MISC_REG_0_SHADOW_MEM_EN_MASK 0x00020000
    #define SEQ_CH0_MISC_REG_0_SHADOW_MEM_EN_SHIFT 17
    #define SEQ_CH0_MISC_REG_0_STAT_EN_MASK 0x00040000
    #define SEQ_CH0_MISC_REG_0_STAT_EN_SHIFT 18
    #define SEQ_CH0_MISC_REG_0_DRAM_BIST_EN_MASK 0x00080000
    #define SEQ_CH0_MISC_REG_0_DRAM_BIST_EN_SHIFT 19
    #define SEQ_CH0_MISC_REG_0_GATE_REQ_EN_MASK 0x00800000
    #define SEQ_CH0_MISC_REG_0_GATE_REQ_EN_SHIFT 23
    #define SEQ_CH0_MISC_REG_0_DDR3_MODE_MASK 0x01000000
    #define SEQ_CH0_MISC_REG_0_DDR3_MODE_SHIFT 24
    #define SEQ_CH0_MISC_REG_0_LOOPBACK_MODE_MASK 0x02000000
    #define SEQ_CH0_MISC_REG_0_LOOPBACK_MODE_SHIFT 25
    #define SEQ_CH0_MISC_REG_0_DBG_MUX_SEL_MASK 0xFC000000
    #define SEQ_CH0_MISC_REG_0_DBG_MUX_SEL_SHIFT 26
#define  SEQ_CH0_PHY_CTRL0 0xC0D8
    #define SEQ_CH0_PHY_CTRL0_RD_TO_DAT_MASK 0x0000001F
    #define SEQ_CH0_PHY_CTRL0_RD_TO_DAT_SHIFT 0
    #define SEQ_CH0_PHY_CTRL0_WR_TO_DAT_MASK 0x00000F80
    #define SEQ_CH0_PHY_CTRL0_WR_TO_DAT_SHIFT 7
    #define SEQ_CH0_PHY_CTRL0_RD_LOCAL_ODT_MASK 0x00030000
    #define SEQ_CH0_PHY_CTRL0_RD_LOCAL_ODT_SHIFT 16
    #define SEQ_CH0_PHY_CTRL0_WR_LOCAL_ODT_MASK 0x000C0000
    #define SEQ_CH0_PHY_CTRL0_WR_LOCAL_ODT_SHIFT 18
    #define SEQ_CH0_PHY_CTRL0_IDLE_LOCAL_ODT_MASK 0x00300000
    #define SEQ_CH0_PHY_CTRL0_IDLE_LOCAL_ODT_SHIFT 20
    #define SEQ_CH0_PHY_CTRL0_RDC_WE_TO_RE_MASK 0x00C00000
    #define SEQ_CH0_PHY_CTRL0_RDC_WE_TO_RE_SHIFT 22
    #define SEQ_CH0_PHY_CTRL0_USE_FIXED_RE_MASK 0x01000000
    #define SEQ_CH0_PHY_CTRL0_USE_FIXED_RE_SHIFT 24
    #define SEQ_CH0_PHY_CTRL0_RDCFF_RST_DIS_MASK 0x02000000
    #define SEQ_CH0_PHY_CTRL0_RDCFF_RST_DIS_SHIFT 25
    #define SEQ_CH0_PHY_CTRL0_RDCFF_RST_ERR_CLR_MASK 0x04000000
    #define SEQ_CH0_PHY_CTRL0_RDCFF_RST_ERR_CLR_SHIFT 26
#define  SEQ_CH0_PHY_CTRL1 0xC0DC
    #define SEQ_CH0_PHY_CTRL1_CTRL_SLAVE_RATIO_MASK 0x000000FF
    #define SEQ_CH0_PHY_CTRL1_CTRL_SLAVE_RATIO_SHIFT 0
    #define SEQ_CH0_PHY_CTRL1_CTRL_SLAVE_FORCE_MASK 0x00000100
    #define SEQ_CH0_PHY_CTRL1_CTRL_SLAVE_FORCE_SHIFT 8
    #define SEQ_CH0_PHY_CTRL1_CTRL_SLAVE_DELAY_MASK 0x0000FE00
    #define SEQ_CH0_PHY_CTRL1_CTRL_SLAVE_DELAY_SHIFT 9
#define  SEQ_CH0_PHY_MISC_REG 0xC0D0
    #define SEQ_CH0_PHY_MISC_REG_DEBUG_MODE_MASK 0x00000004
    #define SEQ_CH0_PHY_MISC_REG_DEBUG_MODE_SHIFT 2
    #define SEQ_CH0_PHY_MISC_REG_TEST_EN_MASK 0x00000008
    #define SEQ_CH0_PHY_MISC_REG_TEST_EN_SHIFT 3
    #define SEQ_CH0_PHY_MISC_REG_BSTCHOP_EN_MASK 0x00000010
    #define SEQ_CH0_PHY_MISC_REG_BSTCHOP_EN_SHIFT 4
    #define SEQ_CH0_PHY_MISC_REG_DATBUS_WIDTH_MASK 0x00000020
    #define SEQ_CH0_PHY_MISC_REG_DATBUS_WIDTH_SHIFT 5
    #define SEQ_CH0_PHY_MISC_REG_RD_LEVEL_START_MASK 0x00000040
    #define SEQ_CH0_PHY_MISC_REG_RD_LEVEL_START_SHIFT 6
    #define SEQ_CH0_PHY_MISC_REG_WR_LEVEL_START_MASK 0x00000080
    #define SEQ_CH0_PHY_MISC_REG_WR_LEVEL_START_SHIFT 7
    #define SEQ_CH0_PHY_MISC_REG_DQ0_WAIT_T_MASK 0x00000F00
    #define SEQ_CH0_PHY_MISC_REG_DQ0_WAIT_T_SHIFT 8
#define  SEQ_CH0_PHY_SLICE0_0 0xC0E0
    #define SEQ_CH0_PHY_SLICE0_0_RD_DQS_SL_RATIO_MASK 0x000000FF
    #define SEQ_CH0_PHY_SLICE0_0_RD_DQS_SL_RATIO_SHIFT 0
    #define SEQ_CH0_PHY_SLICE0_0_RD_DQS_SL_FORCE_MASK 0x00000100
    #define SEQ_CH0_PHY_SLICE0_0_RD_DQS_SL_FORCE_SHIFT 8
    #define SEQ_CH0_PHY_SLICE0_0_RD_DQS_SL_DELAY_MASK 0x0000FE00
    #define SEQ_CH0_PHY_SLICE0_0_RD_DQS_SL_DELAY_SHIFT 9
    #define SEQ_CH0_PHY_SLICE0_0_RD_DQS_DEF_SL_RATIO_MASK 0x00FF0000
    #define SEQ_CH0_PHY_SLICE0_0_RD_DQS_DEF_SL_RATIO_SHIFT 16
#define  SEQ_CH0_PHY_SLICE0_1 0xC0E4
    #define SEQ_CH0_PHY_SLICE0_1_WR_DQS_SL_RATIO_MASK 0x000000FF
    #define SEQ_CH0_PHY_SLICE0_1_WR_DQS_SL_RATIO_SHIFT 0
    #define SEQ_CH0_PHY_SLICE0_1_WR_DQS_SL_FORCE_MASK 0x00000100
    #define SEQ_CH0_PHY_SLICE0_1_WR_DQS_SL_FORCE_SHIFT 8
    #define SEQ_CH0_PHY_SLICE0_1_WR_DQS_SL_DELAY_MASK 0x0000FE00
    #define SEQ_CH0_PHY_SLICE0_1_WR_DQS_SL_DELAY_SHIFT 9
#define  SEQ_CH0_PHY_SLICE0_2 0xC0E8
    #define SEQ_CH0_PHY_SLICE0_2_WR_DQ_SL_RATIO_MASK 0x000000FF
    #define SEQ_CH0_PHY_SLICE0_2_WR_DQ_SL_RATIO_SHIFT 0
    #define SEQ_CH0_PHY_SLICE0_2_WR_DQ_SL_FORCE_MASK 0x00000100
    #define SEQ_CH0_PHY_SLICE0_2_WR_DQ_SL_FORCE_SHIFT 8
    #define SEQ_CH0_PHY_SLICE0_2_WR_DQ_SL_DELAY_MASK 0x0000FE00
    #define SEQ_CH0_PHY_SLICE0_2_WR_DQ_SL_DELAY_SHIFT 9
    #define SEQ_CH0_PHY_SLICE0_2_WR_DQ_OFFSET_MASK 0x007F0000
    #define SEQ_CH0_PHY_SLICE0_2_WR_DQ_OFFSET_SHIFT 16
#define  SEQ_CH0_PHY_SLICE0_3 0xC0EC
    #define SEQ_CH0_PHY_SLICE0_3_FIFO_WE_FORCE_MODE_MASK 0x00000001
    #define SEQ_CH0_PHY_SLICE0_3_FIFO_WE_FORCE_MODE_SHIFT 0
    #define SEQ_CH0_PHY_SLICE0_3_FIFO_WE_SL_RATIO_MASK 0x0000FF00
    #define SEQ_CH0_PHY_SLICE0_3_FIFO_WE_SL_RATIO_SHIFT 8
    #define SEQ_CH0_PHY_SLICE0_3_FIFO_WE_IN_FORCE_MASK 0x00010000
    #define SEQ_CH0_PHY_SLICE0_3_FIFO_WE_IN_FORCE_SHIFT 16
    #define SEQ_CH0_PHY_SLICE0_3_FIFO_WE_IN_DELAY_MASK 0x00FE0000
    #define SEQ_CH0_PHY_SLICE0_3_FIFO_WE_IN_DELAY_SHIFT 17
#define  SEQ_CH0_PHY_SLICE1_0 0xC0F0
    #define SEQ_CH0_PHY_SLICE1_0_RD_DQS_SL_RATIO_MASK 0x000000FF
    #define SEQ_CH0_PHY_SLICE1_0_RD_DQS_SL_RATIO_SHIFT 0
    #define SEQ_CH0_PHY_SLICE1_0_RD_DQS_SL_FORCE_MASK 0x00000100
    #define SEQ_CH0_PHY_SLICE1_0_RD_DQS_SL_FORCE_SHIFT 8
    #define SEQ_CH0_PHY_SLICE1_0_RD_DQS_SL_DELAY_MASK 0x0000FE00
    #define SEQ_CH0_PHY_SLICE1_0_RD_DQS_SL_DELAY_SHIFT 9
    #define SEQ_CH0_PHY_SLICE1_0_RD_DQS_DEF_SL_RATIO_MASK 0x00FF0000
    #define SEQ_CH0_PHY_SLICE1_0_RD_DQS_DEF_SL_RATIO_SHIFT 16
#define  SEQ_CH0_PHY_SLICE1_1 0xC0F4
    #define SEQ_CH0_PHY_SLICE1_1_WR_DQS_SL_RATIO_MASK 0x000000FF
    #define SEQ_CH0_PHY_SLICE1_1_WR_DQS_SL_RATIO_SHIFT 0
    #define SEQ_CH0_PHY_SLICE1_1_WR_DQS_SL_FORCE_MASK 0x00000100
    #define SEQ_CH0_PHY_SLICE1_1_WR_DQS_SL_FORCE_SHIFT 8
    #define SEQ_CH0_PHY_SLICE1_1_WR_DQS_SL_DELAY_MASK 0x0000FE00
    #define SEQ_CH0_PHY_SLICE1_1_WR_DQS_SL_DELAY_SHIFT 9
#define  SEQ_CH0_PHY_SLICE1_2 0xC0F8
    #define SEQ_CH0_PHY_SLICE1_2_WR_DQ_SL_RATIO_MASK 0x000000FF
    #define SEQ_CH0_PHY_SLICE1_2_WR_DQ_SL_RATIO_SHIFT 0
    #define SEQ_CH0_PHY_SLICE1_2_WR_DQ_SL_FORCE_MASK 0x00000100
    #define SEQ_CH0_PHY_SLICE1_2_WR_DQ_SL_FORCE_SHIFT 8
    #define SEQ_CH0_PHY_SLICE1_2_WR_DQ_SL_DELAY_MASK 0x0000FE00
    #define SEQ_CH0_PHY_SLICE1_2_WR_DQ_SL_DELAY_SHIFT 9
    #define SEQ_CH0_PHY_SLICE1_2_WR_DQ_OFFSET_MASK 0x007F0000
    #define SEQ_CH0_PHY_SLICE1_2_WR_DQ_OFFSET_SHIFT 16
#define  SEQ_CH0_PHY_SLICE1_3 0xC0FC
    #define SEQ_CH0_PHY_SLICE1_3_FIFO_WE_FORCE_MODE_MASK 0x00000001
    #define SEQ_CH0_PHY_SLICE1_3_FIFO_WE_FORCE_MODE_SHIFT 0
    #define SEQ_CH0_PHY_SLICE1_3_FIFO_WE_SL_RATIO_MASK 0x0000FF00
    #define SEQ_CH0_PHY_SLICE1_3_FIFO_WE_SL_RATIO_SHIFT 8
    #define SEQ_CH0_PHY_SLICE1_3_FIFO_WE_IN_FORCE_MASK 0x00010000
    #define SEQ_CH0_PHY_SLICE1_3_FIFO_WE_IN_FORCE_SHIFT 16
    #define SEQ_CH0_PHY_SLICE1_3_FIFO_WE_IN_DELAY_MASK 0x00FE0000
    #define SEQ_CH0_PHY_SLICE1_3_FIFO_WE_IN_DELAY_SHIFT 17
#define  SEQ_CH0_PHY_SLICE2_0 0xC100
    #define SEQ_CH0_PHY_SLICE2_0_RD_DQS_SL_RATIO_MASK 0x000000FF
    #define SEQ_CH0_PHY_SLICE2_0_RD_DQS_SL_RATIO_SHIFT 0
    #define SEQ_CH0_PHY_SLICE2_0_RD_DQS_SL_FORCE_MASK 0x00000100
    #define SEQ_CH0_PHY_SLICE2_0_RD_DQS_SL_FORCE_SHIFT 8
    #define SEQ_CH0_PHY_SLICE2_0_RD_DQS_SL_DELAY_MASK 0x0000FE00
    #define SEQ_CH0_PHY_SLICE2_0_RD_DQS_SL_DELAY_SHIFT 9
    #define SEQ_CH0_PHY_SLICE2_0_RD_DQS_DEF_SL_RATIO_MASK 0x00FF0000
    #define SEQ_CH0_PHY_SLICE2_0_RD_DQS_DEF_SL_RATIO_SHIFT 16
#define  SEQ_CH0_PHY_SLICE2_1 0xC104
    #define SEQ_CH0_PHY_SLICE2_1_WR_DQS_SL_RATIO_MASK 0x000000FF
    #define SEQ_CH0_PHY_SLICE2_1_WR_DQS_SL_RATIO_SHIFT 0
    #define SEQ_CH0_PHY_SLICE2_1_WR_DQS_SL_FORCE_MASK 0x00000100
    #define SEQ_CH0_PHY_SLICE2_1_WR_DQS_SL_FORCE_SHIFT 8
    #define SEQ_CH0_PHY_SLICE2_1_WR_DQS_SL_DELAY_MASK 0x0000FE00
    #define SEQ_CH0_PHY_SLICE2_1_WR_DQS_SL_DELAY_SHIFT 9
#define  SEQ_CH0_PHY_SLICE2_2 0xC108
    #define SEQ_CH0_PHY_SLICE2_2_WR_DQ_SL_RATIO_MASK 0x000000FF
    #define SEQ_CH0_PHY_SLICE2_2_WR_DQ_SL_RATIO_SHIFT 0
    #define SEQ_CH0_PHY_SLICE2_2_WR_DQ_SL_FORCE_MASK 0x00000100
    #define SEQ_CH0_PHY_SLICE2_2_WR_DQ_SL_FORCE_SHIFT 8
    #define SEQ_CH0_PHY_SLICE2_2_WR_DQ_SL_DELAY_MASK 0x0000FE00
    #define SEQ_CH0_PHY_SLICE2_2_WR_DQ_SL_DELAY_SHIFT 9
    #define SEQ_CH0_PHY_SLICE2_2_WR_DQ_OFFSET_MASK 0x007F0000
    #define SEQ_CH0_PHY_SLICE2_2_WR_DQ_OFFSET_SHIFT 16
#define  SEQ_CH0_PHY_SLICE3_0 0xC110
    #define SEQ_CH0_PHY_SLICE3_0_RD_DQS_SL_RATIO_MASK 0x000000FF
    #define SEQ_CH0_PHY_SLICE3_0_RD_DQS_SL_RATIO_SHIFT 0
    #define SEQ_CH0_PHY_SLICE3_0_RD_DQS_SL_FORCE_MASK 0x00000100
    #define SEQ_CH0_PHY_SLICE3_0_RD_DQS_SL_FORCE_SHIFT 8
    #define SEQ_CH0_PHY_SLICE3_0_RD_DQS_SL_DELAY_MASK 0x0000FE00
    #define SEQ_CH0_PHY_SLICE3_0_RD_DQS_SL_DELAY_SHIFT 9
    #define SEQ_CH0_PHY_SLICE3_0_RD_DQS_DEF_SL_RATIO_MASK 0x00FF0000
    #define SEQ_CH0_PHY_SLICE3_0_RD_DQS_DEF_SL_RATIO_SHIFT 16
#define  SEQ_CH0_PHY_SLICE3_1 0xC114
    #define SEQ_CH0_PHY_SLICE3_1_WR_DQS_SL_RATIO_MASK 0x000000FF
    #define SEQ_CH0_PHY_SLICE3_1_WR_DQS_SL_RATIO_SHIFT 0
    #define SEQ_CH0_PHY_SLICE3_1_WR_DQS_SL_FORCE_MASK 0x00000100
    #define SEQ_CH0_PHY_SLICE3_1_WR_DQS_SL_FORCE_SHIFT 8
    #define SEQ_CH0_PHY_SLICE3_1_WR_DQS_SL_DELAY_MASK 0x0000FE00
    #define SEQ_CH0_PHY_SLICE3_1_WR_DQS_SL_DELAY_SHIFT 9
#define  SEQ_CH0_PHY_SLICE3_2 0xC118
    #define SEQ_CH0_PHY_SLICE3_2_WR_DQ_SL_RATIO_MASK 0x000000FF
    #define SEQ_CH0_PHY_SLICE3_2_WR_DQ_SL_RATIO_SHIFT 0
    #define SEQ_CH0_PHY_SLICE3_2_WR_DQ_SL_FORCE_MASK 0x00000100
    #define SEQ_CH0_PHY_SLICE3_2_WR_DQ_SL_FORCE_SHIFT 8
    #define SEQ_CH0_PHY_SLICE3_2_WR_DQ_SL_DELAY_MASK 0x0000FE00
    #define SEQ_CH0_PHY_SLICE3_2_WR_DQ_SL_DELAY_SHIFT 9
    #define SEQ_CH0_PHY_SLICE3_2_WR_DQ_OFFSET_MASK 0x007F0000
    #define SEQ_CH0_PHY_SLICE3_2_WR_DQ_OFFSET_SHIFT 16
#define  SEQ_CH0_PHY_STATUS 0xC0D4
    #define SEQ_CH0_PHY_STATUS_RDCFF_RST_ERR_CNT_MASK 0x0000000F
    #define SEQ_CH0_PHY_STATUS_RDCFF_RST_ERR_CNT_SHIFT 0
    #define SEQ_CH0_PHY_STATUS_WR_LEVEL_DONE_MASK 0x00000010
    #define SEQ_CH0_PHY_STATUS_WR_LEVEL_DONE_SHIFT 4
    #define SEQ_CH0_PHY_STATUS_RD_LEVEL_DONE_MASK 0x00000020
    #define SEQ_CH0_PHY_STATUS_RD_LEVEL_DONE_SHIFT 5
    #define SEQ_CH0_PHY_STATUS_DLL_LOCK_MASK 0x000000C0
    #define SEQ_CH0_PHY_STATUS_DLL_LOCK_SHIFT 6
    #define SEQ_CH0_PHY_STATUS_IN_LOCK_STATE_MASK 0x00000F00
    #define SEQ_CH0_PHY_STATUS_IN_LOCK_STATE_SHIFT 8
#define  SEQ_CH0_RD_LOCK_STATUS 0xC048
    #define SEQ_CH0_RD_LOCK_STATUS_READ_ATTEMPT_CL_ID_MASK 0x0003FFFF
    #define SEQ_CH0_RD_LOCK_STATUS_READ_ATTEMPT_CL_ID_SHIFT 0
#define  SEQ_CH0_REFRESH 0xC0A4
    #define SEQ_CH0_REFRESH_REF_BURST_MASK 0x00000007
    #define SEQ_CH0_REFRESH_REF_BURST_SHIFT 0
    #define SEQ_CH0_REFRESH_REF_TO_X32_MASK 0x000000F8
    #define SEQ_CH0_REFRESH_REF_TO_X32_SHIFT 3
    #define SEQ_CH0_REFRESH_REF_MARGIN_MASK 0x000F0000
    #define SEQ_CH0_REFRESH_REF_MARGIN_SHIFT 16
    #define SEQ_CH0_REFRESH_REF_UPDATE_LEVEL_MASK 0x00100000
    #define SEQ_CH0_REFRESH_REF_UPDATE_LEVEL_SHIFT 20
    #define SEQ_CH0_REFRESH_DIS_AUTO_REF_MASK 0x40000000
    #define SEQ_CH0_REFRESH_DIS_AUTO_REF_SHIFT 30
    #define SEQ_CH0_REFRESH_RANK_REF_MASK 0x80000000
    #define SEQ_CH0_REFRESH_RANK_REF_SHIFT 31
#define  SEQ_CH0_REGDAT 0xC054
    #define SEQ_CH0_REGDAT_REQ_DATA_MASK 0xFFFFFFFF
    #define SEQ_CH0_REGDAT_REQ_DATA_SHIFT 0
#define  SEQ_CH0_REGDAT_IDX 0xC058
    #define SEQ_CH0_REGDAT_IDX_DATA_IDX_MASK 0x0000001F
    #define SEQ_CH0_REGDAT_IDX_DATA_IDX_SHIFT 0
    #define SEQ_CH0_REGDAT_IDX_REQ_BE_MASK 0x00000F00
    #define SEQ_CH0_REGDAT_IDX_REQ_BE_SHIFT 8
    #define SEQ_CH0_REGDAT_IDX_DATA_WOP_MASK 0x00001000
    #define SEQ_CH0_REGDAT_IDX_DATA_WOP_SHIFT 12
#define  SEQ_CH0_REGREQ_CTRL 0xC050
    #define SEQ_CH0_REGREQ_CTRL_REQ_SIZE_MASK 0x00000003
    #define SEQ_CH0_REGREQ_CTRL_REQ_SIZE_SHIFT 0
    #define SEQ_CH0_REGREQ_CTRL_REQ_WOP_MASK 0x00000004
    #define SEQ_CH0_REGREQ_CTRL_REQ_WOP_SHIFT 2
    #define SEQ_CH0_REGREQ_CTRL_REQ_URGENT_MASK 0x00000008
    #define SEQ_CH0_REGREQ_CTRL_REQ_URGENT_SHIFT 3
    #define SEQ_CH0_REGREQ_CTRL_REQ_ADR_MASK 0x7FFFFFF0
    #define SEQ_CH0_REGREQ_CTRL_REQ_ADR_SHIFT 4
    #define SEQ_CH0_REGREQ_CTRL_REQ_TAG_MASK 0x80000000
    #define SEQ_CH0_REGREQ_CTRL_REQ_TAG_SHIFT 31
#define  SEQ_CH0_REGREQ_STATUS 0xC05C
    #define SEQ_CH0_REGREQ_STATUS_REQ_IDLE_MASK 0x00000001
    #define SEQ_CH0_REGREQ_STATUS_REQ_IDLE_SHIFT 0
    #define SEQ_CH0_REGREQ_STATUS_REQ_WTAG_MISMATCH_MASK 0x00000002
    #define SEQ_CH0_REGREQ_STATUS_REQ_WTAG_MISMATCH_SHIFT 1
    #define SEQ_CH0_REGREQ_STATUS_REQ_RTAG_MISMATCH_MASK 0x00000004
    #define SEQ_CH0_REGREQ_STATUS_REQ_RTAG_MISMATCH_SHIFT 2
#define  SEQ_CH0_REG_CTRL 0xC020
    #define SEQ_CH0_REG_CTRL_CFGREG_ADDR_MASK 0x0000003F
    #define SEQ_CH0_REG_CTRL_CFGREG_ADDR_SHIFT 0
    #define SEQ_CH0_REG_CTRL_CFGREG_WOP_MASK 0x00000100
    #define SEQ_CH0_REG_CTRL_CFGREG_WOP_SHIFT 8
#define  SEQ_CH0_REG_RDAT 0xC018
    #define SEQ_CH0_REG_RDAT_CFGREG_RDAT_MASK 0xFFFFFFFF
    #define SEQ_CH0_REG_RDAT_CFGREG_RDAT_SHIFT 0
#define  SEQ_CH0_REG_STATUS 0xC01C
    #define SEQ_CH0_REG_STATUS_CFGREG_BUSY_MASK 0x00000001
    #define SEQ_CH0_REG_STATUS_CFGREG_BUSY_SHIFT 0
#define  SEQ_CH0_REG_WDAT 0xC014
    #define SEQ_CH0_REG_WDAT_CFGREG_WDAT_MASK 0xFFFFFFFF
    #define SEQ_CH0_REG_WDAT_CFGREG_WDAT_SHIFT 0
#define  SEQ_CH0_REQ_IDLE_CNT 0xC038
    #define SEQ_CH0_REQ_IDLE_CNT_REG_MASK 0xFFFFFFFF
    #define SEQ_CH0_REQ_IDLE_CNT_REG_SHIFT 0
#define  SEQ_CH0_SECURE_DIRECTIF 0xC03C
    #define SEQ_CH0_SECURE_DIRECTIF_LOCK_EN_MASK 0x00000001
    #define SEQ_CH0_SECURE_DIRECTIF_LOCK_EN_SHIFT 0
    #define SEQ_CH0_SECURE_DIRECTIF_WR_ATTEMPT_MASK 0x10000000
    #define SEQ_CH0_SECURE_DIRECTIF_WR_ATTEMPT_SHIFT 28
    #define SEQ_CH0_SECURE_DIRECTIF_RD_ATTEMPT_MASK 0x20000000
    #define SEQ_CH0_SECURE_DIRECTIF_RD_ATTEMPT_SHIFT 29
    #define SEQ_CH0_SECURE_DIRECTIF_FIX_RANGE_MASK 0x40000000
    #define SEQ_CH0_SECURE_DIRECTIF_FIX_RANGE_SHIFT 30
    #define SEQ_CH0_SECURE_DIRECTIF_SECURE_1MB_MASK 0x80000000
    #define SEQ_CH0_SECURE_DIRECTIF_SECURE_1MB_SHIFT 31
#define  SEQ_CH0_STATUS 0xC028
    #define SEQ_CH0_STATUS_INIT_BUSY_MASK 0x00000001
    #define SEQ_CH0_STATUS_INIT_BUSY_SHIFT 0
    #define SEQ_CH0_STATUS_SEQ_ERROR_MASK 0x00000010
    #define SEQ_CH0_STATUS_SEQ_ERROR_SHIFT 4
    #define SEQ_CH0_STATUS_RING_WVLD_MASK 0x00000100
    #define SEQ_CH0_STATUS_RING_WVLD_SHIFT 8
#define  SEQ_CH0_STATUS_0 0xC008
    #define SEQ_CH0_STATUS_0_DBIST_ERR_CNT_MASK 0x0000003F
    #define SEQ_CH0_STATUS_0_DBIST_ERR_CNT_SHIFT 0
    #define SEQ_CH0_STATUS_0_DBIST_DONE_MASK 0x00000100
    #define SEQ_CH0_STATUS_0_DBIST_DONE_SHIFT 8
    #define SEQ_CH0_STATUS_0_RING_WVLD_ERR_MASK 0x00000200
    #define SEQ_CH0_STATUS_0_RING_WVLD_ERR_SHIFT 9
    #define SEQ_CH0_STATUS_0_LOOPBACK_GOOD_MASK 0x40000000
    #define SEQ_CH0_STATUS_0_LOOPBACK_GOOD_SHIFT 30
    #define SEQ_CH0_STATUS_0_LOOPBACK_DONE_MASK 0x80000000
    #define SEQ_CH0_STATUS_0_LOOPBACK_DONE_SHIFT 31
#define  SEQ_CH0_TIMING0 0xC090
    #define SEQ_CH0_TIMING0_MOD_MASK 0x000003FF
    #define SEQ_CH0_TIMING0_MOD_SHIFT 0
    #define SEQ_CH0_TIMING0_RC_MASK 0x0000FC00
    #define SEQ_CH0_TIMING0_RC_SHIFT 10
    #define SEQ_CH0_TIMING0_RP_MASK 0x000F0000
    #define SEQ_CH0_TIMING0_RP_SHIFT 16
    #define SEQ_CH0_TIMING0_RAS_MIN_MASK 0x01F00000
    #define SEQ_CH0_TIMING0_RAS_MIN_SHIFT 20
    #define SEQ_CH0_TIMING0_RAS_MAX_MASK 0x7E000000
    #define SEQ_CH0_TIMING0_RAS_MAX_SHIFT 25
#define  SEQ_CH0_TIMING1 0xC094
    #define SEQ_CH0_TIMING1_RCD_MASK 0x0000000F
    #define SEQ_CH0_TIMING1_RCD_SHIFT 0
    #define SEQ_CH0_TIMING1_RFC_NOM_X32_MASK 0x0000FFF0
    #define SEQ_CH0_TIMING1_RFC_NOM_X32_SHIFT 4
    #define SEQ_CH0_TIMING1_RFC_MIN_MASK 0x00FF0000
    #define SEQ_CH0_TIMING1_RFC_MIN_SHIFT 16
    #define SEQ_CH0_TIMING1_RRD_MASK 0x07000000
    #define SEQ_CH0_TIMING1_RRD_SHIFT 24
    #define SEQ_CH0_TIMING1_MRD_MASK 0x38000000
    #define SEQ_CH0_TIMING1_MRD_SHIFT 27
    #define SEQ_CH0_TIMING1_CKE_MASK 0xC0000000
    #define SEQ_CH0_TIMING1_CKE_SHIFT 30
#define  SEQ_CH0_TIMING2 0xC098
    #define SEQ_CH0_TIMING2_FAW_MASK 0x0000003F
    #define SEQ_CH0_TIMING2_FAW_SHIFT 0
    #define SEQ_CH0_TIMING2_RD2WR_MASK 0x000007C0
    #define SEQ_CH0_TIMING2_RD2WR_SHIFT 6
    #define SEQ_CH0_TIMING2_WR2RD_MASK 0x0000F800
    #define SEQ_CH0_TIMING2_WR2RD_SHIFT 11
    #define SEQ_CH0_TIMING2_WR_LATENCY_MASK 0x001F0000
    #define SEQ_CH0_TIMING2_WR_LATENCY_SHIFT 16
    #define SEQ_CH0_TIMING2_WR2PRE_MASK 0x03E00000
    #define SEQ_CH0_TIMING2_WR2PRE_SHIFT 21
    #define SEQ_CH0_TIMING2_RD2PRE_MASK 0x7C000000
    #define SEQ_CH0_TIMING2_RD2PRE_SHIFT 26
#define  SEQ_CH0_TIMING3 0xC09C
    #define SEQ_CH0_TIMING3_RD_ODT_DLY_MASK 0x0000000F
    #define SEQ_CH0_TIMING3_RD_ODT_DLY_SHIFT 0
    #define SEQ_CH0_TIMING3_WR_ODT_DLY_MASK 0x000000F0
    #define SEQ_CH0_TIMING3_WR_ODT_DLY_SHIFT 4
    #define SEQ_CH0_TIMING3_RD_ODT_HOLD_MASK 0x00000F00
    #define SEQ_CH0_TIMING3_RD_ODT_HOLD_SHIFT 8
    #define SEQ_CH0_TIMING3_WR_ODT_HOLD_MASK 0x0000F000
    #define SEQ_CH0_TIMING3_WR_ODT_HOLD_SHIFT 12
    #define SEQ_CH0_TIMING3_WR_ODT_BLOCK_MASK 0x00030000
    #define SEQ_CH0_TIMING3_WR_ODT_BLOCK_SHIFT 16
    #define SEQ_CH0_TIMING3_RD_ODT_MASK 0x000C0000
    #define SEQ_CH0_TIMING3_RD_ODT_SHIFT 18
    #define SEQ_CH0_TIMING3_WR_ODT_MASK 0x00300000
    #define SEQ_CH0_TIMING3_WR_ODT_SHIFT 20
    #define SEQ_CH0_TIMING3_WR_MODE_ODT_MASK 0x00800000
    #define SEQ_CH0_TIMING3_WR_MODE_ODT_SHIFT 23
    #define SEQ_CH0_TIMING3_CCD_MASK 0x38000000
    #define SEQ_CH0_TIMING3_CCD_SHIFT 27
#define  SEQ_CH0_TIMING4 0xC0A0
    #define SEQ_CH0_TIMING4_PWRDN_EN_MASK 0x00000001
    #define SEQ_CH0_TIMING4_PWRDN_EN_SHIFT 0
    #define SEQ_CH0_TIMING4_PWRDN_TO_X32_MASK 0x0000003E
    #define SEQ_CH0_TIMING4_PWRDN_TO_X32_SHIFT 1
    #define SEQ_CH0_TIMING4_XP_MASK 0x000007C0
    #define SEQ_CH0_TIMING4_XP_SHIFT 6
    #define SEQ_CH0_TIMING4_POST_SR_GAP_X32_MASK 0x0003F800
    #define SEQ_CH0_TIMING4_POST_SR_GAP_X32_SHIFT 11
    #define SEQ_CH0_TIMING4_PAD_PD_MASK 0x001C0000
    #define SEQ_CH0_TIMING4_PAD_PD_SHIFT 18
    #define SEQ_CH0_TIMING4_DELAY_2T_MASK 0x3FE00000
    #define SEQ_CH0_TIMING4_DELAY_2T_SHIFT 21
    #define SEQ_CH0_TIMING4_EN_2T_MASK 0x40000000
    #define SEQ_CH0_TIMING4_EN_2T_SHIFT 30
    #define SEQ_CH0_TIMING4_SR_EN_MASK 0x80000000
    #define SEQ_CH0_TIMING4_SR_EN_SHIFT 31
#define  SEQ_CH0_TRAN_CTRL0 0xC06C
    #define SEQ_CH0_TRAN_CTRL0_LPR_MAX_STARVE_X32_MASK 0x000007FF
    #define SEQ_CH0_TRAN_CTRL0_LPR_MAX_STARVE_X32_SHIFT 0
    #define SEQ_CH0_TRAN_CTRL0_LPR_XACT_RUN_LENGTH_MASK 0x00007800
    #define SEQ_CH0_TRAN_CTRL0_LPR_XACT_RUN_LENGTH_SHIFT 11
    #define SEQ_CH0_TRAN_CTRL0_LPR_MIN_NON_CRITICAL_MASK 0x3FF80000
    #define SEQ_CH0_TRAN_CTRL0_LPR_MIN_NON_CRITICAL_SHIFT 19
#define  SEQ_CH0_TRAN_CTRL1 0xC070
    #define SEQ_CH0_TRAN_CTRL1_HPR_MAX_STARVE_X32_MASK 0x000007FF
    #define SEQ_CH0_TRAN_CTRL1_HPR_MAX_STARVE_X32_SHIFT 0
    #define SEQ_CH0_TRAN_CTRL1_HPR_XACT_RUN_LENGTH_MASK 0x00007800
    #define SEQ_CH0_TRAN_CTRL1_HPR_XACT_RUN_LENGTH_SHIFT 11
    #define SEQ_CH0_TRAN_CTRL1_HPR_MIN_NON_CRITICAL_MASK 0x3FF80000
    #define SEQ_CH0_TRAN_CTRL1_HPR_MIN_NON_CRITICAL_SHIFT 19
#define  SEQ_CH0_TRAN_CTRL2 0xC074
    #define SEQ_CH0_TRAN_CTRL2_W_XACT_RUN_LENGTH_MASK 0x00007800
    #define SEQ_CH0_TRAN_CTRL2_W_XACT_RUN_LENGTH_SHIFT 11
    #define SEQ_CH0_TRAN_CTRL2_W_MIN_NON_CRITICAL_MASK 0x3FF80000
    #define SEQ_CH0_TRAN_CTRL2_W_MIN_NON_CRITICAL_SHIFT 19
#define  SEQ_CH0_TRAN_CTRL3 0xC078
    #define SEQ_CH0_TRAN_CTRL3_GO2CRIT_HYST_MASK 0x000000FF
    #define SEQ_CH0_TRAN_CTRL3_GO2CRIT_HYST_SHIFT 0
    #define SEQ_CH0_TRAN_CTRL3_GO2CRIT_RD_EN_MASK 0x00000100
    #define SEQ_CH0_TRAN_CTRL3_GO2CRIT_RD_EN_SHIFT 8
    #define SEQ_CH0_TRAN_CTRL3_GO2CRIT_WR_EN_MASK 0x00000200
    #define SEQ_CH0_TRAN_CTRL3_GO2CRIT_WR_EN_SHIFT 9
    #define SEQ_CH0_TRAN_CTRL3_LPR_NUM_ENTRIES_MASK 0x0000FC00
    #define SEQ_CH0_TRAN_CTRL3_LPR_NUM_ENTRIES_SHIFT 10
    #define SEQ_CH0_TRAN_CTRL3_RDWR_IDLE_GAP_MASK 0x007F0000
    #define SEQ_CH0_TRAN_CTRL3_RDWR_IDLE_GAP_SHIFT 16
    #define SEQ_CH0_TRAN_CTRL3_PREFER_WRITE_MASK 0x00800000
    #define SEQ_CH0_TRAN_CTRL3_PREFER_WRITE_SHIFT 23
    #define SEQ_CH0_TRAN_CTRL3_PAGECLOSE_MASK 0x01000000
    #define SEQ_CH0_TRAN_CTRL3_PAGECLOSE_SHIFT 24
    #define SEQ_CH0_TRAN_CTRL3_AUTO_PRE_EN_MASK 0x02000000
    #define SEQ_CH0_TRAN_CTRL3_AUTO_PRE_EN_SHIFT 25
    #define SEQ_CH0_TRAN_CTRL3_FORCE_LP_N_MASK 0x04000000
    #define SEQ_CH0_TRAN_CTRL3_FORCE_LP_N_SHIFT 26
    #define SEQ_CH0_TRAN_CTRL3_DIS_WC_MASK 0x08000000
    #define SEQ_CH0_TRAN_CTRL3_DIS_WC_SHIFT 27
    #define SEQ_CH0_TRAN_CTRL3_DIS_ACT_BYP_MASK 0x10000000
    #define SEQ_CH0_TRAN_CTRL3_DIS_ACT_BYP_SHIFT 28
    #define SEQ_CH0_TRAN_CTRL3_DIS_RD_BYP_MASK 0x20000000
    #define SEQ_CH0_TRAN_CTRL3_DIS_RD_BYP_SHIFT 29
    #define SEQ_CH0_TRAN_CTRL3_DIS_DQUE_MASK 0x40000000
    #define SEQ_CH0_TRAN_CTRL3_DIS_DQUE_SHIFT 30
    #define SEQ_CH0_TRAN_CTRL3_DIS_COL_PG_OPT_MASK 0x80000000
    #define SEQ_CH0_TRAN_CTRL3_DIS_COL_PG_OPT_SHIFT 31
#define  SEQ_CH0_VRG_STATUS 0xC0BC
    #define SEQ_CH0_VRG_STATUS_OP_MODE_MASK 0x00000003
    #define SEQ_CH0_VRG_STATUS_OP_MODE_SHIFT 0
    #define SEQ_CH0_VRG_STATUS_WR_DEPTH_MASK 0x000000FC
    #define SEQ_CH0_VRG_STATUS_WR_DEPTH_SHIFT 2
    #define SEQ_CH0_VRG_STATUS_LPR_DEPTH_MASK 0x00003F00
    #define SEQ_CH0_VRG_STATUS_LPR_DEPTH_SHIFT 8
    #define SEQ_CH0_VRG_STATUS_HPR_DEPTH_MASK 0x003F0000
    #define SEQ_CH0_VRG_STATUS_HPR_DEPTH_SHIFT 16
    #define SEQ_CH0_VRG_STATUS_STALL_MASK 0x00400000
    #define SEQ_CH0_VRG_STATUS_STALL_SHIFT 22
    #define SEQ_CH0_VRG_STATUS_MR_WR_BUSY_MASK 0x00800000
    #define SEQ_CH0_VRG_STATUS_MR_WR_BUSY_SHIFT 23
#define  SEQ_CH0_WRITE_MR 0xC08C
    #define SEQ_CH0_WRITE_MR_MR_DATA_MASK 0x0000FFFF
    #define SEQ_CH0_WRITE_MR_MR_DATA_SHIFT 0
    #define SEQ_CH0_WRITE_MR_MR_ADR_MASK 0x00030000
    #define SEQ_CH0_WRITE_MR_MR_ADR_SHIFT 16
#define  SEQ_CH0_WR_LOCK_STATUS 0xC044
    #define SEQ_CH0_WR_LOCK_STATUS_WRITE_ATTEMPT_CL_ID_MASK 0x0003FFFF
    #define SEQ_CH0_WR_LOCK_STATUS_WRITE_ATTEMPT_CL_ID_SHIFT 0
#define  SEQ_CH0_ZQ0 0xC0AC
    #define SEQ_CH0_ZQ0_T_ZQ_SHORT_NOP_MASK 0x000003FF
    #define SEQ_CH0_ZQ0_T_ZQ_SHORT_NOP_SHIFT 0
    #define SEQ_CH0_ZQ0_T_ZQ_LONG_NOP_MASK 0x003FF000
    #define SEQ_CH0_ZQ0_T_ZQ_LONG_NOP_SHIFT 12
    #define SEQ_CH0_ZQ0_DIS_AUTO_ZQ_MASK 0x40000000
    #define SEQ_CH0_ZQ0_DIS_AUTO_ZQ_SHIFT 30
    #define SEQ_CH0_ZQ0_DO_CALIB_SHORT_MASK 0x80000000
    #define SEQ_CH0_ZQ0_DO_CALIB_SHORT_SHIFT 31
#define  SEQ_CH0_ZQ1 0xC0B0
    #define SEQ_CH0_ZQ1_T_ZQ_SHORT_INT_X1024_MASK 0x000FFFFF
    #define SEQ_CH0_ZQ1_T_ZQ_SHORT_INT_X1024_SHIFT 0
#define  SEQ_CH1_ACTIVE_CNT 0xC434
    #define SEQ_CH1_ACTIVE_CNT_REG_MASK 0xFFFFFFFF
    #define SEQ_CH1_ACTIVE_CNT_REG_SHIFT 0
#define  SEQ_CH1_ADDRMAP0 0xC460
    #define SEQ_CH1_ADDRMAP0_BANK_B0_MASK 0x0000000F
    #define SEQ_CH1_ADDRMAP0_BANK_B0_SHIFT 0
    #define SEQ_CH1_ADDRMAP0_BANK_B1_MASK 0x000000F0
    #define SEQ_CH1_ADDRMAP0_BANK_B1_SHIFT 4
    #define SEQ_CH1_ADDRMAP0_BANK_B2_MASK 0x00000F00
    #define SEQ_CH1_ADDRMAP0_BANK_B2_SHIFT 8
#define  SEQ_CH1_ADDRMAP1 0xC464
    #define SEQ_CH1_ADDRMAP1_COL_B2_MASK 0x0000000F
    #define SEQ_CH1_ADDRMAP1_COL_B2_SHIFT 0
    #define SEQ_CH1_ADDRMAP1_COL_B3_MASK 0x000000F0
    #define SEQ_CH1_ADDRMAP1_COL_B3_SHIFT 4
    #define SEQ_CH1_ADDRMAP1_COL_B4_6_MASK 0x00000F00
    #define SEQ_CH1_ADDRMAP1_COL_B4_6_SHIFT 8
    #define SEQ_CH1_ADDRMAP1_COL_B7_MASK 0x0000F000
    #define SEQ_CH1_ADDRMAP1_COL_B7_SHIFT 12
    #define SEQ_CH1_ADDRMAP1_COL_B8_MASK 0x000F0000
    #define SEQ_CH1_ADDRMAP1_COL_B8_SHIFT 16
    #define SEQ_CH1_ADDRMAP1_COL_B9_MASK 0x00F00000
    #define SEQ_CH1_ADDRMAP1_COL_B9_SHIFT 20
    #define SEQ_CH1_ADDRMAP1_COL_B10_MASK 0x0F000000
    #define SEQ_CH1_ADDRMAP1_COL_B10_SHIFT 24
    #define SEQ_CH1_ADDRMAP1_COL_B11_MASK 0xF0000000
    #define SEQ_CH1_ADDRMAP1_COL_B11_SHIFT 28
#define  SEQ_CH1_ADDRMAP2 0xC468
    #define SEQ_CH1_ADDRMAP2_ROW_B0_MASK 0x0000000F
    #define SEQ_CH1_ADDRMAP2_ROW_B0_SHIFT 0
    #define SEQ_CH1_ADDRMAP2_ROW_B1_MASK 0x000000F0
    #define SEQ_CH1_ADDRMAP2_ROW_B1_SHIFT 4
    #define SEQ_CH1_ADDRMAP2_ROW_B2_11_MASK 0x00000F00
    #define SEQ_CH1_ADDRMAP2_ROW_B2_11_SHIFT 8
    #define SEQ_CH1_ADDRMAP2_ROW_B12_MASK 0x0000F000
    #define SEQ_CH1_ADDRMAP2_ROW_B12_SHIFT 12
    #define SEQ_CH1_ADDRMAP2_ROW_B13_MASK 0x000F0000
    #define SEQ_CH1_ADDRMAP2_ROW_B13_SHIFT 16
    #define SEQ_CH1_ADDRMAP2_ROW_B14_MASK 0x00F00000
    #define SEQ_CH1_ADDRMAP2_ROW_B14_SHIFT 20
    #define SEQ_CH1_ADDRMAP2_ROW_B15_MASK 0x0F000000
    #define SEQ_CH1_ADDRMAP2_ROW_B15_SHIFT 24
#define  SEQ_CH1_CYCLE_CNT 0xC430
    #define SEQ_CH1_CYCLE_CNT_REG_MASK 0xFFFFFFFF
    #define SEQ_CH1_CYCLE_CNT_REG_SHIFT 0
#define  SEQ_CH1_DEBUG_BUS 0xC40C
    #define SEQ_CH1_DEBUG_BUS_REG_MASK 0xFFFFFFFF
    #define SEQ_CH1_DEBUG_BUS_REG_SHIFT 0
#define  SEQ_CH1_DIRECTIF_UNLOCK_RANGE 0xC440
    #define SEQ_CH1_DIRECTIF_UNLOCK_RANGE_START_ADDR_MASK 0x000007FF
    #define SEQ_CH1_DIRECTIF_UNLOCK_RANGE_START_ADDR_SHIFT 0
    #define SEQ_CH1_DIRECTIF_UNLOCK_RANGE_END_ADDR_MASK 0x07FF0000
    #define SEQ_CH1_DIRECTIF_UNLOCK_RANGE_END_ADDR_SHIFT 16
#define  SEQ_CH1_DLL 0xC4A8
    #define SEQ_CH1_DLL_CALIB_MIN_X1024_MASK 0x000000FF
    #define SEQ_CH1_DLL_CALIB_MIN_X1024_SHIFT 0
    #define SEQ_CH1_DLL_CALIB_MAX_X1024_MASK 0x0000FF00
    #define SEQ_CH1_DLL_CALIB_MAX_X1024_SHIFT 8
    #define SEQ_CH1_DLL_DIS_DLL_CALIB_MASK 0x40000000
    #define SEQ_CH1_DLL_DIS_DLL_CALIB_SHIFT 30
    #define SEQ_CH1_DLL_DO_CALIB_MASK 0x80000000
    #define SEQ_CH1_DLL_DO_CALIB_SHIFT 31
#define  SEQ_CH1_DRAM_BIST 0xC410
    #define SEQ_CH1_DRAM_BIST_REQ_SIZE_MASK 0x00000003
    #define SEQ_CH1_DRAM_BIST_REQ_SIZE_SHIFT 0
    #define SEQ_CH1_DRAM_BIST_REQ_WOP_MASK 0x0000000C
    #define SEQ_CH1_DRAM_BIST_REQ_WOP_SHIFT 2
    #define SEQ_CH1_DRAM_BIST_REQ_COUNT_MASK 0x000003F0
    #define SEQ_CH1_DRAM_BIST_REQ_COUNT_SHIFT 4
    #define SEQ_CH1_DRAM_BIST_REQ_ADR_MASK 0x00001000
    #define SEQ_CH1_DRAM_BIST_REQ_ADR_SHIFT 12
    #define SEQ_CH1_DRAM_BIST_RNDM_DAT_MASK 0x00002000
    #define SEQ_CH1_DRAM_BIST_RNDM_DAT_SHIFT 13
    #define SEQ_CH1_DRAM_BIST_RNDM_DAT_CNTR_MASK 0x00004000
    #define SEQ_CH1_DRAM_BIST_RNDM_DAT_CNTR_SHIFT 14
    #define SEQ_CH1_DRAM_BIST_RNDM_WBE_MASK 0x00008000
    #define SEQ_CH1_DRAM_BIST_RNDM_WBE_SHIFT 15
    #define SEQ_CH1_DRAM_BIST_DBIST_STOP_MASK 0x00010000
    #define SEQ_CH1_DRAM_BIST_DBIST_STOP_SHIFT 16
    #define SEQ_CH1_DRAM_BIST_DUMP_ERR_DAT_MASK 0x00020000
    #define SEQ_CH1_DRAM_BIST_DUMP_ERR_DAT_SHIFT 17
#define  SEQ_CH1_DUMMY_REG 0xC400
    #define SEQ_CH1_DUMMY_REG_REG_MASK 0xFFFFFFFF
    #define SEQ_CH1_DUMMY_REG_REG_SHIFT 0
#define  SEQ_CH1_FPGA_CTRL 0xC700
    #define SEQ_CH1_FPGA_CTRL_EN_SCRAMBLE_MASK 0x00000001
    #define SEQ_CH1_FPGA_CTRL_EN_SCRAMBLE_SHIFT 0
    #define SEQ_CH1_FPGA_CTRL_SBC_ACTIVE_MASK 0x00000002
    #define SEQ_CH1_FPGA_CTRL_SBC_ACTIVE_SHIFT 1
#define  SEQ_CH1_INIT0 0xC47C
    #define SEQ_CH1_INIT0_PRE_CKE_X1024_MASK 0x000000FF
    #define SEQ_CH1_INIT0_PRE_CKE_X1024_SHIFT 0
    #define SEQ_CH1_INIT0_POST_CKE_X1024_MASK 0x0000FF00
    #define SEQ_CH1_INIT0_POST_CKE_X1024_SHIFT 8
    #define SEQ_CH1_INIT0_PRE_OCD_X32_MASK 0x000F0000
    #define SEQ_CH1_INIT0_PRE_OCD_X32_SHIFT 16
    #define SEQ_CH1_INIT0_FINAL_WAIT_X32_MASK 0x07F00000
    #define SEQ_CH1_INIT0_FINAL_WAIT_X32_SHIFT 20
    #define SEQ_CH1_INIT0_SKIP_OCD_INIT_MASK 0x80000000
    #define SEQ_CH1_INIT0_SKIP_OCD_INIT_SHIFT 31
#define  SEQ_CH1_INIT1 0xC480
    #define SEQ_CH1_INIT1_DRAM_RSTN_X1024_MASK 0x000000FF
    #define SEQ_CH1_INIT1_DRAM_RSTN_X1024_SHIFT 0
#define  SEQ_CH1_INIT2 0xC484
    #define SEQ_CH1_INIT2_MR_MASK 0x0000FFFF
    #define SEQ_CH1_INIT2_MR_SHIFT 0
    #define SEQ_CH1_INIT2_EMR_MASK 0xFFFF0000
    #define SEQ_CH1_INIT2_EMR_SHIFT 16
#define  SEQ_CH1_INIT3 0xC488
    #define SEQ_CH1_INIT3_EMR2_MASK 0x0000FFFF
    #define SEQ_CH1_INIT3_EMR2_SHIFT 0
    #define SEQ_CH1_INIT3_EMR3_MASK 0xFFFF0000
    #define SEQ_CH1_INIT3_EMR3_SHIFT 16
#define  SEQ_CH1_IOCALIB_CTRL 0xC660
    #define SEQ_CH1_IOCALIB_CTRL_CUSTOM_PCAL150_MASK 0x0000000F
    #define SEQ_CH1_IOCALIB_CTRL_CUSTOM_PCAL150_SHIFT 0
    #define SEQ_CH1_IOCALIB_CTRL_CUSTOM_NCAL150_MASK 0x000000F0
    #define SEQ_CH1_IOCALIB_CTRL_CUSTOM_NCAL150_SHIFT 4
    #define SEQ_CH1_IOCALIB_CTRL_CUSTOM_PCAL240_MASK 0x00000F00
    #define SEQ_CH1_IOCALIB_CTRL_CUSTOM_PCAL240_SHIFT 8
    #define SEQ_CH1_IOCALIB_CTRL_CUSTOM_NCAL240_MASK 0x0000F000
    #define SEQ_CH1_IOCALIB_CTRL_CUSTOM_NCAL240_SHIFT 12
    #define SEQ_CH1_IOCALIB_CTRL_CUSTOM_CALIB_MASK 0x00010000
    #define SEQ_CH1_IOCALIB_CTRL_CUSTOM_CALIB_SHIFT 16
    #define SEQ_CH1_IOCALIB_CTRL_START_CALIB_MASK 0x00020000
    #define SEQ_CH1_IOCALIB_CTRL_START_CALIB_SHIFT 17
    #define SEQ_CH1_IOCALIB_CTRL_DDR2_MODE_MASK 0x00040000
    #define SEQ_CH1_IOCALIB_CTRL_DDR2_MODE_SHIFT 18
    #define SEQ_CH1_IOCALIB_CTRL_POWERDOWN_MODE_MASK 0x00080000
    #define SEQ_CH1_IOCALIB_CTRL_POWERDOWN_MODE_SHIFT 19
    #define SEQ_CH1_IOCALIB_CTRL_CODE_MOD_EN_MASK 0x00100000
    #define SEQ_CH1_IOCALIB_CTRL_CODE_MOD_EN_SHIFT 20
    #define SEQ_CH1_IOCALIB_CTRL_CODE_MOD_VAL_MASK 0x00600000
    #define SEQ_CH1_IOCALIB_CTRL_CODE_MOD_VAL_SHIFT 21
#define  SEQ_CH1_IOCALIB_STATUS 0xC664
    #define SEQ_CH1_IOCALIB_STATUS_CALIB_VAL_PCAL150_MASK 0x0000000F
    #define SEQ_CH1_IOCALIB_STATUS_CALIB_VAL_PCAL150_SHIFT 0
    #define SEQ_CH1_IOCALIB_STATUS_CALIB_VAL_NCAL150_MASK 0x000000F0
    #define SEQ_CH1_IOCALIB_STATUS_CALIB_VAL_NCAL150_SHIFT 4
    #define SEQ_CH1_IOCALIB_STATUS_CALIB_VAL_PCAL240_MASK 0x00000F00
    #define SEQ_CH1_IOCALIB_STATUS_CALIB_VAL_PCAL240_SHIFT 8
    #define SEQ_CH1_IOCALIB_STATUS_CALIB_VAL_NCAL240_MASK 0x0000F000
    #define SEQ_CH1_IOCALIB_STATUS_CALIB_VAL_NCAL240_SHIFT 12
    #define SEQ_CH1_IOCALIB_STATUS_DETECT_CNT_PCAL150_MASK 0x000F0000
    #define SEQ_CH1_IOCALIB_STATUS_DETECT_CNT_PCAL150_SHIFT 16
    #define SEQ_CH1_IOCALIB_STATUS_DETECT_CNT_NCAL150_MASK 0x00F00000
    #define SEQ_CH1_IOCALIB_STATUS_DETECT_CNT_NCAL150_SHIFT 20
    #define SEQ_CH1_IOCALIB_STATUS_DETECT_CNT_PCAL240_MASK 0x0F000000
    #define SEQ_CH1_IOCALIB_STATUS_DETECT_CNT_PCAL240_SHIFT 24
    #define SEQ_CH1_IOCALIB_STATUS_DETECT_CNT_NCAL240_MASK 0xF0000000
    #define SEQ_CH1_IOCALIB_STATUS_DETECT_CNT_NCAL240_SHIFT 28
#define  SEQ_CH1_IO_ADR_A 0xC640
    #define SEQ_CH1_IO_ADR_A_DDR2_MODE_MASK 0x00000001
    #define SEQ_CH1_IO_ADR_A_DDR2_MODE_SHIFT 0
    #define SEQ_CH1_IO_ADR_A_RD_ODT_VAL_MASK 0x0000000E
    #define SEQ_CH1_IO_ADR_A_RD_ODT_VAL_SHIFT 1
    #define SEQ_CH1_IO_ADR_A_DRV_STRENGTH_MASK 0x00000070
    #define SEQ_CH1_IO_ADR_A_DRV_STRENGTH_SHIFT 4
    #define SEQ_CH1_IO_ADR_A_DRVR_DLAY_MASK 0x00000700
    #define SEQ_CH1_IO_ADR_A_DRVR_DLAY_SHIFT 8
    #define SEQ_CH1_IO_ADR_A_DRVR_DUTY_MASK 0x00007000
    #define SEQ_CH1_IO_ADR_A_DRVR_DUTY_SHIFT 12
    #define SEQ_CH1_IO_ADR_A_RCVR_DUTY_MASK 0x00070000
    #define SEQ_CH1_IO_ADR_A_RCVR_DUTY_SHIFT 16
    #define SEQ_CH1_IO_ADR_A_RCVR_DIFEN_MASK 0x00F00000
    #define SEQ_CH1_IO_ADR_A_RCVR_DIFEN_SHIFT 20
    #define SEQ_CH1_IO_ADR_A_RCVR_DIFFDDR2_MASK 0x01000000
    #define SEQ_CH1_IO_ADR_A_RCVR_DIFFDDR2_SHIFT 24
    #define SEQ_CH1_IO_ADR_A_VREF_MUX_MASK 0x06000000
    #define SEQ_CH1_IO_ADR_A_VREF_MUX_SHIFT 25
    #define SEQ_CH1_IO_ADR_A_DODT_EN_MASK 0x10000000
    #define SEQ_CH1_IO_ADR_A_DODT_EN_SHIFT 28
    #define SEQ_CH1_IO_ADR_A_DODT_VAL_MASK 0x60000000
    #define SEQ_CH1_IO_ADR_A_DODT_VAL_SHIFT 29
#define  SEQ_CH1_IO_ADR_B 0xC644
    #define SEQ_CH1_IO_ADR_B_DRVR_SR_EN_MASK 0x0000001F
    #define SEQ_CH1_IO_ADR_B_DRVR_SR_EN_SHIFT 0
    #define SEQ_CH1_IO_ADR_B_DRVR_PEMPH_EN_MASK 0x00000F00
    #define SEQ_CH1_IO_ADR_B_DRVR_PEMPH_EN_SHIFT 8
    #define SEQ_CH1_IO_ADR_B_TRANSMIT_EN_MASK 0x00001000
    #define SEQ_CH1_IO_ADR_B_TRANSMIT_EN_SHIFT 12
    #define SEQ_CH1_IO_ADR_B_RCVR_CMOS_EN_MASK 0x00002000
    #define SEQ_CH1_IO_ADR_B_RCVR_CMOS_EN_SHIFT 13
    #define SEQ_CH1_IO_ADR_B_RCVR_TEN_MASK 0x00004000
    #define SEQ_CH1_IO_ADR_B_RCVR_TEN_SHIFT 14
#define  SEQ_CH1_IO_CLK_A 0xC650
    #define SEQ_CH1_IO_CLK_A_DDR2_MODE_MASK 0x00000001
    #define SEQ_CH1_IO_CLK_A_DDR2_MODE_SHIFT 0
    #define SEQ_CH1_IO_CLK_A_RD_ODT_VAL_MASK 0x0000000E
    #define SEQ_CH1_IO_CLK_A_RD_ODT_VAL_SHIFT 1
    #define SEQ_CH1_IO_CLK_A_DRV_STRENGTH_MASK 0x00000070
    #define SEQ_CH1_IO_CLK_A_DRV_STRENGTH_SHIFT 4
    #define SEQ_CH1_IO_CLK_A_DRVR_DLAY_MASK 0x00000700
    #define SEQ_CH1_IO_CLK_A_DRVR_DLAY_SHIFT 8
    #define SEQ_CH1_IO_CLK_A_DRVR_DUTY_MASK 0x00007000
    #define SEQ_CH1_IO_CLK_A_DRVR_DUTY_SHIFT 12
    #define SEQ_CH1_IO_CLK_A_RCVR_DUTY_MASK 0x00070000
    #define SEQ_CH1_IO_CLK_A_RCVR_DUTY_SHIFT 16
    #define SEQ_CH1_IO_CLK_A_RCVR_DIFEN_MASK 0x00F00000
    #define SEQ_CH1_IO_CLK_A_RCVR_DIFEN_SHIFT 20
    #define SEQ_CH1_IO_CLK_A_RCVR_DIFFDDR2_MASK 0x01000000
    #define SEQ_CH1_IO_CLK_A_RCVR_DIFFDDR2_SHIFT 24
    #define SEQ_CH1_IO_CLK_A_VREF_MUX_MASK 0x06000000
    #define SEQ_CH1_IO_CLK_A_VREF_MUX_SHIFT 25
    #define SEQ_CH1_IO_CLK_A_DODT_EN_MASK 0x10000000
    #define SEQ_CH1_IO_CLK_A_DODT_EN_SHIFT 28
    #define SEQ_CH1_IO_CLK_A_DODT_VAL_MASK 0x60000000
    #define SEQ_CH1_IO_CLK_A_DODT_VAL_SHIFT 29
#define  SEQ_CH1_IO_CLK_B 0xC654
    #define SEQ_CH1_IO_CLK_B_DRVR_SR_EN_MASK 0x0000001F
    #define SEQ_CH1_IO_CLK_B_DRVR_SR_EN_SHIFT 0
    #define SEQ_CH1_IO_CLK_B_DRVR_PEMPH_EN_MASK 0x00000F00
    #define SEQ_CH1_IO_CLK_B_DRVR_PEMPH_EN_SHIFT 8
    #define SEQ_CH1_IO_CLK_B_TRANSMIT_EN_MASK 0x00001000
    #define SEQ_CH1_IO_CLK_B_TRANSMIT_EN_SHIFT 12
    #define SEQ_CH1_IO_CLK_B_RCVR_CMOS_EN_MASK 0x00002000
    #define SEQ_CH1_IO_CLK_B_RCVR_CMOS_EN_SHIFT 13
#define  SEQ_CH1_IO_CMD_A 0xC648
    #define SEQ_CH1_IO_CMD_A_DDR2_MODE_MASK 0x00000001
    #define SEQ_CH1_IO_CMD_A_DDR2_MODE_SHIFT 0
    #define SEQ_CH1_IO_CMD_A_RD_ODT_VAL_MASK 0x0000000E
    #define SEQ_CH1_IO_CMD_A_RD_ODT_VAL_SHIFT 1
    #define SEQ_CH1_IO_CMD_A_DRV_STRENGTH_MASK 0x00000070
    #define SEQ_CH1_IO_CMD_A_DRV_STRENGTH_SHIFT 4
    #define SEQ_CH1_IO_CMD_A_DRVR_DLAY_MASK 0x00000700
    #define SEQ_CH1_IO_CMD_A_DRVR_DLAY_SHIFT 8
    #define SEQ_CH1_IO_CMD_A_DRVR_DUTY_MASK 0x00007000
    #define SEQ_CH1_IO_CMD_A_DRVR_DUTY_SHIFT 12
    #define SEQ_CH1_IO_CMD_A_RCVR_DUTY_MASK 0x00070000
    #define SEQ_CH1_IO_CMD_A_RCVR_DUTY_SHIFT 16
    #define SEQ_CH1_IO_CMD_A_RCVR_DIFEN_MASK 0x00F00000
    #define SEQ_CH1_IO_CMD_A_RCVR_DIFEN_SHIFT 20
    #define SEQ_CH1_IO_CMD_A_RCVR_DIFFDDR2_MASK 0x01000000
    #define SEQ_CH1_IO_CMD_A_RCVR_DIFFDDR2_SHIFT 24
    #define SEQ_CH1_IO_CMD_A_VREF_MUX_MASK 0x06000000
    #define SEQ_CH1_IO_CMD_A_VREF_MUX_SHIFT 25
    #define SEQ_CH1_IO_CMD_A_DODT_EN_MASK 0x10000000
    #define SEQ_CH1_IO_CMD_A_DODT_EN_SHIFT 28
    #define SEQ_CH1_IO_CMD_A_DODT_VAL_MASK 0x60000000
    #define SEQ_CH1_IO_CMD_A_DODT_VAL_SHIFT 29
#define  SEQ_CH1_IO_CMD_B 0xC64C
    #define SEQ_CH1_IO_CMD_B_DRVR_SR_EN_MASK 0x0000001F
    #define SEQ_CH1_IO_CMD_B_DRVR_SR_EN_SHIFT 0
    #define SEQ_CH1_IO_CMD_B_DRVR_PEMPH_EN_MASK 0x00000F00
    #define SEQ_CH1_IO_CMD_B_DRVR_PEMPH_EN_SHIFT 8
    #define SEQ_CH1_IO_CMD_B_TRANSMIT_EN_MASK 0x00001000
    #define SEQ_CH1_IO_CMD_B_TRANSMIT_EN_SHIFT 12
    #define SEQ_CH1_IO_CMD_B_RCVR_CMOS_EN_MASK 0x00002000
    #define SEQ_CH1_IO_CMD_B_RCVR_CMOS_EN_SHIFT 13
    #define SEQ_CH1_IO_CMD_B_RCVR_TEN_MASK 0x00004000
    #define SEQ_CH1_IO_CMD_B_RCVR_TEN_SHIFT 14
#define  SEQ_CH1_IO_DQS_BYTE0_A 0xC608
    #define SEQ_CH1_IO_DQS_BYTE0_A_DDR2_MODE_MASK 0x00000001
    #define SEQ_CH1_IO_DQS_BYTE0_A_DDR2_MODE_SHIFT 0
    #define SEQ_CH1_IO_DQS_BYTE0_A_RD_ODT_VAL_MASK 0x0000000E
    #define SEQ_CH1_IO_DQS_BYTE0_A_RD_ODT_VAL_SHIFT 1
    #define SEQ_CH1_IO_DQS_BYTE0_A_DRV_STRENGTH_MASK 0x00000070
    #define SEQ_CH1_IO_DQS_BYTE0_A_DRV_STRENGTH_SHIFT 4
    #define SEQ_CH1_IO_DQS_BYTE0_A_DRVR_DLAY_MASK 0x00000700
    #define SEQ_CH1_IO_DQS_BYTE0_A_DRVR_DLAY_SHIFT 8
    #define SEQ_CH1_IO_DQS_BYTE0_A_DRVR_DUTY_MASK 0x00007000
    #define SEQ_CH1_IO_DQS_BYTE0_A_DRVR_DUTY_SHIFT 12
    #define SEQ_CH1_IO_DQS_BYTE0_A_RCVR_DUTY_MASK 0x00070000
    #define SEQ_CH1_IO_DQS_BYTE0_A_RCVR_DUTY_SHIFT 16
    #define SEQ_CH1_IO_DQS_BYTE0_A_RCVR_DIFEN_MASK 0x00F00000
    #define SEQ_CH1_IO_DQS_BYTE0_A_RCVR_DIFEN_SHIFT 20
    #define SEQ_CH1_IO_DQS_BYTE0_A_RCVR_DIFFDDR2_MASK 0x01000000
    #define SEQ_CH1_IO_DQS_BYTE0_A_RCVR_DIFFDDR2_SHIFT 24
    #define SEQ_CH1_IO_DQS_BYTE0_A_VREF_MUX_MASK 0x06000000
    #define SEQ_CH1_IO_DQS_BYTE0_A_VREF_MUX_SHIFT 25
    #define SEQ_CH1_IO_DQS_BYTE0_A_DODT_EN_MASK 0x10000000
    #define SEQ_CH1_IO_DQS_BYTE0_A_DODT_EN_SHIFT 28
    #define SEQ_CH1_IO_DQS_BYTE0_A_DODT_VAL_MASK 0x60000000
    #define SEQ_CH1_IO_DQS_BYTE0_A_DODT_VAL_SHIFT 29
#define  SEQ_CH1_IO_DQS_BYTE0_B 0xC60C
    #define SEQ_CH1_IO_DQS_BYTE0_B_DRVR_SR_EN_MASK 0x0000001F
    #define SEQ_CH1_IO_DQS_BYTE0_B_DRVR_SR_EN_SHIFT 0
    #define SEQ_CH1_IO_DQS_BYTE0_B_DRVR_PEMPH_EN_MASK 0x00000F00
    #define SEQ_CH1_IO_DQS_BYTE0_B_DRVR_PEMPH_EN_SHIFT 8
    #define SEQ_CH1_IO_DQS_BYTE0_B_RCVR_CMOS_EN_MASK 0x00002000
    #define SEQ_CH1_IO_DQS_BYTE0_B_RCVR_CMOS_EN_SHIFT 13
    #define SEQ_CH1_IO_DQS_BYTE0_B_RCVR_DIFFERENTIAL_MASK 0x00008000
    #define SEQ_CH1_IO_DQS_BYTE0_B_RCVR_DIFFERENTIAL_SHIFT 15
#define  SEQ_CH1_IO_DQS_BYTE1_A 0xC618
    #define SEQ_CH1_IO_DQS_BYTE1_A_DDR2_MODE_MASK 0x00000001
    #define SEQ_CH1_IO_DQS_BYTE1_A_DDR2_MODE_SHIFT 0
    #define SEQ_CH1_IO_DQS_BYTE1_A_RD_ODT_VAL_MASK 0x0000000E
    #define SEQ_CH1_IO_DQS_BYTE1_A_RD_ODT_VAL_SHIFT 1
    #define SEQ_CH1_IO_DQS_BYTE1_A_DRV_STRENGTH_MASK 0x00000070
    #define SEQ_CH1_IO_DQS_BYTE1_A_DRV_STRENGTH_SHIFT 4
    #define SEQ_CH1_IO_DQS_BYTE1_A_DRVR_DLAY_MASK 0x00000700
    #define SEQ_CH1_IO_DQS_BYTE1_A_DRVR_DLAY_SHIFT 8
    #define SEQ_CH1_IO_DQS_BYTE1_A_DRVR_DUTY_MASK 0x00007000
    #define SEQ_CH1_IO_DQS_BYTE1_A_DRVR_DUTY_SHIFT 12
    #define SEQ_CH1_IO_DQS_BYTE1_A_RCVR_DUTY_MASK 0x00070000
    #define SEQ_CH1_IO_DQS_BYTE1_A_RCVR_DUTY_SHIFT 16
    #define SEQ_CH1_IO_DQS_BYTE1_A_RCVR_DIFEN_MASK 0x00F00000
    #define SEQ_CH1_IO_DQS_BYTE1_A_RCVR_DIFEN_SHIFT 20
    #define SEQ_CH1_IO_DQS_BYTE1_A_RCVR_DIFFDDR2_MASK 0x01000000
    #define SEQ_CH1_IO_DQS_BYTE1_A_RCVR_DIFFDDR2_SHIFT 24
    #define SEQ_CH1_IO_DQS_BYTE1_A_VREF_MUX_MASK 0x06000000
    #define SEQ_CH1_IO_DQS_BYTE1_A_VREF_MUX_SHIFT 25
    #define SEQ_CH1_IO_DQS_BYTE1_A_DODT_EN_MASK 0x10000000
    #define SEQ_CH1_IO_DQS_BYTE1_A_DODT_EN_SHIFT 28
    #define SEQ_CH1_IO_DQS_BYTE1_A_DODT_VAL_MASK 0x60000000
    #define SEQ_CH1_IO_DQS_BYTE1_A_DODT_VAL_SHIFT 29
#define  SEQ_CH1_IO_DQS_BYTE1_B 0xC61C
    #define SEQ_CH1_IO_DQS_BYTE1_B_DRVR_SR_EN_MASK 0x0000001F
    #define SEQ_CH1_IO_DQS_BYTE1_B_DRVR_SR_EN_SHIFT 0
    #define SEQ_CH1_IO_DQS_BYTE1_B_DRVR_PEMPH_EN_MASK 0x00000F00
    #define SEQ_CH1_IO_DQS_BYTE1_B_DRVR_PEMPH_EN_SHIFT 8
    #define SEQ_CH1_IO_DQS_BYTE1_B_RCVR_CMOS_EN_MASK 0x00002000
    #define SEQ_CH1_IO_DQS_BYTE1_B_RCVR_CMOS_EN_SHIFT 13
    #define SEQ_CH1_IO_DQS_BYTE1_B_RCVR_DIFFERENTIAL_MASK 0x00008000
    #define SEQ_CH1_IO_DQS_BYTE1_B_RCVR_DIFFERENTIAL_SHIFT 15
#define  SEQ_CH1_IO_DQS_BYTE2_A 0xC628
    #define SEQ_CH1_IO_DQS_BYTE2_A_DDR2_MODE_MASK 0x00000001
    #define SEQ_CH1_IO_DQS_BYTE2_A_DDR2_MODE_SHIFT 0
    #define SEQ_CH1_IO_DQS_BYTE2_A_RD_ODT_VAL_MASK 0x0000000E
    #define SEQ_CH1_IO_DQS_BYTE2_A_RD_ODT_VAL_SHIFT 1
    #define SEQ_CH1_IO_DQS_BYTE2_A_DRV_STRENGTH_MASK 0x00000070
    #define SEQ_CH1_IO_DQS_BYTE2_A_DRV_STRENGTH_SHIFT 4
    #define SEQ_CH1_IO_DQS_BYTE2_A_DRVR_DLAY_MASK 0x00000700
    #define SEQ_CH1_IO_DQS_BYTE2_A_DRVR_DLAY_SHIFT 8
    #define SEQ_CH1_IO_DQS_BYTE2_A_DRVR_DUTY_MASK 0x00007000
    #define SEQ_CH1_IO_DQS_BYTE2_A_DRVR_DUTY_SHIFT 12
    #define SEQ_CH1_IO_DQS_BYTE2_A_RCVR_DUTY_MASK 0x00070000
    #define SEQ_CH1_IO_DQS_BYTE2_A_RCVR_DUTY_SHIFT 16
    #define SEQ_CH1_IO_DQS_BYTE2_A_RCVR_DIFEN_MASK 0x00F00000
    #define SEQ_CH1_IO_DQS_BYTE2_A_RCVR_DIFEN_SHIFT 20
    #define SEQ_CH1_IO_DQS_BYTE2_A_RCVR_DIFFDDR2_MASK 0x01000000
    #define SEQ_CH1_IO_DQS_BYTE2_A_RCVR_DIFFDDR2_SHIFT 24
    #define SEQ_CH1_IO_DQS_BYTE2_A_VREF_MUX_MASK 0x06000000
    #define SEQ_CH1_IO_DQS_BYTE2_A_VREF_MUX_SHIFT 25
    #define SEQ_CH1_IO_DQS_BYTE2_A_DODT_EN_MASK 0x10000000
    #define SEQ_CH1_IO_DQS_BYTE2_A_DODT_EN_SHIFT 28
    #define SEQ_CH1_IO_DQS_BYTE2_A_DODT_VAL_MASK 0x60000000
    #define SEQ_CH1_IO_DQS_BYTE2_A_DODT_VAL_SHIFT 29
#define  SEQ_CH1_IO_DQS_BYTE2_B 0xC62C
    #define SEQ_CH1_IO_DQS_BYTE2_B_DRVR_SR_EN_MASK 0x0000001F
    #define SEQ_CH1_IO_DQS_BYTE2_B_DRVR_SR_EN_SHIFT 0
    #define SEQ_CH1_IO_DQS_BYTE2_B_DRVR_PEMPH_EN_MASK 0x00000F00
    #define SEQ_CH1_IO_DQS_BYTE2_B_DRVR_PEMPH_EN_SHIFT 8
    #define SEQ_CH1_IO_DQS_BYTE2_B_RCVR_CMOS_EN_MASK 0x00002000
    #define SEQ_CH1_IO_DQS_BYTE2_B_RCVR_CMOS_EN_SHIFT 13
    #define SEQ_CH1_IO_DQS_BYTE2_B_RCVR_DIFFERENTIAL_MASK 0x00008000
    #define SEQ_CH1_IO_DQS_BYTE2_B_RCVR_DIFFERENTIAL_SHIFT 15
#define  SEQ_CH1_IO_DQS_BYTE3_A 0xC638
    #define SEQ_CH1_IO_DQS_BYTE3_A_DDR2_MODE_MASK 0x00000001
    #define SEQ_CH1_IO_DQS_BYTE3_A_DDR2_MODE_SHIFT 0
    #define SEQ_CH1_IO_DQS_BYTE3_A_RD_ODT_VAL_MASK 0x0000000E
    #define SEQ_CH1_IO_DQS_BYTE3_A_RD_ODT_VAL_SHIFT 1
    #define SEQ_CH1_IO_DQS_BYTE3_A_DRV_STRENGTH_MASK 0x00000070
    #define SEQ_CH1_IO_DQS_BYTE3_A_DRV_STRENGTH_SHIFT 4
    #define SEQ_CH1_IO_DQS_BYTE3_A_DRVR_DLAY_MASK 0x00000700
    #define SEQ_CH1_IO_DQS_BYTE3_A_DRVR_DLAY_SHIFT 8
    #define SEQ_CH1_IO_DQS_BYTE3_A_DRVR_DUTY_MASK 0x00007000
    #define SEQ_CH1_IO_DQS_BYTE3_A_DRVR_DUTY_SHIFT 12
    #define SEQ_CH1_IO_DQS_BYTE3_A_RCVR_DUTY_MASK 0x00070000
    #define SEQ_CH1_IO_DQS_BYTE3_A_RCVR_DUTY_SHIFT 16
    #define SEQ_CH1_IO_DQS_BYTE3_A_RCVR_DIFEN_MASK 0x00F00000
    #define SEQ_CH1_IO_DQS_BYTE3_A_RCVR_DIFEN_SHIFT 20
    #define SEQ_CH1_IO_DQS_BYTE3_A_RCVR_DIFFDDR2_MASK 0x01000000
    #define SEQ_CH1_IO_DQS_BYTE3_A_RCVR_DIFFDDR2_SHIFT 24
    #define SEQ_CH1_IO_DQS_BYTE3_A_VREF_MUX_MASK 0x06000000
    #define SEQ_CH1_IO_DQS_BYTE3_A_VREF_MUX_SHIFT 25
    #define SEQ_CH1_IO_DQS_BYTE3_A_DODT_EN_MASK 0x10000000
    #define SEQ_CH1_IO_DQS_BYTE3_A_DODT_EN_SHIFT 28
    #define SEQ_CH1_IO_DQS_BYTE3_A_DODT_VAL_MASK 0x60000000
    #define SEQ_CH1_IO_DQS_BYTE3_A_DODT_VAL_SHIFT 29
#define  SEQ_CH1_IO_DQS_BYTE3_B 0xC63C
    #define SEQ_CH1_IO_DQS_BYTE3_B_DRVR_SR_EN_MASK 0x0000001F
    #define SEQ_CH1_IO_DQS_BYTE3_B_DRVR_SR_EN_SHIFT 0
    #define SEQ_CH1_IO_DQS_BYTE3_B_DRVR_PEMPH_EN_MASK 0x00000F00
    #define SEQ_CH1_IO_DQS_BYTE3_B_DRVR_PEMPH_EN_SHIFT 8
    #define SEQ_CH1_IO_DQS_BYTE3_B_RCVR_CMOS_EN_MASK 0x00002000
    #define SEQ_CH1_IO_DQS_BYTE3_B_RCVR_CMOS_EN_SHIFT 13
    #define SEQ_CH1_IO_DQS_BYTE3_B_RCVR_DIFFERENTIAL_MASK 0x00008000
    #define SEQ_CH1_IO_DQS_BYTE3_B_RCVR_DIFFERENTIAL_SHIFT 15
#define  SEQ_CH1_IO_DQ_BYTE0_A 0xC600
    #define SEQ_CH1_IO_DQ_BYTE0_A_DDR2_MODE_MASK 0x00000001
    #define SEQ_CH1_IO_DQ_BYTE0_A_DDR2_MODE_SHIFT 0
    #define SEQ_CH1_IO_DQ_BYTE0_A_RD_ODT_VAL_MASK 0x0000000E
    #define SEQ_CH1_IO_DQ_BYTE0_A_RD_ODT_VAL_SHIFT 1
    #define SEQ_CH1_IO_DQ_BYTE0_A_DRV_STRENGTH_MASK 0x00000070
    #define SEQ_CH1_IO_DQ_BYTE0_A_DRV_STRENGTH_SHIFT 4
    #define SEQ_CH1_IO_DQ_BYTE0_A_DRVR_DLAY_MASK 0x00000700
    #define SEQ_CH1_IO_DQ_BYTE0_A_DRVR_DLAY_SHIFT 8
    #define SEQ_CH1_IO_DQ_BYTE0_A_DRVR_DUTY_MASK 0x00007000
    #define SEQ_CH1_IO_DQ_BYTE0_A_DRVR_DUTY_SHIFT 12
    #define SEQ_CH1_IO_DQ_BYTE0_A_RCVR_DUTY_MASK 0x00070000
    #define SEQ_CH1_IO_DQ_BYTE0_A_RCVR_DUTY_SHIFT 16
    #define SEQ_CH1_IO_DQ_BYTE0_A_RCVR_DIFEN_MASK 0x00F00000
    #define SEQ_CH1_IO_DQ_BYTE0_A_RCVR_DIFEN_SHIFT 20
    #define SEQ_CH1_IO_DQ_BYTE0_A_RCVR_DIFFDDR2_MASK 0x01000000
    #define SEQ_CH1_IO_DQ_BYTE0_A_RCVR_DIFFDDR2_SHIFT 24
    #define SEQ_CH1_IO_DQ_BYTE0_A_VREF_MUX_MASK 0x06000000
    #define SEQ_CH1_IO_DQ_BYTE0_A_VREF_MUX_SHIFT 25
    #define SEQ_CH1_IO_DQ_BYTE0_A_DODT_EN_MASK 0x10000000
    #define SEQ_CH1_IO_DQ_BYTE0_A_DODT_EN_SHIFT 28
    #define SEQ_CH1_IO_DQ_BYTE0_A_DODT_VAL_MASK 0x60000000
    #define SEQ_CH1_IO_DQ_BYTE0_A_DODT_VAL_SHIFT 29
#define  SEQ_CH1_IO_DQ_BYTE0_B 0xC604
    #define SEQ_CH1_IO_DQ_BYTE0_B_DRVR_SR_EN_MASK 0x0000001F
    #define SEQ_CH1_IO_DQ_BYTE0_B_DRVR_SR_EN_SHIFT 0
    #define SEQ_CH1_IO_DQ_BYTE0_B_DRVR_PEMPH_EN_MASK 0x00000F00
    #define SEQ_CH1_IO_DQ_BYTE0_B_DRVR_PEMPH_EN_SHIFT 8
    #define SEQ_CH1_IO_DQ_BYTE0_B_TRANSMIT_EN_MASK 0x00001000
    #define SEQ_CH1_IO_DQ_BYTE0_B_TRANSMIT_EN_SHIFT 12
    #define SEQ_CH1_IO_DQ_BYTE0_B_RCVR_CMOS_EN_MASK 0x00002000
    #define SEQ_CH1_IO_DQ_BYTE0_B_RCVR_CMOS_EN_SHIFT 13
    #define SEQ_CH1_IO_DQ_BYTE0_B_RCVR_TEN_MASK 0x00004000
    #define SEQ_CH1_IO_DQ_BYTE0_B_RCVR_TEN_SHIFT 14
#define  SEQ_CH1_IO_DQ_BYTE1_A 0xC610
    #define SEQ_CH1_IO_DQ_BYTE1_A_DDR2_MODE_MASK 0x00000001
    #define SEQ_CH1_IO_DQ_BYTE1_A_DDR2_MODE_SHIFT 0
    #define SEQ_CH1_IO_DQ_BYTE1_A_RD_ODT_VAL_MASK 0x0000000E
    #define SEQ_CH1_IO_DQ_BYTE1_A_RD_ODT_VAL_SHIFT 1
    #define SEQ_CH1_IO_DQ_BYTE1_A_DRV_STRENGTH_MASK 0x00000070
    #define SEQ_CH1_IO_DQ_BYTE1_A_DRV_STRENGTH_SHIFT 4
    #define SEQ_CH1_IO_DQ_BYTE1_A_DRVR_DLAY_MASK 0x00000700
    #define SEQ_CH1_IO_DQ_BYTE1_A_DRVR_DLAY_SHIFT 8
    #define SEQ_CH1_IO_DQ_BYTE1_A_DRVR_DUTY_MASK 0x00007000
    #define SEQ_CH1_IO_DQ_BYTE1_A_DRVR_DUTY_SHIFT 12
    #define SEQ_CH1_IO_DQ_BYTE1_A_RCVR_DUTY_MASK 0x00070000
    #define SEQ_CH1_IO_DQ_BYTE1_A_RCVR_DUTY_SHIFT 16
    #define SEQ_CH1_IO_DQ_BYTE1_A_RCVR_DIFEN_MASK 0x00F00000
    #define SEQ_CH1_IO_DQ_BYTE1_A_RCVR_DIFEN_SHIFT 20
    #define SEQ_CH1_IO_DQ_BYTE1_A_RCVR_DIFFDDR2_MASK 0x01000000
    #define SEQ_CH1_IO_DQ_BYTE1_A_RCVR_DIFFDDR2_SHIFT 24
    #define SEQ_CH1_IO_DQ_BYTE1_A_VREF_MUX_MASK 0x06000000
    #define SEQ_CH1_IO_DQ_BYTE1_A_VREF_MUX_SHIFT 25
    #define SEQ_CH1_IO_DQ_BYTE1_A_DODT_EN_MASK 0x10000000
    #define SEQ_CH1_IO_DQ_BYTE1_A_DODT_EN_SHIFT 28
    #define SEQ_CH1_IO_DQ_BYTE1_A_DODT_VAL_MASK 0x60000000
    #define SEQ_CH1_IO_DQ_BYTE1_A_DODT_VAL_SHIFT 29
#define  SEQ_CH1_IO_DQ_BYTE1_B 0xC614
    #define SEQ_CH1_IO_DQ_BYTE1_B_DRVR_SR_EN_MASK 0x0000001F
    #define SEQ_CH1_IO_DQ_BYTE1_B_DRVR_SR_EN_SHIFT 0
    #define SEQ_CH1_IO_DQ_BYTE1_B_DRVR_PEMPH_EN_MASK 0x00000F00
    #define SEQ_CH1_IO_DQ_BYTE1_B_DRVR_PEMPH_EN_SHIFT 8
    #define SEQ_CH1_IO_DQ_BYTE1_B_TRANSMIT_EN_MASK 0x00001000
    #define SEQ_CH1_IO_DQ_BYTE1_B_TRANSMIT_EN_SHIFT 12
    #define SEQ_CH1_IO_DQ_BYTE1_B_RCVR_CMOS_EN_MASK 0x00002000
    #define SEQ_CH1_IO_DQ_BYTE1_B_RCVR_CMOS_EN_SHIFT 13
    #define SEQ_CH1_IO_DQ_BYTE1_B_RCVR_TEN_MASK 0x00004000
    #define SEQ_CH1_IO_DQ_BYTE1_B_RCVR_TEN_SHIFT 14
#define  SEQ_CH1_IO_DQ_BYTE2_A 0xC620
    #define SEQ_CH1_IO_DQ_BYTE2_A_DDR2_MODE_MASK 0x00000001
    #define SEQ_CH1_IO_DQ_BYTE2_A_DDR2_MODE_SHIFT 0
    #define SEQ_CH1_IO_DQ_BYTE2_A_RD_ODT_VAL_MASK 0x0000000E
    #define SEQ_CH1_IO_DQ_BYTE2_A_RD_ODT_VAL_SHIFT 1
    #define SEQ_CH1_IO_DQ_BYTE2_A_DRV_STRENGTH_MASK 0x00000070
    #define SEQ_CH1_IO_DQ_BYTE2_A_DRV_STRENGTH_SHIFT 4
    #define SEQ_CH1_IO_DQ_BYTE2_A_DRVR_DLAY_MASK 0x00000700
    #define SEQ_CH1_IO_DQ_BYTE2_A_DRVR_DLAY_SHIFT 8
    #define SEQ_CH1_IO_DQ_BYTE2_A_DRVR_DUTY_MASK 0x00007000
    #define SEQ_CH1_IO_DQ_BYTE2_A_DRVR_DUTY_SHIFT 12
    #define SEQ_CH1_IO_DQ_BYTE2_A_RCVR_DUTY_MASK 0x00070000
    #define SEQ_CH1_IO_DQ_BYTE2_A_RCVR_DUTY_SHIFT 16
    #define SEQ_CH1_IO_DQ_BYTE2_A_RCVR_DIFEN_MASK 0x00F00000
    #define SEQ_CH1_IO_DQ_BYTE2_A_RCVR_DIFEN_SHIFT 20
    #define SEQ_CH1_IO_DQ_BYTE2_A_RCVR_DIFFDDR2_MASK 0x01000000
    #define SEQ_CH1_IO_DQ_BYTE2_A_RCVR_DIFFDDR2_SHIFT 24
    #define SEQ_CH1_IO_DQ_BYTE2_A_VREF_MUX_MASK 0x06000000
    #define SEQ_CH1_IO_DQ_BYTE2_A_VREF_MUX_SHIFT 25
    #define SEQ_CH1_IO_DQ_BYTE2_A_DODT_EN_MASK 0x10000000
    #define SEQ_CH1_IO_DQ_BYTE2_A_DODT_EN_SHIFT 28
    #define SEQ_CH1_IO_DQ_BYTE2_A_DODT_VAL_MASK 0x60000000
    #define SEQ_CH1_IO_DQ_BYTE2_A_DODT_VAL_SHIFT 29
#define  SEQ_CH1_IO_DQ_BYTE2_B 0xC624
    #define SEQ_CH1_IO_DQ_BYTE2_B_DRVR_SR_EN_MASK 0x0000001F
    #define SEQ_CH1_IO_DQ_BYTE2_B_DRVR_SR_EN_SHIFT 0
    #define SEQ_CH1_IO_DQ_BYTE2_B_DRVR_PEMPH_EN_MASK 0x00000F00
    #define SEQ_CH1_IO_DQ_BYTE2_B_DRVR_PEMPH_EN_SHIFT 8
    #define SEQ_CH1_IO_DQ_BYTE2_B_TRANSMIT_EN_MASK 0x00001000
    #define SEQ_CH1_IO_DQ_BYTE2_B_TRANSMIT_EN_SHIFT 12
    #define SEQ_CH1_IO_DQ_BYTE2_B_RCVR_CMOS_EN_MASK 0x00002000
    #define SEQ_CH1_IO_DQ_BYTE2_B_RCVR_CMOS_EN_SHIFT 13
    #define SEQ_CH1_IO_DQ_BYTE2_B_RCVR_TEN_MASK 0x00004000
    #define SEQ_CH1_IO_DQ_BYTE2_B_RCVR_TEN_SHIFT 14
#define  SEQ_CH1_IO_DQ_BYTE3_A 0xC630
    #define SEQ_CH1_IO_DQ_BYTE3_A_DDR2_MODE_MASK 0x00000001
    #define SEQ_CH1_IO_DQ_BYTE3_A_DDR2_MODE_SHIFT 0
    #define SEQ_CH1_IO_DQ_BYTE3_A_RD_ODT_VAL_MASK 0x0000000E
    #define SEQ_CH1_IO_DQ_BYTE3_A_RD_ODT_VAL_SHIFT 1
    #define SEQ_CH1_IO_DQ_BYTE3_A_DRV_STRENGTH_MASK 0x00000070
    #define SEQ_CH1_IO_DQ_BYTE3_A_DRV_STRENGTH_SHIFT 4
    #define SEQ_CH1_IO_DQ_BYTE3_A_DRVR_DLAY_MASK 0x00000700
    #define SEQ_CH1_IO_DQ_BYTE3_A_DRVR_DLAY_SHIFT 8
    #define SEQ_CH1_IO_DQ_BYTE3_A_DRVR_DUTY_MASK 0x00007000
    #define SEQ_CH1_IO_DQ_BYTE3_A_DRVR_DUTY_SHIFT 12
    #define SEQ_CH1_IO_DQ_BYTE3_A_RCVR_DUTY_MASK 0x00070000
    #define SEQ_CH1_IO_DQ_BYTE3_A_RCVR_DUTY_SHIFT 16
    #define SEQ_CH1_IO_DQ_BYTE3_A_RCVR_DIFEN_MASK 0x00F00000
    #define SEQ_CH1_IO_DQ_BYTE3_A_RCVR_DIFEN_SHIFT 20
    #define SEQ_CH1_IO_DQ_BYTE3_A_RCVR_DIFFDDR2_MASK 0x01000000
    #define SEQ_CH1_IO_DQ_BYTE3_A_RCVR_DIFFDDR2_SHIFT 24
    #define SEQ_CH1_IO_DQ_BYTE3_A_VREF_MUX_MASK 0x06000000
    #define SEQ_CH1_IO_DQ_BYTE3_A_VREF_MUX_SHIFT 25
    #define SEQ_CH1_IO_DQ_BYTE3_A_DODT_EN_MASK 0x10000000
    #define SEQ_CH1_IO_DQ_BYTE3_A_DODT_EN_SHIFT 28
    #define SEQ_CH1_IO_DQ_BYTE3_A_DODT_VAL_MASK 0x60000000
    #define SEQ_CH1_IO_DQ_BYTE3_A_DODT_VAL_SHIFT 29
#define  SEQ_CH1_IO_DQ_BYTE3_B 0xC634
    #define SEQ_CH1_IO_DQ_BYTE3_B_DRVR_SR_EN_MASK 0x0000001F
    #define SEQ_CH1_IO_DQ_BYTE3_B_DRVR_SR_EN_SHIFT 0
    #define SEQ_CH1_IO_DQ_BYTE3_B_DRVR_PEMPH_EN_MASK 0x00000F00
    #define SEQ_CH1_IO_DQ_BYTE3_B_DRVR_PEMPH_EN_SHIFT 8
    #define SEQ_CH1_IO_DQ_BYTE3_B_TRANSMIT_EN_MASK 0x00001000
    #define SEQ_CH1_IO_DQ_BYTE3_B_TRANSMIT_EN_SHIFT 12
    #define SEQ_CH1_IO_DQ_BYTE3_B_RCVR_CMOS_EN_MASK 0x00002000
    #define SEQ_CH1_IO_DQ_BYTE3_B_RCVR_CMOS_EN_SHIFT 13
    #define SEQ_CH1_IO_DQ_BYTE3_B_RCVR_TEN_MASK 0x00004000
    #define SEQ_CH1_IO_DQ_BYTE3_B_RCVR_TEN_SHIFT 14
#define  SEQ_CH1_IO_MISC 0xC658
    #define SEQ_CH1_IO_MISC_VREF_ADJ_MASK 0x0000000F
    #define SEQ_CH1_IO_MISC_VREF_ADJ_SHIFT 0
    #define SEQ_CH1_IO_MISC_VREF_PD_BUF_MASK 0x00000010
    #define SEQ_CH1_IO_MISC_VREF_PD_BUF_SHIFT 4
    #define SEQ_CH1_IO_MISC_VREF_PD_REF_MASK 0x00000020
    #define SEQ_CH1_IO_MISC_VREF_PD_REF_SHIFT 5
    #define SEQ_CH1_IO_MISC_ZQ_PD_MASK 0x00000040
    #define SEQ_CH1_IO_MISC_ZQ_PD_SHIFT 6
    #define SEQ_CH1_IO_MISC_ZQ_PS_MASK 0x00000080
    #define SEQ_CH1_IO_MISC_ZQ_PS_SHIFT 7
    #define SEQ_CH1_IO_MISC_CLK_TIME2_MASK 0x00000200
    #define SEQ_CH1_IO_MISC_CLK_TIME2_SHIFT 9
    #define SEQ_CH1_IO_MISC_DBG_NDQSIN_MASK 0x00000400
    #define SEQ_CH1_IO_MISC_DBG_NDQSIN_SHIFT 10
    #define SEQ_CH1_IO_MISC_DBG_FFWEIN_EN_MASK 0x00000800
    #define SEQ_CH1_IO_MISC_DBG_FFWEIN_EN_SHIFT 11
    #define SEQ_CH1_IO_MISC_DBG_FFWEIN_DAT_MASK 0x00001000
    #define SEQ_CH1_IO_MISC_DBG_FFWEIN_DAT_SHIFT 12
#define  SEQ_CH1_ITM_CTRL 0xC42C
    #define SEQ_CH1_ITM_CTRL_MDLL_RSTN_MASK 0x00000001
    #define SEQ_CH1_ITM_CTRL_MDLL_RSTN_SHIFT 0
    #define SEQ_CH1_ITM_CTRL_MSDLL0_RSTN_MASK 0x00000002
    #define SEQ_CH1_ITM_CTRL_MSDLL0_RSTN_SHIFT 1
    #define SEQ_CH1_ITM_CTRL_MSDLL1_RSTN_MASK 0x00000004
    #define SEQ_CH1_ITM_CTRL_MSDLL1_RSTN_SHIFT 2
    #define SEQ_CH1_ITM_CTRL_MSDLL2_RSTN_MASK 0x00000008
    #define SEQ_CH1_ITM_CTRL_MSDLL2_RSTN_SHIFT 3
    #define SEQ_CH1_ITM_CTRL_MSDLL3_RSTN_MASK 0x00000010
    #define SEQ_CH1_ITM_CTRL_MSDLL3_RSTN_SHIFT 4
    #define SEQ_CH1_ITM_CTRL_DTP_OUT_MASK 0x00000700
    #define SEQ_CH1_ITM_CTRL_DTP_OUT_SHIFT 8
#define  SEQ_CH1_LOOPBACK 0xC4B8
    #define SEQ_CH1_LOOPBACK_ADDR_MASK 0x7FFFFFFF
    #define SEQ_CH1_LOOPBACK_ADDR_SHIFT 0
#define  SEQ_CH1_MISC_REG 0xC424
    #define SEQ_CH1_MISC_REG_MSDCFG_RSTN_MASK 0x00000001
    #define SEQ_CH1_MISC_REG_MSDCFG_RSTN_SHIFT 0
    #define SEQ_CH1_MISC_REG_MSDSEQ_RSTN_MASK 0x00000002
    #define SEQ_CH1_MISC_REG_MSDSEQ_RSTN_SHIFT 1
    #define SEQ_CH1_MISC_REG_M2XLOGIC_RSTN_MASK 0x00000004
    #define SEQ_CH1_MISC_REG_M2XLOGIC_RSTN_SHIFT 2
    #define SEQ_CH1_MISC_REG_MDLOGIC_RSTN_MASK 0x00000008
    #define SEQ_CH1_MISC_REG_MDLOGIC_RSTN_SHIFT 3
    #define SEQ_CH1_MISC_REG_CTRLWRAP_RSTN_MASK 0x00000010
    #define SEQ_CH1_MISC_REG_CTRLWRAP_RSTN_SHIFT 4
    #define SEQ_CH1_MISC_REG_TEST_MODE_MASK 0x00000300
    #define SEQ_CH1_MISC_REG_TEST_MODE_SHIFT 8
    #define SEQ_CH1_MISC_REG_DLL_BYPASS_MASK 0x00000400
    #define SEQ_CH1_MISC_REG_DLL_BYPASS_SHIFT 10
    #define SEQ_CH1_MISC_REG_INIT_BYPASS_MASK 0x00000800
    #define SEQ_CH1_MISC_REG_INIT_BYPASS_SHIFT 11
    #define SEQ_CH1_MISC_REG_SSTL18_PADS_MASK 0x00010000
    #define SEQ_CH1_MISC_REG_SSTL18_PADS_SHIFT 16
    #define SEQ_CH1_MISC_REG_BSTLENGTH_MASK 0x00020000
    #define SEQ_CH1_MISC_REG_BSTLENGTH_SHIFT 17
#define  SEQ_CH1_MISC_REG_0 0xC404
    #define SEQ_CH1_MISC_REG_0_MRCLK_RSTN_MASK 0x00000001
    #define SEQ_CH1_MISC_REG_0_MRCLK_RSTN_SHIFT 0
    #define SEQ_CH1_MISC_REG_0_MCLK_RSTN_MASK 0x00000002
    #define SEQ_CH1_MISC_REG_0_MCLK_RSTN_SHIFT 1
    #define SEQ_CH1_MISC_REG_0_SEQCLK_RSTN_MASK 0x00000004
    #define SEQ_CH1_MISC_REG_0_SEQCLK_RSTN_SHIFT 2
    #define SEQ_CH1_MISC_REG_0_CTRLWRAP_RSTN_MASK 0x00000010
    #define SEQ_CH1_MISC_REG_0_CTRLWRAP_RSTN_SHIFT 4
    #define SEQ_CH1_MISC_REG_0_IPWRAP_RSTN_MASK 0x00000020
    #define SEQ_CH1_MISC_REG_0_IPWRAP_RSTN_SHIFT 5
    #define SEQ_CH1_MISC_REG_0_SOFT_IP_RSTN_MASK 0x00000040
    #define SEQ_CH1_MISC_REG_0_SOFT_IP_RSTN_SHIFT 6
    #define SEQ_CH1_MISC_REG_0_DBIST_RSTN_MASK 0x00000080
    #define SEQ_CH1_MISC_REG_0_DBIST_RSTN_SHIFT 7
    #define SEQ_CH1_MISC_REG_0_PHY_SEQCLK_RSTN_MASK 0x00000100
    #define SEQ_CH1_MISC_REG_0_PHY_SEQCLK_RSTN_SHIFT 8
    #define SEQ_CH1_MISC_REG_0_PHY_SEQ2XCLK_RSTN_MASK 0x00000200
    #define SEQ_CH1_MISC_REG_0_PHY_SEQ2XCLK_RSTN_SHIFT 9
    #define SEQ_CH1_MISC_REG_0_PHY_CALIBCLK_RSTN_MASK 0x00000400
    #define SEQ_CH1_MISC_REG_0_PHY_CALIBCLK_RSTN_SHIFT 10
    #define SEQ_CH1_MISC_REG_0_IO_ASYNC_RSTN_MASK 0x00000800
    #define SEQ_CH1_MISC_REG_0_IO_ASYNC_RSTN_SHIFT 11
    #define SEQ_CH1_MISC_REG_0_BSTLENGTH_MASK 0x00010000
    #define SEQ_CH1_MISC_REG_0_BSTLENGTH_SHIFT 16
    #define SEQ_CH1_MISC_REG_0_SHADOW_MEM_EN_MASK 0x00020000
    #define SEQ_CH1_MISC_REG_0_SHADOW_MEM_EN_SHIFT 17
    #define SEQ_CH1_MISC_REG_0_STAT_EN_MASK 0x00040000
    #define SEQ_CH1_MISC_REG_0_STAT_EN_SHIFT 18
    #define SEQ_CH1_MISC_REG_0_DRAM_BIST_EN_MASK 0x00080000
    #define SEQ_CH1_MISC_REG_0_DRAM_BIST_EN_SHIFT 19
    #define SEQ_CH1_MISC_REG_0_GATE_REQ_EN_MASK 0x00800000
    #define SEQ_CH1_MISC_REG_0_GATE_REQ_EN_SHIFT 23
    #define SEQ_CH1_MISC_REG_0_DDR3_MODE_MASK 0x01000000
    #define SEQ_CH1_MISC_REG_0_DDR3_MODE_SHIFT 24
    #define SEQ_CH1_MISC_REG_0_LOOPBACK_MODE_MASK 0x02000000
    #define SEQ_CH1_MISC_REG_0_LOOPBACK_MODE_SHIFT 25
    #define SEQ_CH1_MISC_REG_0_DBG_MUX_SEL_MASK 0xFC000000
    #define SEQ_CH1_MISC_REG_0_DBG_MUX_SEL_SHIFT 26
#define  SEQ_CH1_PHY_CTRL0 0xC4D8
    #define SEQ_CH1_PHY_CTRL0_RD_TO_DAT_MASK 0x0000001F
    #define SEQ_CH1_PHY_CTRL0_RD_TO_DAT_SHIFT 0
    #define SEQ_CH1_PHY_CTRL0_WR_TO_DAT_MASK 0x00000F80
    #define SEQ_CH1_PHY_CTRL0_WR_TO_DAT_SHIFT 7
    #define SEQ_CH1_PHY_CTRL0_RD_LOCAL_ODT_MASK 0x00030000
    #define SEQ_CH1_PHY_CTRL0_RD_LOCAL_ODT_SHIFT 16
    #define SEQ_CH1_PHY_CTRL0_WR_LOCAL_ODT_MASK 0x000C0000
    #define SEQ_CH1_PHY_CTRL0_WR_LOCAL_ODT_SHIFT 18
    #define SEQ_CH1_PHY_CTRL0_IDLE_LOCAL_ODT_MASK 0x00300000
    #define SEQ_CH1_PHY_CTRL0_IDLE_LOCAL_ODT_SHIFT 20
    #define SEQ_CH1_PHY_CTRL0_RDC_WE_TO_RE_MASK 0x00C00000
    #define SEQ_CH1_PHY_CTRL0_RDC_WE_TO_RE_SHIFT 22
    #define SEQ_CH1_PHY_CTRL0_USE_FIXED_RE_MASK 0x01000000
    #define SEQ_CH1_PHY_CTRL0_USE_FIXED_RE_SHIFT 24
    #define SEQ_CH1_PHY_CTRL0_RDCFF_RST_DIS_MASK 0x02000000
    #define SEQ_CH1_PHY_CTRL0_RDCFF_RST_DIS_SHIFT 25
    #define SEQ_CH1_PHY_CTRL0_RDCFF_RST_ERR_CLR_MASK 0x04000000
    #define SEQ_CH1_PHY_CTRL0_RDCFF_RST_ERR_CLR_SHIFT 26
#define  SEQ_CH1_PHY_CTRL1 0xC4DC
    #define SEQ_CH1_PHY_CTRL1_CTRL_SLAVE_RATIO_MASK 0x000000FF
    #define SEQ_CH1_PHY_CTRL1_CTRL_SLAVE_RATIO_SHIFT 0
    #define SEQ_CH1_PHY_CTRL1_CTRL_SLAVE_FORCE_MASK 0x00000100
    #define SEQ_CH1_PHY_CTRL1_CTRL_SLAVE_FORCE_SHIFT 8
    #define SEQ_CH1_PHY_CTRL1_CTRL_SLAVE_DELAY_MASK 0x0000FE00
    #define SEQ_CH1_PHY_CTRL1_CTRL_SLAVE_DELAY_SHIFT 9
#define  SEQ_CH1_PHY_MISC_REG 0xC4D0
    #define SEQ_CH1_PHY_MISC_REG_DEBUG_MODE_MASK 0x00000004
    #define SEQ_CH1_PHY_MISC_REG_DEBUG_MODE_SHIFT 2
    #define SEQ_CH1_PHY_MISC_REG_TEST_EN_MASK 0x00000008
    #define SEQ_CH1_PHY_MISC_REG_TEST_EN_SHIFT 3
    #define SEQ_CH1_PHY_MISC_REG_BSTCHOP_EN_MASK 0x00000010
    #define SEQ_CH1_PHY_MISC_REG_BSTCHOP_EN_SHIFT 4
    #define SEQ_CH1_PHY_MISC_REG_DATBUS_WIDTH_MASK 0x00000020
    #define SEQ_CH1_PHY_MISC_REG_DATBUS_WIDTH_SHIFT 5
    #define SEQ_CH1_PHY_MISC_REG_RD_LEVEL_START_MASK 0x00000040
    #define SEQ_CH1_PHY_MISC_REG_RD_LEVEL_START_SHIFT 6
    #define SEQ_CH1_PHY_MISC_REG_WR_LEVEL_START_MASK 0x00000080
    #define SEQ_CH1_PHY_MISC_REG_WR_LEVEL_START_SHIFT 7
    #define SEQ_CH1_PHY_MISC_REG_DQ0_WAIT_T_MASK 0x00000F00
    #define SEQ_CH1_PHY_MISC_REG_DQ0_WAIT_T_SHIFT 8
#define  SEQ_CH1_PHY_SLICE0_0 0xC4E0
    #define SEQ_CH1_PHY_SLICE0_0_RD_DQS_SL_RATIO_MASK 0x000000FF
    #define SEQ_CH1_PHY_SLICE0_0_RD_DQS_SL_RATIO_SHIFT 0
    #define SEQ_CH1_PHY_SLICE0_0_RD_DQS_SL_FORCE_MASK 0x00000100
    #define SEQ_CH1_PHY_SLICE0_0_RD_DQS_SL_FORCE_SHIFT 8
    #define SEQ_CH1_PHY_SLICE0_0_RD_DQS_SL_DELAY_MASK 0x0000FE00
    #define SEQ_CH1_PHY_SLICE0_0_RD_DQS_SL_DELAY_SHIFT 9
    #define SEQ_CH1_PHY_SLICE0_0_RD_DQS_DEF_SL_RATIO_MASK 0x00FF0000
    #define SEQ_CH1_PHY_SLICE0_0_RD_DQS_DEF_SL_RATIO_SHIFT 16
#define  SEQ_CH1_PHY_SLICE0_1 0xC4E4
    #define SEQ_CH1_PHY_SLICE0_1_WR_DQS_SL_RATIO_MASK 0x000000FF
    #define SEQ_CH1_PHY_SLICE0_1_WR_DQS_SL_RATIO_SHIFT 0
    #define SEQ_CH1_PHY_SLICE0_1_WR_DQS_SL_FORCE_MASK 0x00000100
    #define SEQ_CH1_PHY_SLICE0_1_WR_DQS_SL_FORCE_SHIFT 8
    #define SEQ_CH1_PHY_SLICE0_1_WR_DQS_SL_DELAY_MASK 0x0000FE00
    #define SEQ_CH1_PHY_SLICE0_1_WR_DQS_SL_DELAY_SHIFT 9
#define  SEQ_CH1_PHY_SLICE0_2 0xC4E8
    #define SEQ_CH1_PHY_SLICE0_2_WR_DQ_SL_RATIO_MASK 0x000000FF
    #define SEQ_CH1_PHY_SLICE0_2_WR_DQ_SL_RATIO_SHIFT 0
    #define SEQ_CH1_PHY_SLICE0_2_WR_DQ_SL_FORCE_MASK 0x00000100
    #define SEQ_CH1_PHY_SLICE0_2_WR_DQ_SL_FORCE_SHIFT 8
    #define SEQ_CH1_PHY_SLICE0_2_WR_DQ_SL_DELAY_MASK 0x0000FE00
    #define SEQ_CH1_PHY_SLICE0_2_WR_DQ_SL_DELAY_SHIFT 9
    #define SEQ_CH1_PHY_SLICE0_2_WR_DQ_OFFSET_MASK 0x007F0000
    #define SEQ_CH1_PHY_SLICE0_2_WR_DQ_OFFSET_SHIFT 16
#define  SEQ_CH1_PHY_SLICE0_3 0xC4EC
    #define SEQ_CH1_PHY_SLICE0_3_FIFO_WE_FORCE_MODE_MASK 0x00000001
    #define SEQ_CH1_PHY_SLICE0_3_FIFO_WE_FORCE_MODE_SHIFT 0
    #define SEQ_CH1_PHY_SLICE0_3_FIFO_WE_SL_RATIO_MASK 0x0000FF00
    #define SEQ_CH1_PHY_SLICE0_3_FIFO_WE_SL_RATIO_SHIFT 8
    #define SEQ_CH1_PHY_SLICE0_3_FIFO_WE_IN_FORCE_MASK 0x00010000
    #define SEQ_CH1_PHY_SLICE0_3_FIFO_WE_IN_FORCE_SHIFT 16
    #define SEQ_CH1_PHY_SLICE0_3_FIFO_WE_IN_DELAY_MASK 0x00FE0000
    #define SEQ_CH1_PHY_SLICE0_3_FIFO_WE_IN_DELAY_SHIFT 17
#define  SEQ_CH1_PHY_SLICE1_0 0xC4F0
    #define SEQ_CH1_PHY_SLICE1_0_RD_DQS_SL_RATIO_MASK 0x000000FF
    #define SEQ_CH1_PHY_SLICE1_0_RD_DQS_SL_RATIO_SHIFT 0
    #define SEQ_CH1_PHY_SLICE1_0_RD_DQS_SL_FORCE_MASK 0x00000100
    #define SEQ_CH1_PHY_SLICE1_0_RD_DQS_SL_FORCE_SHIFT 8
    #define SEQ_CH1_PHY_SLICE1_0_RD_DQS_SL_DELAY_MASK 0x0000FE00
    #define SEQ_CH1_PHY_SLICE1_0_RD_DQS_SL_DELAY_SHIFT 9
    #define SEQ_CH1_PHY_SLICE1_0_RD_DQS_DEF_SL_RATIO_MASK 0x00FF0000
    #define SEQ_CH1_PHY_SLICE1_0_RD_DQS_DEF_SL_RATIO_SHIFT 16
#define  SEQ_CH1_PHY_SLICE1_1 0xC4F4
    #define SEQ_CH1_PHY_SLICE1_1_WR_DQS_SL_RATIO_MASK 0x000000FF
    #define SEQ_CH1_PHY_SLICE1_1_WR_DQS_SL_RATIO_SHIFT 0
    #define SEQ_CH1_PHY_SLICE1_1_WR_DQS_SL_FORCE_MASK 0x00000100
    #define SEQ_CH1_PHY_SLICE1_1_WR_DQS_SL_FORCE_SHIFT 8
    #define SEQ_CH1_PHY_SLICE1_1_WR_DQS_SL_DELAY_MASK 0x0000FE00
    #define SEQ_CH1_PHY_SLICE1_1_WR_DQS_SL_DELAY_SHIFT 9
#define  SEQ_CH1_PHY_SLICE1_2 0xC4F8
    #define SEQ_CH1_PHY_SLICE1_2_WR_DQ_SL_RATIO_MASK 0x000000FF
    #define SEQ_CH1_PHY_SLICE1_2_WR_DQ_SL_RATIO_SHIFT 0
    #define SEQ_CH1_PHY_SLICE1_2_WR_DQ_SL_FORCE_MASK 0x00000100
    #define SEQ_CH1_PHY_SLICE1_2_WR_DQ_SL_FORCE_SHIFT 8
    #define SEQ_CH1_PHY_SLICE1_2_WR_DQ_SL_DELAY_MASK 0x0000FE00
    #define SEQ_CH1_PHY_SLICE1_2_WR_DQ_SL_DELAY_SHIFT 9
    #define SEQ_CH1_PHY_SLICE1_2_WR_DQ_OFFSET_MASK 0x007F0000
    #define SEQ_CH1_PHY_SLICE1_2_WR_DQ_OFFSET_SHIFT 16
#define  SEQ_CH1_PHY_SLICE1_3 0xC4FC
    #define SEQ_CH1_PHY_SLICE1_3_FIFO_WE_FORCE_MODE_MASK 0x00000001
    #define SEQ_CH1_PHY_SLICE1_3_FIFO_WE_FORCE_MODE_SHIFT 0
    #define SEQ_CH1_PHY_SLICE1_3_FIFO_WE_SL_RATIO_MASK 0x0000FF00
    #define SEQ_CH1_PHY_SLICE1_3_FIFO_WE_SL_RATIO_SHIFT 8
    #define SEQ_CH1_PHY_SLICE1_3_FIFO_WE_IN_FORCE_MASK 0x00010000
    #define SEQ_CH1_PHY_SLICE1_3_FIFO_WE_IN_FORCE_SHIFT 16
    #define SEQ_CH1_PHY_SLICE1_3_FIFO_WE_IN_DELAY_MASK 0x00FE0000
    #define SEQ_CH1_PHY_SLICE1_3_FIFO_WE_IN_DELAY_SHIFT 17
#define  SEQ_CH1_PHY_SLICE2_0 0xC500
    #define SEQ_CH1_PHY_SLICE2_0_RD_DQS_SL_RATIO_MASK 0x000000FF
    #define SEQ_CH1_PHY_SLICE2_0_RD_DQS_SL_RATIO_SHIFT 0
    #define SEQ_CH1_PHY_SLICE2_0_RD_DQS_SL_FORCE_MASK 0x00000100
    #define SEQ_CH1_PHY_SLICE2_0_RD_DQS_SL_FORCE_SHIFT 8
    #define SEQ_CH1_PHY_SLICE2_0_RD_DQS_SL_DELAY_MASK 0x0000FE00
    #define SEQ_CH1_PHY_SLICE2_0_RD_DQS_SL_DELAY_SHIFT 9
    #define SEQ_CH1_PHY_SLICE2_0_RD_DQS_DEF_SL_RATIO_MASK 0x00FF0000
    #define SEQ_CH1_PHY_SLICE2_0_RD_DQS_DEF_SL_RATIO_SHIFT 16
#define  SEQ_CH1_PHY_SLICE2_1 0xC504
    #define SEQ_CH1_PHY_SLICE2_1_WR_DQS_SL_RATIO_MASK 0x000000FF
    #define SEQ_CH1_PHY_SLICE2_1_WR_DQS_SL_RATIO_SHIFT 0
    #define SEQ_CH1_PHY_SLICE2_1_WR_DQS_SL_FORCE_MASK 0x00000100
    #define SEQ_CH1_PHY_SLICE2_1_WR_DQS_SL_FORCE_SHIFT 8
    #define SEQ_CH1_PHY_SLICE2_1_WR_DQS_SL_DELAY_MASK 0x0000FE00
    #define SEQ_CH1_PHY_SLICE2_1_WR_DQS_SL_DELAY_SHIFT 9
#define  SEQ_CH1_PHY_SLICE2_2 0xC508
    #define SEQ_CH1_PHY_SLICE2_2_WR_DQ_SL_RATIO_MASK 0x000000FF
    #define SEQ_CH1_PHY_SLICE2_2_WR_DQ_SL_RATIO_SHIFT 0
    #define SEQ_CH1_PHY_SLICE2_2_WR_DQ_SL_FORCE_MASK 0x00000100
    #define SEQ_CH1_PHY_SLICE2_2_WR_DQ_SL_FORCE_SHIFT 8
    #define SEQ_CH1_PHY_SLICE2_2_WR_DQ_SL_DELAY_MASK 0x0000FE00
    #define SEQ_CH1_PHY_SLICE2_2_WR_DQ_SL_DELAY_SHIFT 9
    #define SEQ_CH1_PHY_SLICE2_2_WR_DQ_OFFSET_MASK 0x007F0000
    #define SEQ_CH1_PHY_SLICE2_2_WR_DQ_OFFSET_SHIFT 16
#define  SEQ_CH1_PHY_SLICE3_0 0xC510
    #define SEQ_CH1_PHY_SLICE3_0_RD_DQS_SL_RATIO_MASK 0x000000FF
    #define SEQ_CH1_PHY_SLICE3_0_RD_DQS_SL_RATIO_SHIFT 0
    #define SEQ_CH1_PHY_SLICE3_0_RD_DQS_SL_FORCE_MASK 0x00000100
    #define SEQ_CH1_PHY_SLICE3_0_RD_DQS_SL_FORCE_SHIFT 8
    #define SEQ_CH1_PHY_SLICE3_0_RD_DQS_SL_DELAY_MASK 0x0000FE00
    #define SEQ_CH1_PHY_SLICE3_0_RD_DQS_SL_DELAY_SHIFT 9
    #define SEQ_CH1_PHY_SLICE3_0_RD_DQS_DEF_SL_RATIO_MASK 0x00FF0000
    #define SEQ_CH1_PHY_SLICE3_0_RD_DQS_DEF_SL_RATIO_SHIFT 16
#define  SEQ_CH1_PHY_SLICE3_1 0xC514
    #define SEQ_CH1_PHY_SLICE3_1_WR_DQS_SL_RATIO_MASK 0x000000FF
    #define SEQ_CH1_PHY_SLICE3_1_WR_DQS_SL_RATIO_SHIFT 0
    #define SEQ_CH1_PHY_SLICE3_1_WR_DQS_SL_FORCE_MASK 0x00000100
    #define SEQ_CH1_PHY_SLICE3_1_WR_DQS_SL_FORCE_SHIFT 8
    #define SEQ_CH1_PHY_SLICE3_1_WR_DQS_SL_DELAY_MASK 0x0000FE00
    #define SEQ_CH1_PHY_SLICE3_1_WR_DQS_SL_DELAY_SHIFT 9
#define  SEQ_CH1_PHY_SLICE3_2 0xC518
    #define SEQ_CH1_PHY_SLICE3_2_WR_DQ_SL_RATIO_MASK 0x000000FF
    #define SEQ_CH1_PHY_SLICE3_2_WR_DQ_SL_RATIO_SHIFT 0
    #define SEQ_CH1_PHY_SLICE3_2_WR_DQ_SL_FORCE_MASK 0x00000100
    #define SEQ_CH1_PHY_SLICE3_2_WR_DQ_SL_FORCE_SHIFT 8
    #define SEQ_CH1_PHY_SLICE3_2_WR_DQ_SL_DELAY_MASK 0x0000FE00
    #define SEQ_CH1_PHY_SLICE3_2_WR_DQ_SL_DELAY_SHIFT 9
    #define SEQ_CH1_PHY_SLICE3_2_WR_DQ_OFFSET_MASK 0x007F0000
    #define SEQ_CH1_PHY_SLICE3_2_WR_DQ_OFFSET_SHIFT 16
#define  SEQ_CH1_PHY_STATUS 0xC4D4
    #define SEQ_CH1_PHY_STATUS_RDCFF_RST_ERR_CNT_MASK 0x0000000F
    #define SEQ_CH1_PHY_STATUS_RDCFF_RST_ERR_CNT_SHIFT 0
    #define SEQ_CH1_PHY_STATUS_WR_LEVEL_DONE_MASK 0x00000010
    #define SEQ_CH1_PHY_STATUS_WR_LEVEL_DONE_SHIFT 4
    #define SEQ_CH1_PHY_STATUS_RD_LEVEL_DONE_MASK 0x00000020
    #define SEQ_CH1_PHY_STATUS_RD_LEVEL_DONE_SHIFT 5
    #define SEQ_CH1_PHY_STATUS_DLL_LOCK_MASK 0x000000C0
    #define SEQ_CH1_PHY_STATUS_DLL_LOCK_SHIFT 6
    #define SEQ_CH1_PHY_STATUS_IN_LOCK_STATE_MASK 0x00000F00
    #define SEQ_CH1_PHY_STATUS_IN_LOCK_STATE_SHIFT 8
#define  SEQ_CH1_RD_LOCK_STATUS 0xC448
    #define SEQ_CH1_RD_LOCK_STATUS_READ_ATTEMPT_CL_ID_MASK 0x0003FFFF
    #define SEQ_CH1_RD_LOCK_STATUS_READ_ATTEMPT_CL_ID_SHIFT 0
#define  SEQ_CH1_REFRESH 0xC4A4
    #define SEQ_CH1_REFRESH_REF_BURST_MASK 0x00000007
    #define SEQ_CH1_REFRESH_REF_BURST_SHIFT 0
    #define SEQ_CH1_REFRESH_REF_TO_X32_MASK 0x000000F8
    #define SEQ_CH1_REFRESH_REF_TO_X32_SHIFT 3
    #define SEQ_CH1_REFRESH_REF_MARGIN_MASK 0x000F0000
    #define SEQ_CH1_REFRESH_REF_MARGIN_SHIFT 16
    #define SEQ_CH1_REFRESH_REF_UPDATE_LEVEL_MASK 0x00100000
    #define SEQ_CH1_REFRESH_REF_UPDATE_LEVEL_SHIFT 20
    #define SEQ_CH1_REFRESH_DIS_AUTO_REF_MASK 0x40000000
    #define SEQ_CH1_REFRESH_DIS_AUTO_REF_SHIFT 30
    #define SEQ_CH1_REFRESH_RANK_REF_MASK 0x80000000
    #define SEQ_CH1_REFRESH_RANK_REF_SHIFT 31
#define  SEQ_CH1_REGDAT 0xC454
    #define SEQ_CH1_REGDAT_REQ_DATA_MASK 0xFFFFFFFF
    #define SEQ_CH1_REGDAT_REQ_DATA_SHIFT 0
#define  SEQ_CH1_REGDAT_IDX 0xC458
    #define SEQ_CH1_REGDAT_IDX_DATA_IDX_MASK 0x0000001F
    #define SEQ_CH1_REGDAT_IDX_DATA_IDX_SHIFT 0
    #define SEQ_CH1_REGDAT_IDX_REQ_BE_MASK 0x00000F00
    #define SEQ_CH1_REGDAT_IDX_REQ_BE_SHIFT 8
    #define SEQ_CH1_REGDAT_IDX_DATA_WOP_MASK 0x00001000
    #define SEQ_CH1_REGDAT_IDX_DATA_WOP_SHIFT 12
#define  SEQ_CH1_REGREQ_CTRL 0xC450
    #define SEQ_CH1_REGREQ_CTRL_REQ_SIZE_MASK 0x00000003
    #define SEQ_CH1_REGREQ_CTRL_REQ_SIZE_SHIFT 0
    #define SEQ_CH1_REGREQ_CTRL_REQ_WOP_MASK 0x00000004
    #define SEQ_CH1_REGREQ_CTRL_REQ_WOP_SHIFT 2
    #define SEQ_CH1_REGREQ_CTRL_REQ_URGENT_MASK 0x00000008
    #define SEQ_CH1_REGREQ_CTRL_REQ_URGENT_SHIFT 3
    #define SEQ_CH1_REGREQ_CTRL_REQ_ADR_MASK 0x7FFFFFF0
    #define SEQ_CH1_REGREQ_CTRL_REQ_ADR_SHIFT 4
    #define SEQ_CH1_REGREQ_CTRL_REQ_TAG_MASK 0x80000000
    #define SEQ_CH1_REGREQ_CTRL_REQ_TAG_SHIFT 31
#define  SEQ_CH1_REGREQ_STATUS 0xC45C
    #define SEQ_CH1_REGREQ_STATUS_REQ_IDLE_MASK 0x00000001
    #define SEQ_CH1_REGREQ_STATUS_REQ_IDLE_SHIFT 0
    #define SEQ_CH1_REGREQ_STATUS_REQ_WTAG_MISMATCH_MASK 0x00000002
    #define SEQ_CH1_REGREQ_STATUS_REQ_WTAG_MISMATCH_SHIFT 1
    #define SEQ_CH1_REGREQ_STATUS_REQ_RTAG_MISMATCH_MASK 0x00000004
    #define SEQ_CH1_REGREQ_STATUS_REQ_RTAG_MISMATCH_SHIFT 2
#define  SEQ_CH1_REG_CTRL 0xC420
    #define SEQ_CH1_REG_CTRL_CFGREG_ADDR_MASK 0x0000003F
    #define SEQ_CH1_REG_CTRL_CFGREG_ADDR_SHIFT 0
    #define SEQ_CH1_REG_CTRL_CFGREG_WOP_MASK 0x00000100
    #define SEQ_CH1_REG_CTRL_CFGREG_WOP_SHIFT 8
#define  SEQ_CH1_REG_RDAT 0xC418
    #define SEQ_CH1_REG_RDAT_CFGREG_RDAT_MASK 0xFFFFFFFF
    #define SEQ_CH1_REG_RDAT_CFGREG_RDAT_SHIFT 0
#define  SEQ_CH1_REG_STATUS 0xC41C
    #define SEQ_CH1_REG_STATUS_CFGREG_BUSY_MASK 0x00000001
    #define SEQ_CH1_REG_STATUS_CFGREG_BUSY_SHIFT 0
#define  SEQ_CH1_REG_WDAT 0xC414
    #define SEQ_CH1_REG_WDAT_CFGREG_WDAT_MASK 0xFFFFFFFF
    #define SEQ_CH1_REG_WDAT_CFGREG_WDAT_SHIFT 0
#define  SEQ_CH1_REQ_IDLE_CNT 0xC438
    #define SEQ_CH1_REQ_IDLE_CNT_REG_MASK 0xFFFFFFFF
    #define SEQ_CH1_REQ_IDLE_CNT_REG_SHIFT 0
#define  SEQ_CH1_SECURE_DIRECTIF 0xC43C
    #define SEQ_CH1_SECURE_DIRECTIF_LOCK_EN_MASK 0x00000001
    #define SEQ_CH1_SECURE_DIRECTIF_LOCK_EN_SHIFT 0
    #define SEQ_CH1_SECURE_DIRECTIF_WR_ATTEMPT_MASK 0x10000000
    #define SEQ_CH1_SECURE_DIRECTIF_WR_ATTEMPT_SHIFT 28
    #define SEQ_CH1_SECURE_DIRECTIF_RD_ATTEMPT_MASK 0x20000000
    #define SEQ_CH1_SECURE_DIRECTIF_RD_ATTEMPT_SHIFT 29
    #define SEQ_CH1_SECURE_DIRECTIF_FIX_RANGE_MASK 0x40000000
    #define SEQ_CH1_SECURE_DIRECTIF_FIX_RANGE_SHIFT 30
    #define SEQ_CH1_SECURE_DIRECTIF_SECURE_1MB_MASK 0x80000000
    #define SEQ_CH1_SECURE_DIRECTIF_SECURE_1MB_SHIFT 31
#define  SEQ_CH1_STATUS 0xC428
    #define SEQ_CH1_STATUS_INIT_BUSY_MASK 0x00000001
    #define SEQ_CH1_STATUS_INIT_BUSY_SHIFT 0
    #define SEQ_CH1_STATUS_SEQ_ERROR_MASK 0x00000010
    #define SEQ_CH1_STATUS_SEQ_ERROR_SHIFT 4
    #define SEQ_CH1_STATUS_RING_WVLD_MASK 0x00000100
    #define SEQ_CH1_STATUS_RING_WVLD_SHIFT 8
#define  SEQ_CH1_STATUS_0 0xC408
    #define SEQ_CH1_STATUS_0_DBIST_ERR_CNT_MASK 0x0000003F
    #define SEQ_CH1_STATUS_0_DBIST_ERR_CNT_SHIFT 0
    #define SEQ_CH1_STATUS_0_DBIST_DONE_MASK 0x00000100
    #define SEQ_CH1_STATUS_0_DBIST_DONE_SHIFT 8
    #define SEQ_CH1_STATUS_0_RING_WVLD_ERR_MASK 0x00000200
    #define SEQ_CH1_STATUS_0_RING_WVLD_ERR_SHIFT 9
    #define SEQ_CH1_STATUS_0_LOOPBACK_GOOD_MASK 0x40000000
    #define SEQ_CH1_STATUS_0_LOOPBACK_GOOD_SHIFT 30
    #define SEQ_CH1_STATUS_0_LOOPBACK_DONE_MASK 0x80000000
    #define SEQ_CH1_STATUS_0_LOOPBACK_DONE_SHIFT 31
#define  SEQ_CH1_TIMING0 0xC490
    #define SEQ_CH1_TIMING0_MOD_MASK 0x000003FF
    #define SEQ_CH1_TIMING0_MOD_SHIFT 0
    #define SEQ_CH1_TIMING0_RC_MASK 0x0000FC00
    #define SEQ_CH1_TIMING0_RC_SHIFT 10
    #define SEQ_CH1_TIMING0_RP_MASK 0x000F0000
    #define SEQ_CH1_TIMING0_RP_SHIFT 16
    #define SEQ_CH1_TIMING0_RAS_MIN_MASK 0x01F00000
    #define SEQ_CH1_TIMING0_RAS_MIN_SHIFT 20
    #define SEQ_CH1_TIMING0_RAS_MAX_MASK 0x7E000000
    #define SEQ_CH1_TIMING0_RAS_MAX_SHIFT 25
#define  SEQ_CH1_TIMING1 0xC494
    #define SEQ_CH1_TIMING1_RCD_MASK 0x0000000F
    #define SEQ_CH1_TIMING1_RCD_SHIFT 0
    #define SEQ_CH1_TIMING1_RFC_NOM_X32_MASK 0x0000FFF0
    #define SEQ_CH1_TIMING1_RFC_NOM_X32_SHIFT 4
    #define SEQ_CH1_TIMING1_RFC_MIN_MASK 0x00FF0000
    #define SEQ_CH1_TIMING1_RFC_MIN_SHIFT 16
    #define SEQ_CH1_TIMING1_RRD_MASK 0x07000000
    #define SEQ_CH1_TIMING1_RRD_SHIFT 24
    #define SEQ_CH1_TIMING1_MRD_MASK 0x38000000
    #define SEQ_CH1_TIMING1_MRD_SHIFT 27
    #define SEQ_CH1_TIMING1_CKE_MASK 0xC0000000
    #define SEQ_CH1_TIMING1_CKE_SHIFT 30
#define  SEQ_CH1_TIMING2 0xC498
    #define SEQ_CH1_TIMING2_FAW_MASK 0x0000003F
    #define SEQ_CH1_TIMING2_FAW_SHIFT 0
    #define SEQ_CH1_TIMING2_RD2WR_MASK 0x000007C0
    #define SEQ_CH1_TIMING2_RD2WR_SHIFT 6
    #define SEQ_CH1_TIMING2_WR2RD_MASK 0x0000F800
    #define SEQ_CH1_TIMING2_WR2RD_SHIFT 11
    #define SEQ_CH1_TIMING2_WR_LATENCY_MASK 0x001F0000
    #define SEQ_CH1_TIMING2_WR_LATENCY_SHIFT 16
    #define SEQ_CH1_TIMING2_WR2PRE_MASK 0x03E00000
    #define SEQ_CH1_TIMING2_WR2PRE_SHIFT 21
    #define SEQ_CH1_TIMING2_RD2PRE_MASK 0x7C000000
    #define SEQ_CH1_TIMING2_RD2PRE_SHIFT 26
#define  SEQ_CH1_TIMING3 0xC49C
    #define SEQ_CH1_TIMING3_RD_ODT_DLY_MASK 0x0000000F
    #define SEQ_CH1_TIMING3_RD_ODT_DLY_SHIFT 0
    #define SEQ_CH1_TIMING3_WR_ODT_DLY_MASK 0x000000F0
    #define SEQ_CH1_TIMING3_WR_ODT_DLY_SHIFT 4
    #define SEQ_CH1_TIMING3_RD_ODT_HOLD_MASK 0x00000F00
    #define SEQ_CH1_TIMING3_RD_ODT_HOLD_SHIFT 8
    #define SEQ_CH1_TIMING3_WR_ODT_HOLD_MASK 0x0000F000
    #define SEQ_CH1_TIMING3_WR_ODT_HOLD_SHIFT 12
    #define SEQ_CH1_TIMING3_WR_ODT_BLOCK_MASK 0x00030000
    #define SEQ_CH1_TIMING3_WR_ODT_BLOCK_SHIFT 16
    #define SEQ_CH1_TIMING3_RD_ODT_MASK 0x000C0000
    #define SEQ_CH1_TIMING3_RD_ODT_SHIFT 18
    #define SEQ_CH1_TIMING3_WR_ODT_MASK 0x00300000
    #define SEQ_CH1_TIMING3_WR_ODT_SHIFT 20
    #define SEQ_CH1_TIMING3_WR_MODE_ODT_MASK 0x00800000
    #define SEQ_CH1_TIMING3_WR_MODE_ODT_SHIFT 23
    #define SEQ_CH1_TIMING3_CCD_MASK 0x38000000
    #define SEQ_CH1_TIMING3_CCD_SHIFT 27
#define  SEQ_CH1_TIMING4 0xC4A0
    #define SEQ_CH1_TIMING4_PWRDN_EN_MASK 0x00000001
    #define SEQ_CH1_TIMING4_PWRDN_EN_SHIFT 0
    #define SEQ_CH1_TIMING4_PWRDN_TO_X32_MASK 0x0000003E
    #define SEQ_CH1_TIMING4_PWRDN_TO_X32_SHIFT 1
    #define SEQ_CH1_TIMING4_XP_MASK 0x000007C0
    #define SEQ_CH1_TIMING4_XP_SHIFT 6
    #define SEQ_CH1_TIMING4_POST_SR_GAP_X32_MASK 0x0003F800
    #define SEQ_CH1_TIMING4_POST_SR_GAP_X32_SHIFT 11
    #define SEQ_CH1_TIMING4_PAD_PD_MASK 0x001C0000
    #define SEQ_CH1_TIMING4_PAD_PD_SHIFT 18
    #define SEQ_CH1_TIMING4_DELAY_2T_MASK 0x3FE00000
    #define SEQ_CH1_TIMING4_DELAY_2T_SHIFT 21
    #define SEQ_CH1_TIMING4_EN_2T_MASK 0x40000000
    #define SEQ_CH1_TIMING4_EN_2T_SHIFT 30
    #define SEQ_CH1_TIMING4_SR_EN_MASK 0x80000000
    #define SEQ_CH1_TIMING4_SR_EN_SHIFT 31
#define  SEQ_CH1_TRAN_CTRL0 0xC46C
    #define SEQ_CH1_TRAN_CTRL0_LPR_MAX_STARVE_X32_MASK 0x000007FF
    #define SEQ_CH1_TRAN_CTRL0_LPR_MAX_STARVE_X32_SHIFT 0
    #define SEQ_CH1_TRAN_CTRL0_LPR_XACT_RUN_LENGTH_MASK 0x00007800
    #define SEQ_CH1_TRAN_CTRL0_LPR_XACT_RUN_LENGTH_SHIFT 11
    #define SEQ_CH1_TRAN_CTRL0_LPR_MIN_NON_CRITICAL_MASK 0x3FF80000
    #define SEQ_CH1_TRAN_CTRL0_LPR_MIN_NON_CRITICAL_SHIFT 19
#define  SEQ_CH1_TRAN_CTRL1 0xC470
    #define SEQ_CH1_TRAN_CTRL1_HPR_MAX_STARVE_X32_MASK 0x000007FF
    #define SEQ_CH1_TRAN_CTRL1_HPR_MAX_STARVE_X32_SHIFT 0
    #define SEQ_CH1_TRAN_CTRL1_HPR_XACT_RUN_LENGTH_MASK 0x00007800
    #define SEQ_CH1_TRAN_CTRL1_HPR_XACT_RUN_LENGTH_SHIFT 11
    #define SEQ_CH1_TRAN_CTRL1_HPR_MIN_NON_CRITICAL_MASK 0x3FF80000
    #define SEQ_CH1_TRAN_CTRL1_HPR_MIN_NON_CRITICAL_SHIFT 19
#define  SEQ_CH1_TRAN_CTRL2 0xC474
    #define SEQ_CH1_TRAN_CTRL2_W_XACT_RUN_LENGTH_MASK 0x00007800
    #define SEQ_CH1_TRAN_CTRL2_W_XACT_RUN_LENGTH_SHIFT 11
    #define SEQ_CH1_TRAN_CTRL2_W_MIN_NON_CRITICAL_MASK 0x3FF80000
    #define SEQ_CH1_TRAN_CTRL2_W_MIN_NON_CRITICAL_SHIFT 19
#define  SEQ_CH1_TRAN_CTRL3 0xC478
    #define SEQ_CH1_TRAN_CTRL3_GO2CRIT_HYST_MASK 0x000000FF
    #define SEQ_CH1_TRAN_CTRL3_GO2CRIT_HYST_SHIFT 0
    #define SEQ_CH1_TRAN_CTRL3_GO2CRIT_RD_EN_MASK 0x00000100
    #define SEQ_CH1_TRAN_CTRL3_GO2CRIT_RD_EN_SHIFT 8
    #define SEQ_CH1_TRAN_CTRL3_GO2CRIT_WR_EN_MASK 0x00000200
    #define SEQ_CH1_TRAN_CTRL3_GO2CRIT_WR_EN_SHIFT 9
    #define SEQ_CH1_TRAN_CTRL3_LPR_NUM_ENTRIES_MASK 0x0000FC00
    #define SEQ_CH1_TRAN_CTRL3_LPR_NUM_ENTRIES_SHIFT 10
    #define SEQ_CH1_TRAN_CTRL3_RDWR_IDLE_GAP_MASK 0x007F0000
    #define SEQ_CH1_TRAN_CTRL3_RDWR_IDLE_GAP_SHIFT 16
    #define SEQ_CH1_TRAN_CTRL3_PREFER_WRITE_MASK 0x00800000
    #define SEQ_CH1_TRAN_CTRL3_PREFER_WRITE_SHIFT 23
    #define SEQ_CH1_TRAN_CTRL3_PAGECLOSE_MASK 0x01000000
    #define SEQ_CH1_TRAN_CTRL3_PAGECLOSE_SHIFT 24
    #define SEQ_CH1_TRAN_CTRL3_AUTO_PRE_EN_MASK 0x02000000
    #define SEQ_CH1_TRAN_CTRL3_AUTO_PRE_EN_SHIFT 25
    #define SEQ_CH1_TRAN_CTRL3_FORCE_LP_N_MASK 0x04000000
    #define SEQ_CH1_TRAN_CTRL3_FORCE_LP_N_SHIFT 26
    #define SEQ_CH1_TRAN_CTRL3_DIS_WC_MASK 0x08000000
    #define SEQ_CH1_TRAN_CTRL3_DIS_WC_SHIFT 27
    #define SEQ_CH1_TRAN_CTRL3_DIS_ACT_BYP_MASK 0x10000000
    #define SEQ_CH1_TRAN_CTRL3_DIS_ACT_BYP_SHIFT 28
    #define SEQ_CH1_TRAN_CTRL3_DIS_RD_BYP_MASK 0x20000000
    #define SEQ_CH1_TRAN_CTRL3_DIS_RD_BYP_SHIFT 29
    #define SEQ_CH1_TRAN_CTRL3_DIS_DQUE_MASK 0x40000000
    #define SEQ_CH1_TRAN_CTRL3_DIS_DQUE_SHIFT 30
    #define SEQ_CH1_TRAN_CTRL3_DIS_COL_PG_OPT_MASK 0x80000000
    #define SEQ_CH1_TRAN_CTRL3_DIS_COL_PG_OPT_SHIFT 31
#define  SEQ_CH1_VRG_STATUS 0xC4BC
    #define SEQ_CH1_VRG_STATUS_OP_MODE_MASK 0x00000003
    #define SEQ_CH1_VRG_STATUS_OP_MODE_SHIFT 0
    #define SEQ_CH1_VRG_STATUS_WR_DEPTH_MASK 0x000000FC
    #define SEQ_CH1_VRG_STATUS_WR_DEPTH_SHIFT 2
    #define SEQ_CH1_VRG_STATUS_LPR_DEPTH_MASK 0x00003F00
    #define SEQ_CH1_VRG_STATUS_LPR_DEPTH_SHIFT 8
    #define SEQ_CH1_VRG_STATUS_HPR_DEPTH_MASK 0x003F0000
    #define SEQ_CH1_VRG_STATUS_HPR_DEPTH_SHIFT 16
    #define SEQ_CH1_VRG_STATUS_STALL_MASK 0x00400000
    #define SEQ_CH1_VRG_STATUS_STALL_SHIFT 22
    #define SEQ_CH1_VRG_STATUS_MR_WR_BUSY_MASK 0x00800000
    #define SEQ_CH1_VRG_STATUS_MR_WR_BUSY_SHIFT 23
#define  SEQ_CH1_WRITE_MR 0xC48C
    #define SEQ_CH1_WRITE_MR_MR_DATA_MASK 0x0000FFFF
    #define SEQ_CH1_WRITE_MR_MR_DATA_SHIFT 0
    #define SEQ_CH1_WRITE_MR_MR_ADR_MASK 0x00030000
    #define SEQ_CH1_WRITE_MR_MR_ADR_SHIFT 16
#define  SEQ_CH1_WR_LOCK_STATUS 0xC444
    #define SEQ_CH1_WR_LOCK_STATUS_WRITE_ATTEMPT_CL_ID_MASK 0x0003FFFF
    #define SEQ_CH1_WR_LOCK_STATUS_WRITE_ATTEMPT_CL_ID_SHIFT 0
#define  SEQ_CH1_ZQ0 0xC4AC
    #define SEQ_CH1_ZQ0_T_ZQ_SHORT_NOP_MASK 0x000003FF
    #define SEQ_CH1_ZQ0_T_ZQ_SHORT_NOP_SHIFT 0
    #define SEQ_CH1_ZQ0_T_ZQ_LONG_NOP_MASK 0x003FF000
    #define SEQ_CH1_ZQ0_T_ZQ_LONG_NOP_SHIFT 12
    #define SEQ_CH1_ZQ0_DIS_AUTO_ZQ_MASK 0x40000000
    #define SEQ_CH1_ZQ0_DIS_AUTO_ZQ_SHIFT 30
    #define SEQ_CH1_ZQ0_DO_CALIB_SHORT_MASK 0x80000000
    #define SEQ_CH1_ZQ0_DO_CALIB_SHORT_SHIFT 31
#define  SEQ_CH1_ZQ1 0xC4B0
    #define SEQ_CH1_ZQ1_T_ZQ_SHORT_INT_X1024_MASK 0x000FFFFF
    #define SEQ_CH1_ZQ1_T_ZQ_SHORT_INT_X1024_SHIFT 0
#define  SF_BUF_CTRL 0x65E0
    #define SF_OUTBUF_ENDIAN_MASK 0x00000800
    #define SF_OUTBUF_ENDIAN_SHIFT 11
    #define SF_MEM_URGENT_MASK 0x00010000
    #define SF_MEM_URGENT_SHIFT 16
    #define SF_MEM_URGENT_WATERMARK_MASK 0x03F00000
    #define SF_MEM_URGENT_WATERMARK_SHIFT 20
#define  SF_NOT_TO_MEM_RID 0x67EC
    #define RIDA_NOT_TO_MEM_MASK 0x00000001
    #define RIDA_NOT_TO_MEM_SHIFT 0
    #define RIDA_MASK 0x0000007E
    #define RIDA_SHIFT 1
    #define RIDB_NOT_TO_MEM_MASK 0x00000200
    #define RIDB_NOT_TO_MEM_SHIFT 9
    #define RIDB_MASK 0x0000FC00
    #define RIDB_SHIFT 10
    #define RIDC_NOT_TO_MEM_MASK 0x00040000
    #define RIDC_NOT_TO_MEM_SHIFT 18
    #define RIDC_MASK 0x01F80000
    #define RIDC_SHIFT 19
#define  SF_PATTERN0_MATCH 0x6430
    #define SF_PATTERN0_MATCH_PATTERN_MASK 0xFFFFFFFF
    #define SF_PATTERN0_MATCH_PATTERN_SHIFT 0
#define  SF_PATTERN1_MATCH 0x6434
    #define SF_PATTERN1_MATCH_PATTERN_MASK 0xFFFFFFFF
    #define SF_PATTERN1_MATCH_PATTERN_SHIFT 0
#define  SF_PATTERN2_MATCH 0x6440
    #define SF_PATTERN2_MATCH_PATTERN_MASK 0xFFFFFFFF
    #define SF_PATTERN2_MATCH_PATTERN_SHIFT 0
#define  SF_PATTERN3_MATCH 0x6444
    #define SF_PATTERN3_MATCH_PATTERN_MASK 0xFFFFFFFF
    #define SF_PATTERN3_MATCH_PATTERN_SHIFT 0
#define  SF_PATTERN4_MATCH 0x644C
    #define SF_PATTERN4_MATCH_PATTERN_MASK 0xFFFFFFFF
    #define SF_PATTERN4_MATCH_PATTERN_SHIFT 0
#define  SF_PATTERN5_MATCH 0x6450
    #define SF_PATTERN5_MATCH_PATTERN_MASK 0xFFFFFFFF
    #define SF_PATTERN5_MATCH_PATTERN_SHIFT 0
#define  SF_PATTERN6_MATCH 0x6460
    #define SF_PATTERN6_MATCH_PATTERN_MASK 0xFFFFFFFF
    #define SF_PATTERN6_MATCH_PATTERN_SHIFT 0
#define  SF_PATTERN7_MATCH 0x6464
    #define SF_PATTERN7_MATCH_PATTERN_MASK 0xFFFFFFFF
    #define SF_PATTERN7_MATCH_PATTERN_SHIFT 0
#define  SF_RING0_HEAD 0x6420
    #define SF_RING0_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING0_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING10_HEAD 0x64A8
    #define SF_RING10_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING10_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING11_HEAD 0x64B8
    #define SF_RING11_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING11_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING12_HEAD 0x64C8
    #define SF_RING12_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING12_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING13_HEAD 0x64D8
    #define SF_RING13_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING13_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING14_HEAD 0x65F0
    #define SF_RING14_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING14_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING15_HEAD 0x65F4
    #define SF_RING15_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING15_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING16_HEAD 0x660C
    #define SF_RING16_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING16_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING17_HEAD 0x6610
    #define SF_RING17_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING17_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING18_HEAD 0x6614
    #define SF_RING18_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING18_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING19_HEAD 0x6618
    #define SF_RING19_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING19_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING1_HEAD 0x6424
    #define SF_RING1_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING1_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING20_HEAD 0x661C
    #define SF_RING20_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING20_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING21_HEAD 0x6620
    #define SF_RING21_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING21_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING22_HEAD 0x6624
    #define SF_RING22_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING22_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING23_HEAD 0x6628
    #define SF_RING23_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING23_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING24_HEAD 0x662C
    #define SF_RING24_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING24_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING25_HEAD 0x6630
    #define SF_RING25_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING25_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING26_HEAD 0x6634
    #define SF_RING26_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING26_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING27_HEAD 0x6638
    #define SF_RING27_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING27_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING28_HEAD 0x663C
    #define SF_RING28_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING28_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING29_HEAD 0x6640
    #define SF_RING29_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING29_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING2_HEAD 0x6428
    #define SF_RING2_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING2_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING30_HEAD 0x6644
    #define SF_RING30_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING30_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING31_HEAD 0x6648
    #define SF_RING31_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING31_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING32_HEAD 0x664C
    #define SF_RING32_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING32_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING33_HEAD 0x6650
    #define SF_RING33_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING33_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING34_HEAD 0x6654
    #define SF_RING34_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING34_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING35_HEAD 0x6658
    #define SF_RING35_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING35_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING36_HEAD 0x665C
    #define SF_RING36_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING36_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING37_HEAD 0x6660
    #define SF_RING37_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING37_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING38_HEAD 0x6664
    #define SF_RING38_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING38_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING39_HEAD 0x6668
    #define SF_RING39_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING39_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING3_HEAD 0x642C
    #define SF_RING3_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING3_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING40_HEAD 0x666C
    #define SF_RING40_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING40_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING41_HEAD 0x6670
    #define SF_RING41_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING41_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING42_HEAD 0x6674
    #define SF_RING42_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING42_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING43_HEAD 0x6678
    #define SF_RING43_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING43_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING44_HEAD 0x667C
    #define SF_RING44_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING44_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING45_HEAD 0x6680
    #define SF_RING45_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING45_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING46_HEAD 0x6684
    #define SF_RING46_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING46_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING47_HEAD 0x6688
    #define SF_RING47_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING47_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING48_HEAD 0x668C
    #define SF_RING48_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING48_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING49_HEAD 0x6690
    #define SF_RING49_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING49_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING4_HEAD 0x6448
    #define SF_RING4_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING4_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING50_HEAD 0x6694
    #define SF_RING50_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING50_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING51_HEAD 0x6698
    #define SF_RING51_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING51_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING52_HEAD 0x669C
    #define SF_RING52_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING52_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING53_HEAD 0x66A0
    #define SF_RING53_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING53_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING54_HEAD 0x66A4
    #define SF_RING54_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING54_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING55_HEAD 0x66A8
    #define SF_RING55_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING55_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING56_HEAD 0x66AC
    #define SF_RING56_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING56_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING57_HEAD 0x66B0
    #define SF_RING57_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING57_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING58_HEAD 0x66B4
    #define SF_RING58_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING58_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING59_HEAD 0x66B8
    #define SF_RING59_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING59_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING5_HEAD 0x6458
    #define SF_RING5_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING5_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING60_HEAD 0x66BC
    #define SF_RING60_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING60_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING61_HEAD 0x66C0
    #define SF_RING61_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING61_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING62_HEAD 0x66C4
    #define SF_RING62_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING62_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING63_HEAD 0x66C8
    #define SF_RING63_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING63_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING6_HEAD 0x6468
    #define SF_RING6_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING6_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING7_HEAD 0x6478
    #define SF_RING7_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING7_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING8_HEAD 0x6488
    #define SF_RING8_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING8_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING9_HEAD 0x6498
    #define SF_RING9_HEAD_HEAD_PTR_MASK 0x7FFFFFFF
    #define SF_RING9_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING_BASE_TOP_TAIL_ADR 0x6400
    #define SF_RING_BASE_TOP_TAIL_ADR_SF_RING_MASK 0x0000007F
    #define SF_RING_BASE_TOP_TAIL_ADR_SF_RING_SHIFT 0
    #define SF_BASE_TOP_MASK 0x00010000
    #define SF_BASE_TOP_SHIFT 16
    #define SF_BASE_UPPER_MASK 0x00700000
    #define SF_BASE_UPPER_SHIFT 20
    #define SF_TOP_UPPER_MASK 0x07000000
    #define SF_TOP_UPPER_SHIFT 24
#define  SF_RING_BASE_TOP_TAIL_DATA 0x6404
    #define SF_RING_BASE_TOP_TAIL_DATA_MASK 0xFFFFFFFF
    #define SF_RING_BASE_TOP_TAIL_DATA_SHIFT 0
#define  SF_RING_CTRL_ADR 0x6408
    #define SF_RING_CTRL_ADR_SF_RING_MASK 0x0000007F
    #define SF_RING_CTRL_ADR_SF_RING_SHIFT 0
#define  SF_RING_CTRL_DATA 0x640C
    #define RING_WHOLE_PACKET_MASK 0x00000002
    #define RING_WHOLE_PACKET_SHIFT 1
    #define RING_PES_SID_CHKN_MASK 0x00000008
    #define RING_PES_SID_CHKN_SHIFT 3
    #define RING_INT_CTRL_MASK 0x000000F0
    #define RING_INT_CTRL_SHIFT 4
    #define RING_PES2ES_MASK 0x00000100
    #define RING_PES2ES_SHIFT 8
    #define RING_CC_FILTER_MASK 0x00000200
    #define RING_CC_FILTER_SHIFT 9
    #define RING_TIMESTAMP_MASK 0x00000400
    #define RING_TIMESTAMP_SHIFT 10
    #define RING_INC_TTS_CHOOSE_MASK 0x00007800
    #define RING_INC_TTS_CHOOSE_SHIFT 11
    #define PUSI_MASK_MASK 0x00008000
    #define PUSI_MASK_SHIFT 15
    #define TP_MASK_MASK 0x00010000
    #define TP_MASK_SHIFT 16
    #define DI_MASK_MASK 0x00020000
    #define DI_MASK_SHIFT 17
    #define RAI_MASK_MASK 0x00040000
    #define RAI_MASK_SHIFT 18
    #define ESPI_MASK_MASK 0x00080000
    #define ESPI_MASK_SHIFT 19
    #define PCR_MASK_MASK 0x00100000
    #define PCR_MASK_SHIFT 20
    #define OPCR_MASK_MASK 0x00200000
    #define OPCR_MASK_SHIFT 21
    #define SPF_MASK_MASK 0x00400000
    #define SPF_MASK_SHIFT 22
    #define TPD_MASK_MASK 0x00800000
    #define TPD_MASK_SHIFT 23
    #define AFE_MASK_MASK 0x01000000
    #define AFE_MASK_SHIFT 24
    #define FIRST_PKT_MASK_MASK 0x02000000
    #define FIRST_PKT_MASK_SHIFT 25
    #define TSC_MASK_MASK 0x08000000
    #define TSC_MASK_SHIFT 27
    #define TEI_MASK_MASK 0x10000000
    #define TEI_MASK_SHIFT 28
    #define PTS_DTS_MASK_MASK 0x20000000
    #define PTS_DTS_MASK_SHIFT 29
    #define AF_SIZE_MASK_MASK 0x40000000
    #define AF_SIZE_MASK_SHIFT 30
    #define PATTERN_MASK_MASK 0x80000000
    #define PATTERN_MASK_SHIFT 31
#define  SF_RING_CTRL_LDATA 0x6418
    #define PUSI_MATCH_MASK 0x00000001
    #define PUSI_MATCH_SHIFT 0
    #define TP_MATCH_MASK 0x00000002
    #define TP_MATCH_SHIFT 1
    #define DI_MATCH_MASK 0x00000004
    #define DI_MATCH_SHIFT 2
    #define RAI_MATCH_MASK 0x00000008
    #define RAI_MATCH_SHIFT 3
    #define ESPI_MATCH_MASK 0x00000010
    #define ESPI_MATCH_SHIFT 4
    #define PCR_MATCH_MASK 0x00000020
    #define PCR_MATCH_SHIFT 5
    #define OPCR_MATCH_MASK 0x00000040
    #define OPCR_MATCH_SHIFT 6
    #define SPF_MATCH_MASK 0x00000080
    #define SPF_MATCH_SHIFT 7
    #define TPD_MATCH_MASK 0x00000100
    #define TPD_MATCH_SHIFT 8
    #define AFE_MATCH_MASK 0x00000200
    #define AFE_MATCH_SHIFT 9
    #define AF_SIZE_MATCH_MASK 0x00007C00
    #define AF_SIZE_MATCH_SHIFT 10
    #define PATTERN_SEL_MASK 0x00070000
    #define PATTERN_SEL_SHIFT 16
    #define TIMER_SEL_MASK 0x00700000
    #define TIMER_SEL_SHIFT 20
    #define LOG_RID_MASK 0x3F000000
    #define LOG_RID_SHIFT 24
#define  SF_RING_ES_START_PTR_ADR 0x6700
    #define SF_RING_ES_START_PTR_ADR_SF_RING_MASK 0x0000007F
    #define SF_RING_ES_START_PTR_ADR_SF_RING_SHIFT 0
#define  SF_RING_ES_START_PTR_DATA 0x6704
    #define SF_RING_ES_START_PTR_MASK 0x7FFFFFFF
    #define SF_RING_ES_START_PTR_SHIFT 0
    #define SF_RING_ES_START_PTR_RD_VALID_MASK 0x80000000
    #define SF_RING_ES_START_PTR_RD_VALID_SHIFT 31
#define  SF_RING_PTS_DTS_ADR 0x6600
    #define SF_RING_PTS_DTS_ADR_SF_RING_MASK 0x0000007F
    #define SF_RING_PTS_DTS_ADR_SF_RING_SHIFT 0
    #define SF_DTS_MASK 0x00010000
    #define SF_DTS_SHIFT 16
#define  SF_RING_PTS_DTS_DATA_L 0x6604
    #define SF_RING_PTS_DTS_DATA_L_MASK 0xFFFFFFFF
    #define SF_RING_PTS_DTS_DATA_L_SHIFT 0
#define  SF_RING_PTS_DTS_DATA_U 0x6608
    #define SF_RING_PTS_DTS_DATA_U_MASK 0x00000001
    #define SF_RING_PTS_DTS_DATA_U_SHIFT 0
    #define SF_RING_PTS_DTS_VALID_MASK 0x00010000
    #define SF_RING_PTS_DTS_VALID_SHIFT 16
    #define SF_RING_PTS_DTS_RD_VALID_MASK 0x80000000
    #define SF_RING_PTS_DTS_RD_VALID_SHIFT 31
#define  SF_STATUS_ADR 0x65E8
    #define SF_STATUS_ADR_MASK 0x0000007F
    #define SF_STATUS_ADR_SHIFT 0
#define  SF_STATUS_DATA 0x65EC
    #define CC_ERR_SEEN_MASK 0x00020000
    #define CC_ERR_SEEN_SHIFT 17
    #define OVERFLOW_MASK 0x00040000
    #define OVERFLOW_SHIFT 18
    #define PTS_SEEN_MASK 0x00080000
    #define PTS_SEEN_SHIFT 19
    #define DTS_SEEN_MASK 0x00100000
    #define DTS_SEEN_SHIFT 20
    #define DATA_VALID_MASK 0x80000000
    #define DATA_VALID_SHIFT 31
#define  SLD0_CTRL 0xA128
    #define SLD0_CTRL_PICT_STRUCT_MASK 0x00000003
    #define SLD0_CTRL_PICT_STRUCT_SHIFT 0
    #define SLD0_CTRL_PICT_TYPE_MASK 0x0000000C
    #define SLD0_CTRL_PICT_TYPE_SHIFT 2
    #define SLD0_CTRL_DEC_MPEG_FRMT_MASK 0x00000030
    #define SLD0_CTRL_DEC_MPEG_FRMT_SHIFT 4
    #define SLD0_CTRL_ENC_MPEG_FRMT_MASK 0x000000C0
    #define SLD0_CTRL_ENC_MPEG_FRMT_SHIFT 6
    #define SLD0_CTRL_QSCALE_TYPE_MASK 0x00000100
    #define SLD0_CTRL_QSCALE_TYPE_SHIFT 8
    #define SLD0_CTRL_FRM_PRED_DCT_MASK 0x00000200
    #define SLD0_CTRL_FRM_PRED_DCT_SHIFT 9
    #define SLD0_CTRL_CV_MASK 0x00000400
    #define SLD0_CTRL_CV_SHIFT 10
    #define SLD0_CTRL_MB_TOTAL_MASK 0x3FFF0000
    #define SLD0_CTRL_MB_TOTAL_SHIFT 16
#define  SLD0_HOST_INT_MASK 0xA10C
    #define SLD0_HOST_INT_MASK_DONE_HOST_INT_MASK 0x00000001
    #define SLD0_HOST_INT_MASK_DONE_HOST_INT_SHIFT 0
    #define SLD0_HOST_INT_MASK_ERROR_HOST_INT_MASK 0x00000002
    #define SLD0_HOST_INT_MASK_ERROR_HOST_INT_SHIFT 1
#define  SLD0_IBB_BIT_OFFSET 0xA138
    #define SLD0_IBB_BIT_OFFSET_OFFSET_MASK 0x0000001F
    #define SLD0_IBB_BIT_OFFSET_OFFSET_SHIFT 0
#define  SLD0_IBB_TAIL_ADR 0xA134
    #define SLD0_IBB_TAIL_ADR_BASE_MASK 0x07FFFFFC
    #define SLD0_IBB_TAIL_ADR_BASE_SHIFT 2
#define  SLD0_INFO 0xA17C
    #define SLD0_INFO_MB_ADR_MASK 0x00003FFF
    #define SLD0_INFO_MB_ADR_SHIFT 0
    #define SLD0_INFO_QSCALE_MASK 0x007F0000
    #define SLD0_INFO_QSCALE_SHIFT 16
#define  SLD0_INT_CTRL 0xA104
    #define SLD0_INT_CTRL_DONE_EN_MASK 0x00000001
    #define SLD0_INT_CTRL_DONE_EN_SHIFT 0
    #define SLD0_INT_CTRL_ERROR_EN_MASK 0x00000002
    #define SLD0_INT_CTRL_ERROR_EN_SHIFT 1
#define  SLD0_INT_STATUS 0xA108
    #define SLD0_INT_STATUS_DONE_INT_MASK 0x00000001
    #define SLD0_INT_STATUS_DONE_INT_SHIFT 0
    #define SLD0_INT_STATUS_ERROR_INT_MASK 0x00000002
    #define SLD0_INT_STATUS_ERROR_INT_SHIFT 1
#define  SLD0_MVA_STATUS 0xA180
    #define SLD0_MVA_STATUS_DATA_MASK 0xFFFFFFFF
    #define SLD0_MVA_STATUS_DATA_SHIFT 0
#define  SLD0_PROC_INT_MASK 0xA110
    #define SLD0_PROC_INT_MASK_DONE_PROC_INT_MASK_MASK 0x00000001
    #define SLD0_PROC_INT_MASK_DONE_PROC_INT_MASK_SHIFT 0
    #define SLD0_PROC_INT_MASK_ERROR_PROC_INT_MASK_MASK 0x00000002
    #define SLD0_PROC_INT_MASK_ERROR_PROC_INT_MASK_SHIFT 1
#define  SLD0_STATUS 0xA130
    #define SLD0_STATUS_DONE_MASK 0x00000001
    #define SLD0_STATUS_DONE_SHIFT 0
    #define SLD0_STATUS_DIP_END_MASK 0x07FFFFFC
    #define SLD0_STATUS_DIP_END_SHIFT 2
    #define SLD0_STATUS_ERROR_MASK 0xF0000000
    #define SLD0_STATUS_ERROR_SHIFT 28
#define  SLD0_TRIG 0xA12C
    #define SLD0_TRIG_START_CODE_MASK 0x000000FF
    #define SLD0_TRIG_START_CODE_SHIFT 0
    #define SLD0_TRIG_DEC_MB_CNT_MASK 0x3FFF0000
    #define SLD0_TRIG_DEC_MB_CNT_SHIFT 16
#define  SLD1_CTRL 0xA528
    #define SLD1_CTRL_PICT_STRUCT_MASK 0x00000003
    #define SLD1_CTRL_PICT_STRUCT_SHIFT 0
    #define SLD1_CTRL_PICT_TYPE_MASK 0x0000000C
    #define SLD1_CTRL_PICT_TYPE_SHIFT 2
    #define SLD1_CTRL_DEC_MPEG_FRMT_MASK 0x00000030
    #define SLD1_CTRL_DEC_MPEG_FRMT_SHIFT 4
    #define SLD1_CTRL_ENC_MPEG_FRMT_MASK 0x000000C0
    #define SLD1_CTRL_ENC_MPEG_FRMT_SHIFT 6
    #define SLD1_CTRL_QSCALE_TYPE_MASK 0x00000100
    #define SLD1_CTRL_QSCALE_TYPE_SHIFT 8
    #define SLD1_CTRL_FRM_PRED_DCT_MASK 0x00000200
    #define SLD1_CTRL_FRM_PRED_DCT_SHIFT 9
    #define SLD1_CTRL_CV_MASK 0x00000400
    #define SLD1_CTRL_CV_SHIFT 10
    #define SLD1_CTRL_MB_TOTAL_MASK 0x3FFF0000
    #define SLD1_CTRL_MB_TOTAL_SHIFT 16
#define  SLD1_HOST_INT_MASK 0xA50C
    #define SLD1_HOST_INT_MASK_DONE_HOST_INT_MASK 0x00000001
    #define SLD1_HOST_INT_MASK_DONE_HOST_INT_SHIFT 0
    #define SLD1_HOST_INT_MASK_ERROR_HOST_INT_MASK 0x00000002
    #define SLD1_HOST_INT_MASK_ERROR_HOST_INT_SHIFT 1
#define  SLD1_IBB_BIT_OFFSET 0xA538
    #define SLD1_IBB_BIT_OFFSET_OFFSET_MASK 0x0000001F
    #define SLD1_IBB_BIT_OFFSET_OFFSET_SHIFT 0
#define  SLD1_IBB_TAIL_ADR 0xA534
    #define SLD1_IBB_TAIL_ADR_BASE_MASK 0x07FFFFFC
    #define SLD1_IBB_TAIL_ADR_BASE_SHIFT 2
#define  SLD1_INFO 0xA57C
    #define SLD1_INFO_MB_ADR_MASK 0x00003FFF
    #define SLD1_INFO_MB_ADR_SHIFT 0
    #define SLD1_INFO_QSCALE_MASK 0x007F0000
    #define SLD1_INFO_QSCALE_SHIFT 16
#define  SLD1_INT_CTRL 0xA504
    #define SLD1_INT_CTRL_DONE_EN_MASK 0x00000001
    #define SLD1_INT_CTRL_DONE_EN_SHIFT 0
    #define SLD1_INT_CTRL_ERROR_EN_MASK 0x00000002
    #define SLD1_INT_CTRL_ERROR_EN_SHIFT 1
#define  SLD1_INT_STATUS 0xA508
    #define SLD1_INT_STATUS_DONE_INT_MASK 0x00000001
    #define SLD1_INT_STATUS_DONE_INT_SHIFT 0
    #define SLD1_INT_STATUS_ERROR_INT_MASK 0x00000002
    #define SLD1_INT_STATUS_ERROR_INT_SHIFT 1
#define  SLD1_MVA_STATUS 0xA580
    #define SLD1_MVA_STATUS_DATA_MASK 0xFFFFFFFF
    #define SLD1_MVA_STATUS_DATA_SHIFT 0
#define  SLD1_PROC_INT_MASK 0xA510
    #define SLD1_PROC_INT_MASK_DONE_PROC_INT_MASK_MASK 0x00000001
    #define SLD1_PROC_INT_MASK_DONE_PROC_INT_MASK_SHIFT 0
    #define SLD1_PROC_INT_MASK_ERROR_PROC_INT_MASK_MASK 0x00000002
    #define SLD1_PROC_INT_MASK_ERROR_PROC_INT_MASK_SHIFT 1
#define  SLD1_STATUS 0xA530
    #define SLD1_STATUS_DONE_MASK 0x00000001
    #define SLD1_STATUS_DONE_SHIFT 0
    #define SLD1_STATUS_DIP_END_MASK 0x07FFFFFC
    #define SLD1_STATUS_DIP_END_SHIFT 2
    #define SLD1_STATUS_ERROR_MASK 0xF0000000
    #define SLD1_STATUS_ERROR_SHIFT 28
#define  SLD1_TRIG 0xA52C
    #define SLD1_TRIG_START_CODE_MASK 0x000000FF
    #define SLD1_TRIG_START_CODE_SHIFT 0
    #define SLD1_TRIG_DEC_MB_CNT_MASK 0x3FFF0000
    #define SLD1_TRIG_DEC_MB_CNT_SHIFT 16
#define  SMCC_CSR_CTRL_REG 0xF004
    #define SMCC_CSR_CTRL_REG_ADDR_MASK 0x000001FC
    #define SMCC_CSR_CTRL_REG_ADDR_SHIFT 2
    #define SMCC_CSR_CTRL_REG_WOP_MASK 0x80000000
    #define SMCC_CSR_CTRL_REG_WOP_SHIFT 31
#define  SMCC_CSR_CTRL_REG1 0xF204
    #define ADDR1_MASK 0x000001FC
    #define ADDR1_SHIFT 2
    #define WOP1_MASK 0x80000000
    #define WOP1_SHIFT 31
#define  SMCC_CSR_STATUS_REG 0xF000
    #define SMCC_CSR_STATUS_REG_CSR_BUSY_MASK 0x00000001
    #define SMCC_CSR_STATUS_REG_CSR_BUSY_SHIFT 0
    #define CSR_ERR_MASK 0x00000002
    #define CSR_ERR_SHIFT 1
#define  SMCC_CSR_STATUS_REG1 0xF200
    #define CSR_BUSY1_MASK 0x00000001
    #define CSR_BUSY1_SHIFT 0
    #define CSR_ERR1_MASK 0x00000002
    #define CSR_ERR1_SHIFT 1
#define  SMCC_CTRL_REG 0xF040
    #define SMCC_CTRL_REG_SOFT_RST_MASK 0x00000001
    #define SMCC_CTRL_REG_SOFT_RST_SHIFT 0
    #define SMCC_CTRL_REG_TSM_WR_MAX_WAIT_MASK 0x00003F00
    #define SMCC_CTRL_REG_TSM_WR_MAX_WAIT_SHIFT 8
    #define SMCC_CTRL_REG_MEM_BRIDGE_HALT_MASK 0x00010000
    #define SMCC_CTRL_REG_MEM_BRIDGE_HALT_SHIFT 16
    #define ARB_TIMER_MASK 0x00F00000
    #define ARB_TIMER_SHIFT 20
#define  SMCC_CTRL_REG1 0xF240
    #define SOFT_RST1_MASK 0x00000001
    #define SOFT_RST1_SHIFT 0
    #define TSM_WR_MAX_WAIT1_MASK 0x00003F00
    #define TSM_WR_MAX_WAIT1_SHIFT 8
    #define MEM_BRIDGE_HALT1_MASK 0x00010000
    #define MEM_BRIDGE_HALT1_SHIFT 16
    #define ARB_TIMER1_MASK 0x00F00000
    #define ARB_TIMER1_SHIFT 20
#define  SMCC_DEBUG_REG 0xF050
    #define SMCC_DEBUG_REG_DEBUG_DATA_MASK 0xFFFFFFFF
    #define SMCC_DEBUG_REG_DEBUG_DATA_SHIFT 0
#define  SMCC_DEBUG_REG1 0xF250
    #define DEBUG_DATA1_MASK 0xFFFFFFFF
    #define DEBUG_DATA1_SHIFT 0
#define  SMCC_DUMMY_REG 0xF054
    #define DUMMY_DATA_MASK 0xFFFFFFFF
    #define DUMMY_DATA_SHIFT 0
#define  SMCC_DUMMY_REG1 0xF254
    #define DUMMY_DATA1_MASK 0xFFFFFFFF
    #define DUMMY_DATA1_SHIFT 0
#define  SMCC_INT_EN_REG 0xF02C
    #define SMCC_INT_EN_REG_INT_EN_MASK 0x00000001
    #define SMCC_INT_EN_REG_INT_EN_SHIFT 0
    #define OWN_BIT_CLR_INT_EN_MASK 0x00000010
    #define OWN_BIT_CLR_INT_EN_SHIFT 4
#define  SMCC_INT_EN_REG1 0xF22C
    #define INT_EN1_MASK 0x00000001
    #define INT_EN1_SHIFT 0
    #define OWN_BIT_CLR_INT_EN1_MASK 0x00000010
    #define OWN_BIT_CLR_INT_EN1_SHIFT 4
#define  SMCC_IP_RAW_INT_MASK_REG 0xF028
    #define IP_RAW_INT_EN_MASK 0xFFFFFFFF
    #define IP_RAW_INT_EN_SHIFT 0
#define  SMCC_IP_RAW_INT_MASK_REG1 0xF228
    #define IP_RAW_INT_EN1_MASK 0xFFFFFFFF
    #define IP_RAW_INT_EN1_SHIFT 0
#define  SMCC_IP_RAW_INT_REG 0xF024
    #define IP_RAW_INT_MASK 0xFFFFFFFF
    #define IP_RAW_INT_SHIFT 0
#define  SMCC_IP_RAW_INT_REG1 0xF224
    #define IP_RAW_INT1_MASK 0xFFFFFFFF
    #define IP_RAW_INT1_SHIFT 0
#define  SMCC_NEG_DRV_REG 0xF048
    #define SMCC_NEG_DRV_REG_NEG_EDGE_EN_MASK 0x00000001
    #define SMCC_NEG_DRV_REG_NEG_EDGE_EN_SHIFT 0
#define  SMCC_NEG_DRV_REG1 0xF248
    #define SMCC_NEG_DRV_REG1_NEG_EDGE_EN1_MASK 0x00000001
    #define SMCC_NEG_DRV_REG1_NEG_EDGE_EN1_SHIFT 0
#define  SMCC_NEG_SAMPL_REG 0xF044
    #define SMCC_NEG_SAMPL_REG_NEG_EDGE_EN_MASK 0x00000001
    #define SMCC_NEG_SAMPL_REG_NEG_EDGE_EN_SHIFT 0
#define  SMCC_NEG_SAMPL_REG1 0xF244
    #define SMCC_NEG_SAMPL_REG1_NEG_EDGE_EN1_MASK 0x00000001
    #define SMCC_NEG_SAMPL_REG1_NEG_EDGE_EN1_SHIFT 0
#define  SMCC_RDAT_REG 0xF00C
    #define RDAT_MASK 0xFFFFFFFF
    #define RDAT_SHIFT 0
#define  SMCC_RDAT_REG1 0xF20C
    #define RDAT1_MASK 0xFFFFFFFF
    #define RDAT1_SHIFT 0
#define  SMCC_STATUS_REG 0xF020
    #define IP_INT_STATUS_MASK 0x00000001
    #define IP_INT_STATUS_SHIFT 0
    #define IP_INT_ENABLE_MASK 0x00000002
    #define IP_INT_ENABLE_SHIFT 1
    #define OWN_BIT_CLR_STATUS_MASK 0x00000010
    #define OWN_BIT_CLR_STATUS_SHIFT 4
    #define SMCC_STATUS_REG_MEM_BRIDGE_IDLE_MASK 0x00010000
    #define SMCC_STATUS_REG_MEM_BRIDGE_IDLE_SHIFT 16
#define  SMCC_STATUS_REG1 0xF220
    #define IP_INT_STATUS1_MASK 0x00000001
    #define IP_INT_STATUS1_SHIFT 0
    #define IP_INT_ENABLE1_MASK 0x00000002
    #define IP_INT_ENABLE1_SHIFT 1
    #define OWN_BIT_CLR_STATUS1_MASK 0x00000010
    #define OWN_BIT_CLR_STATUS1_SHIFT 4
    #define MEM_BRIDGE_IDLE1_MASK 0x00010000
    #define MEM_BRIDGE_IDLE1_SHIFT 16
#define  SMCC_WDAT_REG 0xF008
    #define SMCC_WDAT_REG_WDAT_MASK 0xFFFFFFFF
    #define SMCC_WDAT_REG_WDAT_SHIFT 0
#define  SMCC_WDAT_REG1 0xF208
    #define WDAT1_MASK 0xFFFFFFFF
    #define WDAT1_SHIFT 0
#define  SMS_CTRL 0x8C08
    #define SMS_CTRL_MBAFF_FLAG_MASK 0x00000001
    #define SMS_CTRL_MBAFF_FLAG_SHIFT 0
    #define SCALE_OUT_EN_MASK 0x00000004
    #define SCALE_OUT_EN_SHIFT 2
    #define VAR_EN_MASK 0x00000010
    #define VAR_EN_SHIFT 4
    #define VAR_FLD_EN_MASK 0x00000020
    #define VAR_FLD_EN_SHIFT 5
    #define VAR_FF_OUT_EN_MASK 0x00000040
    #define VAR_FF_OUT_EN_SHIFT 6
    #define L0_SRCH_EN_MASK 0x00000100
    #define L0_SRCH_EN_SHIFT 8
    #define L1_SRCH_EN_MASK 0x00000200
    #define L1_SRCH_EN_SHIFT 9
    #define SMS_CTRL_TILE_MODE_MASK 0x00003000
    #define SMS_CTRL_TILE_MODE_SHIFT 12
    #define FIELD_COST_EN_MASK 0x00010000
    #define FIELD_COST_EN_SHIFT 16
    #define MV_COST_EN_MASK 0x00020000
    #define MV_COST_EN_SHIFT 17
    #define SMS_CTRL_READ_ACCEL_MASK 0x00100000
    #define SMS_CTRL_READ_ACCEL_SHIFT 20
    #define SMS_CTRL_INT_EN_MASK 0x80000000
    #define SMS_CTRL_INT_EN_SHIFT 31
#define  SMS_CUR_PITCH 0x8C14
    #define SMS_CUR_PITCH_CUR_PITCH_MASK 0x00000FE0
    #define SMS_CUR_PITCH_CUR_PITCH_SHIFT 5
#define  SMS_DUMMY_REG 0x8C0C
    #define SMS_DUMMY_REG_DUMMY_BITS_MASK 0xFFFFFFFF
    #define SMS_DUMMY_REG_DUMMY_BITS_SHIFT 0
#define  SMS_INT_STATUS 0x8C04
    #define SMS_INT_STATUS_SMS_INT_MASK 0x00000001
    #define SMS_INT_STATUS_SMS_INT_SHIFT 0
#define  SMS_MVA_BASE 0x8C2C
    #define SMS_MVA_BASE_ADDR_MASK 0x7FFFFFE0
    #define SMS_MVA_BASE_ADDR_SHIFT 5
#define  SMS_PICT_SIZE 0x8C10
    #define SMS_PICT_SIZE_PICT_MB_WIDTH_MASK 0x000000FF
    #define SMS_PICT_SIZE_PICT_MB_WIDTH_SHIFT 0
    #define SMS_PICT_SIZE_PICT_MB_HEIGHT_MASK 0x0000FF00
    #define SMS_PICT_SIZE_PICT_MB_HEIGHT_SHIFT 8
#define  SMS_STATUS 0x8C00
    #define SMS_BUSY_MASK 0x00000001
    #define SMS_BUSY_SHIFT 0
#define  SMS_SUM_L0_COST 0x8C34
    #define SUM_L0_COST_MASK 0x003FFFFF
    #define SUM_L0_COST_SHIFT 0
#define  SMS_SUM_L1_COST 0x8C38
    #define SUM_L1_COST_MASK 0x003FFFFF
    #define SUM_L1_COST_SHIFT 0
#define  SMS_VAR_BASE 0x8C30
    #define SMS_VAR_BASE_ADDR_MASK 0x7FFFFFE0
    #define SMS_VAR_BASE_ADDR_SHIFT 5
#define  SMS_Y2_CUR_BASE 0x8C1C
    #define SMS_Y2_CUR_BASE_ADDR_MASK 0x7FFFFFE0
    #define SMS_Y2_CUR_BASE_ADDR_SHIFT 5
#define  SMS_Y_CUR_BASE 0x8C18
    #define SMS_Y_CUR_BASE_ADDR_MASK 0x7FFFFFE0
    #define SMS_Y_CUR_BASE_ADDR_SHIFT 5
#define  SMS_Y_L0_BASE 0x8C20
    #define SMS_Y_L0_BASE_ADDR_MASK 0x7FFFFF00
    #define SMS_Y_L0_BASE_ADDR_SHIFT 8
#define  SMS_Y_L1_BASE 0x8C24
    #define SMS_Y_L1_BASE_ADDR_MASK 0x7FFFFF00
    #define SMS_Y_L1_BASE_ADDR_SHIFT 8
#define  SMS_Y_SCL_OUT_BASE 0x8C28
    #define SMS_Y_SCL_OUT_BASE_ADDR_MASK 0x7FFFFF00
    #define SMS_Y_SCL_OUT_BASE_ADDR_SHIFT 8
#define  SPDIF_CODE_RD_ADDR 0x1624
    #define SPDIF_CODE_RD_ADDR_CURR_RD_ADDR_MASK 0x7FFFFFF0
    #define SPDIF_CODE_RD_ADDR_CURR_RD_ADDR_SHIFT 4
#define  SPDIF_DATA_RD_ADDR 0x1614
    #define SPDIF_DATA_RD_ADDR_CURR_RD_ADDR_MASK 0x7FFFFFF0
    #define SPDIF_DATA_RD_ADDR_CURR_RD_ADDR_SHIFT 4
#define  SPDIF_DATA_WR_ADDR 0x1714
    #define SPDIF_DATA_WR_ADDR_CURR_WR_ADDR_MASK 0x7FFFFFF0
    #define SPDIF_DATA_WR_ADDR_CURR_WR_ADDR_SHIFT 4
#define  SPDIF_RDES0 0x1718
    #define SPDIF_RDES0_NUM_FRAME_MASK 0x000000FF
    #define SPDIF_RDES0_NUM_FRAME_SHIFT 0
    #define SPDIF_RDES0_IOC_MASK 0x00008000
    #define SPDIF_RDES0_IOC_SHIFT 15
    #define SPDIF_RDES0_RDWRN_MASK 0x80000000
    #define SPDIF_RDES0_RDWRN_SHIFT 31
#define  SPDIF_RDES1 0x171C
    #define SPDIF_RDES1_DATA_BUF_ADDR_MASK 0x7FFFFFE0
    #define SPDIF_RDES1_DATA_BUF_ADDR_SHIFT 5
#define  SPDIF_RDES2 0x1720
    #define TIMESTAMP_BUF_ADDR_MASK 0x7FFFFFF8
    #define TIMESTAMP_BUF_ADDR_SHIFT 3
#define  SPDIF_RX_90KHZ_DEN 0x1754
    #define SPDIF_RX_90KHZ_DEN_DEN_MASK 0xFFFFFFFF
    #define SPDIF_RX_90KHZ_DEN_DEN_SHIFT 0
#define  SPDIF_RX_90KHZ_NUM 0x1750
    #define SPDIF_RX_90KHZ_NUM_NUM_MASK 0xFFFFFFFF
    #define SPDIF_RX_90KHZ_NUM_NUM_SHIFT 0
#define  SPDIF_RX_CH1_STATUS_LOWER 0x1774
    #define CH1_STATUS_L_MASK 0xFFFFFFFF
    #define CH1_STATUS_L_SHIFT 0
#define  SPDIF_RX_CH1_STATUS_UPPER 0x1770
    #define CH1_STATUS_U_MASK 0x000003FF
    #define CH1_STATUS_U_SHIFT 0
#define  SPDIF_RX_CH2_STATUS_LOWER 0x177C
    #define CH2_STATUS_L_MASK 0xFFFFFFFF
    #define CH2_STATUS_L_SHIFT 0
#define  SPDIF_RX_CH2_STATUS_UPPER 0x1778
    #define CH2_STATUS_U_MASK 0x000003FF
    #define CH2_STATUS_U_SHIFT 0
#define  SPDIF_RX_CONFIG 0x1700
    #define SPDIF_RX_CONFIG_CHANNEL_EN_MASK 0x00000001
    #define SPDIF_RX_CONFIG_CHANNEL_EN_SHIFT 0
    #define SPDIF_RX_CONFIG_OPERATE_MODE_MASK 0x00000030
    #define SPDIF_RX_CONFIG_OPERATE_MODE_SHIFT 4
    #define CAPTURE_MODE_MASK 0x00000040
    #define CAPTURE_MODE_SHIFT 6
    #define SPDIF_RX_CONFIG_ENDIAN_MASK 0x00000100
    #define SPDIF_RX_CONFIG_ENDIAN_SHIFT 8
    #define LPF_DEPTH_MASK 0x0000F000
    #define LPF_DEPTH_SHIFT 12
    #define SPDIF_RX_CONFIG_RESETN_MASK 0x80000000
    #define SPDIF_RX_CONFIG_RESETN_SHIFT 31
#define  SPDIF_RX_DEBUG_REG 0x17F8
    #define SPDIF_RX_DEBUG_REG_DEBUG_DATA_MASK 0xFFFFFFFF
    #define SPDIF_RX_DEBUG_REG_DEBUG_DATA_SHIFT 0
#define  SPDIF_RX_DEN 0x1764
    #define SPDIF_RX_DEN_DEN_MASK 0xFFFFFFFF
    #define SPDIF_RX_DEN_DEN_SHIFT 0
#define  SPDIF_RX_DESC_STATUS 0x1710
    #define SPDIF_RX_DESC_STATUS_CURR_FRAME_NUM_MASK 0x000000FF
    #define SPDIF_RX_DESC_STATUS_CURR_FRAME_NUM_SHIFT 0
    #define SPDIF_RX_DESC_STATUS_FILLED_ENTRIES_MASK 0x00000700
    #define SPDIF_RX_DESC_STATUS_FILLED_ENTRIES_SHIFT 8
    #define SPDIF_RX_DESC_STATUS_DESC_FULL_MASK 0x40000000
    #define SPDIF_RX_DESC_STATUS_DESC_FULL_SHIFT 30
    #define SPDIF_RX_DESC_STATUS_DESC_EMPTY_MASK 0x80000000
    #define SPDIF_RX_DESC_STATUS_DESC_EMPTY_SHIFT 31
#define  SPDIF_RX_DUMMY_REG 0x17FC
    #define SPDIF_RX_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define SPDIF_RX_DUMMY_REG_DATA_SHIFT 0
#define  SPDIF_RX_FOUR_PULSE 0x1744
    #define SPDIF_RX_FOUR_PULSE_WIDTH_MASK 0x000001FF
    #define SPDIF_RX_FOUR_PULSE_WIDTH_SHIFT 0
#define  SPDIF_RX_GENLOCK_LOWER 0x176C
    #define SPDIF_RX_GENLOCK_LOWER_GENLOCK_L_MASK 0xFFFFFFFF
    #define SPDIF_RX_GENLOCK_LOWER_GENLOCK_L_SHIFT 0
#define  SPDIF_RX_GENLOCK_UPPER 0x1768
    #define SPDIF_RX_GENLOCK_UPPER_GENLOCK_U_MASK 0x000003FF
    #define SPDIF_RX_GENLOCK_UPPER_GENLOCK_U_SHIFT 0
#define  SPDIF_RX_HOST_INT_MASK 0x1704
    #define SPDIF_RX_HOST_INT_MASK_OF_INT_MASK 0x00000001
    #define SPDIF_RX_HOST_INT_MASK_OF_INT_SHIFT 0
    #define SPDIF_RX_HOST_INT_MASK_INT_MASK 0x00000100
    #define SPDIF_RX_HOST_INT_MASK_INT_SHIFT 8
    #define SPDIF_RX_HOST_INT_MASK_SHORT_PULSE_INT_MASK 0x00010000
    #define SPDIF_RX_HOST_INT_MASK_SHORT_PULSE_INT_SHIFT 16
    #define SPDIF_RX_HOST_INT_MASK_SHORT_FRAME_INT_MASK 0x00020000
    #define SPDIF_RX_HOST_INT_MASK_SHORT_FRAME_INT_SHIFT 17
    #define SPDIF_RX_HOST_INT_MASK_LOCKED_INT_MASK 0x00040000
    #define SPDIF_RX_HOST_INT_MASK_LOCKED_INT_SHIFT 18
    #define SPDIF_RX_HOST_INT_MASK_LOST_LOCKED_INT_MASK 0x00080000
    #define SPDIF_RX_HOST_INT_MASK_LOST_LOCKED_INT_SHIFT 19
#define  SPDIF_RX_INT_STATUS 0x170C
    #define SPDIF_RX_INT_STATUS_OF_INT_MASK 0x00000001
    #define SPDIF_RX_INT_STATUS_OF_INT_SHIFT 0
    #define SPDIF_RX_INT_STATUS_INT_MASK 0x00000100
    #define SPDIF_RX_INT_STATUS_INT_SHIFT 8
    #define SPDIF_RX_INT_STATUS_SHORT_PULSE_INT_MASK 0x00010000
    #define SPDIF_RX_INT_STATUS_SHORT_PULSE_INT_SHIFT 16
    #define SPDIF_RX_INT_STATUS_SHORT_FRAME_INT_MASK 0x00020000
    #define SPDIF_RX_INT_STATUS_SHORT_FRAME_INT_SHIFT 17
    #define SPDIF_RX_INT_STATUS_LOCKED_INT_MASK 0x00040000
    #define SPDIF_RX_INT_STATUS_LOCKED_INT_SHIFT 18
    #define SPDIF_RX_INT_STATUS_LOST_LOCKED_INT_MASK 0x00080000
    #define SPDIF_RX_INT_STATUS_LOST_LOCKED_INT_SHIFT 19
#define  SPDIF_RX_LOOPBACK_CTRL 0x178C
    #define SPDIF_RX_LOOPBACK_CTRL_ENABLE_MASK 0x00000001
    #define SPDIF_RX_LOOPBACK_CTRL_ENABLE_SHIFT 0
#define  SPDIF_RX_MAX 0x172C
    #define SPDIF_RX_MAX_PULSE_WIDTH_MASK 0x000001FF
    #define SPDIF_RX_MAX_PULSE_WIDTH_SHIFT 0
#define  SPDIF_RX_MIN 0x1730
    #define SPDIF_RX_MIN_PULSE_WIDTH_MASK 0x000001FF
    #define SPDIF_RX_MIN_PULSE_WIDTH_SHIFT 0
#define  SPDIF_RX_MIPS_INT_MASK 0x1708
    #define SPDIF_RX_MIPS_INT_MASK_OF_INT_MASK 0x00000001
    #define SPDIF_RX_MIPS_INT_MASK_OF_INT_SHIFT 0
    #define SPDIF_RX_MIPS_INT_MASK_INT_MASK 0x00000100
    #define SPDIF_RX_MIPS_INT_MASK_INT_SHIFT 8
    #define SPDIF_RX_MIPS_INT_MASK_SHORT_PULSE_INT_MASK 0x00010000
    #define SPDIF_RX_MIPS_INT_MASK_SHORT_PULSE_INT_SHIFT 16
    #define SPDIF_RX_MIPS_INT_MASK_SHORT_FRAME_INT_MASK 0x00020000
    #define SPDIF_RX_MIPS_INT_MASK_SHORT_FRAME_INT_SHIFT 17
    #define SPDIF_RX_MIPS_INT_MASK_LOCKED_INT_MASK 0x00040000
    #define SPDIF_RX_MIPS_INT_MASK_LOCKED_INT_SHIFT 18
    #define SPDIF_RX_MIPS_INT_MASK_LOST_LOCKED_INT_MASK 0x00080000
    #define SPDIF_RX_MIPS_INT_MASK_LOST_LOCKED_INT_SHIFT 19
#define  SPDIF_RX_MISS_SUBFRAME 0x1780
    #define NUM_MISS_SUBFRAME_MASK 0x000001FF
    #define NUM_MISS_SUBFRAME_SHIFT 0
#define  SPDIF_RX_NUM 0x1760
    #define SPDIF_RX_NUM_NUM_MASK 0xFFFFFFFF
    #define SPDIF_RX_NUM_NUM_SHIFT 0
#define  SPDIF_RX_ONE_PULSE 0x1738
    #define SPDIF_RX_ONE_PULSE_WIDTH_MASK 0x000001FF
    #define SPDIF_RX_ONE_PULSE_WIDTH_SHIFT 0
#define  SPDIF_RX_PREAMBLE 0x1748
    #define SPDIF_RX_PREAMBLE_B_MASK 0x0000000F
    #define SPDIF_RX_PREAMBLE_B_SHIFT 0
    #define SPDIF_RX_PREAMBLE_M_MASK 0x000000F0
    #define SPDIF_RX_PREAMBLE_M_SHIFT 4
    #define SPDIF_RX_PREAMBLE_W_MASK 0x00000F00
    #define SPDIF_RX_PREAMBLE_W_SHIFT 8
#define  SPDIF_RX_SHORT_PULSE 0x1734
    #define SPDIF_RX_SHORT_PULSE_WIDTH_MASK 0x000001FF
    #define SPDIF_RX_SHORT_PULSE_WIDTH_SHIFT 0
#define  SPDIF_RX_STATUS_SHORT_FRAME 0x1784
    #define SPDIF_RX_STATUS_SHORT_FRAME_ERR_CNT_MASK 0xFFFFFFFF
    #define SPDIF_RX_STATUS_SHORT_FRAME_ERR_CNT_SHIFT 0
#define  SPDIF_RX_STATUS_SHORT_PULSE 0x1788
    #define SPDIF_RX_STATUS_SHORT_PULSE_ERR_CNT_MASK 0xFFFFFFFF
    #define SPDIF_RX_STATUS_SHORT_PULSE_ERR_CNT_SHIFT 0
#define  SPDIF_RX_THREE_PULSE 0x1740
    #define SPDIF_RX_THREE_PULSE_WIDTH_MASK 0x000001FF
    #define SPDIF_RX_THREE_PULSE_WIDTH_SHIFT 0
#define  SPDIF_RX_TIMESTAMP_SEL 0x1758
    #define SPDIF_RX_TIMESTAMP_SEL_TIMESTAMP_SEL_MASK 0x00000007
    #define SPDIF_RX_TIMESTAMP_SEL_TIMESTAMP_SEL_SHIFT 0
#define  SPDIF_RX_TWO_PULSE 0x173C
    #define SPDIF_RX_TWO_PULSE_WIDTH_MASK 0x000001FF
    #define SPDIF_RX_TWO_PULSE_WIDTH_SHIFT 0
#define  SPDIF_TDES0 0x1618
    #define SPDIF_TDES0_NUM_FRAME_MASK 0x000000FF
    #define SPDIF_TDES0_NUM_FRAME_SHIFT 0
    #define SPDIF_TDES0_IOC_MASK 0x00008000
    #define SPDIF_TDES0_IOC_SHIFT 15
    #define SPDIF_TDES0_RDWRN_MASK 0x80000000
    #define SPDIF_TDES0_RDWRN_SHIFT 31
#define  SPDIF_TDES1 0x161C
    #define SPDIF_TDES1_DATA_BUF_ADDR_MASK 0x7FFFFFE0
    #define SPDIF_TDES1_DATA_BUF_ADDR_SHIFT 5
#define  SPDIF_TDES2 0x1620
    #define CODE_BUF_ADDR_MASK 0x7FFFFFE0
    #define CODE_BUF_ADDR_SHIFT 5
#define  SPDIF_TIMESTAMP_FREQ 0x1728
    #define TIMESTAMP_FREQ_MASK 0x000000FF
    #define TIMESTAMP_FREQ_SHIFT 0
#define  SPDIF_TIMESTAMP_WR_ADDR 0x1724
    #define SPDIF_TIMESTAMP_WR_ADDR_CURR_WR_ADDR_MASK 0x7FFFFFF8
    #define SPDIF_TIMESTAMP_WR_ADDR_CURR_WR_ADDR_SHIFT 3
#define  SPDIF_TX_CONFIG 0x1600
    #define SPDIF_TX_CONFIG_CHANNEL_EN_MASK 0x00000001
    #define SPDIF_TX_CONFIG_CHANNEL_EN_SHIFT 0
    #define SPDIF_TX_CONFIG_OPERATE_MODE_MASK 0x00000030
    #define SPDIF_TX_CONFIG_OPERATE_MODE_SHIFT 4
    #define SPDIF_TX_CONFIG_ENDIAN_MASK 0x00000100
    #define SPDIF_TX_CONFIG_ENDIAN_SHIFT 8
    #define SPDIF_TX_CONFIG_UF_CTRL_EN_MASK 0x00200000
    #define SPDIF_TX_CONFIG_UF_CTRL_EN_SHIFT 21
    #define SPDIF_TX_CONFIG_RESETN_MASK 0x80000000
    #define SPDIF_TX_CONFIG_RESETN_SHIFT 31
#define  SPDIF_TX_DEBUG_REG 0x16F8
    #define SPDIF_TX_DEBUG_REG_DEBUG_DATA_MASK 0xFFFFFFFF
    #define SPDIF_TX_DEBUG_REG_DEBUG_DATA_SHIFT 0
#define  SPDIF_TX_DEN 0x1634
    #define SPDIF_TX_DEN_DEN_MASK 0xFFFFFFFF
    #define SPDIF_TX_DEN_DEN_SHIFT 0
#define  SPDIF_TX_DESC_STATUS 0x1610
    #define SPDIF_TX_DESC_STATUS_CURR_FRAME_NUM_MASK 0x000000FF
    #define SPDIF_TX_DESC_STATUS_CURR_FRAME_NUM_SHIFT 0
    #define SPDIF_TX_DESC_STATUS_FILLED_ENTRIES_MASK 0x00000700
    #define SPDIF_TX_DESC_STATUS_FILLED_ENTRIES_SHIFT 8
    #define SPDIF_TX_DESC_STATUS_DESC_FULL_MASK 0x40000000
    #define SPDIF_TX_DESC_STATUS_DESC_FULL_SHIFT 30
    #define SPDIF_TX_DESC_STATUS_DESC_EMPTY_MASK 0x80000000
    #define SPDIF_TX_DESC_STATUS_DESC_EMPTY_SHIFT 31
#define  SPDIF_TX_DUMMY_REG 0x16FC
    #define SPDIF_TX_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define SPDIF_TX_DUMMY_REG_DATA_SHIFT 0
#define  SPDIF_TX_GENLOCK_LOWER 0x163C
    #define SPDIF_TX_GENLOCK_LOWER_GENLOCK_L_MASK 0xFFFFFFFF
    #define SPDIF_TX_GENLOCK_LOWER_GENLOCK_L_SHIFT 0
#define  SPDIF_TX_GENLOCK_UPPER 0x1638
    #define SPDIF_TX_GENLOCK_UPPER_GENLOCK_U_MASK 0x000003FF
    #define SPDIF_TX_GENLOCK_UPPER_GENLOCK_U_SHIFT 0
#define  SPDIF_TX_HOST_INT_MASK 0x1604
    #define SPDIF_TX_HOST_INT_MASK_UF_INT_MASK 0x00000001
    #define SPDIF_TX_HOST_INT_MASK_UF_INT_SHIFT 0
    #define SPDIF_TX_HOST_INT_MASK_INT_MASK 0x00000100
    #define SPDIF_TX_HOST_INT_MASK_INT_SHIFT 8
#define  SPDIF_TX_INT_STATUS 0x160C
    #define SPDIF_TX_INT_STATUS_UF_INT_MASK 0x00000001
    #define SPDIF_TX_INT_STATUS_UF_INT_SHIFT 0
    #define SPDIF_TX_INT_STATUS_INT_MASK 0x00000100
    #define SPDIF_TX_INT_STATUS_INT_SHIFT 8
#define  SPDIF_TX_MIPS_INT_MASK 0x1608
    #define SPDIF_TX_MIPS_INT_MASK_UF_INT_MASK 0x00000001
    #define SPDIF_TX_MIPS_INT_MASK_UF_INT_SHIFT 0
    #define SPDIF_TX_MIPS_INT_MASK_INT_MASK 0x00000100
    #define SPDIF_TX_MIPS_INT_MASK_INT_SHIFT 8
#define  SPDIF_TX_NUM 0x1630
    #define SPDIF_TX_NUM_NUM_MASK 0xFFFFFFFF
    #define SPDIF_TX_NUM_NUM_SHIFT 0
#define  SPDIF_TX_PREAMBLE 0x1628
    #define SPDIF_TX_PREAMBLE_B_MASK 0x0000000F
    #define SPDIF_TX_PREAMBLE_B_SHIFT 0
    #define SPDIF_TX_PREAMBLE_M_MASK 0x000000F0
    #define SPDIF_TX_PREAMBLE_M_SHIFT 4
    #define SPDIF_TX_PREAMBLE_W_MASK 0x00000F00
    #define SPDIF_TX_PREAMBLE_W_SHIFT 8
#define  SPI_CFG 0x10AC
    #define HOLD_EN_MASK 0x00000001
    #define HOLD_EN_SHIFT 0
    #define XFER_SIZE_MASK 0x00000006
    #define XFER_SIZE_SHIFT 1
    #define CAP_EDGE_MASK 0x00000008
    #define CAP_EDGE_SHIFT 3
    #define RATE_SEL_MASK 0x00000030
    #define RATE_SEL_SHIFT 4
#define  SPI_RDAT 0x10B4
    #define SPI_RDAT_MASK 0xFFFFFFFF
    #define SPI_RDAT_SHIFT 0
#define  SPI_STATUS 0x10B8
    #define SPI_BUSY_MASK 0x00000001
    #define SPI_BUSY_SHIFT 0
#define  SPI_WDAT 0x10B0
    #define SPI_WDAT_MASK 0xFFFFFFFF
    #define SPI_WDAT_SHIFT 0
#define  SYNC_DET_CRC0 0x6010
    #define SYNC_DET_CRC0_DATA_MASK 0x000000FF
    #define SYNC_DET_CRC0_DATA_SHIFT 0
#define  SYNC_DET_CRC1 0x6014
    #define SYNC_DET_CRC1_DATA_MASK 0x000000FF
    #define SYNC_DET_CRC1_DATA_SHIFT 0
#define  SYNC_DET_CTRL 0x6000
    #define PCK_LENGTH_TS0_MASK 0x00000001
    #define PCK_LENGTH_TS0_SHIFT 0
    #define PCK_LENGTH_TS1_MASK 0x00000002
    #define PCK_LENGTH_TS1_SHIFT 1
    #define SER_PAR_SEL0_MASK 0x00000100
    #define SER_PAR_SEL0_SHIFT 8
    #define DIRECTV_MODE0_MASK 0x00001000
    #define DIRECTV_MODE0_SHIFT 12
    #define DIRECTV_MODE1_MASK 0x00002000
    #define DIRECTV_MODE1_SHIFT 13
    #define PARTIAL_TS0_MASK 0x00004000
    #define PARTIAL_TS0_SHIFT 14
    #define PARTIAL_TS1_MASK 0x00008000
    #define PARTIAL_TS1_SHIFT 15
    #define USE_SYNCBIT0_MASK 0x00010000
    #define USE_SYNCBIT0_SHIFT 16
    #define USE_SYNCBIT1_MASK 0x00020000
    #define USE_SYNCBIT1_SHIFT 17
    #define SRC_INPUT0_EN_MASK 0x01000000
    #define SRC_INPUT0_EN_SHIFT 24
    #define SRC_INPUT1_EN_MASK 0x02000000
    #define SRC_INPUT1_EN_SHIFT 25
#define  SYNC_DET_EDGE_RST_CTRL 0x6008
    #define OF_AUTORST_DIS_MASK 0x00000003
    #define OF_AUTORST_DIS_SHIFT 0
    #define VAL_ACTIVE_HIGH_MASK 0x00000300
    #define VAL_ACTIVE_HIGH_SHIFT 8
    #define USE_NEGEDGE_MASK 0x03000000
    #define USE_NEGEDGE_SHIFT 24
#define  SYNC_DET_LOCK_SRCH 0x6030
    #define SYNC_DET_LOCK_SRCH_LOCK_MASK 0x0000000F
    #define SYNC_DET_LOCK_SRCH_LOCK_SHIFT 0
    #define SRCH_MASK 0x00000F00
    #define SRCH_SHIFT 8
#define  SYNC_DET_POD_CTRL 0x600C
    #define DROP_NULL0_MASK 0x00000100
    #define DROP_NULL0_SHIFT 8
    #define DROP_NULL1_MASK 0x00000200
    #define DROP_NULL1_SHIFT 9
#define  SYNC_DET_STATUS 0x6004
    #define SYNCMODE0_MASK 0x00000001
    #define SYNCMODE0_SHIFT 0
    #define SYNCMODE1_MASK 0x00000002
    #define SYNCMODE1_SHIFT 1
#define  SYS_FRM_CNT 0x6138
    #define SYS_FRM_CNT_FRM_CNT_MASK 0xFFFFFFFF
    #define SYS_FRM_CNT_FRM_CNT_SHIFT 0
#define  SYS_FRM_CNT_CTRL 0x613C
    #define SYS_FRM_CNT_CTRL_ENABLE_MASK 0x00000001
    #define SYS_FRM_CNT_CTRL_ENABLE_SHIFT 0
#define  SYS_RTP_TIMERH 0x6134
    #define RTP_DATA_U_MASK 0x00000001
    #define RTP_DATA_U_SHIFT 0
#define  SYS_RTP_TIMERL 0x6130
    #define RTP_DATA_L_MASK 0xFFFFFFFF
    #define RTP_DATA_L_SHIFT 0
#define  TSD_CHANNEL_CTRL 0x6150
    #define CH0_MSTR_EN_MASK 0x00000001
    #define CH0_MSTR_EN_SHIFT 0
    #define CH1_MSTR_EN_MASK 0x00000002
    #define CH1_MSTR_EN_SHIFT 1
    #define CH2_MSTR_EN_MASK 0x00000004
    #define CH2_MSTR_EN_SHIFT 2
    #define CH3_MSTR_EN_MASK 0x00000008
    #define CH3_MSTR_EN_SHIFT 3
    #define CH4_MSTR_EN_MASK 0x00000010
    #define CH4_MSTR_EN_SHIFT 4
    #define CH5_MSTR_EN_MASK 0x00000020
    #define CH5_MSTR_EN_SHIFT 5
    #define CH6_MSTR_EN_MASK 0x00000040
    #define CH6_MSTR_EN_SHIFT 6
    #define CH7_MSTR_EN_MASK 0x00000080
    #define CH7_MSTR_EN_SHIFT 7
    #define CH8_MSTR_EN_MASK 0x00000100
    #define CH8_MSTR_EN_SHIFT 8
    #define CH9_MSTR_EN_MASK 0x00000200
    #define CH9_MSTR_EN_SHIFT 9
    #define CH10_MSTR_EN_MASK 0x00000400
    #define CH10_MSTR_EN_SHIFT 10
    #define CH11_MSTR_EN_MASK 0x00000800
    #define CH11_MSTR_EN_SHIFT 11
    #define CH12_MSTR_EN_MASK 0x00001000
    #define CH12_MSTR_EN_SHIFT 12
    #define CH13_MSTR_EN_MASK 0x00002000
    #define CH13_MSTR_EN_SHIFT 13
    #define CH14_MSTR_EN_MASK 0x00004000
    #define CH14_MSTR_EN_SHIFT 14
    #define CH15_MSTR_EN_MASK 0x00008000
    #define CH15_MSTR_EN_SHIFT 15
    #define CH16_MSTR_EN_MASK 0x00010000
    #define CH16_MSTR_EN_SHIFT 16
    #define CH17_MSTR_EN_MASK 0x00020000
    #define CH17_MSTR_EN_SHIFT 17
    #define CH18_MSTR_EN_MASK 0x00040000
    #define CH18_MSTR_EN_SHIFT 18
    #define CH19_MSTR_EN_MASK 0x00080000
    #define CH19_MSTR_EN_SHIFT 19
    #define CH20_MSTR_EN_MASK 0x00100000
    #define CH20_MSTR_EN_SHIFT 20
    #define CH21_MSTR_EN_MASK 0x00200000
    #define CH21_MSTR_EN_SHIFT 21
    #define CH22_MSTR_EN_MASK 0x00400000
    #define CH22_MSTR_EN_SHIFT 22
    #define CH23_MSTR_EN_MASK 0x00800000
    #define CH23_MSTR_EN_SHIFT 23
    #define CH24_MSTR_EN_MASK 0x01000000
    #define CH24_MSTR_EN_SHIFT 24
    #define CH25_MSTR_EN_MASK 0x02000000
    #define CH25_MSTR_EN_SHIFT 25
    #define CH26_MSTR_EN_MASK 0x04000000
    #define CH26_MSTR_EN_SHIFT 26
    #define CH27_MSTR_EN_MASK 0x08000000
    #define CH27_MSTR_EN_SHIFT 27
    #define CH28_MSTR_EN_MASK 0x10000000
    #define CH28_MSTR_EN_SHIFT 28
    #define CH29_MSTR_EN_MASK 0x20000000
    #define CH29_MSTR_EN_SHIFT 29
    #define CH30_MSTR_EN_MASK 0x40000000
    #define CH30_MSTR_EN_SHIFT 30
    #define CH31_MSTR_EN_MASK 0x80000000
    #define CH31_MSTR_EN_SHIFT 31
#define  TSD_CHANNEL_CTRL_1 0x62E8
    #define CH32_MSTR_EN_MASK 0x00000001
    #define CH32_MSTR_EN_SHIFT 0
    #define CH33_MSTR_EN_MASK 0x00000002
    #define CH33_MSTR_EN_SHIFT 1
    #define CH34_MSTR_EN_MASK 0x00000004
    #define CH34_MSTR_EN_SHIFT 2
    #define CH35_MSTR_EN_MASK 0x00000008
    #define CH35_MSTR_EN_SHIFT 3
    #define CH36_MSTR_EN_MASK 0x00000010
    #define CH36_MSTR_EN_SHIFT 4
    #define CH37_MSTR_EN_MASK 0x00000020
    #define CH37_MSTR_EN_SHIFT 5
    #define CH38_MSTR_EN_MASK 0x00000040
    #define CH38_MSTR_EN_SHIFT 6
    #define CH39_MSTR_EN_MASK 0x00000080
    #define CH39_MSTR_EN_SHIFT 7
    #define CH40_MSTR_EN_MASK 0x00000100
    #define CH40_MSTR_EN_SHIFT 8
    #define CH41_MSTR_EN_MASK 0x00000200
    #define CH41_MSTR_EN_SHIFT 9
    #define CH42_MSTR_EN_MASK 0x00000400
    #define CH42_MSTR_EN_SHIFT 10
    #define CH43_MSTR_EN_MASK 0x00000800
    #define CH43_MSTR_EN_SHIFT 11
    #define CH44_MSTR_EN_MASK 0x00001000
    #define CH44_MSTR_EN_SHIFT 12
    #define CH45_MSTR_EN_MASK 0x00002000
    #define CH45_MSTR_EN_SHIFT 13
    #define CH46_MSTR_EN_MASK 0x00004000
    #define CH46_MSTR_EN_SHIFT 14
    #define CH47_MSTR_EN_MASK 0x00008000
    #define CH47_MSTR_EN_SHIFT 15
    #define CH48_MSTR_EN_MASK 0x00010000
    #define CH48_MSTR_EN_SHIFT 16
    #define CH49_MSTR_EN_MASK 0x00020000
    #define CH49_MSTR_EN_SHIFT 17
    #define CH50_MSTR_EN_MASK 0x00040000
    #define CH50_MSTR_EN_SHIFT 18
    #define CH51_MSTR_EN_MASK 0x00080000
    #define CH51_MSTR_EN_SHIFT 19
    #define CH52_MSTR_EN_MASK 0x00100000
    #define CH52_MSTR_EN_SHIFT 20
    #define CH53_MSTR_EN_MASK 0x00200000
    #define CH53_MSTR_EN_SHIFT 21
    #define CH54_MSTR_EN_MASK 0x00400000
    #define CH54_MSTR_EN_SHIFT 22
    #define CH55_MSTR_EN_MASK 0x00800000
    #define CH55_MSTR_EN_SHIFT 23
    #define CH56_MSTR_EN_MASK 0x01000000
    #define CH56_MSTR_EN_SHIFT 24
    #define CH57_MSTR_EN_MASK 0x02000000
    #define CH57_MSTR_EN_SHIFT 25
    #define CH58_MSTR_EN_MASK 0x04000000
    #define CH58_MSTR_EN_SHIFT 26
    #define CH59_MSTR_EN_MASK 0x08000000
    #define CH59_MSTR_EN_SHIFT 27
    #define CH60_MSTR_EN_MASK 0x10000000
    #define CH60_MSTR_EN_SHIFT 28
    #define CH61_MSTR_EN_MASK 0x20000000
    #define CH61_MSTR_EN_SHIFT 29
    #define CH62_MSTR_EN_MASK 0x40000000
    #define CH62_MSTR_EN_SHIFT 30
    #define CH63_MSTR_EN_MASK 0x80000000
    #define CH63_MSTR_EN_SHIFT 31
#define  TSD_DEBUG_REG 0x63E8
    #define TSD_DEBUG_REG_DATA_MASK 0x000FFFFF
    #define TSD_DEBUG_REG_DATA_SHIFT 0
#define  TSD_DEN 0x6144
    #define TSD_DEN_DEN_MASK 0xFFFFFFFF
    #define TSD_DEN_DEN_SHIFT 0
#define  TSD_DUMMY_REG 0x63FC
    #define TSD_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define TSD_DUMMY_REG_DATA_SHIFT 0
#define  TSD_DVO1_PS_MODE_STATUS 0x63F4
    #define TSD_DVO1_PS_MODE_STATUS_BYTE_COUNT_MASK 0x00000FFF
    #define TSD_DVO1_PS_MODE_STATUS_BYTE_COUNT_SHIFT 0
    #define TSD_DVO1_PS_MODE_STATUS_SER_COUNT_MASK 0x00007000
    #define TSD_DVO1_PS_MODE_STATUS_SER_COUNT_SHIFT 12
#define  TSD_GENLOCK_CTRL 0x609C
    #define PCR_TOGGLE_SEL_MASK 0x00000003
    #define PCR_TOGGLE_SEL_SHIFT 0
#define  TSD_GENLOCK_LOWER 0x614C
    #define TSD_GENLOCK_LOWER_GENLOCK_L_MASK 0xFFFFFFFF
    #define TSD_GENLOCK_LOWER_GENLOCK_L_SHIFT 0
#define  TSD_GENLOCK_UPPER 0x6148
    #define TSD_GENLOCK_UPPER_GENLOCK_U_MASK 0x000003FF
    #define TSD_GENLOCK_UPPER_GENLOCK_U_SHIFT 0
#define  TSD_HOST_INT_MASK0 0x6164
    #define TSD_HOST_INT_MASK0_INT_EN_PFBUF_OF0_MASK 0x00000001
    #define TSD_HOST_INT_MASK0_INT_EN_PFBUF_OF0_SHIFT 0
    #define TSD_HOST_INT_MASK0_INT_EN_PFBUF_OF1_MASK 0x00000002
    #define TSD_HOST_INT_MASK0_INT_EN_PFBUF_OF1_SHIFT 1
    #define TSD_HOST_INT_MASK0_INT_EN_TEI_ERROR_MASK 0x00000100
    #define TSD_HOST_INT_MASK0_INT_EN_TEI_ERROR_SHIFT 8
#define  TSD_HOST_INT_MASK1 0x67B4
    #define TSD_HOST_INT_MASK1_INT_EN_RING0_ERR_MASK 0x00000001
    #define TSD_HOST_INT_MASK1_INT_EN_RING0_ERR_SHIFT 0
    #define TSD_HOST_INT_MASK1_INT_EN_RING1_ERR_MASK 0x00000002
    #define TSD_HOST_INT_MASK1_INT_EN_RING1_ERR_SHIFT 1
    #define TSD_HOST_INT_MASK1_INT_EN_RING2_ERR_MASK 0x00000004
    #define TSD_HOST_INT_MASK1_INT_EN_RING2_ERR_SHIFT 2
    #define TSD_HOST_INT_MASK1_INT_EN_RING3_ERR_MASK 0x00000008
    #define TSD_HOST_INT_MASK1_INT_EN_RING3_ERR_SHIFT 3
    #define TSD_HOST_INT_MASK1_INT_EN_RING4_ERR_MASK 0x00000010
    #define TSD_HOST_INT_MASK1_INT_EN_RING4_ERR_SHIFT 4
    #define TSD_HOST_INT_MASK1_INT_EN_RING5_ERR_MASK 0x00000020
    #define TSD_HOST_INT_MASK1_INT_EN_RING5_ERR_SHIFT 5
    #define TSD_HOST_INT_MASK1_INT_EN_RING6_ERR_MASK 0x00000040
    #define TSD_HOST_INT_MASK1_INT_EN_RING6_ERR_SHIFT 6
    #define TSD_HOST_INT_MASK1_INT_EN_RING7_ERR_MASK 0x00000080
    #define TSD_HOST_INT_MASK1_INT_EN_RING7_ERR_SHIFT 7
    #define TSD_HOST_INT_MASK1_INT_EN_RING8_ERR_MASK 0x00000100
    #define TSD_HOST_INT_MASK1_INT_EN_RING8_ERR_SHIFT 8
    #define TSD_HOST_INT_MASK1_INT_EN_RING9_ERR_MASK 0x00000200
    #define TSD_HOST_INT_MASK1_INT_EN_RING9_ERR_SHIFT 9
    #define TSD_HOST_INT_MASK1_INT_EN_RING10_ERR_MASK 0x00000400
    #define TSD_HOST_INT_MASK1_INT_EN_RING10_ERR_SHIFT 10
    #define TSD_HOST_INT_MASK1_INT_EN_RING11_ERR_MASK 0x00000800
    #define TSD_HOST_INT_MASK1_INT_EN_RING11_ERR_SHIFT 11
    #define TSD_HOST_INT_MASK1_INT_EN_RING12_ERR_MASK 0x00001000
    #define TSD_HOST_INT_MASK1_INT_EN_RING12_ERR_SHIFT 12
    #define TSD_HOST_INT_MASK1_INT_EN_RING13_ERR_MASK 0x00002000
    #define TSD_HOST_INT_MASK1_INT_EN_RING13_ERR_SHIFT 13
    #define TSD_HOST_INT_MASK1_INT_EN_RING14_ERR_MASK 0x00004000
    #define TSD_HOST_INT_MASK1_INT_EN_RING14_ERR_SHIFT 14
    #define TSD_HOST_INT_MASK1_INT_EN_RING15_ERR_MASK 0x00008000
    #define TSD_HOST_INT_MASK1_INT_EN_RING15_ERR_SHIFT 15
    #define TSD_HOST_INT_MASK1_INT_EN_RING16_ERR_MASK 0x00010000
    #define TSD_HOST_INT_MASK1_INT_EN_RING16_ERR_SHIFT 16
    #define TSD_HOST_INT_MASK1_INT_EN_RING17_ERR_MASK 0x00020000
    #define TSD_HOST_INT_MASK1_INT_EN_RING17_ERR_SHIFT 17
    #define TSD_HOST_INT_MASK1_INT_EN_RING18_ERR_MASK 0x00040000
    #define TSD_HOST_INT_MASK1_INT_EN_RING18_ERR_SHIFT 18
    #define TSD_HOST_INT_MASK1_INT_EN_RING19_ERR_MASK 0x00080000
    #define TSD_HOST_INT_MASK1_INT_EN_RING19_ERR_SHIFT 19
    #define TSD_HOST_INT_MASK1_INT_EN_RING20_ERR_MASK 0x00100000
    #define TSD_HOST_INT_MASK1_INT_EN_RING20_ERR_SHIFT 20
    #define TSD_HOST_INT_MASK1_INT_EN_RING21_ERR_MASK 0x00200000
    #define TSD_HOST_INT_MASK1_INT_EN_RING21_ERR_SHIFT 21
    #define TSD_HOST_INT_MASK1_INT_EN_RING22_ERR_MASK 0x00400000
    #define TSD_HOST_INT_MASK1_INT_EN_RING22_ERR_SHIFT 22
    #define TSD_HOST_INT_MASK1_INT_EN_RING23_ERR_MASK 0x00800000
    #define TSD_HOST_INT_MASK1_INT_EN_RING23_ERR_SHIFT 23
    #define TSD_HOST_INT_MASK1_INT_EN_RING24_ERR_MASK 0x01000000
    #define TSD_HOST_INT_MASK1_INT_EN_RING24_ERR_SHIFT 24
    #define TSD_HOST_INT_MASK1_INT_EN_RING25_ERR_MASK 0x02000000
    #define TSD_HOST_INT_MASK1_INT_EN_RING25_ERR_SHIFT 25
    #define TSD_HOST_INT_MASK1_INT_EN_RING26_ERR_MASK 0x04000000
    #define TSD_HOST_INT_MASK1_INT_EN_RING26_ERR_SHIFT 26
    #define TSD_HOST_INT_MASK1_INT_EN_RING27_ERR_MASK 0x08000000
    #define TSD_HOST_INT_MASK1_INT_EN_RING27_ERR_SHIFT 27
    #define TSD_HOST_INT_MASK1_INT_EN_RING28_ERR_MASK 0x10000000
    #define TSD_HOST_INT_MASK1_INT_EN_RING28_ERR_SHIFT 28
    #define TSD_HOST_INT_MASK1_INT_EN_RING29_ERR_MASK 0x20000000
    #define TSD_HOST_INT_MASK1_INT_EN_RING29_ERR_SHIFT 29
    #define TSD_HOST_INT_MASK1_INT_EN_RING30_ERR_MASK 0x40000000
    #define TSD_HOST_INT_MASK1_INT_EN_RING30_ERR_SHIFT 30
    #define TSD_HOST_INT_MASK1_INT_EN_RING31_ERR_MASK 0x80000000
    #define TSD_HOST_INT_MASK1_INT_EN_RING31_ERR_SHIFT 31
#define  TSD_HOST_INT_MASK1_1 0x6738
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING32_ERR_MASK 0x00000001
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING32_ERR_SHIFT 0
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING33_ERR_MASK 0x00000002
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING33_ERR_SHIFT 1
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING34_ERR_MASK 0x00000004
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING34_ERR_SHIFT 2
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING35_ERR_MASK 0x00000008
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING35_ERR_SHIFT 3
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING36_ERR_MASK 0x00000010
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING36_ERR_SHIFT 4
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING37_ERR_MASK 0x00000020
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING37_ERR_SHIFT 5
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING38_ERR_MASK 0x00000040
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING38_ERR_SHIFT 6
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING39_ERR_MASK 0x00000080
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING39_ERR_SHIFT 7
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING40_ERR_MASK 0x00000100
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING40_ERR_SHIFT 8
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING41_ERR_MASK 0x00000200
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING41_ERR_SHIFT 9
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING42_ERR_MASK 0x00000400
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING42_ERR_SHIFT 10
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING43_ERR_MASK 0x00000800
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING43_ERR_SHIFT 11
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING44_ERR_MASK 0x00001000
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING44_ERR_SHIFT 12
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING45_ERR_MASK 0x00002000
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING45_ERR_SHIFT 13
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING46_ERR_MASK 0x00004000
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING46_ERR_SHIFT 14
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING47_ERR_MASK 0x00008000
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING47_ERR_SHIFT 15
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING48_ERR_MASK 0x00010000
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING48_ERR_SHIFT 16
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING49_ERR_MASK 0x00020000
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING49_ERR_SHIFT 17
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING50_ERR_MASK 0x00040000
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING50_ERR_SHIFT 18
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING51_ERR_MASK 0x00080000
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING51_ERR_SHIFT 19
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING52_ERR_MASK 0x00100000
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING52_ERR_SHIFT 20
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING53_ERR_MASK 0x00200000
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING53_ERR_SHIFT 21
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING54_ERR_MASK 0x00400000
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING54_ERR_SHIFT 22
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING55_ERR_MASK 0x00800000
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING55_ERR_SHIFT 23
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING56_ERR_MASK 0x01000000
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING56_ERR_SHIFT 24
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING57_ERR_MASK 0x02000000
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING57_ERR_SHIFT 25
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING58_ERR_MASK 0x04000000
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING58_ERR_SHIFT 26
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING59_ERR_MASK 0x08000000
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING59_ERR_SHIFT 27
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING60_ERR_MASK 0x10000000
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING60_ERR_SHIFT 28
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING61_ERR_MASK 0x20000000
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING61_ERR_SHIFT 29
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING62_ERR_MASK 0x40000000
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING62_ERR_SHIFT 30
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING63_ERR_MASK 0x80000000
    #define TSD_HOST_INT_MASK1_1_INT_EN_RING63_ERR_SHIFT 31
#define  TSD_HOST_INT_MASK4 0x67D8
    #define TSD_HOST_INT_MASK4_INT_EN_RING0_DATA_MASK 0x00000001
    #define TSD_HOST_INT_MASK4_INT_EN_RING0_DATA_SHIFT 0
    #define TSD_HOST_INT_MASK4_INT_EN_RING1_DATA_MASK 0x00000002
    #define TSD_HOST_INT_MASK4_INT_EN_RING1_DATA_SHIFT 1
    #define TSD_HOST_INT_MASK4_INT_EN_RING2_DATA_MASK 0x00000004
    #define TSD_HOST_INT_MASK4_INT_EN_RING2_DATA_SHIFT 2
    #define TSD_HOST_INT_MASK4_INT_EN_RING3_DATA_MASK 0x00000008
    #define TSD_HOST_INT_MASK4_INT_EN_RING3_DATA_SHIFT 3
    #define TSD_HOST_INT_MASK4_INT_EN_RING4_DATA_MASK 0x00000010
    #define TSD_HOST_INT_MASK4_INT_EN_RING4_DATA_SHIFT 4
    #define TSD_HOST_INT_MASK4_INT_EN_RING5_DATA_MASK 0x00000020
    #define TSD_HOST_INT_MASK4_INT_EN_RING5_DATA_SHIFT 5
    #define TSD_HOST_INT_MASK4_INT_EN_RING6_DATA_MASK 0x00000040
    #define TSD_HOST_INT_MASK4_INT_EN_RING6_DATA_SHIFT 6
    #define TSD_HOST_INT_MASK4_INT_EN_RING7_DATA_MASK 0x00000080
    #define TSD_HOST_INT_MASK4_INT_EN_RING7_DATA_SHIFT 7
    #define TSD_HOST_INT_MASK4_INT_EN_RING8_DATA_MASK 0x00000100
    #define TSD_HOST_INT_MASK4_INT_EN_RING8_DATA_SHIFT 8
    #define TSD_HOST_INT_MASK4_INT_EN_RING9_DATA_MASK 0x00000200
    #define TSD_HOST_INT_MASK4_INT_EN_RING9_DATA_SHIFT 9
    #define TSD_HOST_INT_MASK4_INT_EN_RING10_DATA_MASK 0x00000400
    #define TSD_HOST_INT_MASK4_INT_EN_RING10_DATA_SHIFT 10
    #define TSD_HOST_INT_MASK4_INT_EN_RING11_DATA_MASK 0x00000800
    #define TSD_HOST_INT_MASK4_INT_EN_RING11_DATA_SHIFT 11
    #define TSD_HOST_INT_MASK4_INT_EN_RING12_DATA_MASK 0x00001000
    #define TSD_HOST_INT_MASK4_INT_EN_RING12_DATA_SHIFT 12
    #define TSD_HOST_INT_MASK4_INT_EN_RING13_DATA_MASK 0x00002000
    #define TSD_HOST_INT_MASK4_INT_EN_RING13_DATA_SHIFT 13
    #define TSD_HOST_INT_MASK4_INT_EN_RING14_DATA_MASK 0x00004000
    #define TSD_HOST_INT_MASK4_INT_EN_RING14_DATA_SHIFT 14
    #define TSD_HOST_INT_MASK4_INT_EN_RING15_DATA_MASK 0x00008000
    #define TSD_HOST_INT_MASK4_INT_EN_RING15_DATA_SHIFT 15
    #define TSD_HOST_INT_MASK4_INT_EN_RING16_DATA_MASK 0x00010000
    #define TSD_HOST_INT_MASK4_INT_EN_RING16_DATA_SHIFT 16
    #define TSD_HOST_INT_MASK4_INT_EN_RING17_DATA_MASK 0x00020000
    #define TSD_HOST_INT_MASK4_INT_EN_RING17_DATA_SHIFT 17
    #define TSD_HOST_INT_MASK4_INT_EN_RING18_DATA_MASK 0x00040000
    #define TSD_HOST_INT_MASK4_INT_EN_RING18_DATA_SHIFT 18
    #define TSD_HOST_INT_MASK4_INT_EN_RING19_DATA_MASK 0x00080000
    #define TSD_HOST_INT_MASK4_INT_EN_RING19_DATA_SHIFT 19
    #define TSD_HOST_INT_MASK4_INT_EN_RING20_DATA_MASK 0x00100000
    #define TSD_HOST_INT_MASK4_INT_EN_RING20_DATA_SHIFT 20
    #define TSD_HOST_INT_MASK4_INT_EN_RING21_DATA_MASK 0x00200000
    #define TSD_HOST_INT_MASK4_INT_EN_RING21_DATA_SHIFT 21
    #define TSD_HOST_INT_MASK4_INT_EN_RING22_DATA_MASK 0x00400000
    #define TSD_HOST_INT_MASK4_INT_EN_RING22_DATA_SHIFT 22
    #define TSD_HOST_INT_MASK4_INT_EN_RING23_DATA_MASK 0x00800000
    #define TSD_HOST_INT_MASK4_INT_EN_RING23_DATA_SHIFT 23
    #define TSD_HOST_INT_MASK4_INT_EN_RING24_DATA_MASK 0x01000000
    #define TSD_HOST_INT_MASK4_INT_EN_RING24_DATA_SHIFT 24
    #define TSD_HOST_INT_MASK4_INT_EN_RING25_DATA_MASK 0x02000000
    #define TSD_HOST_INT_MASK4_INT_EN_RING25_DATA_SHIFT 25
    #define TSD_HOST_INT_MASK4_INT_EN_RING26_DATA_MASK 0x04000000
    #define TSD_HOST_INT_MASK4_INT_EN_RING26_DATA_SHIFT 26
    #define TSD_HOST_INT_MASK4_INT_EN_RING27_DATA_MASK 0x08000000
    #define TSD_HOST_INT_MASK4_INT_EN_RING27_DATA_SHIFT 27
    #define TSD_HOST_INT_MASK4_INT_EN_RING28_DATA_MASK 0x10000000
    #define TSD_HOST_INT_MASK4_INT_EN_RING28_DATA_SHIFT 28
    #define TSD_HOST_INT_MASK4_INT_EN_RING29_DATA_MASK 0x20000000
    #define TSD_HOST_INT_MASK4_INT_EN_RING29_DATA_SHIFT 29
    #define TSD_HOST_INT_MASK4_INT_EN_RING30_DATA_MASK 0x40000000
    #define TSD_HOST_INT_MASK4_INT_EN_RING30_DATA_SHIFT 30
    #define TSD_HOST_INT_MASK4_INT_EN_RING31_DATA_MASK 0x80000000
    #define TSD_HOST_INT_MASK4_INT_EN_RING31_DATA_SHIFT 31
#define  TSD_HOST_INT_MASK4_1 0x6744
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING32_DATA_MASK 0x00000001
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING32_DATA_SHIFT 0
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING33_DATA_MASK 0x00000002
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING33_DATA_SHIFT 1
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING34_DATA_MASK 0x00000004
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING34_DATA_SHIFT 2
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING35_DATA_MASK 0x00000008
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING35_DATA_SHIFT 3
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING36_DATA_MASK 0x00000010
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING36_DATA_SHIFT 4
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING37_DATA_MASK 0x00000020
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING37_DATA_SHIFT 5
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING38_DATA_MASK 0x00000040
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING38_DATA_SHIFT 6
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING39_DATA_MASK 0x00000080
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING39_DATA_SHIFT 7
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING40_DATA_MASK 0x00000100
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING40_DATA_SHIFT 8
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING41_DATA_MASK 0x00000200
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING41_DATA_SHIFT 9
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING42_DATA_MASK 0x00000400
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING42_DATA_SHIFT 10
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING43_DATA_MASK 0x00000800
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING43_DATA_SHIFT 11
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING44_DATA_MASK 0x00001000
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING44_DATA_SHIFT 12
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING45_DATA_MASK 0x00002000
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING45_DATA_SHIFT 13
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING46_DATA_MASK 0x00004000
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING46_DATA_SHIFT 14
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING47_DATA_MASK 0x00008000
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING47_DATA_SHIFT 15
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING48_DATA_MASK 0x00010000
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING48_DATA_SHIFT 16
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING49_DATA_MASK 0x00020000
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING49_DATA_SHIFT 17
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING50_DATA_MASK 0x00040000
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING50_DATA_SHIFT 18
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING51_DATA_MASK 0x00080000
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING51_DATA_SHIFT 19
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING52_DATA_MASK 0x00100000
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING52_DATA_SHIFT 20
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING53_DATA_MASK 0x00200000
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING53_DATA_SHIFT 21
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING54_DATA_MASK 0x00400000
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING54_DATA_SHIFT 22
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING55_DATA_MASK 0x00800000
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING55_DATA_SHIFT 23
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING56_DATA_MASK 0x01000000
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING56_DATA_SHIFT 24
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING57_DATA_MASK 0x02000000
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING57_DATA_SHIFT 25
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING58_DATA_MASK 0x04000000
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING58_DATA_SHIFT 26
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING59_DATA_MASK 0x08000000
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING59_DATA_SHIFT 27
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING60_DATA_MASK 0x10000000
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING60_DATA_SHIFT 28
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING61_DATA_MASK 0x20000000
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING61_DATA_SHIFT 29
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING62_DATA_MASK 0x40000000
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING62_DATA_SHIFT 30
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING63_DATA_MASK 0x80000000
    #define TSD_HOST_INT_MASK4_1_INT_EN_RING63_DATA_SHIFT 31
#define  TSD_INT_STATUS0 0x6160
    #define PFBUF_OF0_MASK 0x00000001
    #define PFBUF_OF0_SHIFT 0
    #define PFBUF_OF1_MASK 0x00000002
    #define PFBUF_OF1_SHIFT 1
    #define TEI_ERROR_MASK 0x00000100
    #define TEI_ERROR_SHIFT 8
#define  TSD_INT_STATUS1 0x67B0
    #define RING0_ERR_MASK 0x00000001
    #define RING0_ERR_SHIFT 0
    #define RING1_ERR_MASK 0x00000002
    #define RING1_ERR_SHIFT 1
    #define RING2_ERR_MASK 0x00000004
    #define RING2_ERR_SHIFT 2
    #define RING3_ERR_MASK 0x00000008
    #define RING3_ERR_SHIFT 3
    #define RING4_ERR_MASK 0x00000010
    #define RING4_ERR_SHIFT 4
    #define RING5_ERR_MASK 0x00000020
    #define RING5_ERR_SHIFT 5
    #define RING6_ERR_MASK 0x00000040
    #define RING6_ERR_SHIFT 6
    #define RING7_ERR_MASK 0x00000080
    #define RING7_ERR_SHIFT 7
    #define RING8_ERR_MASK 0x00000100
    #define RING8_ERR_SHIFT 8
    #define RING9_ERR_MASK 0x00000200
    #define RING9_ERR_SHIFT 9
    #define RING10_ERR_MASK 0x00000400
    #define RING10_ERR_SHIFT 10
    #define RING11_ERR_MASK 0x00000800
    #define RING11_ERR_SHIFT 11
    #define RING12_ERR_MASK 0x00001000
    #define RING12_ERR_SHIFT 12
    #define RING13_ERR_MASK 0x00002000
    #define RING13_ERR_SHIFT 13
    #define RING14_ERR_MASK 0x00004000
    #define RING14_ERR_SHIFT 14
    #define RING15_ERR_MASK 0x00008000
    #define RING15_ERR_SHIFT 15
    #define RING16_ERR_MASK 0x00010000
    #define RING16_ERR_SHIFT 16
    #define RING17_ERR_MASK 0x00020000
    #define RING17_ERR_SHIFT 17
    #define RING18_ERR_MASK 0x00040000
    #define RING18_ERR_SHIFT 18
    #define RING19_ERR_MASK 0x00080000
    #define RING19_ERR_SHIFT 19
    #define RING20_ERR_MASK 0x00100000
    #define RING20_ERR_SHIFT 20
    #define RING21_ERR_MASK 0x00200000
    #define RING21_ERR_SHIFT 21
    #define RING22_ERR_MASK 0x00400000
    #define RING22_ERR_SHIFT 22
    #define RING23_ERR_MASK 0x00800000
    #define RING23_ERR_SHIFT 23
    #define RING24_ERR_MASK 0x01000000
    #define RING24_ERR_SHIFT 24
    #define RING25_ERR_MASK 0x02000000
    #define RING25_ERR_SHIFT 25
    #define RING26_ERR_MASK 0x04000000
    #define RING26_ERR_SHIFT 26
    #define RING27_ERR_MASK 0x08000000
    #define RING27_ERR_SHIFT 27
    #define RING28_ERR_MASK 0x10000000
    #define RING28_ERR_SHIFT 28
    #define RING29_ERR_MASK 0x20000000
    #define RING29_ERR_SHIFT 29
    #define RING30_ERR_MASK 0x40000000
    #define RING30_ERR_SHIFT 30
    #define RING31_ERR_MASK 0x80000000
    #define RING31_ERR_SHIFT 31
#define  TSD_INT_STATUS1_1 0x6734
    #define RING32_ERR_MASK 0x00000001
    #define RING32_ERR_SHIFT 0
    #define RING33_ERR_MASK 0x00000002
    #define RING33_ERR_SHIFT 1
    #define RING34_ERR_MASK 0x00000004
    #define RING34_ERR_SHIFT 2
    #define RING35_ERR_MASK 0x00000008
    #define RING35_ERR_SHIFT 3
    #define RING36_ERR_MASK 0x00000010
    #define RING36_ERR_SHIFT 4
    #define RING37_ERR_MASK 0x00000020
    #define RING37_ERR_SHIFT 5
    #define RING38_ERR_MASK 0x00000040
    #define RING38_ERR_SHIFT 6
    #define RING39_ERR_MASK 0x00000080
    #define RING39_ERR_SHIFT 7
    #define RING40_ERR_MASK 0x00000100
    #define RING40_ERR_SHIFT 8
    #define RING41_ERR_MASK 0x00000200
    #define RING41_ERR_SHIFT 9
    #define RING42_ERR_MASK 0x00000400
    #define RING42_ERR_SHIFT 10
    #define RING43_ERR_MASK 0x00000800
    #define RING43_ERR_SHIFT 11
    #define RING44_ERR_MASK 0x00001000
    #define RING44_ERR_SHIFT 12
    #define RING45_ERR_MASK 0x00002000
    #define RING45_ERR_SHIFT 13
    #define RING46_ERR_MASK 0x00004000
    #define RING46_ERR_SHIFT 14
    #define RING47_ERR_MASK 0x00008000
    #define RING47_ERR_SHIFT 15
    #define RING48_ERR_MASK 0x00010000
    #define RING48_ERR_SHIFT 16
    #define RING49_ERR_MASK 0x00020000
    #define RING49_ERR_SHIFT 17
    #define RING50_ERR_MASK 0x00040000
    #define RING50_ERR_SHIFT 18
    #define RING51_ERR_MASK 0x00080000
    #define RING51_ERR_SHIFT 19
    #define RING52_ERR_MASK 0x00100000
    #define RING52_ERR_SHIFT 20
    #define RING53_ERR_MASK 0x00200000
    #define RING53_ERR_SHIFT 21
    #define RING54_ERR_MASK 0x00400000
    #define RING54_ERR_SHIFT 22
    #define RING55_ERR_MASK 0x00800000
    #define RING55_ERR_SHIFT 23
    #define RING56_ERR_MASK 0x01000000
    #define RING56_ERR_SHIFT 24
    #define RING57_ERR_MASK 0x02000000
    #define RING57_ERR_SHIFT 25
    #define RING58_ERR_MASK 0x04000000
    #define RING58_ERR_SHIFT 26
    #define RING59_ERR_MASK 0x08000000
    #define RING59_ERR_SHIFT 27
    #define RING60_ERR_MASK 0x10000000
    #define RING60_ERR_SHIFT 28
    #define RING61_ERR_MASK 0x20000000
    #define RING61_ERR_SHIFT 29
    #define RING62_ERR_MASK 0x40000000
    #define RING62_ERR_SHIFT 30
    #define RING63_ERR_MASK 0x80000000
    #define RING63_ERR_SHIFT 31
#define  TSD_INT_STATUS4 0x67D4
    #define RING0_DATA_MASK 0x00000001
    #define RING0_DATA_SHIFT 0
    #define RING1_DATA_MASK 0x00000002
    #define RING1_DATA_SHIFT 1
    #define RING2_DATA_MASK 0x00000004
    #define RING2_DATA_SHIFT 2
    #define RING3_DATA_MASK 0x00000008
    #define RING3_DATA_SHIFT 3
    #define RING4_DATA_MASK 0x00000010
    #define RING4_DATA_SHIFT 4
    #define RING5_DATA_MASK 0x00000020
    #define RING5_DATA_SHIFT 5
    #define RING6_DATA_MASK 0x00000040
    #define RING6_DATA_SHIFT 6
    #define RING7_DATA_MASK 0x00000080
    #define RING7_DATA_SHIFT 7
    #define RING8_DATA_MASK 0x00000100
    #define RING8_DATA_SHIFT 8
    #define RING9_DATA_MASK 0x00000200
    #define RING9_DATA_SHIFT 9
    #define RING10_DATA_MASK 0x00000400
    #define RING10_DATA_SHIFT 10
    #define RING11_DATA_MASK 0x00000800
    #define RING11_DATA_SHIFT 11
    #define RING12_DATA_MASK 0x00001000
    #define RING12_DATA_SHIFT 12
    #define RING13_DATA_MASK 0x00002000
    #define RING13_DATA_SHIFT 13
    #define RING14_DATA_MASK 0x00004000
    #define RING14_DATA_SHIFT 14
    #define RING15_DATA_MASK 0x00008000
    #define RING15_DATA_SHIFT 15
    #define RING16_DATA_MASK 0x00010000
    #define RING16_DATA_SHIFT 16
    #define RING17_DATA_MASK 0x00020000
    #define RING17_DATA_SHIFT 17
    #define RING18_DATA_MASK 0x00040000
    #define RING18_DATA_SHIFT 18
    #define RING19_DATA_MASK 0x00080000
    #define RING19_DATA_SHIFT 19
    #define RING20_DATA_MASK 0x00100000
    #define RING20_DATA_SHIFT 20
    #define RING21_DATA_MASK 0x00200000
    #define RING21_DATA_SHIFT 21
    #define RING22_DATA_MASK 0x00400000
    #define RING22_DATA_SHIFT 22
    #define RING23_DATA_MASK 0x00800000
    #define RING23_DATA_SHIFT 23
    #define RING24_DATA_MASK 0x01000000
    #define RING24_DATA_SHIFT 24
    #define RING25_DATA_MASK 0x02000000
    #define RING25_DATA_SHIFT 25
    #define RING26_DATA_MASK 0x04000000
    #define RING26_DATA_SHIFT 26
    #define RING27_DATA_MASK 0x08000000
    #define RING27_DATA_SHIFT 27
    #define RING28_DATA_MASK 0x10000000
    #define RING28_DATA_SHIFT 28
    #define RING29_DATA_MASK 0x20000000
    #define RING29_DATA_SHIFT 29
    #define RING30_DATA_MASK 0x40000000
    #define RING30_DATA_SHIFT 30
    #define RING31_DATA_MASK 0x80000000
    #define RING31_DATA_SHIFT 31
#define  TSD_INT_STATUS4_1 0x6740
    #define RING32_DATA_MASK 0x00000001
    #define RING32_DATA_SHIFT 0
    #define RING33_DATA_MASK 0x00000002
    #define RING33_DATA_SHIFT 1
    #define RING34_DATA_MASK 0x00000004
    #define RING34_DATA_SHIFT 2
    #define RING35_DATA_MASK 0x00000008
    #define RING35_DATA_SHIFT 3
    #define RING36_DATA_MASK 0x00000010
    #define RING36_DATA_SHIFT 4
    #define RING37_DATA_MASK 0x00000020
    #define RING37_DATA_SHIFT 5
    #define RING38_DATA_MASK 0x00000040
    #define RING38_DATA_SHIFT 6
    #define RING39_DATA_MASK 0x00000080
    #define RING39_DATA_SHIFT 7
    #define RING40_DATA_MASK 0x00000100
    #define RING40_DATA_SHIFT 8
    #define RING41_DATA_MASK 0x00000200
    #define RING41_DATA_SHIFT 9
    #define RING42_DATA_MASK 0x00000400
    #define RING42_DATA_SHIFT 10
    #define RING43_DATA_MASK 0x00000800
    #define RING43_DATA_SHIFT 11
    #define RING44_DATA_MASK 0x00001000
    #define RING44_DATA_SHIFT 12
    #define RING45_DATA_MASK 0x00002000
    #define RING45_DATA_SHIFT 13
    #define RING46_DATA_MASK 0x00004000
    #define RING46_DATA_SHIFT 14
    #define RING47_DATA_MASK 0x00008000
    #define RING47_DATA_SHIFT 15
    #define RING48_DATA_MASK 0x00010000
    #define RING48_DATA_SHIFT 16
    #define RING49_DATA_MASK 0x00020000
    #define RING49_DATA_SHIFT 17
    #define RING50_DATA_MASK 0x00040000
    #define RING50_DATA_SHIFT 18
    #define RING51_DATA_MASK 0x00080000
    #define RING51_DATA_SHIFT 19
    #define RING52_DATA_MASK 0x00100000
    #define RING52_DATA_SHIFT 20
    #define RING53_DATA_MASK 0x00200000
    #define RING53_DATA_SHIFT 21
    #define RING54_DATA_MASK 0x00400000
    #define RING54_DATA_SHIFT 22
    #define RING55_DATA_MASK 0x00800000
    #define RING55_DATA_SHIFT 23
    #define RING56_DATA_MASK 0x01000000
    #define RING56_DATA_SHIFT 24
    #define RING57_DATA_MASK 0x02000000
    #define RING57_DATA_SHIFT 25
    #define RING58_DATA_MASK 0x04000000
    #define RING58_DATA_SHIFT 26
    #define RING59_DATA_MASK 0x08000000
    #define RING59_DATA_SHIFT 27
    #define RING60_DATA_MASK 0x10000000
    #define RING60_DATA_SHIFT 28
    #define RING61_DATA_MASK 0x20000000
    #define RING61_DATA_SHIFT 29
    #define RING62_DATA_MASK 0x40000000
    #define RING62_DATA_SHIFT 30
    #define RING63_DATA_MASK 0x80000000
    #define RING63_DATA_SHIFT 31
#define  TSD_MEMARB_CTRL 0x63EC
    #define TSD_MEMARB_CTRL_PF_ARB_DIS_MASK 0x00000001
    #define TSD_MEMARB_CTRL_PF_ARB_DIS_SHIFT 0
    #define TSD_MEMARB_CTRL_ABS_PRIORITY_MASK 0x00000002
    #define TSD_MEMARB_CTRL_ABS_PRIORITY_SHIFT 1
    #define TSD_MEMARB_CTRL_CLI0_TIMER_MASK 0x000000F0
    #define TSD_MEMARB_CTRL_CLI0_TIMER_SHIFT 4
    #define TSD_MEMARB_CTRL_CLI1_TIMER_MASK 0x00000F00
    #define TSD_MEMARB_CTRL_CLI1_TIMER_SHIFT 8
    #define TSD_MEMARB_CTRL_CLI2_TIMER_MASK 0x0000F000
    #define TSD_MEMARB_CTRL_CLI2_TIMER_SHIFT 12
    #define TSD_MEMARB_CTRL_CLI3_TIMER_MASK 0x000F0000
    #define TSD_MEMARB_CTRL_CLI3_TIMER_SHIFT 16
#define  TSD_MIPS_INT_MASK0 0x6168
    #define TSD_MIPS_INT_MASK0_INT_EN_PFBUF_OF0_MASK 0x00000001
    #define TSD_MIPS_INT_MASK0_INT_EN_PFBUF_OF0_SHIFT 0
    #define TSD_MIPS_INT_MASK0_INT_EN_PFBUF_OF1_MASK 0x00000002
    #define TSD_MIPS_INT_MASK0_INT_EN_PFBUF_OF1_SHIFT 1
    #define TSD_MIPS_INT_MASK0_INT_EN_TEI_ERROR_MASK 0x00000100
    #define TSD_MIPS_INT_MASK0_INT_EN_TEI_ERROR_SHIFT 8
#define  TSD_MIPS_INT_MASK1 0x67B8
    #define TSD_MIPS_INT_MASK1_INT_EN_RING0_ERR_MASK 0x00000001
    #define TSD_MIPS_INT_MASK1_INT_EN_RING0_ERR_SHIFT 0
    #define TSD_MIPS_INT_MASK1_INT_EN_RING1_ERR_MASK 0x00000002
    #define TSD_MIPS_INT_MASK1_INT_EN_RING1_ERR_SHIFT 1
    #define TSD_MIPS_INT_MASK1_INT_EN_RING2_ERR_MASK 0x00000004
    #define TSD_MIPS_INT_MASK1_INT_EN_RING2_ERR_SHIFT 2
    #define TSD_MIPS_INT_MASK1_INT_EN_RING3_ERR_MASK 0x00000008
    #define TSD_MIPS_INT_MASK1_INT_EN_RING3_ERR_SHIFT 3
    #define TSD_MIPS_INT_MASK1_INT_EN_RING4_ERR_MASK 0x00000010
    #define TSD_MIPS_INT_MASK1_INT_EN_RING4_ERR_SHIFT 4
    #define TSD_MIPS_INT_MASK1_INT_EN_RING5_ERR_MASK 0x00000020
    #define TSD_MIPS_INT_MASK1_INT_EN_RING5_ERR_SHIFT 5
    #define TSD_MIPS_INT_MASK1_INT_EN_RING6_ERR_MASK 0x00000040
    #define TSD_MIPS_INT_MASK1_INT_EN_RING6_ERR_SHIFT 6
    #define TSD_MIPS_INT_MASK1_INT_EN_RING7_ERR_MASK 0x00000080
    #define TSD_MIPS_INT_MASK1_INT_EN_RING7_ERR_SHIFT 7
    #define TSD_MIPS_INT_MASK1_INT_EN_RING8_ERR_MASK 0x00000100
    #define TSD_MIPS_INT_MASK1_INT_EN_RING8_ERR_SHIFT 8
    #define TSD_MIPS_INT_MASK1_INT_EN_RING9_ERR_MASK 0x00000200
    #define TSD_MIPS_INT_MASK1_INT_EN_RING9_ERR_SHIFT 9
    #define TSD_MIPS_INT_MASK1_INT_EN_RING10_ERR_MASK 0x00000400
    #define TSD_MIPS_INT_MASK1_INT_EN_RING10_ERR_SHIFT 10
    #define TSD_MIPS_INT_MASK1_INT_EN_RING11_ERR_MASK 0x00000800
    #define TSD_MIPS_INT_MASK1_INT_EN_RING11_ERR_SHIFT 11
    #define TSD_MIPS_INT_MASK1_INT_EN_RING12_ERR_MASK 0x00001000
    #define TSD_MIPS_INT_MASK1_INT_EN_RING12_ERR_SHIFT 12
    #define TSD_MIPS_INT_MASK1_INT_EN_RING13_ERR_MASK 0x00002000
    #define TSD_MIPS_INT_MASK1_INT_EN_RING13_ERR_SHIFT 13
    #define TSD_MIPS_INT_MASK1_INT_EN_RING14_ERR_MASK 0x00004000
    #define TSD_MIPS_INT_MASK1_INT_EN_RING14_ERR_SHIFT 14
    #define TSD_MIPS_INT_MASK1_INT_EN_RING15_ERR_MASK 0x00008000
    #define TSD_MIPS_INT_MASK1_INT_EN_RING15_ERR_SHIFT 15
    #define TSD_MIPS_INT_MASK1_INT_EN_RING16_ERR_MASK 0x00010000
    #define TSD_MIPS_INT_MASK1_INT_EN_RING16_ERR_SHIFT 16
    #define TSD_MIPS_INT_MASK1_INT_EN_RING17_ERR_MASK 0x00020000
    #define TSD_MIPS_INT_MASK1_INT_EN_RING17_ERR_SHIFT 17
    #define TSD_MIPS_INT_MASK1_INT_EN_RING18_ERR_MASK 0x00040000
    #define TSD_MIPS_INT_MASK1_INT_EN_RING18_ERR_SHIFT 18
    #define TSD_MIPS_INT_MASK1_INT_EN_RING19_ERR_MASK 0x00080000
    #define TSD_MIPS_INT_MASK1_INT_EN_RING19_ERR_SHIFT 19
    #define TSD_MIPS_INT_MASK1_INT_EN_RING20_ERR_MASK 0x00100000
    #define TSD_MIPS_INT_MASK1_INT_EN_RING20_ERR_SHIFT 20
    #define TSD_MIPS_INT_MASK1_INT_EN_RING21_ERR_MASK 0x00200000
    #define TSD_MIPS_INT_MASK1_INT_EN_RING21_ERR_SHIFT 21
    #define TSD_MIPS_INT_MASK1_INT_EN_RING22_ERR_MASK 0x00400000
    #define TSD_MIPS_INT_MASK1_INT_EN_RING22_ERR_SHIFT 22
    #define TSD_MIPS_INT_MASK1_INT_EN_RING23_ERR_MASK 0x00800000
    #define TSD_MIPS_INT_MASK1_INT_EN_RING23_ERR_SHIFT 23
    #define TSD_MIPS_INT_MASK1_INT_EN_RING24_ERR_MASK 0x01000000
    #define TSD_MIPS_INT_MASK1_INT_EN_RING24_ERR_SHIFT 24
    #define TSD_MIPS_INT_MASK1_INT_EN_RING25_ERR_MASK 0x02000000
    #define TSD_MIPS_INT_MASK1_INT_EN_RING25_ERR_SHIFT 25
    #define TSD_MIPS_INT_MASK1_INT_EN_RING26_ERR_MASK 0x04000000
    #define TSD_MIPS_INT_MASK1_INT_EN_RING26_ERR_SHIFT 26
    #define TSD_MIPS_INT_MASK1_INT_EN_RING27_ERR_MASK 0x08000000
    #define TSD_MIPS_INT_MASK1_INT_EN_RING27_ERR_SHIFT 27
    #define TSD_MIPS_INT_MASK1_INT_EN_RING28_ERR_MASK 0x10000000
    #define TSD_MIPS_INT_MASK1_INT_EN_RING28_ERR_SHIFT 28
    #define TSD_MIPS_INT_MASK1_INT_EN_RING29_ERR_MASK 0x20000000
    #define TSD_MIPS_INT_MASK1_INT_EN_RING29_ERR_SHIFT 29
    #define TSD_MIPS_INT_MASK1_INT_EN_RING30_ERR_MASK 0x40000000
    #define TSD_MIPS_INT_MASK1_INT_EN_RING30_ERR_SHIFT 30
    #define TSD_MIPS_INT_MASK1_INT_EN_RING31_ERR_MASK 0x80000000
    #define TSD_MIPS_INT_MASK1_INT_EN_RING31_ERR_SHIFT 31
#define  TSD_MIPS_INT_MASK1_1 0x673C
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING32_ERR_MASK 0x00000001
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING32_ERR_SHIFT 0
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING33_ERR_MASK 0x00000002
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING33_ERR_SHIFT 1
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING34_ERR_MASK 0x00000004
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING34_ERR_SHIFT 2
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING35_ERR_MASK 0x00000008
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING35_ERR_SHIFT 3
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING36_ERR_MASK 0x00000010
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING36_ERR_SHIFT 4
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING37_ERR_MASK 0x00000020
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING37_ERR_SHIFT 5
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING38_ERR_MASK 0x00000040
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING38_ERR_SHIFT 6
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING39_ERR_MASK 0x00000080
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING39_ERR_SHIFT 7
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING40_ERR_MASK 0x00000100
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING40_ERR_SHIFT 8
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING41_ERR_MASK 0x00000200
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING41_ERR_SHIFT 9
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING42_ERR_MASK 0x00000400
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING42_ERR_SHIFT 10
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING43_ERR_MASK 0x00000800
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING43_ERR_SHIFT 11
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING44_ERR_MASK 0x00001000
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING44_ERR_SHIFT 12
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING45_ERR_MASK 0x00002000
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING45_ERR_SHIFT 13
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING46_ERR_MASK 0x00004000
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING46_ERR_SHIFT 14
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING47_ERR_MASK 0x00008000
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING47_ERR_SHIFT 15
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING48_ERR_MASK 0x00010000
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING48_ERR_SHIFT 16
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING49_ERR_MASK 0x00020000
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING49_ERR_SHIFT 17
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING50_ERR_MASK 0x00040000
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING50_ERR_SHIFT 18
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING51_ERR_MASK 0x00080000
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING51_ERR_SHIFT 19
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING52_ERR_MASK 0x00100000
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING52_ERR_SHIFT 20
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING53_ERR_MASK 0x00200000
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING53_ERR_SHIFT 21
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING54_ERR_MASK 0x00400000
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING54_ERR_SHIFT 22
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING55_ERR_MASK 0x00800000
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING55_ERR_SHIFT 23
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING56_ERR_MASK 0x01000000
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING56_ERR_SHIFT 24
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING57_ERR_MASK 0x02000000
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING57_ERR_SHIFT 25
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING58_ERR_MASK 0x04000000
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING58_ERR_SHIFT 26
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING59_ERR_MASK 0x08000000
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING59_ERR_SHIFT 27
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING60_ERR_MASK 0x10000000
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING60_ERR_SHIFT 28
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING61_ERR_MASK 0x20000000
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING61_ERR_SHIFT 29
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING62_ERR_MASK 0x40000000
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING62_ERR_SHIFT 30
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING63_ERR_MASK 0x80000000
    #define TSD_MIPS_INT_MASK1_1_INT_EN_RING63_ERR_SHIFT 31
#define  TSD_MIPS_INT_MASK4 0x67DC
    #define TSD_MIPS_INT_MASK4_INT_EN_RING0_DATA_MASK 0x00000001
    #define TSD_MIPS_INT_MASK4_INT_EN_RING0_DATA_SHIFT 0
    #define TSD_MIPS_INT_MASK4_INT_EN_RING1_DATA_MASK 0x00000002
    #define TSD_MIPS_INT_MASK4_INT_EN_RING1_DATA_SHIFT 1
    #define TSD_MIPS_INT_MASK4_INT_EN_RING2_DATA_MASK 0x00000004
    #define TSD_MIPS_INT_MASK4_INT_EN_RING2_DATA_SHIFT 2
    #define TSD_MIPS_INT_MASK4_INT_EN_RING3_DATA_MASK 0x00000008
    #define TSD_MIPS_INT_MASK4_INT_EN_RING3_DATA_SHIFT 3
    #define TSD_MIPS_INT_MASK4_INT_EN_RING4_DATA_MASK 0x00000010
    #define TSD_MIPS_INT_MASK4_INT_EN_RING4_DATA_SHIFT 4
    #define TSD_MIPS_INT_MASK4_INT_EN_RING5_DATA_MASK 0x00000020
    #define TSD_MIPS_INT_MASK4_INT_EN_RING5_DATA_SHIFT 5
    #define TSD_MIPS_INT_MASK4_INT_EN_RING6_DATA_MASK 0x00000040
    #define TSD_MIPS_INT_MASK4_INT_EN_RING6_DATA_SHIFT 6
    #define TSD_MIPS_INT_MASK4_INT_EN_RING7_DATA_MASK 0x00000080
    #define TSD_MIPS_INT_MASK4_INT_EN_RING7_DATA_SHIFT 7
    #define TSD_MIPS_INT_MASK4_INT_EN_RING8_DATA_MASK 0x00000100
    #define TSD_MIPS_INT_MASK4_INT_EN_RING8_DATA_SHIFT 8
    #define TSD_MIPS_INT_MASK4_INT_EN_RING9_DATA_MASK 0x00000200
    #define TSD_MIPS_INT_MASK4_INT_EN_RING9_DATA_SHIFT 9
    #define TSD_MIPS_INT_MASK4_INT_EN_RING10_DATA_MASK 0x00000400
    #define TSD_MIPS_INT_MASK4_INT_EN_RING10_DATA_SHIFT 10
    #define TSD_MIPS_INT_MASK4_INT_EN_RING11_DATA_MASK 0x00000800
    #define TSD_MIPS_INT_MASK4_INT_EN_RING11_DATA_SHIFT 11
    #define TSD_MIPS_INT_MASK4_INT_EN_RING12_DATA_MASK 0x00001000
    #define TSD_MIPS_INT_MASK4_INT_EN_RING12_DATA_SHIFT 12
    #define TSD_MIPS_INT_MASK4_INT_EN_RING13_DATA_MASK 0x00002000
    #define TSD_MIPS_INT_MASK4_INT_EN_RING13_DATA_SHIFT 13
    #define TSD_MIPS_INT_MASK4_INT_EN_RING14_DATA_MASK 0x00004000
    #define TSD_MIPS_INT_MASK4_INT_EN_RING14_DATA_SHIFT 14
    #define TSD_MIPS_INT_MASK4_INT_EN_RING15_DATA_MASK 0x00008000
    #define TSD_MIPS_INT_MASK4_INT_EN_RING15_DATA_SHIFT 15
    #define TSD_MIPS_INT_MASK4_INT_EN_RING16_DATA_MASK 0x00010000
    #define TSD_MIPS_INT_MASK4_INT_EN_RING16_DATA_SHIFT 16
    #define TSD_MIPS_INT_MASK4_INT_EN_RING17_DATA_MASK 0x00020000
    #define TSD_MIPS_INT_MASK4_INT_EN_RING17_DATA_SHIFT 17
    #define TSD_MIPS_INT_MASK4_INT_EN_RING18_DATA_MASK 0x00040000
    #define TSD_MIPS_INT_MASK4_INT_EN_RING18_DATA_SHIFT 18
    #define TSD_MIPS_INT_MASK4_INT_EN_RING19_DATA_MASK 0x00080000
    #define TSD_MIPS_INT_MASK4_INT_EN_RING19_DATA_SHIFT 19
    #define TSD_MIPS_INT_MASK4_INT_EN_RING20_DATA_MASK 0x00100000
    #define TSD_MIPS_INT_MASK4_INT_EN_RING20_DATA_SHIFT 20
    #define TSD_MIPS_INT_MASK4_INT_EN_RING21_DATA_MASK 0x00200000
    #define TSD_MIPS_INT_MASK4_INT_EN_RING21_DATA_SHIFT 21
    #define TSD_MIPS_INT_MASK4_INT_EN_RING22_DATA_MASK 0x00400000
    #define TSD_MIPS_INT_MASK4_INT_EN_RING22_DATA_SHIFT 22
    #define TSD_MIPS_INT_MASK4_INT_EN_RING23_DATA_MASK 0x00800000
    #define TSD_MIPS_INT_MASK4_INT_EN_RING23_DATA_SHIFT 23
    #define TSD_MIPS_INT_MASK4_INT_EN_RING24_DATA_MASK 0x01000000
    #define TSD_MIPS_INT_MASK4_INT_EN_RING24_DATA_SHIFT 24
    #define TSD_MIPS_INT_MASK4_INT_EN_RING25_DATA_MASK 0x02000000
    #define TSD_MIPS_INT_MASK4_INT_EN_RING25_DATA_SHIFT 25
    #define TSD_MIPS_INT_MASK4_INT_EN_RING26_DATA_MASK 0x04000000
    #define TSD_MIPS_INT_MASK4_INT_EN_RING26_DATA_SHIFT 26
    #define TSD_MIPS_INT_MASK4_INT_EN_RING27_DATA_MASK 0x08000000
    #define TSD_MIPS_INT_MASK4_INT_EN_RING27_DATA_SHIFT 27
    #define TSD_MIPS_INT_MASK4_INT_EN_RING28_DATA_MASK 0x10000000
    #define TSD_MIPS_INT_MASK4_INT_EN_RING28_DATA_SHIFT 28
    #define TSD_MIPS_INT_MASK4_INT_EN_RING29_DATA_MASK 0x20000000
    #define TSD_MIPS_INT_MASK4_INT_EN_RING29_DATA_SHIFT 29
    #define TSD_MIPS_INT_MASK4_INT_EN_RING30_DATA_MASK 0x40000000
    #define TSD_MIPS_INT_MASK4_INT_EN_RING30_DATA_SHIFT 30
    #define TSD_MIPS_INT_MASK4_INT_EN_RING31_DATA_MASK 0x80000000
    #define TSD_MIPS_INT_MASK4_INT_EN_RING31_DATA_SHIFT 31
#define  TSD_MIPS_INT_MASK4_1 0x6748
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING32_DATA_MASK 0x00000001
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING32_DATA_SHIFT 0
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING33_DATA_MASK 0x00000002
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING33_DATA_SHIFT 1
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING34_DATA_MASK 0x00000004
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING34_DATA_SHIFT 2
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING35_DATA_MASK 0x00000008
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING35_DATA_SHIFT 3
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING36_DATA_MASK 0x00000010
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING36_DATA_SHIFT 4
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING37_DATA_MASK 0x00000020
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING37_DATA_SHIFT 5
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING38_DATA_MASK 0x00000040
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING38_DATA_SHIFT 6
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING39_DATA_MASK 0x00000080
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING39_DATA_SHIFT 7
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING40_DATA_MASK 0x00000100
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING40_DATA_SHIFT 8
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING41_DATA_MASK 0x00000200
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING41_DATA_SHIFT 9
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING42_DATA_MASK 0x00000400
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING42_DATA_SHIFT 10
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING43_DATA_MASK 0x00000800
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING43_DATA_SHIFT 11
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING44_DATA_MASK 0x00001000
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING44_DATA_SHIFT 12
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING45_DATA_MASK 0x00002000
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING45_DATA_SHIFT 13
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING46_DATA_MASK 0x00004000
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING46_DATA_SHIFT 14
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING47_DATA_MASK 0x00008000
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING47_DATA_SHIFT 15
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING48_DATA_MASK 0x00010000
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING48_DATA_SHIFT 16
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING49_DATA_MASK 0x00020000
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING49_DATA_SHIFT 17
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING50_DATA_MASK 0x00040000
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING50_DATA_SHIFT 18
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING51_DATA_MASK 0x00080000
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING51_DATA_SHIFT 19
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING52_DATA_MASK 0x00100000
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING52_DATA_SHIFT 20
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING53_DATA_MASK 0x00200000
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING53_DATA_SHIFT 21
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING54_DATA_MASK 0x00400000
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING54_DATA_SHIFT 22
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING55_DATA_MASK 0x00800000
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING55_DATA_SHIFT 23
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING56_DATA_MASK 0x01000000
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING56_DATA_SHIFT 24
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING57_DATA_MASK 0x02000000
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING57_DATA_SHIFT 25
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING58_DATA_MASK 0x04000000
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING58_DATA_SHIFT 26
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING59_DATA_MASK 0x08000000
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING59_DATA_SHIFT 27
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING60_DATA_MASK 0x10000000
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING60_DATA_SHIFT 28
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING61_DATA_MASK 0x20000000
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING61_DATA_SHIFT 29
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING62_DATA_MASK 0x40000000
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING62_DATA_SHIFT 30
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING63_DATA_MASK 0x80000000
    #define TSD_MIPS_INT_MASK4_1_INT_EN_RING63_DATA_SHIFT 31
#define  TSD_NUM 0x6140
    #define TSD_NUM_NUM_MASK 0xFFFFFFFF
    #define TSD_NUM_NUM_SHIFT 0
#define  TSD_PS_MODE_STATUS 0x63F0
    #define TSD_PS_MODE_STATUS_BYTE_COUNT_MASK 0x00000FFF
    #define TSD_PS_MODE_STATUS_BYTE_COUNT_SHIFT 0
    #define TSD_PS_MODE_STATUS_SER_COUNT_MASK 0x00007000
    #define TSD_PS_MODE_STATUS_SER_COUNT_SHIFT 12
#define  TSD_SFT_RSTN 0x6034
    #define M_SFT_RSTN_MASK 0x00000001
    #define M_SFT_RSTN_SHIFT 0
    #define X_SFT_RSTN_MASK 0x00000004
    #define X_SFT_RSTN_SHIFT 2
    #define B_SFT_RSTN_MASK 0x00000008
    #define B_SFT_RSTN_SHIFT 3
    #define D_SFT_RSTN_MASK 0x00000010
    #define D_SFT_RSTN_SHIFT 4
    #define B1_SFT_RSTN_MASK 0x00000040
    #define B1_SFT_RSTN_SHIFT 6
    #define TDE_ENABLE_MASK 0x00020000
    #define TDE_ENABLE_SHIFT 17
#define  TSD_SF_DUMMY_REG 0x67FC
    #define TSD_SF_DUMMY_REG_DUMMY_REG_MASK 0xFFFFFFFF
    #define TSD_SF_DUMMY_REG_DUMMY_REG_SHIFT 0
#define  TSD_SYNC_MUX_CTRL 0x6154
    #define TSD_SYNC_MUX_CTRL_FETCH_RATE_EN_MASK 0x00000001
    #define TSD_SYNC_MUX_CTRL_FETCH_RATE_EN_SHIFT 0
    #define TSD_SYNC_MUX_CTRL_FETCH_RATE_MASK 0x003FFF00
    #define TSD_SYNC_MUX_CTRL_FETCH_RATE_SHIFT 8
#define  TSD_SYNC_TMUX_CTRL 0x6158
    #define TSD_SYNC_TMUX_CTRL_FETCH_RATE_EN_MASK 0x00000001
    #define TSD_SYNC_TMUX_CTRL_FETCH_RATE_EN_SHIFT 0
    #define TSD_SYNC_TMUX_CTRL_FETCH_RATE_MASK 0x003FFF00
    #define TSD_SYNC_TMUX_CTRL_FETCH_RATE_SHIFT 8
#define  TSD_TEI_CNT 0x63DC
    #define TEI_PACKET_CNT_MASK 0x000000FF
    #define TEI_PACKET_CNT_SHIFT 0
    #define TEI_CNT_RESET_MASK 0x00000100
    #define TEI_CNT_RESET_SHIFT 8
#define  TSD_TEI_STATUS_ADR 0x63E0
    #define TEI_ADR_MASK 0x0000007F
    #define TEI_ADR_SHIFT 0
#define  TSD_TEI_STATUS_DAT 0x63E4
    #define TEI_ERR_SEEN_MASK 0xFFFFFFFF
    #define TEI_ERR_SEEN_SHIFT 0
#define  TTS_INCR0_VAL 0x60EC
    #define TTS_INCR0_MASK 0xFFFFFFFF
    #define TTS_INCR0_SHIFT 0
#define  TTS_INCR1_VAL 0x60F0
    #define TTS_INCR1_MASK 0xFFFFFFFF
    #define TTS_INCR1_SHIFT 0
#define  TTS_LATCH0_VAL 0x6234
    #define TTS_LATCH0_MASK 0xFFFFFFFF
    #define TTS_LATCH0_SHIFT 0
#define  TTS_LATCH1_VAL 0x6238
    #define TTS_LATCH1_MASK 0xFFFFFFFF
    #define TTS_LATCH1_SHIFT 0
#define  UART0_ALTERNATE_CLK_DIV 0xF444
    #define UART0_ALTERNATE_CLK_DIV_ALTERNATE_EN_MASK 0x00000001
    #define UART0_ALTERNATE_CLK_DIV_ALTERNATE_EN_SHIFT 0
    #define UART0_ALTERNATE_CLK_DIV_SRC_DIV_MASK 0x00001FF0
    #define UART0_ALTERNATE_CLK_DIV_SRC_DIV_SHIFT 4
    #define UART0_ALTERNATE_CLK_DIV_DST_DIV_MASK 0x01FF0000
    #define UART0_ALTERNATE_CLK_DIV_DST_DIV_SHIFT 16
#define  UART0_CTRL_REG 0xF41C
    #define UART0_CTRL_REG_CTRL_TX_MASK 0x00000001
    #define UART0_CTRL_REG_CTRL_TX_SHIFT 0
    #define UART0_CTRL_REG_TX_INVERT_MASK 0x00000010
    #define UART0_CTRL_REG_TX_INVERT_SHIFT 4
    #define UART0_CTRL_REG_RX_INVERT_MASK 0x00000100
    #define UART0_CTRL_REG_RX_INVERT_SHIFT 8
    #define UART0_CTRL_REG_RX_RECOVER_MASK 0x00000200
    #define UART0_CTRL_REG_RX_RECOVER_SHIFT 9
    #define UART0_CTRL_REG_CONTROL_RX_MASK 0x00001000
    #define UART0_CTRL_REG_CONTROL_RX_SHIFT 12
    #define UART0_CTRL_REG_HW_FLOW_CTRL_EN_MASK 0x00010000
    #define UART0_CTRL_REG_HW_FLOW_CTRL_EN_SHIFT 16
    #define UART0_CTRL_REG_CTSN_INVERT_MASK 0x00020000
    #define UART0_CTRL_REG_CTSN_INVERT_SHIFT 17
    #define UART0_CTRL_REG_RTSN_INVERT_MASK 0x00040000
    #define UART0_CTRL_REG_RTSN_INVERT_SHIFT 18
    #define UART0_CTRL_REG_TIMEOUT_WAIT_MASK 0x0FF00000
    #define UART0_CTRL_REG_TIMEOUT_WAIT_SHIFT 20
    #define UART0_CTRL_REG_SOFT_RESET_MASK 0x10000000
    #define UART0_CTRL_REG_SOFT_RESET_SHIFT 28
    #define RCLK_SEL_MASK 0x20000000
    #define RCLK_SEL_SHIFT 29
    #define BAUDOUT_EN_MASK 0x40000000
    #define BAUDOUT_EN_SHIFT 30
    #define UART0_CTRL_REG_AUTO_FLUSH_MASK 0x80000000
    #define UART0_CTRL_REG_AUTO_FLUSH_SHIFT 31
#define  UART0_INFO 0xF440
    #define UART0_INFO_RX_FIFO_ENTRIES_MASK 0x0000003F
    #define UART0_INFO_RX_FIFO_ENTRIES_SHIFT 0
    #define UART0_INFO_TX_FIFO_ENTRIES_MASK 0x00003F00
    #define UART0_INFO_TX_FIFO_ENTRIES_SHIFT 8
    #define UART0_INFO_BAUD_DIVLSB_MASK 0x00FF0000
    #define UART0_INFO_BAUD_DIVLSB_SHIFT 16
#define  UART0_INTEN_DIVMSB 0xF404
    #define UART0_INTEN_DIVMSB_INTEN_DIVMSB_DATA_MASK 0x000000FF
    #define UART0_INTEN_DIVMSB_INTEN_DIVMSB_DATA_SHIFT 0
#define  UART0_INTID_FIFOCTRL 0xF408
    #define UART0_INTID_FIFOCTRL_INTID_FIFOCTRL_DATA_MASK 0x000000FF
    #define UART0_INTID_FIFOCTRL_INTID_FIFOCTRL_DATA_SHIFT 0
#define  UART0_INT_MASK 0xF43C
    #define UART0_INT_MASK_RECIEVE_DATA_RDY_MASK 0x00000001
    #define UART0_INT_MASK_RECIEVE_DATA_RDY_SHIFT 0
    #define UART0_INT_MASK_TRANSMIT_DONE_EMPTY_MASK 0x00000002
    #define UART0_INT_MASK_TRANSMIT_DONE_EMPTY_SHIFT 1
    #define UART0_INT_MASK_RECIVER_LINE_MASK 0x00000004
    #define UART0_INT_MASK_RECIVER_LINE_SHIFT 2
    #define UART0_INT_MASK_MODEM_MASK 0x00000008
    #define UART0_INT_MASK_MODEM_SHIFT 3
    #define UART0_INT_MASK_TIMEOUT_MASK 0x00000010
    #define UART0_INT_MASK_TIMEOUT_SHIFT 4
#define  UART0_INT_STATUS 0xF438
    #define UART0_INT_STATUS_RECIEVE_DATA_RDY_MASK 0x00000001
    #define UART0_INT_STATUS_RECIEVE_DATA_RDY_SHIFT 0
    #define UART0_INT_STATUS_TRANSMIT_DONE_EMPTY_MASK 0x00000002
    #define UART0_INT_STATUS_TRANSMIT_DONE_EMPTY_SHIFT 1
    #define UART0_INT_STATUS_RECIVER_LINE_MASK 0x00000004
    #define UART0_INT_STATUS_RECIVER_LINE_SHIFT 2
    #define UART0_INT_STATUS_MODEM_MASK 0x00000008
    #define UART0_INT_STATUS_MODEM_SHIFT 3
    #define UART0_INT_STATUS_TIMEOUT_MASK 0x00000010
    #define UART0_INT_STATUS_TIMEOUT_SHIFT 4
#define  UART0_LINE_CTRL 0xF40C
    #define UART0_LINE_CTRL_CHAR_LEN_MASK 0x00000003
    #define UART0_LINE_CTRL_CHAR_LEN_SHIFT 0
    #define UART0_LINE_CTRL_STOP_BITS_MASK 0x00000004
    #define UART0_LINE_CTRL_STOP_BITS_SHIFT 2
    #define UART0_LINE_CTRL_PARITY_EN_MASK 0x00000008
    #define UART0_LINE_CTRL_PARITY_EN_SHIFT 3
    #define UART0_LINE_CTRL_EVEN_PARITY_MASK 0x00000010
    #define UART0_LINE_CTRL_EVEN_PARITY_SHIFT 4
    #define UART0_LINE_CTRL_STICK_PARITY_MASK 0x00000020
    #define UART0_LINE_CTRL_STICK_PARITY_SHIFT 5
    #define UART0_LINE_CTRL_BREAK_COND_MASK 0x00000040
    #define UART0_LINE_CTRL_BREAK_COND_SHIFT 6
    #define UART0_LINE_CTRL_DIVISOR_ACCESS_MASK 0x00000080
    #define UART0_LINE_CTRL_DIVISOR_ACCESS_SHIFT 7
#define  UART0_LINE_STATUS 0xF414
    #define UART0_LINE_STATUS_RECIEVE_RDY_MASK 0x00000001
    #define UART0_LINE_STATUS_RECIEVE_RDY_SHIFT 0
    #define UART0_LINE_STATUS_OVERRUN_MASK 0x00000002
    #define UART0_LINE_STATUS_OVERRUN_SHIFT 1
    #define UART0_LINE_STATUS_PARITY_ERR_MASK 0x00000004
    #define UART0_LINE_STATUS_PARITY_ERR_SHIFT 2
    #define UART0_LINE_STATUS_FRAME_ERR_MASK 0x00000008
    #define UART0_LINE_STATUS_FRAME_ERR_SHIFT 3
    #define UART0_LINE_STATUS_BREAK_IND_MASK 0x00000010
    #define UART0_LINE_STATUS_BREAK_IND_SHIFT 4
    #define UART0_LINE_STATUS_TF_EMPTY_MASK 0x00000020
    #define UART0_LINE_STATUS_TF_EMPTY_SHIFT 5
    #define UART0_LINE_STATUS_TRANS_EMPTY_MASK 0x00000040
    #define UART0_LINE_STATUS_TRANS_EMPTY_SHIFT 6
    #define UART0_LINE_STATUS_ERROR_MASK 0x00000080
    #define UART0_LINE_STATUS_ERROR_SHIFT 7
#define  UART0_MODEM_CTRL 0xF418
    #define UART0_MODEM_CTRL_DATA_TERM_RDY_MASK 0x00000001
    #define UART0_MODEM_CTRL_DATA_TERM_RDY_SHIFT 0
    #define UART0_MODEM_CTRL_REQ_TO_SEND_MASK 0x00000002
    #define UART0_MODEM_CTRL_REQ_TO_SEND_SHIFT 1
    #define UART0_MODEM_CTRL_USER_OUTPUT_MASK 0x00000004
    #define UART0_MODEM_CTRL_USER_OUTPUT_SHIFT 2
    #define UART0_MODEM_CTRL_USER_OUTPUT2_MASK 0x00000008
    #define UART0_MODEM_CTRL_USER_OUTPUT2_SHIFT 3
#define  UART0_MODEM_STATUS 0xF410
    #define UART0_MODEM_STATUS_CTSN_CHANGED_MASK 0x00000001
    #define UART0_MODEM_STATUS_CTSN_CHANGED_SHIFT 0
    #define UART0_MODEM_STATUS_DSRN_CHANGED_MASK 0x00000002
    #define UART0_MODEM_STATUS_DSRN_CHANGED_SHIFT 1
    #define UART0_MODEM_STATUS_RIN_RISING_EDGE_MASK 0x00000004
    #define UART0_MODEM_STATUS_RIN_RISING_EDGE_SHIFT 2
    #define UART0_MODEM_STATUS_DCDN_CHANGED_MASK 0x00000008
    #define UART0_MODEM_STATUS_DCDN_CHANGED_SHIFT 3
    #define UART0_MODEM_STATUS_CLEAR_TO_SEND_MASK 0x00000010
    #define UART0_MODEM_STATUS_CLEAR_TO_SEND_SHIFT 4
    #define UART0_MODEM_STATUS_DATA_SEND_REQ_MASK 0x00000020
    #define UART0_MODEM_STATUS_DATA_SEND_REQ_SHIFT 5
    #define UART0_MODEM_STATUS_RING_IND_MASK 0x00000040
    #define UART0_MODEM_STATUS_RING_IND_SHIFT 6
    #define UART0_MODEM_STATUS_DATA_CAR_DETECT_MASK 0x00000080
    #define UART0_MODEM_STATUS_DATA_CAR_DETECT_SHIFT 7
#define  UART0_RING_BASE 0xF420
    #define UART0_RING_BASE_BASE_MASK 0x7FFFFFF8
    #define UART0_RING_BASE_BASE_SHIFT 3
#define  UART0_RING_HEAD 0xF424
    #define UART0_RING_HEAD_HEAD_MASK 0x00003FFF
    #define UART0_RING_HEAD_HEAD_SHIFT 0
#define  UART0_RING_SIZE 0xF42C
    #define UART0_RING_SIZE_SIZE_MASK 0x00003FFF
    #define UART0_RING_SIZE_SIZE_SHIFT 0
#define  UART0_RING_TAIL 0xF428
    #define UART0_RING_TAIL_TAIL_MASK 0x00003FFF
    #define UART0_RING_TAIL_TAIL_SHIFT 0
#define  UART0_RX_TX_DIVLSB 0xF400
    #define UART0_RX_TX_DIVLSB_RX_TX_LSB_DATA_MASK 0x000000FF
    #define UART0_RX_TX_DIVLSB_RX_TX_LSB_DATA_SHIFT 0
#define  UART0_XMIT_BASE 0xF430
    #define UART0_XMIT_BASE_BASE_MASK 0x7FFFFFF8
    #define UART0_XMIT_BASE_BASE_SHIFT 3
#define  UART0_XMIT_SIZE 0xF434
    #define UART0_XMIT_SIZE_SIZE_MASK 0x00003FFF
    #define UART0_XMIT_SIZE_SIZE_SHIFT 0
#define  UART1_ALTERNATE_CLK_DIV 0xF494
    #define UART1_ALTERNATE_CLK_DIV_ALTERNATE_EN_MASK 0x00000001
    #define UART1_ALTERNATE_CLK_DIV_ALTERNATE_EN_SHIFT 0
    #define UART1_ALTERNATE_CLK_DIV_SRC_DIV_MASK 0x00001FF0
    #define UART1_ALTERNATE_CLK_DIV_SRC_DIV_SHIFT 4
    #define UART1_ALTERNATE_CLK_DIV_DST_DIV_MASK 0x01FF0000
    #define UART1_ALTERNATE_CLK_DIV_DST_DIV_SHIFT 16
#define  UART1_CTRL_REG 0xF46C
    #define UART1_CTRL_REG_CTRL_TX_MASK 0x00000001
    #define UART1_CTRL_REG_CTRL_TX_SHIFT 0
    #define UART1_CTRL_REG_TX_INVERT_MASK 0x00000010
    #define UART1_CTRL_REG_TX_INVERT_SHIFT 4
    #define UART1_CTRL_REG_RX_INVERT_MASK 0x00000100
    #define UART1_CTRL_REG_RX_INVERT_SHIFT 8
    #define UART1_CTRL_REG_RX_RECOVER_MASK 0x00000200
    #define UART1_CTRL_REG_RX_RECOVER_SHIFT 9
    #define UART1_CTRL_REG_CONTROL_RX_MASK 0x00001000
    #define UART1_CTRL_REG_CONTROL_RX_SHIFT 12
    #define UART1_CTRL_REG_HW_FLOW_CTRL_EN_MASK 0x00010000
    #define UART1_CTRL_REG_HW_FLOW_CTRL_EN_SHIFT 16
    #define UART1_CTRL_REG_CTSN_INVERT_MASK 0x00020000
    #define UART1_CTRL_REG_CTSN_INVERT_SHIFT 17
    #define UART1_CTRL_REG_RTSN_INVERT_MASK 0x00040000
    #define UART1_CTRL_REG_RTSN_INVERT_SHIFT 18
    #define UART1_CTRL_REG_TIMEOUT_WAIT_MASK 0x0FF00000
    #define UART1_CTRL_REG_TIMEOUT_WAIT_SHIFT 20
    #define UART1_CTRL_REG_SOFT_RESET_MASK 0x10000000
    #define UART1_CTRL_REG_SOFT_RESET_SHIFT 28
    #define UART1_CTRL_REG_AUTO_FLUSH_MASK 0x80000000
    #define UART1_CTRL_REG_AUTO_FLUSH_SHIFT 31
#define  UART1_INFO 0xF490
    #define UART1_INFO_RX_FIFO_ENTRIES_MASK 0x0000003F
    #define UART1_INFO_RX_FIFO_ENTRIES_SHIFT 0
    #define UART1_INFO_TX_FIFO_ENTRIES_MASK 0x00003F00
    #define UART1_INFO_TX_FIFO_ENTRIES_SHIFT 8
    #define UART1_INFO_BAUD_DIVLSB_MASK 0x00FF0000
    #define UART1_INFO_BAUD_DIVLSB_SHIFT 16
#define  UART1_INTEN_DIVMSB 0xF454
    #define UART1_INTEN_DIVMSB_INTEN_DIVMSB_DATA_MASK 0x000000FF
    #define UART1_INTEN_DIVMSB_INTEN_DIVMSB_DATA_SHIFT 0
#define  UART1_INTID_FIFOCTRL 0xF458
    #define UART1_INTID_FIFOCTRL_INTID_FIFOCTRL_DATA_MASK 0x000000FF
    #define UART1_INTID_FIFOCTRL_INTID_FIFOCTRL_DATA_SHIFT 0
#define  UART1_INT_MASK 0xF48C
    #define UART1_INT_MASK_RECIEVE_DATA_RDY_MASK 0x00000001
    #define UART1_INT_MASK_RECIEVE_DATA_RDY_SHIFT 0
    #define UART1_INT_MASK_TRANSMIT_DONE_EMPTY_MASK 0x00000002
    #define UART1_INT_MASK_TRANSMIT_DONE_EMPTY_SHIFT 1
    #define UART1_INT_MASK_RECIVER_LINE_MASK 0x00000004
    #define UART1_INT_MASK_RECIVER_LINE_SHIFT 2
    #define UART1_INT_MASK_MODEM_MASK 0x00000008
    #define UART1_INT_MASK_MODEM_SHIFT 3
    #define UART1_INT_MASK_TIMEOUT_MASK 0x00000010
    #define UART1_INT_MASK_TIMEOUT_SHIFT 4
#define  UART1_INT_STATUS 0xF488
    #define UART1_INT_STATUS_RECIEVE_DATA_RDY_MASK 0x00000001
    #define UART1_INT_STATUS_RECIEVE_DATA_RDY_SHIFT 0
    #define UART1_INT_STATUS_TRANSMIT_DONE_EMPTY_MASK 0x00000002
    #define UART1_INT_STATUS_TRANSMIT_DONE_EMPTY_SHIFT 1
    #define UART1_INT_STATUS_RECIVER_LINE_MASK 0x00000004
    #define UART1_INT_STATUS_RECIVER_LINE_SHIFT 2
    #define UART1_INT_STATUS_MODEM_MASK 0x00000008
    #define UART1_INT_STATUS_MODEM_SHIFT 3
    #define UART1_INT_STATUS_TIMEOUT_MASK 0x00000010
    #define UART1_INT_STATUS_TIMEOUT_SHIFT 4
#define  UART1_LINE_CTRL 0xF45C
    #define UART1_LINE_CTRL_CHAR_LEN_MASK 0x00000003
    #define UART1_LINE_CTRL_CHAR_LEN_SHIFT 0
    #define UART1_LINE_CTRL_STOP_BITS_MASK 0x00000004
    #define UART1_LINE_CTRL_STOP_BITS_SHIFT 2
    #define UART1_LINE_CTRL_PARITY_EN_MASK 0x00000008
    #define UART1_LINE_CTRL_PARITY_EN_SHIFT 3
    #define UART1_LINE_CTRL_EVEN_PARITY_MASK 0x00000010
    #define UART1_LINE_CTRL_EVEN_PARITY_SHIFT 4
    #define UART1_LINE_CTRL_STICK_PARITY_MASK 0x00000020
    #define UART1_LINE_CTRL_STICK_PARITY_SHIFT 5
    #define UART1_LINE_CTRL_BREAK_COND_MASK 0x00000040
    #define UART1_LINE_CTRL_BREAK_COND_SHIFT 6
    #define UART1_LINE_CTRL_DIVISOR_ACCESS_MASK 0x00000080
    #define UART1_LINE_CTRL_DIVISOR_ACCESS_SHIFT 7
#define  UART1_LINE_STATUS 0xF464
    #define UART1_LINE_STATUS_RECIEVE_RDY_MASK 0x00000001
    #define UART1_LINE_STATUS_RECIEVE_RDY_SHIFT 0
    #define UART1_LINE_STATUS_OVERRUN_MASK 0x00000002
    #define UART1_LINE_STATUS_OVERRUN_SHIFT 1
    #define UART1_LINE_STATUS_PARITY_ERR_MASK 0x00000004
    #define UART1_LINE_STATUS_PARITY_ERR_SHIFT 2
    #define UART1_LINE_STATUS_FRAME_ERR_MASK 0x00000008
    #define UART1_LINE_STATUS_FRAME_ERR_SHIFT 3
    #define UART1_LINE_STATUS_BREAK_IND_MASK 0x00000010
    #define UART1_LINE_STATUS_BREAK_IND_SHIFT 4
    #define UART1_LINE_STATUS_TF_EMPTY_MASK 0x00000020
    #define UART1_LINE_STATUS_TF_EMPTY_SHIFT 5
    #define UART1_LINE_STATUS_TRANS_EMPTY_MASK 0x00000040
    #define UART1_LINE_STATUS_TRANS_EMPTY_SHIFT 6
    #define UART1_LINE_STATUS_ERROR_MASK 0x00000080
    #define UART1_LINE_STATUS_ERROR_SHIFT 7
#define  UART1_MODEM_CTRL 0xF468
    #define UART1_MODEM_CTRL_DATA_TERM_RDY_MASK 0x00000001
    #define UART1_MODEM_CTRL_DATA_TERM_RDY_SHIFT 0
    #define UART1_MODEM_CTRL_REQ_TO_SEND_MASK 0x00000002
    #define UART1_MODEM_CTRL_REQ_TO_SEND_SHIFT 1
    #define UART1_MODEM_CTRL_USER_OUTPUT_MASK 0x00000004
    #define UART1_MODEM_CTRL_USER_OUTPUT_SHIFT 2
    #define UART1_MODEM_CTRL_USER_OUTPUT2_MASK 0x00000008
    #define UART1_MODEM_CTRL_USER_OUTPUT2_SHIFT 3
#define  UART1_MODEM_STATUS 0xF460
    #define UART1_MODEM_STATUS_CTSN_CHANGED_MASK 0x00000001
    #define UART1_MODEM_STATUS_CTSN_CHANGED_SHIFT 0
    #define UART1_MODEM_STATUS_DSRN_CHANGED_MASK 0x00000002
    #define UART1_MODEM_STATUS_DSRN_CHANGED_SHIFT 1
    #define UART1_MODEM_STATUS_RIN_RISING_EDGE_MASK 0x00000004
    #define UART1_MODEM_STATUS_RIN_RISING_EDGE_SHIFT 2
    #define UART1_MODEM_STATUS_DCDN_CHANGED_MASK 0x00000008
    #define UART1_MODEM_STATUS_DCDN_CHANGED_SHIFT 3
    #define UART1_MODEM_STATUS_CLEAR_TO_SEND_MASK 0x00000010
    #define UART1_MODEM_STATUS_CLEAR_TO_SEND_SHIFT 4
    #define UART1_MODEM_STATUS_DATA_SEND_REQ_MASK 0x00000020
    #define UART1_MODEM_STATUS_DATA_SEND_REQ_SHIFT 5
    #define UART1_MODEM_STATUS_RING_IND_MASK 0x00000040
    #define UART1_MODEM_STATUS_RING_IND_SHIFT 6
    #define UART1_MODEM_STATUS_DATA_CAR_DETECT_MASK 0x00000080
    #define UART1_MODEM_STATUS_DATA_CAR_DETECT_SHIFT 7
#define  UART1_RING_BASE 0xF470
    #define UART1_RING_BASE_BASE_MASK 0x7FFFFFF8
    #define UART1_RING_BASE_BASE_SHIFT 3
#define  UART1_RING_HEAD 0xF474
    #define UART1_RING_HEAD_HEAD_MASK 0x00003FFF
    #define UART1_RING_HEAD_HEAD_SHIFT 0
#define  UART1_RING_SIZE 0xF47C
    #define UART1_RING_SIZE_SIZE_MASK 0x00003FFF
    #define UART1_RING_SIZE_SIZE_SHIFT 0
#define  UART1_RING_TAIL 0xF478
    #define UART1_RING_TAIL_TAIL_MASK 0x00003FFF
    #define UART1_RING_TAIL_TAIL_SHIFT 0
#define  UART1_RX_TX_DIVLSB 0xF450
    #define UART1_RX_TX_DIVLSB_RX_TX_LSB_DATA_MASK 0x000000FF
    #define UART1_RX_TX_DIVLSB_RX_TX_LSB_DATA_SHIFT 0
#define  UART1_XMIT_BASE 0xF480
    #define UART1_XMIT_BASE_BASE_MASK 0x7FFFFFF8
    #define UART1_XMIT_BASE_BASE_SHIFT 3
#define  UART1_XMIT_SIZE 0xF484
    #define UART1_XMIT_SIZE_SIZE_MASK 0x00003FFF
    #define UART1_XMIT_SIZE_SIZE_SHIFT 0
#define  USBD_ACK 0x25D4
    #define SETUP_CMD_EMPTY_ACK_MASK 0x00000001
    #define SETUP_CMD_EMPTY_ACK_SHIFT 0
    #define IN_DATA_FIFO_FULL_ACK_MASK 0x00000002
    #define IN_DATA_FIFO_FULL_ACK_SHIFT 1
    #define OUT_DATA_FIFO_EMPTY_ACK_MASK 0x00000004
    #define OUT_DATA_FIFO_EMPTY_ACK_SHIFT 2
    #define INT_IN_FIFO_FULL_ACK_MASK 0x00000008
    #define INT_IN_FIFO_FULL_ACK_SHIFT 3
#define  USBD_BULKIN0_CTRL 0x2440
    #define USBD_BULKIN0_CTRL_CONFIG_MASK 0x0000000F
    #define USBD_BULKIN0_CTRL_CONFIG_SHIFT 0
    #define USBD_BULKIN0_CTRL_INTERFACE_MASK 0x000000F0
    #define USBD_BULKIN0_CTRL_INTERFACE_SHIFT 4
    #define USBD_BULKIN0_CTRL_ALTERNATE_MASK 0x00000F00
    #define USBD_BULKIN0_CTRL_ALTERNATE_SHIFT 8
    #define USBD_BULKIN0_CTRL_EP_NUM_MASK 0x0000F000
    #define USBD_BULKIN0_CTRL_EP_NUM_SHIFT 12
    #define USBD_BULKIN0_CTRL_PKT_SIZE_MASK 0x03FF0000
    #define USBD_BULKIN0_CTRL_PKT_SIZE_SHIFT 16
    #define USBD_BULKIN0_CTRL_ENABLE_MASK 0x10000000
    #define USBD_BULKIN0_CTRL_ENABLE_SHIFT 28
#define  USBD_BULKIN0_CUR_STATUS 0x2454
    #define USBD_BULKIN0_CUR_STATUS_CUR_PKT_SOP_MASK 0x7FFFFFFF
    #define USBD_BULKIN0_CUR_STATUS_CUR_PKT_SOP_SHIFT 0
#define  USBD_BULKIN0_DESC_FIFO_ADR_RD 0x244C
    #define USBD_BULKIN0_DESC_FIFO_ADR_RD_BASE_ADDR_MASK 0x7FFFFFFF
    #define USBD_BULKIN0_DESC_FIFO_ADR_RD_BASE_ADDR_SHIFT 0
#define  USBD_BULKIN0_DESC_FIFO_ADR_WR 0x2444
    #define USBD_BULKIN0_DESC_FIFO_ADR_WR_BASE_ADDR_MASK 0x7FFFFFFF
    #define USBD_BULKIN0_DESC_FIFO_ADR_WR_BASE_ADDR_SHIFT 0
#define  USBD_BULKIN0_DESC_FIFO_LOAD 0x2448
    #define USBD_BULKIN0_DESC_FIFO_LOAD_MAX_SIZE_MASK 0x0000FFFF
    #define USBD_BULKIN0_DESC_FIFO_LOAD_MAX_SIZE_SHIFT 0
    #define USBD_BULKIN0_DESC_FIFO_LOAD_INT_EN_MASK 0x01000000
    #define USBD_BULKIN0_DESC_FIFO_LOAD_INT_EN_SHIFT 24
#define  USBD_BULKIN0_DESC_FIFO_POP 0x2450
    #define USBD_BULKIN0_DESC_FIFO_POP_MAX_SIZE_MASK 0x0000FFFF
    #define USBD_BULKIN0_DESC_FIFO_POP_MAX_SIZE_SHIFT 0
    #define USBD_BULKIN0_DESC_FIFO_POP_INT_EN_MASK 0x01000000
    #define USBD_BULKIN0_DESC_FIFO_POP_INT_EN_SHIFT 24
#define  USBD_BULKIN0_STATUS1 0x2458
    #define USBD_BULKIN0_STATUS1_REMAIN_SIZE_MASK 0x0000FFFF
    #define USBD_BULKIN0_STATUS1_REMAIN_SIZE_SHIFT 0
    #define USBD_BULKIN0_STATUS1_FILLED_BYTES_MASK 0x03FF0000
    #define USBD_BULKIN0_STATUS1_FILLED_BYTES_SHIFT 16
    #define USBD_BULKIN0_STATUS1_DESC_EMPTY_MASK 0x10000000
    #define USBD_BULKIN0_STATUS1_DESC_EMPTY_SHIFT 28
    #define USBD_BULKIN0_STATUS1_ENTRY_FINISH_MASK 0x20000000
    #define USBD_BULKIN0_STATUS1_ENTRY_FINISH_SHIFT 29
    #define USBD_BULKIN0_STATUS1_DESC_FULL_MASK 0x40000000
    #define USBD_BULKIN0_STATUS1_DESC_FULL_SHIFT 30
    #define USBD_BULKIN0_STATUS1_BULKBUF_EMPTY_MASK 0x80000000
    #define USBD_BULKIN0_STATUS1_BULKBUF_EMPTY_SHIFT 31
#define  USBD_BULKIN0_STATUS2 0x245C
    #define USBD_BULKIN0_STATUS2_FINISHED_ENTRIES_MASK 0x70000000
    #define USBD_BULKIN0_STATUS2_FINISHED_ENTRIES_SHIFT 28
#define  USBD_BULKIN1_CTRL 0x2460
    #define USBD_BULKIN1_CTRL_CONFIG_MASK 0x0000000F
    #define USBD_BULKIN1_CTRL_CONFIG_SHIFT 0
    #define USBD_BULKIN1_CTRL_INTERFACE_MASK 0x000000F0
    #define USBD_BULKIN1_CTRL_INTERFACE_SHIFT 4
    #define USBD_BULKIN1_CTRL_ALTERNATE_MASK 0x00000F00
    #define USBD_BULKIN1_CTRL_ALTERNATE_SHIFT 8
    #define USBD_BULKIN1_CTRL_EP_NUM_MASK 0x0000F000
    #define USBD_BULKIN1_CTRL_EP_NUM_SHIFT 12
    #define USBD_BULKIN1_CTRL_PKT_SIZE_MASK 0x03FF0000
    #define USBD_BULKIN1_CTRL_PKT_SIZE_SHIFT 16
    #define USBD_BULKIN1_CTRL_ENABLE_MASK 0x10000000
    #define USBD_BULKIN1_CTRL_ENABLE_SHIFT 28
#define  USBD_BULKIN1_CUR_STATUS 0x2474
    #define USBD_BULKIN1_CUR_STATUS_CUR_PKT_SOP_MASK 0x7FFFFFFF
    #define USBD_BULKIN1_CUR_STATUS_CUR_PKT_SOP_SHIFT 0
#define  USBD_BULKIN1_DESC_FIFO_ADR_RD 0x246C
    #define USBD_BULKIN1_DESC_FIFO_ADR_RD_BASE_ADDR_MASK 0x7FFFFFFF
    #define USBD_BULKIN1_DESC_FIFO_ADR_RD_BASE_ADDR_SHIFT 0
#define  USBD_BULKIN1_DESC_FIFO_ADR_WR 0x2464
    #define USBD_BULKIN1_DESC_FIFO_ADR_WR_BASE_ADDR_MASK 0x7FFFFFFF
    #define USBD_BULKIN1_DESC_FIFO_ADR_WR_BASE_ADDR_SHIFT 0
#define  USBD_BULKIN1_DESC_FIFO_LOAD 0x2468
    #define USBD_BULKIN1_DESC_FIFO_LOAD_MAX_SIZE_MASK 0x0000FFFF
    #define USBD_BULKIN1_DESC_FIFO_LOAD_MAX_SIZE_SHIFT 0
    #define USBD_BULKIN1_DESC_FIFO_LOAD_INT_EN_MASK 0x01000000
    #define USBD_BULKIN1_DESC_FIFO_LOAD_INT_EN_SHIFT 24
#define  USBD_BULKIN1_DESC_FIFO_POP 0x2470
    #define USBD_BULKIN1_DESC_FIFO_POP_MAX_SIZE_MASK 0x0000FFFF
    #define USBD_BULKIN1_DESC_FIFO_POP_MAX_SIZE_SHIFT 0
    #define USBD_BULKIN1_DESC_FIFO_POP_INT_EN_MASK 0x01000000
    #define USBD_BULKIN1_DESC_FIFO_POP_INT_EN_SHIFT 24
#define  USBD_BULKIN1_STATUS1 0x2478
    #define USBD_BULKIN1_STATUS1_REMAIN_SIZE_MASK 0x0000FFFF
    #define USBD_BULKIN1_STATUS1_REMAIN_SIZE_SHIFT 0
    #define USBD_BULKIN1_STATUS1_FILLED_BYTES_MASK 0x03FF0000
    #define USBD_BULKIN1_STATUS1_FILLED_BYTES_SHIFT 16
    #define USBD_BULKIN1_STATUS1_DESC_EMPTY_MASK 0x10000000
    #define USBD_BULKIN1_STATUS1_DESC_EMPTY_SHIFT 28
    #define USBD_BULKIN1_STATUS1_ENTRY_FINISH_MASK 0x20000000
    #define USBD_BULKIN1_STATUS1_ENTRY_FINISH_SHIFT 29
    #define USBD_BULKIN1_STATUS1_DESC_FULL_MASK 0x40000000
    #define USBD_BULKIN1_STATUS1_DESC_FULL_SHIFT 30
    #define USBD_BULKIN1_STATUS1_BULKBUF_EMPTY_MASK 0x80000000
    #define USBD_BULKIN1_STATUS1_BULKBUF_EMPTY_SHIFT 31
#define  USBD_BULKIN1_STATUS2 0x247C
    #define USBD_BULKIN1_STATUS2_FINISHED_ENTRIES_MASK 0x70000000
    #define USBD_BULKIN1_STATUS2_FINISHED_ENTRIES_SHIFT 28
#define  USBD_BULKIN2_CTRL 0x2480
    #define USBD_BULKIN2_CTRL_CONFIG_MASK 0x0000000F
    #define USBD_BULKIN2_CTRL_CONFIG_SHIFT 0
    #define USBD_BULKIN2_CTRL_INTERFACE_MASK 0x000000F0
    #define USBD_BULKIN2_CTRL_INTERFACE_SHIFT 4
    #define USBD_BULKIN2_CTRL_ALTERNATE_MASK 0x00000F00
    #define USBD_BULKIN2_CTRL_ALTERNATE_SHIFT 8
    #define USBD_BULKIN2_CTRL_EP_NUM_MASK 0x0000F000
    #define USBD_BULKIN2_CTRL_EP_NUM_SHIFT 12
    #define USBD_BULKIN2_CTRL_PKT_SIZE_MASK 0x03FF0000
    #define USBD_BULKIN2_CTRL_PKT_SIZE_SHIFT 16
    #define USBD_BULKIN2_CTRL_ENABLE_MASK 0x10000000
    #define USBD_BULKIN2_CTRL_ENABLE_SHIFT 28
#define  USBD_BULKIN2_CUR_STATUS 0x2494
    #define USBD_BULKIN2_CUR_STATUS_CUR_PKT_SOP_MASK 0x7FFFFFFF
    #define USBD_BULKIN2_CUR_STATUS_CUR_PKT_SOP_SHIFT 0
#define  USBD_BULKIN2_DESC_FIFO_ADR_RD 0x248C
    #define USBD_BULKIN2_DESC_FIFO_ADR_RD_BASE_ADDR_MASK 0x7FFFFFFF
    #define USBD_BULKIN2_DESC_FIFO_ADR_RD_BASE_ADDR_SHIFT 0
#define  USBD_BULKIN2_DESC_FIFO_ADR_WR 0x2484
    #define USBD_BULKIN2_DESC_FIFO_ADR_WR_BASE_ADDR_MASK 0x7FFFFFFF
    #define USBD_BULKIN2_DESC_FIFO_ADR_WR_BASE_ADDR_SHIFT 0
#define  USBD_BULKIN2_DESC_FIFO_LOAD 0x2488
    #define USBD_BULKIN2_DESC_FIFO_LOAD_MAX_SIZE_MASK 0x0000FFFF
    #define USBD_BULKIN2_DESC_FIFO_LOAD_MAX_SIZE_SHIFT 0
    #define USBD_BULKIN2_DESC_FIFO_LOAD_INT_EN_MASK 0x01000000
    #define USBD_BULKIN2_DESC_FIFO_LOAD_INT_EN_SHIFT 24
#define  USBD_BULKIN2_DESC_FIFO_POP 0x2490
    #define USBD_BULKIN2_DESC_FIFO_POP_MAX_SIZE_MASK 0x0000FFFF
    #define USBD_BULKIN2_DESC_FIFO_POP_MAX_SIZE_SHIFT 0
    #define USBD_BULKIN2_DESC_FIFO_POP_INT_EN_MASK 0x01000000
    #define USBD_BULKIN2_DESC_FIFO_POP_INT_EN_SHIFT 24
#define  USBD_BULKIN2_STATUS1 0x2498
    #define USBD_BULKIN2_STATUS1_REMAIN_SIZE_MASK 0x0000FFFF
    #define USBD_BULKIN2_STATUS1_REMAIN_SIZE_SHIFT 0
    #define USBD_BULKIN2_STATUS1_FILLED_BYTES_MASK 0x03FF0000
    #define USBD_BULKIN2_STATUS1_FILLED_BYTES_SHIFT 16
    #define USBD_BULKIN2_STATUS1_DESC_EMPTY_MASK 0x10000000
    #define USBD_BULKIN2_STATUS1_DESC_EMPTY_SHIFT 28
    #define USBD_BULKIN2_STATUS1_ENTRY_FINISH_MASK 0x20000000
    #define USBD_BULKIN2_STATUS1_ENTRY_FINISH_SHIFT 29
    #define USBD_BULKIN2_STATUS1_DESC_FULL_MASK 0x40000000
    #define USBD_BULKIN2_STATUS1_DESC_FULL_SHIFT 30
    #define USBD_BULKIN2_STATUS1_BULKBUF_EMPTY_MASK 0x80000000
    #define USBD_BULKIN2_STATUS1_BULKBUF_EMPTY_SHIFT 31
#define  USBD_BULKIN2_STATUS2 0x249C
    #define USBD_BULKIN2_STATUS2_FINISHED_ENTRIES_MASK 0x70000000
    #define USBD_BULKIN2_STATUS2_FINISHED_ENTRIES_SHIFT 28
#define  USBD_BULKIN3_CTRL 0x24A0
    #define USBD_BULKIN3_CTRL_CONFIG_MASK 0x0000000F
    #define USBD_BULKIN3_CTRL_CONFIG_SHIFT 0
    #define USBD_BULKIN3_CTRL_INTERFACE_MASK 0x000000F0
    #define USBD_BULKIN3_CTRL_INTERFACE_SHIFT 4
    #define USBD_BULKIN3_CTRL_ALTERNATE_MASK 0x00000F00
    #define USBD_BULKIN3_CTRL_ALTERNATE_SHIFT 8
    #define USBD_BULKIN3_CTRL_EP_NUM_MASK 0x0000F000
    #define USBD_BULKIN3_CTRL_EP_NUM_SHIFT 12
    #define USBD_BULKIN3_CTRL_PKT_SIZE_MASK 0x03FF0000
    #define USBD_BULKIN3_CTRL_PKT_SIZE_SHIFT 16
    #define USBD_BULKIN3_CTRL_ENABLE_MASK 0x10000000
    #define USBD_BULKIN3_CTRL_ENABLE_SHIFT 28
#define  USBD_BULKIN3_CUR_STATUS 0x24B4
    #define USBD_BULKIN3_CUR_STATUS_CUR_PKT_SOP_MASK 0x7FFFFFFF
    #define USBD_BULKIN3_CUR_STATUS_CUR_PKT_SOP_SHIFT 0
#define  USBD_BULKIN3_DESC_FIFO_ADR_RD 0x24AC
    #define USBD_BULKIN3_DESC_FIFO_ADR_RD_BASE_ADDR_MASK 0x7FFFFFFF
    #define USBD_BULKIN3_DESC_FIFO_ADR_RD_BASE_ADDR_SHIFT 0
#define  USBD_BULKIN3_DESC_FIFO_ADR_WR 0x24A4
    #define USBD_BULKIN3_DESC_FIFO_ADR_WR_BASE_ADDR_MASK 0x7FFFFFFF
    #define USBD_BULKIN3_DESC_FIFO_ADR_WR_BASE_ADDR_SHIFT 0
#define  USBD_BULKIN3_DESC_FIFO_LOAD 0x24A8
    #define USBD_BULKIN3_DESC_FIFO_LOAD_MAX_SIZE_MASK 0x0000FFFF
    #define USBD_BULKIN3_DESC_FIFO_LOAD_MAX_SIZE_SHIFT 0
    #define USBD_BULKIN3_DESC_FIFO_LOAD_INT_EN_MASK 0x01000000
    #define USBD_BULKIN3_DESC_FIFO_LOAD_INT_EN_SHIFT 24
#define  USBD_BULKIN3_DESC_FIFO_POP 0x24B0
    #define USBD_BULKIN3_DESC_FIFO_POP_MAX_SIZE_MASK 0x0000FFFF
    #define USBD_BULKIN3_DESC_FIFO_POP_MAX_SIZE_SHIFT 0
    #define USBD_BULKIN3_DESC_FIFO_POP_INT_EN_MASK 0x01000000
    #define USBD_BULKIN3_DESC_FIFO_POP_INT_EN_SHIFT 24
#define  USBD_BULKIN3_STATUS1 0x24B8
    #define USBD_BULKIN3_STATUS1_REMAIN_SIZE_MASK 0x0000FFFF
    #define USBD_BULKIN3_STATUS1_REMAIN_SIZE_SHIFT 0
    #define USBD_BULKIN3_STATUS1_FILLED_BYTES_MASK 0x03FF0000
    #define USBD_BULKIN3_STATUS1_FILLED_BYTES_SHIFT 16
    #define USBD_BULKIN3_STATUS1_DESC_EMPTY_MASK 0x10000000
    #define USBD_BULKIN3_STATUS1_DESC_EMPTY_SHIFT 28
    #define USBD_BULKIN3_STATUS1_ENTRY_FINISH_MASK 0x20000000
    #define USBD_BULKIN3_STATUS1_ENTRY_FINISH_SHIFT 29
    #define USBD_BULKIN3_STATUS1_DESC_FULL_MASK 0x40000000
    #define USBD_BULKIN3_STATUS1_DESC_FULL_SHIFT 30
    #define USBD_BULKIN3_STATUS1_BULKBUF_EMPTY_MASK 0x80000000
    #define USBD_BULKIN3_STATUS1_BULKBUF_EMPTY_SHIFT 31
#define  USBD_BULKIN3_STATUS2 0x24BC
    #define USBD_BULKIN3_STATUS2_FINISHED_ENTRIES_MASK 0x70000000
    #define USBD_BULKIN3_STATUS2_FINISHED_ENTRIES_SHIFT 28
#define  USBD_BULKIN4_CTRL 0x24C0
    #define USBD_BULKIN4_CTRL_CONFIG_MASK 0x0000000F
    #define USBD_BULKIN4_CTRL_CONFIG_SHIFT 0
    #define USBD_BULKIN4_CTRL_INTERFACE_MASK 0x000000F0
    #define USBD_BULKIN4_CTRL_INTERFACE_SHIFT 4
    #define USBD_BULKIN4_CTRL_ALTERNATE_MASK 0x00000F00
    #define USBD_BULKIN4_CTRL_ALTERNATE_SHIFT 8
    #define USBD_BULKIN4_CTRL_EP_NUM_MASK 0x0000F000
    #define USBD_BULKIN4_CTRL_EP_NUM_SHIFT 12
    #define USBD_BULKIN4_CTRL_PKT_SIZE_MASK 0x03FF0000
    #define USBD_BULKIN4_CTRL_PKT_SIZE_SHIFT 16
    #define USBD_BULKIN4_CTRL_ENABLE_MASK 0x10000000
    #define USBD_BULKIN4_CTRL_ENABLE_SHIFT 28
#define  USBD_BULKIN4_CUR_STATUS 0x24D4
    #define USBD_BULKIN4_CUR_STATUS_CUR_PKT_SOP_MASK 0x7FFFFFFF
    #define USBD_BULKIN4_CUR_STATUS_CUR_PKT_SOP_SHIFT 0
#define  USBD_BULKIN4_DESC_FIFO_ADR_RD 0x24CC
    #define USBD_BULKIN4_DESC_FIFO_ADR_RD_BASE_ADDR_MASK 0x7FFFFFFF
    #define USBD_BULKIN4_DESC_FIFO_ADR_RD_BASE_ADDR_SHIFT 0
#define  USBD_BULKIN4_DESC_FIFO_ADR_WR 0x24C4
    #define USBD_BULKIN4_DESC_FIFO_ADR_WR_BASE_ADDR_MASK 0x7FFFFFFF
    #define USBD_BULKIN4_DESC_FIFO_ADR_WR_BASE_ADDR_SHIFT 0
#define  USBD_BULKIN4_DESC_FIFO_LOAD 0x24C8
    #define USBD_BULKIN4_DESC_FIFO_LOAD_MAX_SIZE_MASK 0x0000FFFF
    #define USBD_BULKIN4_DESC_FIFO_LOAD_MAX_SIZE_SHIFT 0
    #define USBD_BULKIN4_DESC_FIFO_LOAD_INT_EN_MASK 0x01000000
    #define USBD_BULKIN4_DESC_FIFO_LOAD_INT_EN_SHIFT 24
#define  USBD_BULKIN4_DESC_FIFO_POP 0x24D0
    #define USBD_BULKIN4_DESC_FIFO_POP_MAX_SIZE_MASK 0x0000FFFF
    #define USBD_BULKIN4_DESC_FIFO_POP_MAX_SIZE_SHIFT 0
    #define USBD_BULKIN4_DESC_FIFO_POP_INT_EN_MASK 0x01000000
    #define USBD_BULKIN4_DESC_FIFO_POP_INT_EN_SHIFT 24
#define  USBD_BULKIN4_STATUS1 0x24D8
    #define USBD_BULKIN4_STATUS1_REMAIN_SIZE_MASK 0x0000FFFF
    #define USBD_BULKIN4_STATUS1_REMAIN_SIZE_SHIFT 0
    #define USBD_BULKIN4_STATUS1_FILLED_BYTES_MASK 0x03FF0000
    #define USBD_BULKIN4_STATUS1_FILLED_BYTES_SHIFT 16
    #define USBD_BULKIN4_STATUS1_DESC_EMPTY_MASK 0x10000000
    #define USBD_BULKIN4_STATUS1_DESC_EMPTY_SHIFT 28
    #define USBD_BULKIN4_STATUS1_ENTRY_FINISH_MASK 0x20000000
    #define USBD_BULKIN4_STATUS1_ENTRY_FINISH_SHIFT 29
    #define USBD_BULKIN4_STATUS1_DESC_FULL_MASK 0x40000000
    #define USBD_BULKIN4_STATUS1_DESC_FULL_SHIFT 30
    #define USBD_BULKIN4_STATUS1_BULKBUF_EMPTY_MASK 0x80000000
    #define USBD_BULKIN4_STATUS1_BULKBUF_EMPTY_SHIFT 31
#define  USBD_BULKIN4_STATUS2 0x24DC
    #define USBD_BULKIN4_STATUS2_FINISHED_ENTRIES_MASK 0x70000000
    #define USBD_BULKIN4_STATUS2_FINISHED_ENTRIES_SHIFT 28
#define  USBD_BULKOUT0_CTRL 0x24E0
    #define USBD_BULKOUT0_CTRL_CONFIG_MASK 0x0000000F
    #define USBD_BULKOUT0_CTRL_CONFIG_SHIFT 0
    #define USBD_BULKOUT0_CTRL_INTERFACE_MASK 0x000000F0
    #define USBD_BULKOUT0_CTRL_INTERFACE_SHIFT 4
    #define USBD_BULKOUT0_CTRL_ALTERNATE_MASK 0x00000F00
    #define USBD_BULKOUT0_CTRL_ALTERNATE_SHIFT 8
    #define USBD_BULKOUT0_CTRL_EP_NUM_MASK 0x0000F000
    #define USBD_BULKOUT0_CTRL_EP_NUM_SHIFT 12
    #define USBD_BULKOUT0_CTRL_PKT_SIZE_MASK 0x03FF0000
    #define USBD_BULKOUT0_CTRL_PKT_SIZE_SHIFT 16
    #define USBD_BULKOUT0_CTRL_ENABLE_MASK 0x10000000
    #define USBD_BULKOUT0_CTRL_ENABLE_SHIFT 28
#define  USBD_BULKOUT0_CUR_STATUS 0x24F4
    #define USBD_BULKOUT0_CUR_STATUS_CUR_PKT_SOP_MASK 0x7FFFFFFF
    #define USBD_BULKOUT0_CUR_STATUS_CUR_PKT_SOP_SHIFT 0
#define  USBD_BULKOUT0_DESC_FIFO_ADR_RD 0x24EC
    #define USBD_BULKOUT0_DESC_FIFO_ADR_RD_BASE_ADDR_MASK 0x7FFFFFFF
    #define USBD_BULKOUT0_DESC_FIFO_ADR_RD_BASE_ADDR_SHIFT 0
#define  USBD_BULKOUT0_DESC_FIFO_ADR_WR 0x24E4
    #define USBD_BULKOUT0_DESC_FIFO_ADR_WR_BASE_ADDR_MASK 0x7FFFFFFF
    #define USBD_BULKOUT0_DESC_FIFO_ADR_WR_BASE_ADDR_SHIFT 0
#define  USBD_BULKOUT0_DESC_FIFO_LOAD 0x24E8
    #define USBD_BULKOUT0_DESC_FIFO_LOAD_MAX_SIZE_MASK 0x0000FFFF
    #define USBD_BULKOUT0_DESC_FIFO_LOAD_MAX_SIZE_SHIFT 0
    #define USBD_BULKOUT0_DESC_FIFO_LOAD_INT_EN_MASK 0x01000000
    #define USBD_BULKOUT0_DESC_FIFO_LOAD_INT_EN_SHIFT 24
#define  USBD_BULKOUT0_DESC_FIFO_POP 0x24F0
    #define USBD_BULKOUT0_DESC_FIFO_POP_MAX_SIZE_MASK 0x0000FFFF
    #define USBD_BULKOUT0_DESC_FIFO_POP_MAX_SIZE_SHIFT 0
    #define USBD_BULKOUT0_DESC_FIFO_POP_INT_EN_MASK 0x01000000
    #define USBD_BULKOUT0_DESC_FIFO_POP_INT_EN_SHIFT 24
#define  USBD_BULKOUT0_STATUS1 0x24F8
    #define USBD_BULKOUT0_STATUS1_REMAIN_SIZE_MASK 0x0000FFFF
    #define USBD_BULKOUT0_STATUS1_REMAIN_SIZE_SHIFT 0
    #define USBD_BULKOUT0_STATUS1_FILLED_BYTES_MASK 0x03FF0000
    #define USBD_BULKOUT0_STATUS1_FILLED_BYTES_SHIFT 16
    #define USBD_BULKOUT0_STATUS1_DESC_EMPTY_MASK 0x10000000
    #define USBD_BULKOUT0_STATUS1_DESC_EMPTY_SHIFT 28
    #define USBD_BULKOUT0_STATUS1_ENTRY_FINISH_MASK 0x20000000
    #define USBD_BULKOUT0_STATUS1_ENTRY_FINISH_SHIFT 29
    #define USBD_BULKOUT0_STATUS1_DESC_FULL_MASK 0x40000000
    #define USBD_BULKOUT0_STATUS1_DESC_FULL_SHIFT 30
    #define USBD_BULKOUT0_STATUS1_BULKBUF_FULL_MASK 0x80000000
    #define USBD_BULKOUT0_STATUS1_BULKBUF_FULL_SHIFT 31
#define  USBD_BULKOUT0_STATUS2 0x24FC
    #define USBD_BULKOUT0_STATUS2_RCVD_BYTES_MASK 0x0000FFFF
    #define USBD_BULKOUT0_STATUS2_RCVD_BYTES_SHIFT 0
    #define USBD_BULKOUT0_STATUS2_FINISHED_ENTRIES_MASK 0x70000000
    #define USBD_BULKOUT0_STATUS2_FINISHED_ENTRIES_SHIFT 28
#define  USBD_BULKOUT1_CTRL 0x2500
    #define USBD_BULKOUT1_CTRL_CONFIG_MASK 0x0000000F
    #define USBD_BULKOUT1_CTRL_CONFIG_SHIFT 0
    #define USBD_BULKOUT1_CTRL_INTERFACE_MASK 0x000000F0
    #define USBD_BULKOUT1_CTRL_INTERFACE_SHIFT 4
    #define USBD_BULKOUT1_CTRL_ALTERNATE_MASK 0x00000F00
    #define USBD_BULKOUT1_CTRL_ALTERNATE_SHIFT 8
    #define USBD_BULKOUT1_CTRL_EP_NUM_MASK 0x0000F000
    #define USBD_BULKOUT1_CTRL_EP_NUM_SHIFT 12
    #define USBD_BULKOUT1_CTRL_PKT_SIZE_MASK 0x03FF0000
    #define USBD_BULKOUT1_CTRL_PKT_SIZE_SHIFT 16
    #define USBD_BULKOUT1_CTRL_ENABLE_MASK 0x10000000
    #define USBD_BULKOUT1_CTRL_ENABLE_SHIFT 28
#define  USBD_BULKOUT1_CUR_STATUS 0x2514
    #define USBD_BULKOUT1_CUR_STATUS_CUR_PKT_SOP_MASK 0x7FFFFFFF
    #define USBD_BULKOUT1_CUR_STATUS_CUR_PKT_SOP_SHIFT 0
#define  USBD_BULKOUT1_DESC_FIFO_ADR_RD 0x250C
    #define USBD_BULKOUT1_DESC_FIFO_ADR_RD_BASE_ADDR_MASK 0x7FFFFFFF
    #define USBD_BULKOUT1_DESC_FIFO_ADR_RD_BASE_ADDR_SHIFT 0
#define  USBD_BULKOUT1_DESC_FIFO_ADR_WR 0x2504
    #define USBD_BULKOUT1_DESC_FIFO_ADR_WR_BASE_ADDR_MASK 0x7FFFFFFF
    #define USBD_BULKOUT1_DESC_FIFO_ADR_WR_BASE_ADDR_SHIFT 0
#define  USBD_BULKOUT1_DESC_FIFO_LOAD 0x2508
    #define USBD_BULKOUT1_DESC_FIFO_LOAD_MAX_SIZE_MASK 0x0000FFFF
    #define USBD_BULKOUT1_DESC_FIFO_LOAD_MAX_SIZE_SHIFT 0
    #define USBD_BULKOUT1_DESC_FIFO_LOAD_INT_EN_MASK 0x01000000
    #define USBD_BULKOUT1_DESC_FIFO_LOAD_INT_EN_SHIFT 24
#define  USBD_BULKOUT1_DESC_FIFO_POP 0x2510
    #define USBD_BULKOUT1_DESC_FIFO_POP_MAX_SIZE_MASK 0x0000FFFF
    #define USBD_BULKOUT1_DESC_FIFO_POP_MAX_SIZE_SHIFT 0
    #define USBD_BULKOUT1_DESC_FIFO_POP_INT_EN_MASK 0x01000000
    #define USBD_BULKOUT1_DESC_FIFO_POP_INT_EN_SHIFT 24
#define  USBD_BULKOUT1_STATUS1 0x2518
    #define USBD_BULKOUT1_STATUS1_REMAIN_SIZE_MASK 0x0000FFFF
    #define USBD_BULKOUT1_STATUS1_REMAIN_SIZE_SHIFT 0
    #define USBD_BULKOUT1_STATUS1_FILLED_BYTES_MASK 0x03FF0000
    #define USBD_BULKOUT1_STATUS1_FILLED_BYTES_SHIFT 16
    #define USBD_BULKOUT1_STATUS1_DESC_EMPTY_MASK 0x10000000
    #define USBD_BULKOUT1_STATUS1_DESC_EMPTY_SHIFT 28
    #define USBD_BULKOUT1_STATUS1_ENTRY_FINISH_MASK 0x20000000
    #define USBD_BULKOUT1_STATUS1_ENTRY_FINISH_SHIFT 29
    #define USBD_BULKOUT1_STATUS1_DESC_FULL_MASK 0x40000000
    #define USBD_BULKOUT1_STATUS1_DESC_FULL_SHIFT 30
    #define USBD_BULKOUT1_STATUS1_BULKBUF_FULL_MASK 0x80000000
    #define USBD_BULKOUT1_STATUS1_BULKBUF_FULL_SHIFT 31
#define  USBD_BULKOUT1_STATUS2 0x251C
    #define USBD_BULKOUT1_STATUS2_RCVD_BYTES_MASK 0x0000FFFF
    #define USBD_BULKOUT1_STATUS2_RCVD_BYTES_SHIFT 0
    #define USBD_BULKOUT1_STATUS2_FINISHED_ENTRIES_MASK 0x70000000
    #define USBD_BULKOUT1_STATUS2_FINISHED_ENTRIES_SHIFT 28
#define  USBD_BULKOUT2_CTRL 0x2520
    #define USBD_BULKOUT2_CTRL_CONFIG_MASK 0x0000000F
    #define USBD_BULKOUT2_CTRL_CONFIG_SHIFT 0
    #define USBD_BULKOUT2_CTRL_INTERFACE_MASK 0x000000F0
    #define USBD_BULKOUT2_CTRL_INTERFACE_SHIFT 4
    #define USBD_BULKOUT2_CTRL_ALTERNATE_MASK 0x00000F00
    #define USBD_BULKOUT2_CTRL_ALTERNATE_SHIFT 8
    #define USBD_BULKOUT2_CTRL_EP_NUM_MASK 0x0000F000
    #define USBD_BULKOUT2_CTRL_EP_NUM_SHIFT 12
    #define USBD_BULKOUT2_CTRL_PKT_SIZE_MASK 0x03FF0000
    #define USBD_BULKOUT2_CTRL_PKT_SIZE_SHIFT 16
    #define USBD_BULKOUT2_CTRL_ENABLE_MASK 0x10000000
    #define USBD_BULKOUT2_CTRL_ENABLE_SHIFT 28
#define  USBD_BULKOUT2_CUR_STATUS 0x2534
    #define USBD_BULKOUT2_CUR_STATUS_CUR_PKT_SOP_MASK 0x7FFFFFFF
    #define USBD_BULKOUT2_CUR_STATUS_CUR_PKT_SOP_SHIFT 0
#define  USBD_BULKOUT2_DESC_FIFO_ADR_RD 0x252C
    #define USBD_BULKOUT2_DESC_FIFO_ADR_RD_BASE_ADDR_MASK 0x7FFFFFFF
    #define USBD_BULKOUT2_DESC_FIFO_ADR_RD_BASE_ADDR_SHIFT 0
#define  USBD_BULKOUT2_DESC_FIFO_ADR_WR 0x2524
    #define USBD_BULKOUT2_DESC_FIFO_ADR_WR_BASE_ADDR_MASK 0x7FFFFFFF
    #define USBD_BULKOUT2_DESC_FIFO_ADR_WR_BASE_ADDR_SHIFT 0
#define  USBD_BULKOUT2_DESC_FIFO_LOAD 0x2528
    #define USBD_BULKOUT2_DESC_FIFO_LOAD_MAX_SIZE_MASK 0x0000FFFF
    #define USBD_BULKOUT2_DESC_FIFO_LOAD_MAX_SIZE_SHIFT 0
    #define USBD_BULKOUT2_DESC_FIFO_LOAD_INT_EN_MASK 0x01000000
    #define USBD_BULKOUT2_DESC_FIFO_LOAD_INT_EN_SHIFT 24
#define  USBD_BULKOUT2_DESC_FIFO_POP 0x2530
    #define USBD_BULKOUT2_DESC_FIFO_POP_MAX_SIZE_MASK 0x0000FFFF
    #define USBD_BULKOUT2_DESC_FIFO_POP_MAX_SIZE_SHIFT 0
    #define USBD_BULKOUT2_DESC_FIFO_POP_INT_EN_MASK 0x01000000
    #define USBD_BULKOUT2_DESC_FIFO_POP_INT_EN_SHIFT 24
#define  USBD_BULKOUT2_STATUS1 0x2538
    #define USBD_BULKOUT2_STATUS1_REMAIN_SIZE_MASK 0x0000FFFF
    #define USBD_BULKOUT2_STATUS1_REMAIN_SIZE_SHIFT 0
    #define USBD_BULKOUT2_STATUS1_FILLED_BYTES_MASK 0x03FF0000
    #define USBD_BULKOUT2_STATUS1_FILLED_BYTES_SHIFT 16
    #define USBD_BULKOUT2_STATUS1_DESC_EMPTY_MASK 0x10000000
    #define USBD_BULKOUT2_STATUS1_DESC_EMPTY_SHIFT 28
    #define USBD_BULKOUT2_STATUS1_ENTRY_FINISH_MASK 0x20000000
    #define USBD_BULKOUT2_STATUS1_ENTRY_FINISH_SHIFT 29
    #define USBD_BULKOUT2_STATUS1_DESC_FULL_MASK 0x40000000
    #define USBD_BULKOUT2_STATUS1_DESC_FULL_SHIFT 30
    #define USBD_BULKOUT2_STATUS1_BULKBUF_FULL_MASK 0x80000000
    #define USBD_BULKOUT2_STATUS1_BULKBUF_FULL_SHIFT 31
#define  USBD_BULKOUT2_STATUS2 0x253C
    #define USBD_BULKOUT2_STATUS2_RCVD_BYTES_MASK 0x0000FFFF
    #define USBD_BULKOUT2_STATUS2_RCVD_BYTES_SHIFT 0
    #define USBD_BULKOUT2_STATUS2_FINISHED_ENTRIES_MASK 0x70000000
    #define USBD_BULKOUT2_STATUS2_FINISHED_ENTRIES_SHIFT 28
#define  USBD_BULKOUT3_CTRL 0x2540
    #define USBD_BULKOUT3_CTRL_CONFIG_MASK 0x0000000F
    #define USBD_BULKOUT3_CTRL_CONFIG_SHIFT 0
    #define USBD_BULKOUT3_CTRL_INTERFACE_MASK 0x000000F0
    #define USBD_BULKOUT3_CTRL_INTERFACE_SHIFT 4
    #define USBD_BULKOUT3_CTRL_ALTERNATE_MASK 0x00000F00
    #define USBD_BULKOUT3_CTRL_ALTERNATE_SHIFT 8
    #define USBD_BULKOUT3_CTRL_EP_NUM_MASK 0x0000F000
    #define USBD_BULKOUT3_CTRL_EP_NUM_SHIFT 12
    #define USBD_BULKOUT3_CTRL_PKT_SIZE_MASK 0x03FF0000
    #define USBD_BULKOUT3_CTRL_PKT_SIZE_SHIFT 16
    #define USBD_BULKOUT3_CTRL_ENABLE_MASK 0x10000000
    #define USBD_BULKOUT3_CTRL_ENABLE_SHIFT 28
#define  USBD_BULKOUT3_CUR_STATUS 0x2554
    #define USBD_BULKOUT3_CUR_STATUS_CUR_PKT_SOP_MASK 0x7FFFFFFF
    #define USBD_BULKOUT3_CUR_STATUS_CUR_PKT_SOP_SHIFT 0
#define  USBD_BULKOUT3_DESC_FIFO_ADR_RD 0x254C
    #define USBD_BULKOUT3_DESC_FIFO_ADR_RD_BASE_ADDR_MASK 0x7FFFFFFF
    #define USBD_BULKOUT3_DESC_FIFO_ADR_RD_BASE_ADDR_SHIFT 0
#define  USBD_BULKOUT3_DESC_FIFO_ADR_WR 0x2544
    #define USBD_BULKOUT3_DESC_FIFO_ADR_WR_BASE_ADDR_MASK 0x7FFFFFFF
    #define USBD_BULKOUT3_DESC_FIFO_ADR_WR_BASE_ADDR_SHIFT 0
#define  USBD_BULKOUT3_DESC_FIFO_LOAD 0x2548
    #define USBD_BULKOUT3_DESC_FIFO_LOAD_MAX_SIZE_MASK 0x0000FFFF
    #define USBD_BULKOUT3_DESC_FIFO_LOAD_MAX_SIZE_SHIFT 0
    #define USBD_BULKOUT3_DESC_FIFO_LOAD_INT_EN_MASK 0x01000000
    #define USBD_BULKOUT3_DESC_FIFO_LOAD_INT_EN_SHIFT 24
#define  USBD_BULKOUT3_DESC_FIFO_POP 0x2550
    #define USBD_BULKOUT3_DESC_FIFO_POP_MAX_SIZE_MASK 0x0000FFFF
    #define USBD_BULKOUT3_DESC_FIFO_POP_MAX_SIZE_SHIFT 0
    #define USBD_BULKOUT3_DESC_FIFO_POP_INT_EN_MASK 0x01000000
    #define USBD_BULKOUT3_DESC_FIFO_POP_INT_EN_SHIFT 24
#define  USBD_BULKOUT3_STATUS1 0x2558
    #define USBD_BULKOUT3_STATUS1_REMAIN_SIZE_MASK 0x0000FFFF
    #define USBD_BULKOUT3_STATUS1_REMAIN_SIZE_SHIFT 0
    #define USBD_BULKOUT3_STATUS1_FILLED_BYTES_MASK 0x03FF0000
    #define USBD_BULKOUT3_STATUS1_FILLED_BYTES_SHIFT 16
    #define USBD_BULKOUT3_STATUS1_DESC_EMPTY_MASK 0x10000000
    #define USBD_BULKOUT3_STATUS1_DESC_EMPTY_SHIFT 28
    #define USBD_BULKOUT3_STATUS1_ENTRY_FINISH_MASK 0x20000000
    #define USBD_BULKOUT3_STATUS1_ENTRY_FINISH_SHIFT 29
    #define USBD_BULKOUT3_STATUS1_DESC_FULL_MASK 0x40000000
    #define USBD_BULKOUT3_STATUS1_DESC_FULL_SHIFT 30
    #define USBD_BULKOUT3_STATUS1_BULKBUF_FULL_MASK 0x80000000
    #define USBD_BULKOUT3_STATUS1_BULKBUF_FULL_SHIFT 31
#define  USBD_BULKOUT3_STATUS2 0x255C
    #define USBD_BULKOUT3_STATUS2_RCVD_BYTES_MASK 0x0000FFFF
    #define USBD_BULKOUT3_STATUS2_RCVD_BYTES_SHIFT 0
    #define USBD_BULKOUT3_STATUS2_FINISHED_ENTRIES_MASK 0x70000000
    #define USBD_BULKOUT3_STATUS2_FINISHED_ENTRIES_SHIFT 28
#define  USBD_DEBUG 0x25C0
    #define USBD_DEBUG_DEBUG_DATA_MASK 0x000FFFFF
    #define USBD_DEBUG_DEBUG_DATA_SHIFT 0
#define  USBD_DUMMY_REG 0x25C4
    #define USBD_DUMMY_REG_DUMMY_BITS_MASK 0xFFFFFFFF
    #define USBD_DUMMY_REG_DUMMY_BITS_SHIFT 0
#define  USBD_EP0_CTRL 0x2400
    #define REG_ADDR_MASK 0x0000FFFF
    #define REG_ADDR_SHIFT 0
    #define REG_WOP_MASK 0x00010000
    #define REG_WOP_SHIFT 16
    #define REG_CSR_SEL_MASK 0x00060000
    #define REG_CSR_SEL_SHIFT 17
    #define USBD_EP0_CTRL_OP_MODE_MASK 0x30000000
    #define USBD_EP0_CTRL_OP_MODE_SHIFT 28
#define  USBD_EP0_CTRL1 0x25D0
    #define EP0_PKT_SIZE_MASK 0x0000007F
    #define EP0_PKT_SIZE_SHIFT 0
    #define EP0_IN_LEN_MASK 0x00007F00
    #define EP0_IN_LEN_SHIFT 8
    #define EP0_IN_FIFO_EMPTY_INT_EN_MASK 0x00010000
    #define EP0_IN_FIFO_EMPTY_INT_EN_SHIFT 16
#define  USBD_EP0_RD_DATA 0x240C
    #define EP0_RD_DATA_MASK 0xFFFFFFFF
    #define EP0_RD_DATA_SHIFT 0
#define  USBD_EP0_STATUS 0x2404
    #define OP_BUSY_MASK 0x00000001
    #define OP_BUSY_SHIFT 0
    #define EP0_OUT_LEN_MASK 0x00007F00
    #define EP0_OUT_LEN_SHIFT 8
#define  USBD_EP0_WR_DATA 0x2408
    #define EP0_WR_DATA_MASK 0xFFFFFFFF
    #define EP0_WR_DATA_SHIFT 0
#define  USBD_EP_TRANS_STATUS 0x2438
    #define EP0_VCI_TRANS_IDLE_MASK 0x00000001
    #define EP0_VCI_TRANS_IDLE_SHIFT 0
    #define BULKIN0_VCI_TRANS_IDLE_MASK 0x00000002
    #define BULKIN0_VCI_TRANS_IDLE_SHIFT 1
    #define BULKIN1_VCI_TRANS_IDLE_MASK 0x00000004
    #define BULKIN1_VCI_TRANS_IDLE_SHIFT 2
    #define BULKIN2_VCI_TRANS_IDLE_MASK 0x00000008
    #define BULKIN2_VCI_TRANS_IDLE_SHIFT 3
    #define BULKIN3_VCI_TRANS_IDLE_MASK 0x00000010
    #define BULKIN3_VCI_TRANS_IDLE_SHIFT 4
    #define BULKIN4_VCI_TRANS_IDLE_MASK 0x00000020
    #define BULKIN4_VCI_TRANS_IDLE_SHIFT 5
    #define BULKOUT0_VCI_TRANS_IDLE_MASK 0x00000040
    #define BULKOUT0_VCI_TRANS_IDLE_SHIFT 6
    #define BULKOUT1_VCI_TRANS_IDLE_MASK 0x00000080
    #define BULKOUT1_VCI_TRANS_IDLE_SHIFT 7
    #define BULKOUT2_VCI_TRANS_IDLE_MASK 0x00000100
    #define BULKOUT2_VCI_TRANS_IDLE_SHIFT 8
    #define BULKOUT3_VCI_TRANS_IDLE_MASK 0x00000200
    #define BULKOUT3_VCI_TRANS_IDLE_SHIFT 9
    #define INTIN0_VCI_TRANS_IDLE_MASK 0x00000400
    #define INTIN0_VCI_TRANS_IDLE_SHIFT 10
    #define ISOIN0_VCI_TRANS_IDLE_MASK 0x00000800
    #define ISOIN0_VCI_TRANS_IDLE_SHIFT 11
    #define ISOIN1_VCI_TRANS_IDLE_MASK 0x00001000
    #define ISOIN1_VCI_TRANS_IDLE_SHIFT 12
    #define EP0_FB_TRANS_IDLE_MASK 0x00002000
    #define EP0_FB_TRANS_IDLE_SHIFT 13
    #define BULKIN0_FB_TRANS_IDLE_MASK 0x00004000
    #define BULKIN0_FB_TRANS_IDLE_SHIFT 14
    #define BULKIN1_FB_TRANS_IDLE_MASK 0x00008000
    #define BULKIN1_FB_TRANS_IDLE_SHIFT 15
    #define BULKIN2_FB_TRANS_IDLE_MASK 0x00010000
    #define BULKIN2_FB_TRANS_IDLE_SHIFT 16
    #define BULKIN3_FB_TRANS_IDLE_MASK 0x00020000
    #define BULKIN3_FB_TRANS_IDLE_SHIFT 17
    #define BULKIN4_FB_TRANS_IDLE_MASK 0x00040000
    #define BULKIN4_FB_TRANS_IDLE_SHIFT 18
    #define BULKOUT0_FB_TRANS_IDLE_MASK 0x00080000
    #define BULKOUT0_FB_TRANS_IDLE_SHIFT 19
    #define BULKOUT1_FB_TRANS_IDLE_MASK 0x00100000
    #define BULKOUT1_FB_TRANS_IDLE_SHIFT 20
    #define BULKOUT2_FB_TRANS_IDLE_MASK 0x00200000
    #define BULKOUT2_FB_TRANS_IDLE_SHIFT 21
    #define BULKOUT3_FB_TRANS_IDLE_MASK 0x00400000
    #define BULKOUT3_FB_TRANS_IDLE_SHIFT 22
    #define ISOIN0_FB_TRANS_IDLE_MASK 0x00800000
    #define ISOIN0_FB_TRANS_IDLE_SHIFT 23
    #define ISOIN1_FB_TRANS_IDLE_MASK 0x01000000
    #define ISOIN1_FB_TRANS_IDLE_SHIFT 24
    #define EP0_REG_TRANS_IDLE_MASK 0x02000000
    #define EP0_REG_TRANS_IDLE_SHIFT 25
#define  USBD_HOST_INT_MASK 0x2414
    #define HOST_EP0_INT_EN_REG_RD_MASK 0x00000001
    #define HOST_EP0_INT_EN_REG_RD_SHIFT 0
    #define HOST_EP0_INT_EN_REG_WR_MASK 0x00000002
    #define HOST_EP0_INT_EN_REG_WR_SHIFT 1
    #define HOST_EP0_INT_EN_MEM_RD_MASK 0x00000004
    #define HOST_EP0_INT_EN_MEM_RD_SHIFT 2
    #define HOST_EP0_INT_EN_MEM_WR_MASK 0x00000008
    #define HOST_EP0_INT_EN_MEM_WR_SHIFT 3
    #define HOST_EP0_INT_EN_SETUP_RCVD_MASK 0x00000010
    #define HOST_EP0_INT_EN_SETUP_RCVD_SHIFT 4
    #define HOST_EP0_INT_EN_EP0_IN_EMPTY_MASK 0x00000020
    #define HOST_EP0_INT_EN_EP0_IN_EMPTY_SHIFT 5
    #define HOST_EP0_INT_EN_EP0_OUT_RCVD_MASK 0x00000040
    #define HOST_EP0_INT_EN_EP0_OUT_RCVD_SHIFT 6
    #define HOST_INT_EN_SUSPEND_MASK 0x00000080
    #define HOST_INT_EN_SUSPEND_SHIFT 7
    #define HOST_INT_EN_WAKEUP_MASK 0x00000100
    #define HOST_INT_EN_WAKEUP_SHIFT 8
    #define HOST_INT_EN_RESET_MASK 0x00000200
    #define HOST_INT_EN_RESET_SHIFT 9
    #define HOST_BULKIN0_INT_EN_TRANS_DONE_MASK 0x00000400
    #define HOST_BULKIN0_INT_EN_TRANS_DONE_SHIFT 10
    #define HOST_BULKIN1_INT_EN_TRANS_DONE_MASK 0x00000800
    #define HOST_BULKIN1_INT_EN_TRANS_DONE_SHIFT 11
    #define HOST_BULKIN2_INT_EN_TRANS_DONE_MASK 0x00001000
    #define HOST_BULKIN2_INT_EN_TRANS_DONE_SHIFT 12
    #define HOST_BULKIN3_INT_EN_TRANS_DONE_MASK 0x00002000
    #define HOST_BULKIN3_INT_EN_TRANS_DONE_SHIFT 13
    #define HOST_BULKIN4_INT_EN_TRANS_DONE_MASK 0x00004000
    #define HOST_BULKIN4_INT_EN_TRANS_DONE_SHIFT 14
    #define HOST_BULKOUT0_INT_EN_TRANS_DONE_MASK 0x00008000
    #define HOST_BULKOUT0_INT_EN_TRANS_DONE_SHIFT 15
    #define HOST_BULKOUT1_INT_EN_TRANS_DONE_MASK 0x00010000
    #define HOST_BULKOUT1_INT_EN_TRANS_DONE_SHIFT 16
    #define HOST_BULKOUT2_INT_EN_TRANS_DONE_MASK 0x00020000
    #define HOST_BULKOUT2_INT_EN_TRANS_DONE_SHIFT 17
    #define HOST_BULKOUT3_INT_EN_TRANS_DONE_MASK 0x00040000
    #define HOST_BULKOUT3_INT_EN_TRANS_DONE_SHIFT 18
    #define HOST_INTIN0_INT_EN_EMPTY_MASK 0x00080000
    #define HOST_INTIN0_INT_EN_EMPTY_SHIFT 19
    #define HOST_ISOIN0_INT_EN_TRANS_DONE_MASK 0x00100000
    #define HOST_ISOIN0_INT_EN_TRANS_DONE_SHIFT 20
    #define HOST_ISOIN1_INT_EN_TRANS_DONE_MASK 0x00200000
    #define HOST_ISOIN1_INT_EN_TRANS_DONE_SHIFT 21
    #define HOST_BULKOUT0_INT_EN_TRANS_ERR_MASK 0x00400000
    #define HOST_BULKOUT0_INT_EN_TRANS_ERR_SHIFT 22
    #define HOST_BULKOUT1_INT_EN_TRANS_ERR_MASK 0x00800000
    #define HOST_BULKOUT1_INT_EN_TRANS_ERR_SHIFT 23
    #define HOST_BULKOUT2_INT_EN_TRANS_ERR_MASK 0x01000000
    #define HOST_BULKOUT2_INT_EN_TRANS_ERR_SHIFT 24
    #define HOST_BULKOUT3_INT_EN_TRANS_ERR_MASK 0x02000000
    #define HOST_BULKOUT3_INT_EN_TRANS_ERR_SHIFT 25
    #define HOST_ISOIN0_INT_EN_TRANS_ERR_MASK 0x04000000
    #define HOST_ISOIN0_INT_EN_TRANS_ERR_SHIFT 26
    #define HOST_ISOIN1_INT_EN_TRANS_ERR_MASK 0x08000000
    #define HOST_ISOIN1_INT_EN_TRANS_ERR_SHIFT 27
    #define HOST_INT_EN_SPEED_MASK 0x10000000
    #define HOST_INT_EN_SPEED_SHIFT 28
    #define HOST_INT_EN_SETCONFIGURATION_MASK 0x20000000
    #define HOST_INT_EN_SETCONFIGURATION_SHIFT 29
    #define HOST_INT_EN_SETINTERFACE_MASK 0x40000000
    #define HOST_INT_EN_SETINTERFACE_SHIFT 30
#define  USBD_INTIN0_CTRL 0x2560
    #define USBD_INTIN0_CTRL_CONFIG_MASK 0x0000000F
    #define USBD_INTIN0_CTRL_CONFIG_SHIFT 0
    #define USBD_INTIN0_CTRL_INTERFACE_MASK 0x000000F0
    #define USBD_INTIN0_CTRL_INTERFACE_SHIFT 4
    #define USBD_INTIN0_CTRL_ALTERNATE_MASK 0x00000F00
    #define USBD_INTIN0_CTRL_ALTERNATE_SHIFT 8
    #define USBD_INTIN0_CTRL_EP_NUM_MASK 0x0000F000
    #define USBD_INTIN0_CTRL_EP_NUM_SHIFT 12
    #define INTIN0_PKT_LEN_MASK 0x007F0000
    #define INTIN0_PKT_LEN_SHIFT 16
    #define USBD_INTIN0_CTRL_ENABLE_MASK 0x10000000
    #define USBD_INTIN0_CTRL_ENABLE_SHIFT 28
    #define INTIN0_EMPTY_INT_EN_MASK 0x20000000
    #define INTIN0_EMPTY_INT_EN_SHIFT 29
#define  USBD_INTIN0_CUR_STATUS 0x2564
    #define INTIN0_FIFO_EMPTY_MASK 0x00000001
    #define INTIN0_FIFO_EMPTY_SHIFT 0
#define  USBD_INT_STATUS 0x2410
    #define EP0_INT_REG_RD_MASK 0x00000001
    #define EP0_INT_REG_RD_SHIFT 0
    #define EP0_INT_REG_WR_MASK 0x00000002
    #define EP0_INT_REG_WR_SHIFT 1
    #define EP0_INT_MEM_RD_MASK 0x00000004
    #define EP0_INT_MEM_RD_SHIFT 2
    #define EP0_INT_MEM_WR_MASK 0x00000008
    #define EP0_INT_MEM_WR_SHIFT 3
    #define EP0_INT_SETUP_RCVD_MASK 0x00000010
    #define EP0_INT_SETUP_RCVD_SHIFT 4
    #define EP0_INT_EP0_IN_EMPTY_MASK 0x00000020
    #define EP0_INT_EP0_IN_EMPTY_SHIFT 5
    #define EP0_INT_EP0_OUT_RCVD_MASK 0x00000040
    #define EP0_INT_EP0_OUT_RCVD_SHIFT 6
    #define INT_SUSPEND_MASK 0x00000080
    #define INT_SUSPEND_SHIFT 7
    #define INT_WAKEUP_MASK 0x00000100
    #define INT_WAKEUP_SHIFT 8
    #define INT_RESET_MASK 0x00000200
    #define INT_RESET_SHIFT 9
    #define BULKIN0_INT_TRANS_DONE_MASK 0x00000400
    #define BULKIN0_INT_TRANS_DONE_SHIFT 10
    #define BULKIN1_INT_TRANS_DONE_MASK 0x00000800
    #define BULKIN1_INT_TRANS_DONE_SHIFT 11
    #define BULKIN2_INT_TRANS_DONE_MASK 0x00001000
    #define BULKIN2_INT_TRANS_DONE_SHIFT 12
    #define BULKIN3_INT_TRANS_DONE_MASK 0x00002000
    #define BULKIN3_INT_TRANS_DONE_SHIFT 13
    #define BULKIN4_INT_TRANS_DONE_MASK 0x00004000
    #define BULKIN4_INT_TRANS_DONE_SHIFT 14
    #define BULKOUT0_INT_TRANS_DONE_MASK 0x00008000
    #define BULKOUT0_INT_TRANS_DONE_SHIFT 15
    #define BULKOUT1_INT_TRANS_DONE_MASK 0x00010000
    #define BULKOUT1_INT_TRANS_DONE_SHIFT 16
    #define BULKOUT2_INT_TRANS_DONE_MASK 0x00020000
    #define BULKOUT2_INT_TRANS_DONE_SHIFT 17
    #define BULKOUT3_INT_TRANS_DONE_MASK 0x00040000
    #define BULKOUT3_INT_TRANS_DONE_SHIFT 18
    #define INTIN0_INT_EMPTY_MASK 0x00080000
    #define INTIN0_INT_EMPTY_SHIFT 19
    #define ISOIN0_INT_TRANS_DONE_MASK 0x00100000
    #define ISOIN0_INT_TRANS_DONE_SHIFT 20
    #define ISOIN1_INT_TRANS_DONE_MASK 0x00200000
    #define ISOIN1_INT_TRANS_DONE_SHIFT 21
    #define BULKOUT0_INT_TRANS_ERR_MASK 0x00400000
    #define BULKOUT0_INT_TRANS_ERR_SHIFT 22
    #define BULKOUT1_INT_TRANS_ERR_MASK 0x00800000
    #define BULKOUT1_INT_TRANS_ERR_SHIFT 23
    #define BULKOUT2_INT_TRANS_ERR_MASK 0x01000000
    #define BULKOUT2_INT_TRANS_ERR_SHIFT 24
    #define BULKOUT3_INT_TRANS_ERR_MASK 0x02000000
    #define BULKOUT3_INT_TRANS_ERR_SHIFT 25
    #define ISOIN0_INT_TRANS_ERR_MASK 0x04000000
    #define ISOIN0_INT_TRANS_ERR_SHIFT 26
    #define ISOIN1_INT_TRANS_ERR_MASK 0x08000000
    #define ISOIN1_INT_TRANS_ERR_SHIFT 27
    #define INT_SPEED_MASK 0x10000000
    #define INT_SPEED_SHIFT 28
    #define INT_SETCONFIGURATION_MASK 0x20000000
    #define INT_SETCONFIGURATION_SHIFT 29
    #define INT_SETINTERFACE_MASK 0x40000000
    #define INT_SETINTERFACE_SHIFT 30
#define  USBD_ISOIN0_CTRL 0x2580
    #define USBD_ISOIN0_CTRL_PKT_OFFSET_MASK 0x0000FFF0
    #define USBD_ISOIN0_CTRL_PKT_OFFSET_SHIFT 4
    #define USBD_ISOIN0_CTRL_PKT_SIZE_MASK 0x07FF0000
    #define USBD_ISOIN0_CTRL_PKT_SIZE_SHIFT 16
    #define USBD_ISOIN0_CTRL_ENABLE_MASK 0x10000000
    #define USBD_ISOIN0_CTRL_ENABLE_SHIFT 28
#define  USBD_ISOIN0_CTRL1 0x259C
    #define USBD_ISOIN0_CTRL1_CONFIG_MASK 0x0000000F
    #define USBD_ISOIN0_CTRL1_CONFIG_SHIFT 0
    #define USBD_ISOIN0_CTRL1_INTERFACE_MASK 0x000000F0
    #define USBD_ISOIN0_CTRL1_INTERFACE_SHIFT 4
    #define USBD_ISOIN0_CTRL1_ALTERNATE_MASK 0x00000F00
    #define USBD_ISOIN0_CTRL1_ALTERNATE_SHIFT 8
    #define USBD_ISOIN0_CTRL1_EP_NUM_MASK 0x0000F000
    #define USBD_ISOIN0_CTRL1_EP_NUM_SHIFT 12
#define  USBD_ISOIN0_CUR_STATUS 0x2594
    #define USBD_ISOIN0_CUR_STATUS_FB_OFFSET_SOP_MASK 0x7FFFFFF0
    #define USBD_ISOIN0_CUR_STATUS_FB_OFFSET_SOP_SHIFT 4
#define  USBD_ISOIN0_DESC_FIFO_ADR_RD 0x258C
    #define USBD_ISOIN0_DESC_FIFO_ADR_RD_FB_OFFSET_MASK 0x7FFFFFF0
    #define USBD_ISOIN0_DESC_FIFO_ADR_RD_FB_OFFSET_SHIFT 4
#define  USBD_ISOIN0_DESC_FIFO_ADR_WR 0x2584
    #define USBD_ISOIN0_DESC_FIFO_ADR_WR_FB_OFFSET_MASK 0x7FFFFFF0
    #define USBD_ISOIN0_DESC_FIFO_ADR_WR_FB_OFFSET_SHIFT 4
#define  USBD_ISOIN0_DESC_FIFO_LOAD 0x2588
    #define USBD_ISOIN0_DESC_FIFO_LOAD_PKT_NUM_MASK 0x0000007F
    #define USBD_ISOIN0_DESC_FIFO_LOAD_PKT_NUM_SHIFT 0
    #define USBD_ISOIN0_DESC_FIFO_LOAD_INT_EN_MASK 0x00000080
    #define USBD_ISOIN0_DESC_FIFO_LOAD_INT_EN_SHIFT 7
#define  USBD_ISOIN0_DESC_FIFO_POP 0x2590
    #define USBD_ISOIN0_DESC_FIFO_POP_PKT_NUM_MASK 0x0000007F
    #define USBD_ISOIN0_DESC_FIFO_POP_PKT_NUM_SHIFT 0
    #define USBD_ISOIN0_DESC_FIFO_POP_INT_EN_MASK 0x00000080
    #define USBD_ISOIN0_DESC_FIFO_POP_INT_EN_SHIFT 7
#define  USBD_ISOIN0_STATUS1 0x2598
    #define USBD_ISOIN0_STATUS1_DESC_EMPTY_MASK 0x10000000
    #define USBD_ISOIN0_STATUS1_DESC_EMPTY_SHIFT 28
    #define USBD_ISOIN0_STATUS1_ENTRY_FINISH_MASK 0x20000000
    #define USBD_ISOIN0_STATUS1_ENTRY_FINISH_SHIFT 29
    #define USBD_ISOIN0_STATUS1_DESC_FULL_MASK 0x40000000
    #define USBD_ISOIN0_STATUS1_DESC_FULL_SHIFT 30
    #define USBD_ISOIN0_STATUS1_ISOFIFO_EMPTY_MASK 0x80000000
    #define USBD_ISOIN0_STATUS1_ISOFIFO_EMPTY_SHIFT 31
#define  USBD_ISOIN1_CTRL 0x25A0
    #define USBD_ISOIN1_CTRL_PKT_OFFSET_MASK 0x0000FFF0
    #define USBD_ISOIN1_CTRL_PKT_OFFSET_SHIFT 4
    #define USBD_ISOIN1_CTRL_PKT_SIZE_MASK 0x07FF0000
    #define USBD_ISOIN1_CTRL_PKT_SIZE_SHIFT 16
    #define USBD_ISOIN1_CTRL_ENABLE_MASK 0x10000000
    #define USBD_ISOIN1_CTRL_ENABLE_SHIFT 28
#define  USBD_ISOIN1_CTRL1 0x25BC
    #define USBD_ISOIN1_CTRL1_CONFIG_MASK 0x0000000F
    #define USBD_ISOIN1_CTRL1_CONFIG_SHIFT 0
    #define USBD_ISOIN1_CTRL1_INTERFACE_MASK 0x000000F0
    #define USBD_ISOIN1_CTRL1_INTERFACE_SHIFT 4
    #define USBD_ISOIN1_CTRL1_ALTERNATE_MASK 0x00000F00
    #define USBD_ISOIN1_CTRL1_ALTERNATE_SHIFT 8
    #define USBD_ISOIN1_CTRL1_EP_NUM_MASK 0x0000F000
    #define USBD_ISOIN1_CTRL1_EP_NUM_SHIFT 12
#define  USBD_ISOIN1_CUR_STATUS 0x25B4
    #define USBD_ISOIN1_CUR_STATUS_FB_OFFSET_SOP_MASK 0x7FFFFFF0
    #define USBD_ISOIN1_CUR_STATUS_FB_OFFSET_SOP_SHIFT 4
#define  USBD_ISOIN1_DESC_FIFO_ADR_RD 0x25AC
    #define USBD_ISOIN1_DESC_FIFO_ADR_RD_FB_OFFSET_MASK 0x7FFFFFF0
    #define USBD_ISOIN1_DESC_FIFO_ADR_RD_FB_OFFSET_SHIFT 4
#define  USBD_ISOIN1_DESC_FIFO_ADR_WR 0x25A4
    #define USBD_ISOIN1_DESC_FIFO_ADR_WR_FB_OFFSET_MASK 0x7FFFFFF0
    #define USBD_ISOIN1_DESC_FIFO_ADR_WR_FB_OFFSET_SHIFT 4
#define  USBD_ISOIN1_DESC_FIFO_LOAD 0x25A8
    #define USBD_ISOIN1_DESC_FIFO_LOAD_PKT_NUM_MASK 0x0000007F
    #define USBD_ISOIN1_DESC_FIFO_LOAD_PKT_NUM_SHIFT 0
    #define USBD_ISOIN1_DESC_FIFO_LOAD_INT_EN_MASK 0x00000080
    #define USBD_ISOIN1_DESC_FIFO_LOAD_INT_EN_SHIFT 7
#define  USBD_ISOIN1_DESC_FIFO_POP 0x25B0
    #define USBD_ISOIN1_DESC_FIFO_POP_PKT_NUM_MASK 0x0000007F
    #define USBD_ISOIN1_DESC_FIFO_POP_PKT_NUM_SHIFT 0
    #define USBD_ISOIN1_DESC_FIFO_POP_INT_EN_MASK 0x00000080
    #define USBD_ISOIN1_DESC_FIFO_POP_INT_EN_SHIFT 7
#define  USBD_ISOIN1_STATUS1 0x25B8
    #define USBD_ISOIN1_STATUS1_DESC_EMPTY_MASK 0x10000000
    #define USBD_ISOIN1_STATUS1_DESC_EMPTY_SHIFT 28
    #define USBD_ISOIN1_STATUS1_ENTRY_FINISH_MASK 0x20000000
    #define USBD_ISOIN1_STATUS1_ENTRY_FINISH_SHIFT 29
    #define USBD_ISOIN1_STATUS1_DESC_FULL_MASK 0x40000000
    #define USBD_ISOIN1_STATUS1_DESC_FULL_SHIFT 30
    #define USBD_ISOIN1_STATUS1_ISOFIFO_EMPTY_MASK 0x80000000
    #define USBD_ISOIN1_STATUS1_ISOFIFO_EMPTY_SHIFT 31
#define  USBD_MIPS_INT_MASK 0x2418
    #define MIPS_EP0_INT_EN_REG_RD_MASK 0x00000001
    #define MIPS_EP0_INT_EN_REG_RD_SHIFT 0
    #define MIPS_EP0_INT_EN_REG_WR_MASK 0x00000002
    #define MIPS_EP0_INT_EN_REG_WR_SHIFT 1
    #define MIPS_EP0_INT_EN_MEM_RD_MASK 0x00000004
    #define MIPS_EP0_INT_EN_MEM_RD_SHIFT 2
    #define MIPS_EP0_INT_EN_MEM_WR_MASK 0x00000008
    #define MIPS_EP0_INT_EN_MEM_WR_SHIFT 3
    #define MIPS_EP0_INT_EN_SETUP_RCVD_MASK 0x00000010
    #define MIPS_EP0_INT_EN_SETUP_RCVD_SHIFT 4
    #define MIPS_EP0_INT_EN_EP0_IN_EMPTY_MASK 0x00000020
    #define MIPS_EP0_INT_EN_EP0_IN_EMPTY_SHIFT 5
    #define MIPS_EP0_INT_EN_EP0_OUT_RCVD_MASK 0x00000040
    #define MIPS_EP0_INT_EN_EP0_OUT_RCVD_SHIFT 6
    #define MIPS_INT_EN_SUSPEND_MASK 0x00000080
    #define MIPS_INT_EN_SUSPEND_SHIFT 7
    #define MIPS_INT_EN_WAKEUP_MASK 0x00000100
    #define MIPS_INT_EN_WAKEUP_SHIFT 8
    #define MIPS_INT_EN_RESET_MASK 0x00000200
    #define MIPS_INT_EN_RESET_SHIFT 9
    #define MIPS_BULKIN0_INT_EN_TRANS_DONE_MASK 0x00000400
    #define MIPS_BULKIN0_INT_EN_TRANS_DONE_SHIFT 10
    #define MIPS_BULKIN1_INT_EN_TRANS_DONE_MASK 0x00000800
    #define MIPS_BULKIN1_INT_EN_TRANS_DONE_SHIFT 11
    #define MIPS_BULKIN2_INT_EN_TRANS_DONE_MASK 0x00001000
    #define MIPS_BULKIN2_INT_EN_TRANS_DONE_SHIFT 12
    #define MIPS_BULKIN3_INT_EN_TRANS_DONE_MASK 0x00002000
    #define MIPS_BULKIN3_INT_EN_TRANS_DONE_SHIFT 13
    #define MIPS_BULKIN4_INT_EN_TRANS_DONE_MASK 0x00004000
    #define MIPS_BULKIN4_INT_EN_TRANS_DONE_SHIFT 14
    #define MIPS_BULKOUT0_INT_EN_TRANS_DONE_MASK 0x00008000
    #define MIPS_BULKOUT0_INT_EN_TRANS_DONE_SHIFT 15
    #define MIPS_BULKOUT1_INT_EN_TRANS_DONE_MASK 0x00010000
    #define MIPS_BULKOUT1_INT_EN_TRANS_DONE_SHIFT 16
    #define MIPS_BULKOUT2_INT_EN_TRANS_DONE_MASK 0x00020000
    #define MIPS_BULKOUT2_INT_EN_TRANS_DONE_SHIFT 17
    #define MIPS_BULKOUT3_INT_EN_TRANS_DONE_MASK 0x00040000
    #define MIPS_BULKOUT3_INT_EN_TRANS_DONE_SHIFT 18
    #define MIPS_INTIN0_INT_EN_EMPTY_MASK 0x00080000
    #define MIPS_INTIN0_INT_EN_EMPTY_SHIFT 19
    #define MIPS_ISOIN0_INT_EN_TRANS_DONE_MASK 0x00100000
    #define MIPS_ISOIN0_INT_EN_TRANS_DONE_SHIFT 20
    #define MIPS_ISOIN1_INT_EN_TRANS_DONE_MASK 0x00200000
    #define MIPS_ISOIN1_INT_EN_TRANS_DONE_SHIFT 21
    #define MIPS_BULKOUT0_INT_EN_TRANS_ERR_MASK 0x00400000
    #define MIPS_BULKOUT0_INT_EN_TRANS_ERR_SHIFT 22
    #define MIPS_BULKOUT1_INT_EN_TRANS_ERR_MASK 0x00800000
    #define MIPS_BULKOUT1_INT_EN_TRANS_ERR_SHIFT 23
    #define MIPS_BULKOUT2_INT_EN_TRANS_ERR_MASK 0x01000000
    #define MIPS_BULKOUT2_INT_EN_TRANS_ERR_SHIFT 24
    #define MIPS_BULKOUT3_INT_EN_TRANS_ERR_MASK 0x02000000
    #define MIPS_BULKOUT3_INT_EN_TRANS_ERR_SHIFT 25
    #define MIPS_ISOIN0_INT_EN_TRANS_ERR_MASK 0x04000000
    #define MIPS_ISOIN0_INT_EN_TRANS_ERR_SHIFT 26
    #define MIPS_ISOIN1_INT_EN_TRANS_ERR_MASK 0x08000000
    #define MIPS_ISOIN1_INT_EN_TRANS_ERR_SHIFT 27
    #define MIPS_INT_EN_SPEED_MASK 0x10000000
    #define MIPS_INT_EN_SPEED_SHIFT 28
    #define MIPS_INT_EN_SETCONFIGURATION_MASK 0x20000000
    #define MIPS_INT_EN_SETCONFIGURATION_SHIFT 29
    #define MIPS_INT_EN_SETINTERFACE_MASK 0x40000000
    #define MIPS_INT_EN_SETINTERFACE_SHIFT 30
#define  USBD_PHY_CLK_CTRL 0x242C
    #define PHY_REFCLKDIV_MASK 0x00000003
    #define PHY_REFCLKDIV_SHIFT 0
    #define PHY_REFCLKSEL_MASK 0x0000000C
    #define PHY_REFCLKSEL_SHIFT 2
    #define PHY_COMMONONN_MASK 0x00000010
    #define PHY_COMMONONN_SHIFT 4
#define  USBD_PHY_CTRL 0x2430
    #define PHY_PORT0_H_D_MASK 0x00000001
    #define PHY_PORT0_H_D_SHIFT 0
    #define PHY_PORT1_H_D_MASK 0x00000002
    #define PHY_PORT1_H_D_SHIFT 1
    #define PHY_PORT0_RESET_MASK 0x00000010
    #define PHY_PORT0_RESET_SHIFT 4
    #define PHY_PORT1_RESET_MASK 0x00000020
    #define PHY_PORT1_RESET_SHIFT 5
    #define PHY_PORT0_VBUSVLDEXT_MASK 0x00000100
    #define PHY_PORT0_VBUSVLDEXT_SHIFT 8
    #define PHY_PORT1_VBUSVLDEXT_ENB_MASK 0x00000800
    #define PHY_PORT1_VBUSVLDEXT_ENB_SHIFT 11
    #define PHY_PORT0_SUSPENDM_MASK 0x00001000
    #define PHY_PORT0_SUSPENDM_SHIFT 12
    #define PHY_PORT1_SUSPENDM_ENB_MASK 0x00008000
    #define PHY_PORT1_SUSPENDM_ENB_SHIFT 15
    #define PHY_TX_ENABLE_N_MASK 0x00010000
    #define PHY_TX_ENABLE_N_SHIFT 16
    #define PHY_TX_BIT_STUFF_EN_MASK 0x00020000
    #define PHY_TX_BIT_STUFF_EN_SHIFT 17
    #define PHY_TX_BIT_STUFF_EN_H_MASK 0x00040000
    #define PHY_TX_BIT_STUFF_EN_H_SHIFT 18
    #define PHY_DM_PULLDOWN_MASK 0x00080000
    #define PHY_DM_PULLDOWN_SHIFT 19
    #define PHY_DP_PULLDOWN_MASK 0x00100000
    #define PHY_DP_PULLDOWN_SHIFT 20
    #define PHY_WORD_INTERFACE_MASK 0x00200000
    #define PHY_WORD_INTERFACE_SHIFT 21
    #define PHY_FS_DATA_EXT_MASK 0x00400000
    #define PHY_FS_DATA_EXT_SHIFT 22
    #define PHY_FS_SE0_EXT_MASK 0x00800000
    #define PHY_FS_SE0_EXT_SHIFT 23
    #define PHY_FS_XCVR_OWNER_MASK 0x01000000
    #define PHY_FS_XCVR_OWNER_SHIFT 24
    #define PHY_PORT0_SLEEPM_MASK 0x02000000
    #define PHY_PORT0_SLEEPM_SHIFT 25
    #define PHY_PORT1_SLEEPM_MASK 0x04000000
    #define PHY_PORT1_SLEEPM_SHIFT 26
#define  USBD_PHY_LOOPBACKDATA0 0x25FC
    #define PHY_LOOPBACKDATA0_MASK 0x0000FFFF
    #define PHY_LOOPBACKDATA0_SHIFT 0
    #define PHY_LOOPBACKDATA1_MASK 0xFFFF0000
    #define PHY_LOOPBACKDATA1_SHIFT 16
#define  USBD_PHY_LOOPBACKPATTERN 0x25F8
    #define PHY_LOOPBACKPATTERN_MASK 0x0000FFFF
    #define PHY_LOOPBACKPATTERN_SHIFT 0
#define  USBD_PHY_OVERRIDE0 0x25EC
    #define PHY_COMPDISTUNE0_MASK 0x00000007
    #define PHY_COMPDISTUNE0_SHIFT 0
    #define PHY_COMPDISTUNE1_MASK 0x00000070
    #define PHY_COMPDISTUNE1_SHIFT 4
    #define PHY_SQRXTUNE0_MASK 0x00070000
    #define PHY_SQRXTUNE0_SHIFT 16
    #define PHY_SQRXTUNE1_MASK 0x00700000
    #define PHY_SQRXTUNE1_SHIFT 20
#define  USBD_PHY_OVERRIDE1 0x25F0
    #define PHY_TXFSLSTUNE0_MASK 0x0000000F
    #define PHY_TXFSLSTUNE0_SHIFT 0
    #define PHY_TXFSLSTUNE1_MASK 0x000000F0
    #define PHY_TXFSLSTUNE1_SHIFT 4
    #define PHY_TXPREEMPHASISTUNE_MASK 0x00030000
    #define PHY_TXPREEMPHASISTUNE_SHIFT 16
    #define PHY_TXRISETUNE_MASK 0x00300000
    #define PHY_TXRISETUNE_SHIFT 20
#define  USBD_PHY_OVERRIDE2 0x25F4
    #define PHY_TXVREFTUNE0_MASK 0x0000000F
    #define PHY_TXVREFTUNE0_SHIFT 0
    #define PHY_TXVREFTUNE1_MASK 0x000000F0
    #define PHY_TXVREFTUNE1_SHIFT 4
    #define PHY_TXHSXVTUNE0_MASK 0x00030000
    #define PHY_TXHSXVTUNE0_SHIFT 16
    #define PHY_TXHSXVTUNE1_MASK 0x000C0000
    #define PHY_TXHSXVTUNE1_SHIFT 18
#define  USBD_PHY_STATUS 0x25E8
    #define PHY_TESTDATAOUT0_MASK 0x0000000F
    #define PHY_TESTDATAOUT0_SHIFT 0
    #define PHY_TESTDATAOUT1_MASK 0x000000F0
    #define PHY_TESTDATAOUT1_SHIFT 4
    #define PHY_BISTDONE_MASK 0x00010000
    #define PHY_BISTDONE_SHIFT 16
    #define PHY_BISTERROR_MASK 0x00020000
    #define PHY_BISTERROR_SHIFT 17
    #define PHY_FSLSRCV_MASK 0x00040000
    #define PHY_FSLSRCV_SHIFT 18
    #define PHY_FSVPLUS_MASK 0x00080000
    #define PHY_FSVPLUS_SHIFT 19
    #define PHY_FSVMINUS_MASK 0x00100000
    #define PHY_FSVMINUS_SHIFT 20
    #define PHY_LOOPBACKDONE0_MASK 0x00200000
    #define PHY_LOOPBACKDONE0_SHIFT 21
    #define PHY_LOOPBACKDONE1_MASK 0x00400000
    #define PHY_LOOPBACKDONE1_SHIFT 22
#define  USBD_PHY_TEST 0x2434
    #define PHY_TESTDATAIN0_MASK 0x000000FF
    #define PHY_TESTDATAIN0_SHIFT 0
    #define PHY_TESTADDR0_MASK 0x00000F00
    #define PHY_TESTADDR0_SHIFT 8
    #define PHY_TESTDATAOUTSEL0_MASK 0x00001000
    #define PHY_TESTDATAOUTSEL0_SHIFT 12
    #define PHY_TESTCLK0_MASK 0x00002000
    #define PHY_TESTCLK0_SHIFT 13
    #define PHY_TESTDATAIN1_MASK 0x00FF0000
    #define PHY_TESTDATAIN1_SHIFT 16
    #define PHY_TESTADDR1_MASK 0x0F000000
    #define PHY_TESTADDR1_SHIFT 24
    #define PHY_TESTDATAOUTSEL1_MASK 0x10000000
    #define PHY_TESTDATAOUTSEL1_SHIFT 28
    #define PHY_TESTCLK1_MASK 0x20000000
    #define PHY_TESTCLK1_SHIFT 29
    #define SS_SETCLR_RMTWKP_ENA_I_MASK 0x40000000
    #define SS_SETCLR_RMTWKP_ENA_I_SHIFT 30
    #define SS_SET_OPMODE_POR_I_MASK 0x80000000
    #define SS_SET_OPMODE_POR_I_SHIFT 31
#define  USBD_PHY_TEST2 0x25E4
    #define PHY_BISTEN_MASK 0x00000001
    #define PHY_BISTEN_SHIFT 0
    #define PHY_LSBIST_MASK 0x00000002
    #define PHY_LSBIST_SHIFT 1
    #define PHY_FSBIST_MASK 0x00000004
    #define PHY_FSBIST_SHIFT 2
    #define PHY_HSBIST_MASK 0x00000008
    #define PHY_HSBIST_SHIFT 3
    #define PHY_LOOPBACKENB_MASK 0x00000030
    #define PHY_LOOPBACKENB_SHIFT 4
    #define PHY_ATERESET_MASK 0x00000100
    #define PHY_ATERESET_SHIFT 8
    #define PHY_VATESTENB_MASK 0x00000200
    #define PHY_VATESTENB_SHIFT 9
#define  USBD_SETUP_CMD0 0x25C8
    #define USBD_SETUP_CMD0_DATA_MASK 0xFFFFFFFF
    #define USBD_SETUP_CMD0_DATA_SHIFT 0
#define  USBD_SETUP_CMD1 0x25CC
    #define USBD_SETUP_CMD1_DATA_MASK 0xFFFFFFFF
    #define USBD_SETUP_CMD1_DATA_SHIFT 0
#define  USBD_SOFT_RST 0x243C
    #define PHY_SOFT_RST_MASK 0x00000001
    #define PHY_SOFT_RST_SHIFT 0
    #define UDC20_SOFT_RST_MASK 0x00000002
    #define UDC20_SOFT_RST_SHIFT 1
    #define EP0_SOFT_RST_MASK 0x00000004
    #define EP0_SOFT_RST_SHIFT 2
    #define BULKIN0_SOFT_RST_MASK 0x00000008
    #define BULKIN0_SOFT_RST_SHIFT 3
    #define BULKIN1_SOFT_RST_MASK 0x00000010
    #define BULKIN1_SOFT_RST_SHIFT 4
    #define BULKIN2_SOFT_RST_MASK 0x00000020
    #define BULKIN2_SOFT_RST_SHIFT 5
    #define BULKIN3_SOFT_RST_MASK 0x00000040
    #define BULKIN3_SOFT_RST_SHIFT 6
    #define BULKIN4_SOFT_RST_MASK 0x00000080
    #define BULKIN4_SOFT_RST_SHIFT 7
    #define BULKOUT0_SOFT_RST_MASK 0x00000100
    #define BULKOUT0_SOFT_RST_SHIFT 8
    #define BULKOUT1_SOFT_RST_MASK 0x00000200
    #define BULKOUT1_SOFT_RST_SHIFT 9
    #define BULKOUT2_SOFT_RST_MASK 0x00000400
    #define BULKOUT2_SOFT_RST_SHIFT 10
    #define BULKOUT3_SOFT_RST_MASK 0x00000800
    #define BULKOUT3_SOFT_RST_SHIFT 11
    #define INTIN0_SOFT_RST_MASK 0x00001000
    #define INTIN0_SOFT_RST_SHIFT 12
    #define ISOIN0_SOFT_RST_MASK 0x00002000
    #define ISOIN0_SOFT_RST_SHIFT 13
    #define ISOIN1_SOFT_RST_MASK 0x00004000
    #define ISOIN1_SOFT_RST_SHIFT 14
    #define VCIF_SOFT_RST_MASK 0x00008000
    #define VCIF_SOFT_RST_SHIFT 15
    #define ARB_SOFT_RST_MASK 0x00010000
    #define ARB_SOFT_RST_SHIFT 16
#define  USBD_UDC20_CTRL 0x2420
    #define APP_PHYIF_8BIT_MASK 0x00000004
    #define APP_PHYIF_8BIT_SHIFT 2
    #define APP_SELF_PWR_MASK 0x00000008
    #define APP_SELF_PWR_SHIFT 3
    #define APP_SYNCCMD_SUP_MASK 0x00000010
    #define APP_SYNCCMD_SUP_SHIFT 4
    #define APP_SETDESC_SUP_MASK 0x00000020
    #define APP_SETDESC_SUP_SHIFT 5
    #define APP_DEV_RMTWKUP_MASK 0x00000040
    #define APP_DEV_RMTWKUP_SHIFT 6
    #define APP_RAM_IF_MASK 0x00000080
    #define APP_RAM_IF_SHIFT 7
    #define APP_TAT_RESP_MASK 0x00000100
    #define APP_TAT_RESP_SHIFT 8
    #define APP_CSRPRG_SUP_MASK 0x00000200
    #define APP_CSRPRG_SUP_SHIFT 9
    #define APP_RESUME_MASK 0x00000400
    #define APP_RESUME_SHIFT 10
    #define APP_STALL_MASK 0x00000800
    #define APP_STALL_SHIFT 11
    #define APP_DONE_CSR_MASK 0x00001000
    #define APP_DONE_CSR_SHIFT 12
    #define APP_DEV_DISCON_MASK 0x00002000
    #define APP_DEV_DISCON_SHIFT 13
    #define APP_SCALE_DOWN_MASK 0x00004000
    #define APP_SCALE_DOWN_SHIFT 14
    #define APP_NZ_LEN_PKT_STALL_MASK 0x00008000
    #define APP_NZ_LEN_PKT_STALL_SHIFT 15
    #define APP_NZ_LEN_PKT_STALL_ALL_MASK 0x00010000
    #define APP_NZ_LEN_PKT_STALL_ALL_SHIFT 16
    #define APP_ENABLE_ERRATIC_ERR_MASK 0x00020000
    #define APP_ENABLE_ERRATIC_ERR_SHIFT 17
    #define APP_STALL_CLR_EP0_HALT_MASK 0x00040000
    #define APP_STALL_CLR_EP0_HALT_SHIFT 18
    #define HS_TIMEOUT_CALIB_MASK 0x00380000
    #define HS_TIMEOUT_CALIB_SHIFT 19
    #define FS_TIMEOUT_CALIB_MASK 0x01C00000
    #define FS_TIMEOUT_CALIB_SHIFT 22
    #define SOFT_DISCON_SEL_MASK 0x10000000
    #define SOFT_DISCON_SEL_SHIFT 28
    #define SOFT_DISCON_TRIG_MASK 0x20000000
    #define SOFT_DISCON_TRIG_SHIFT 29
#define  USBD_UDC20_STATUS0 0x2424
    #define UDC20_EARLY_SUSPEND_MASK 0x00000001
    #define UDC20_EARLY_SUSPEND_SHIFT 0
    #define UDC20_SUSPEND_MASK 0x00000002
    #define UDC20_SUSPEND_SHIFT 1
    #define UDC20_USBRESET_MASK 0x00000004
    #define UDC20_USBRESET_SHIFT 2
    #define UDC20_CFG_MASK 0x00000078
    #define UDC20_CFG_SHIFT 3
    #define UDC20_INTF_MASK 0x00000780
    #define UDC20_INTF_SHIFT 7
    #define UDC20_ALTINTF_MASK 0x00007800
    #define UDC20_ALTINTF_SHIFT 11
    #define UDC20_HST_SETCFG_MASK 0x00008000
    #define UDC20_HST_SETCFG_SHIFT 15
    #define UDC20_HST_SETINTF_MASK 0x00010000
    #define UDC20_HST_SETINTF_SHIFT 16
    #define UDC20_ENUM_SPEED_MASK 0x00060000
    #define UDC20_ENUM_SPEED_SHIFT 17
    #define UDC20_ENUMON_MASK 0x00080000
    #define UDC20_ENUMON_SHIFT 19
    #define UDC20_SETCSRS_MASK 0x00100000
    #define UDC20_SETCSRS_SHIFT 20
    #define UDC20_ERRATIC_ERR_MASK 0x00200000
    #define UDC20_ERRATIC_ERR_SHIFT 21
    #define UDC20_PHYMODE_MASK 0x00C00000
    #define UDC20_PHYMODE_SHIFT 22
    #define UDC20_RMT_WKUP_FEAT_MASK 0x01000000
    #define UDC20_RMT_WKUP_FEAT_SHIFT 24
#define  USBD_UDC20_STATUS1 0x2428
    #define UDC20_SETUP_MASK 0x00000001
    #define UDC20_SETUP_SHIFT 0
    #define UDC20_SOF_MASK 0x00000002
    #define UDC20_SOF_SHIFT 1
    #define UDC20_TIMESTAMP_MASK 0x00001FFC
    #define UDC20_TIMESTAMP_SHIFT 2
    #define UDC20_UFRAME_NUM_MASK 0x0000E000
    #define UDC20_UFRAME_NUM_SHIFT 13
#define  USBH1_CSR_STATUS_REG 0x2100
    #define USBH1_CSR_STATUS_REG_USBH_CSR_BUSY_MASK 0x00000001
    #define USBH1_CSR_STATUS_REG_USBH_CSR_BUSY_SHIFT 0
    #define USBH1_CSR_STATUS_REG_USBH_CSR_ERR_MASK 0x00000002
    #define USBH1_CSR_STATUS_REG_USBH_CSR_ERR_SHIFT 1
#define  USBH1_CTRL_REG 0x2120
    #define USBH1_CTRL_REG_MEM_BRIDGE_HALT_MASK 0x00000001
    #define USBH1_CTRL_REG_MEM_BRIDGE_HALT_SHIFT 0
    #define USBH1_CTRL_REG_SDUH_INT_MASK 0x00000002
    #define USBH1_CTRL_REG_SDUH_INT_SHIFT 1
    #define USBH1_CTRL_REG_SOFT_RESET_MASK 0x00000004
    #define USBH1_CTRL_REG_SOFT_RESET_SHIFT 2
    #define USBH1_CTRL_REG_EXT_MEM_ARB_TIMER_MASK 0x000000F0
    #define USBH1_CTRL_REG_EXT_MEM_ARB_TIMER_SHIFT 4
    #define USBH1_CTRL_REG_OHCI_12_STOP_MASK 0x00000100
    #define USBH1_CTRL_REG_OHCI_12_STOP_SHIFT 8
    #define USBH1_CTRL_REG_OHCI_48_STOP_MASK 0x00000200
    #define USBH1_CTRL_REG_OHCI_48_STOP_SHIFT 9
    #define USBH1_CTRL_REG_OHCI_SUSP_LGCY_MASK 0x00001000
    #define USBH1_CTRL_REG_OHCI_SUSP_LGCY_SHIFT 12
    #define USBH1_CTRL_REG_APP_START_CLK_MASK 0x00002000
    #define USBH1_CTRL_REG_APP_START_CLK_SHIFT 13
    #define USBH1_CTRL_REG_TSM_WR_MAX_WAIT_MASK 0x003F0000
    #define USBH1_CTRL_REG_TSM_WR_MAX_WAIT_SHIFT 16
#define  USBH1_DUMMY_REG 0x213C
    #define USBH1_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define USBH1_DUMMY_REG_DATA_SHIFT 0
#define  USBH1_EHCI_CSR_CTRL_REG 0x2104
    #define USBH1_EHCI_CSR_CTRL_REG_ADDR_MASK 0x000000FC
    #define USBH1_EHCI_CSR_CTRL_REG_ADDR_SHIFT 2
    #define USBH1_EHCI_CSR_CTRL_REG_WOP_MASK 0x80000000
    #define USBH1_EHCI_CSR_CTRL_REG_WOP_SHIFT 31
#define  USBH1_HOST_INT_MASK 0x2134
    #define USBH1_HOST_INT_MASK_EHCI_INT_STATUS_EN_MASK 0x00000002
    #define USBH1_HOST_INT_MASK_EHCI_INT_STATUS_EN_SHIFT 1
    #define USBH1_HOST_INT_MASK_OHCI_INT_STATUS_EN_MASK 0x00000004
    #define USBH1_HOST_INT_MASK_OHCI_INT_STATUS_EN_SHIFT 2
    #define USBH1_HOST_INT_MASK_OHCI_BRIDGE_INT_EN_MASK 0x00000008
    #define USBH1_HOST_INT_MASK_OHCI_BRIDGE_INT_EN_SHIFT 3
#define  USBH1_MIPS_INT_MASK 0x2138
    #define USBH1_MIPS_INT_MASK_EHCI_INT_STATUS_EN_MASK 0x00000002
    #define USBH1_MIPS_INT_MASK_EHCI_INT_STATUS_EN_SHIFT 1
    #define USBH1_MIPS_INT_MASK_OHCI_INT_STATUS_EN_MASK 0x00000004
    #define USBH1_MIPS_INT_MASK_OHCI_INT_STATUS_EN_SHIFT 2
    #define USBH1_MIPS_INT_MASK_OHCI_BRIDGE_INT_EN_MASK 0x00000008
    #define USBH1_MIPS_INT_MASK_OHCI_BRIDGE_INT_EN_SHIFT 3
#define  USBH1_OHCI_INT_EN_REG 0x2128
    #define USBH1_OHCI_INT_EN_REG_RMTWKP_EN_MASK 0x00000001
    #define USBH1_OHCI_INT_EN_REG_RMTWKP_EN_SHIFT 0
    #define USBH1_OHCI_INT_EN_REG_SOF_EN_MASK 0x00000002
    #define USBH1_OHCI_INT_EN_REG_SOF_EN_SHIFT 1
    #define USBH1_OHCI_INT_EN_REG_GLOBALSUSPEND_EN_MASK 0x00000004
    #define USBH1_OHCI_INT_EN_REG_GLOBALSUSPEND_EN_SHIFT 2
    #define USBH1_OHCI_INT_EN_REG_DRWE_EN_MASK 0x00000008
    #define USBH1_OHCI_INT_EN_REG_DRWE_EN_SHIFT 3
    #define USBH1_OHCI_INT_EN_REG_RWE_EN_MASK 0x00000010
    #define USBH1_OHCI_INT_EN_REG_RWE_EN_SHIFT 4
    #define USBH1_OHCI_INT_EN_REG_CCS_EN_PORT0_MASK 0x00000020
    #define USBH1_OHCI_INT_EN_REG_CCS_EN_PORT0_SHIFT 5
    #define USBH1_OHCI_INT_EN_REG_CCS_EN_PORT1_MASK 0x00000040
    #define USBH1_OHCI_INT_EN_REG_CCS_EN_PORT1_SHIFT 6
#define  USBH1_OHCI_OP_CSR_CTRL_REG 0x210C
    #define USBH1_OHCI_OP_CSR_CTRL_REG_ADDR_MASK 0x0000007C
    #define USBH1_OHCI_OP_CSR_CTRL_REG_ADDR_SHIFT 2
    #define USBH1_OHCI_OP_CSR_CTRL_REG_WOP_MASK 0x80000000
    #define USBH1_OHCI_OP_CSR_CTRL_REG_WOP_SHIFT 31
#define  USBH1_OHCI_STATUS_REG 0x2124
    #define USBH1_OHCI_STATUS_REG_RMTWKP_MASK 0x00000001
    #define USBH1_OHCI_STATUS_REG_RMTWKP_SHIFT 0
    #define USBH1_OHCI_STATUS_REG_SOF_MASK 0x00000002
    #define USBH1_OHCI_STATUS_REG_SOF_SHIFT 1
    #define USBH1_OHCI_STATUS_REG_GLOBALSUSPEND_MASK 0x00000004
    #define USBH1_OHCI_STATUS_REG_GLOBALSUSPEND_SHIFT 2
    #define USBH1_OHCI_STATUS_REG_DRWE_MASK 0x00000008
    #define USBH1_OHCI_STATUS_REG_DRWE_SHIFT 3
    #define USBH1_OHCI_STATUS_REG_RWE_MASK 0x00000010
    #define USBH1_OHCI_STATUS_REG_RWE_SHIFT 4
    #define USBH1_OHCI_STATUS_REG_CCS_PORT0_MASK 0x00000020
    #define USBH1_OHCI_STATUS_REG_CCS_PORT0_SHIFT 5
    #define USBH1_OHCI_STATUS_REG_CCS_PORT1_MASK 0x00000040
    #define USBH1_OHCI_STATUS_REG_CCS_PORT1_SHIFT 6
#define  USBH1_OHCI_TRANS_CTRL_REG 0x2118
    #define USBH1_OHCI_TRANS_CTRL_REG_MAX_TRANS_MASK 0x000003FF
    #define USBH1_OHCI_TRANS_CTRL_REG_MAX_TRANS_SHIFT 0
    #define USBH1_OHCI_TRANS_CTRL_REG_MAX_WAIT_MASK 0xFFFF0000
    #define USBH1_OHCI_TRANS_CTRL_REG_MAX_WAIT_SHIFT 16
#define  USBH1_PHY_CTRL_REG 0x2130
    #define USBH1_PHY_CTRL_REG_USBH_PHY_TX_BIT_STUFF_EN_0_MASK 0x00002000
    #define USBH1_PHY_CTRL_REG_USBH_PHY_TX_BIT_STUFF_EN_0_SHIFT 13
    #define USBH1_PHY_CTRL_REG_USBH_PHY_TX_BIT_STUFF_EN_H_0_MASK 0x00004000
    #define USBH1_PHY_CTRL_REG_USBH_PHY_TX_BIT_STUFF_EN_H_0_SHIFT 14
    #define USBH1_PHY_CTRL_REG_USBH_PHY_DM_PULLDOWN_0_MASK 0x00008000
    #define USBH1_PHY_CTRL_REG_USBH_PHY_DM_PULLDOWN_0_SHIFT 15
    #define USBH1_PHY_CTRL_REG_USBH_PHY_DP_PULLDOWN_0_MASK 0x00010000
    #define USBH1_PHY_CTRL_REG_USBH_PHY_DP_PULLDOWN_0_SHIFT 16
    #define USBH1_PHY_CTRL_REG_USBH_PHY_WORD_INTERFACE_0_MASK 0x00040000
    #define USBH1_PHY_CTRL_REG_USBH_PHY_WORD_INTERFACE_0_SHIFT 18
    #define USBH1_PHY_CTRL_REG_USBH_PHY_TX_BIT_STUFF_EN_1_MASK 0x00800000
    #define USBH1_PHY_CTRL_REG_USBH_PHY_TX_BIT_STUFF_EN_1_SHIFT 23
    #define USBH1_PHY_CTRL_REG_USBH_PHY_TX_BIT_STUFF_EN_H_1_MASK 0x01000000
    #define USBH1_PHY_CTRL_REG_USBH_PHY_TX_BIT_STUFF_EN_H_1_SHIFT 24
    #define USBH1_PHY_CTRL_REG_USBH_PHY_DM_PULLDOWN_1_MASK 0x02000000
    #define USBH1_PHY_CTRL_REG_USBH_PHY_DM_PULLDOWN_1_SHIFT 25
    #define USBH1_PHY_CTRL_REG_USBH_PHY_DP_PULLDOWN_1_MASK 0x04000000
    #define USBH1_PHY_CTRL_REG_USBH_PHY_DP_PULLDOWN_1_SHIFT 26
    #define USBH1_PHY_CTRL_REG_USBH_PHY_WORD_INTERFACE_1_MASK 0x10000000
    #define USBH1_PHY_CTRL_REG_USBH_PHY_WORD_INTERFACE_1_SHIFT 28
    #define USBH1_PHY_CTRL_REG_USBH_PHY_PORT_RESET_0_MASK 0x20000000
    #define USBH1_PHY_CTRL_REG_USBH_PHY_PORT_RESET_0_SHIFT 29
    #define USBH1_PHY_CTRL_REG_USBH_PHY_PORT_RESET_1_MASK 0x40000000
    #define USBH1_PHY_CTRL_REG_USBH_PHY_PORT_RESET_1_SHIFT 30
#define  USBH1_RDAT_REG 0x2114
    #define USBH1_RDAT_REG_USBH_RDAT_MASK 0xFFFFFFFF
    #define USBH1_RDAT_REG_USBH_RDAT_SHIFT 0
#define  USBH1_STATUS_REG 0x211C
    #define USBH1_STATUS_REG_MEM_BRIDGE_IDLE_MASK 0x00000001
    #define USBH1_STATUS_REG_MEM_BRIDGE_IDLE_SHIFT 0
    #define USBH1_STATUS_REG_EHCI_INT_STATUS_MASK 0x00000002
    #define USBH1_STATUS_REG_EHCI_INT_STATUS_SHIFT 1
    #define USBH1_STATUS_REG_OHCI_INT_STATUS_MASK 0x00000004
    #define USBH1_STATUS_REG_OHCI_INT_STATUS_SHIFT 2
    #define USBH1_STATUS_REG_OHCI_BRIDGE_INT_MASK 0x00000008
    #define USBH1_STATUS_REG_OHCI_BRIDGE_INT_SHIFT 3
    #define USBH1_STATUS_REG_EHCI_USB_STATUS_MASK 0x003F0000
    #define USBH1_STATUS_REG_EHCI_USB_STATUS_SHIFT 16
    #define USBH1_STATUS_REG_EHCI_LPSMC_STATE_MASK 0x03C00000
    #define USBH1_STATUS_REG_EHCI_LPSMC_STATE_SHIFT 22
#define  USBH1_STRAPS_AND_CFG_REG 0x212C
    #define USBH1_STRAPS_AND_CFG_REG_FLADJ_VAL_HOST_MASK 0x0000003F
    #define USBH1_STRAPS_AND_CFG_REG_FLADJ_VAL_HOST_SHIFT 0
    #define USBH1_STRAPS_AND_CFG_REG_AUTOPPD_ON_OVERCUR_EN_MASK 0x00000040
    #define USBH1_STRAPS_AND_CFG_REG_AUTOPPD_ON_OVERCUR_EN_SHIFT 6
    #define USBH1_STRAPS_AND_CFG_REG_APP_PRT_OVRCUR_PORT0_MASK 0x00000080
    #define USBH1_STRAPS_AND_CFG_REG_APP_PRT_OVRCUR_PORT0_SHIFT 7
    #define USBH1_STRAPS_AND_CFG_REG_APP_PRT_OVRCUR_PORT1_MASK 0x00000100
    #define USBH1_STRAPS_AND_CFG_REG_APP_PRT_OVRCUR_PORT1_SHIFT 8
    #define USBH1_STRAPS_AND_CFG_REG_EHCI_PRT_PWR0_12MHZ_EN_MASK 0x00000200
    #define USBH1_STRAPS_AND_CFG_REG_EHCI_PRT_PWR0_12MHZ_EN_SHIFT 9
    #define USBH1_STRAPS_AND_CFG_REG_EHCI_PRT_PWR0_60MHZ_EN_MASK 0x00000400
    #define USBH1_STRAPS_AND_CFG_REG_EHCI_PRT_PWR0_60MHZ_EN_SHIFT 10
    #define USBH1_STRAPS_AND_CFG_REG_EHCI_PRT_PWR1_12MHZ_EN_MASK 0x00000800
    #define USBH1_STRAPS_AND_CFG_REG_EHCI_PRT_PWR1_12MHZ_EN_SHIFT 11
    #define USBH1_STRAPS_AND_CFG_REG_EHCI_PRT_PWR1_60MHZ_EN_MASK 0x00001000
    #define USBH1_STRAPS_AND_CFG_REG_EHCI_PRT_PWR1_60MHZ_EN_SHIFT 12
    #define USBH1_STRAPS_AND_CFG_REG_UTMI_BACKWARD_ENB_MASK 0x00002000
    #define USBH1_STRAPS_AND_CFG_REG_UTMI_BACKWARD_ENB_SHIFT 13
    #define USBH1_STRAPS_AND_CFG_REG_RESUME_UTMI_PLS_DIS_MASK 0x00004000
    #define USBH1_STRAPS_AND_CFG_REG_RESUME_UTMI_PLS_DIS_SHIFT 14
#define  USBH1_WDAT_REG 0x2110
    #define USBH1_WDAT_REG_USBH_WDAT_MASK 0xFFFFFFFF
    #define USBH1_WDAT_REG_USBH_WDAT_SHIFT 0
#define  USBH_CSR_STATUS_REG 0x2000
    #define USBH_CSR_STATUS_REG_USBH_CSR_BUSY_MASK 0x00000001
    #define USBH_CSR_STATUS_REG_USBH_CSR_BUSY_SHIFT 0
    #define USBH_CSR_STATUS_REG_USBH_CSR_ERR_MASK 0x00000002
    #define USBH_CSR_STATUS_REG_USBH_CSR_ERR_SHIFT 1
#define  USBH_CTRL_REG 0x2020
    #define USBH_CTRL_REG_MEM_BRIDGE_HALT_MASK 0x00000001
    #define USBH_CTRL_REG_MEM_BRIDGE_HALT_SHIFT 0
    #define USBH_CTRL_REG_SDUH_INT_MASK 0x00000002
    #define USBH_CTRL_REG_SDUH_INT_SHIFT 1
    #define USBH_CTRL_REG_SOFT_RESET_MASK 0x00000004
    #define USBH_CTRL_REG_SOFT_RESET_SHIFT 2
    #define USBH_CTRL_REG_EXT_MEM_ARB_TIMER_MASK 0x000000F0
    #define USBH_CTRL_REG_EXT_MEM_ARB_TIMER_SHIFT 4
    #define USBH_CTRL_REG_OHCI_12_STOP_MASK 0x00000100
    #define USBH_CTRL_REG_OHCI_12_STOP_SHIFT 8
    #define USBH_CTRL_REG_OHCI_48_STOP_MASK 0x00000200
    #define USBH_CTRL_REG_OHCI_48_STOP_SHIFT 9
    #define USBH_CTRL_REG_OHCI_SUSP_LGCY_MASK 0x00001000
    #define USBH_CTRL_REG_OHCI_SUSP_LGCY_SHIFT 12
    #define USBH_CTRL_REG_APP_START_CLK_MASK 0x00002000
    #define USBH_CTRL_REG_APP_START_CLK_SHIFT 13
    #define USBH_CTRL_REG_TSM_WR_MAX_WAIT_MASK 0x003F0000
    #define USBH_CTRL_REG_TSM_WR_MAX_WAIT_SHIFT 16
#define  USBH_DEBUG_REG 0x2050
    #define USBH_DEBUG_REG_DEBUG_DATA_MASK 0x000FFFFF
    #define USBH_DEBUG_REG_DEBUG_DATA_SHIFT 0
#define  USBH_DUMMY_REG 0x203C
    #define USBH_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define USBH_DUMMY_REG_DATA_SHIFT 0
#define  USBH_EHCI_CSR_CTRL_REG 0x2004
    #define USBH_EHCI_CSR_CTRL_REG_ADDR_MASK 0x000000FC
    #define USBH_EHCI_CSR_CTRL_REG_ADDR_SHIFT 2
    #define USBH_EHCI_CSR_CTRL_REG_WOP_MASK 0x80000000
    #define USBH_EHCI_CSR_CTRL_REG_WOP_SHIFT 31
#define  USBH_HOST_INT_MASK 0x2034
    #define USBH_HOST_INT_MASK_EHCI_INT_STATUS_EN_MASK 0x00000002
    #define USBH_HOST_INT_MASK_EHCI_INT_STATUS_EN_SHIFT 1
    #define USBH_HOST_INT_MASK_OHCI_INT_STATUS_EN_MASK 0x00000004
    #define USBH_HOST_INT_MASK_OHCI_INT_STATUS_EN_SHIFT 2
    #define USBH_HOST_INT_MASK_OHCI_BRIDGE_INT_EN_MASK 0x00000008
    #define USBH_HOST_INT_MASK_OHCI_BRIDGE_INT_EN_SHIFT 3
#define  USBH_MIPS_INT_MASK 0x2038
    #define USBH_MIPS_INT_MASK_EHCI_INT_STATUS_EN_MASK 0x00000002
    #define USBH_MIPS_INT_MASK_EHCI_INT_STATUS_EN_SHIFT 1
    #define USBH_MIPS_INT_MASK_OHCI_INT_STATUS_EN_MASK 0x00000004
    #define USBH_MIPS_INT_MASK_OHCI_INT_STATUS_EN_SHIFT 2
    #define USBH_MIPS_INT_MASK_OHCI_BRIDGE_INT_EN_MASK 0x00000008
    #define USBH_MIPS_INT_MASK_OHCI_BRIDGE_INT_EN_SHIFT 3
#define  USBH_OHCI_INT_EN_REG 0x2028
    #define USBH_OHCI_INT_EN_REG_RMTWKP_EN_MASK 0x00000001
    #define USBH_OHCI_INT_EN_REG_RMTWKP_EN_SHIFT 0
    #define USBH_OHCI_INT_EN_REG_SOF_EN_MASK 0x00000002
    #define USBH_OHCI_INT_EN_REG_SOF_EN_SHIFT 1
    #define USBH_OHCI_INT_EN_REG_GLOBALSUSPEND_EN_MASK 0x00000004
    #define USBH_OHCI_INT_EN_REG_GLOBALSUSPEND_EN_SHIFT 2
    #define USBH_OHCI_INT_EN_REG_DRWE_EN_MASK 0x00000008
    #define USBH_OHCI_INT_EN_REG_DRWE_EN_SHIFT 3
    #define USBH_OHCI_INT_EN_REG_RWE_EN_MASK 0x00000010
    #define USBH_OHCI_INT_EN_REG_RWE_EN_SHIFT 4
    #define USBH_OHCI_INT_EN_REG_CCS_EN_PORT0_MASK 0x00000020
    #define USBH_OHCI_INT_EN_REG_CCS_EN_PORT0_SHIFT 5
    #define USBH_OHCI_INT_EN_REG_CCS_EN_PORT1_MASK 0x00000040
    #define USBH_OHCI_INT_EN_REG_CCS_EN_PORT1_SHIFT 6
#define  USBH_OHCI_OP_CSR_CTRL_REG 0x200C
    #define USBH_OHCI_OP_CSR_CTRL_REG_ADDR_MASK 0x0000007C
    #define USBH_OHCI_OP_CSR_CTRL_REG_ADDR_SHIFT 2
    #define USBH_OHCI_OP_CSR_CTRL_REG_WOP_MASK 0x80000000
    #define USBH_OHCI_OP_CSR_CTRL_REG_WOP_SHIFT 31
#define  USBH_OHCI_STATUS_REG 0x2024
    #define USBH_OHCI_STATUS_REG_RMTWKP_MASK 0x00000001
    #define USBH_OHCI_STATUS_REG_RMTWKP_SHIFT 0
    #define USBH_OHCI_STATUS_REG_SOF_MASK 0x00000002
    #define USBH_OHCI_STATUS_REG_SOF_SHIFT 1
    #define USBH_OHCI_STATUS_REG_GLOBALSUSPEND_MASK 0x00000004
    #define USBH_OHCI_STATUS_REG_GLOBALSUSPEND_SHIFT 2
    #define USBH_OHCI_STATUS_REG_DRWE_MASK 0x00000008
    #define USBH_OHCI_STATUS_REG_DRWE_SHIFT 3
    #define USBH_OHCI_STATUS_REG_RWE_MASK 0x00000010
    #define USBH_OHCI_STATUS_REG_RWE_SHIFT 4
    #define USBH_OHCI_STATUS_REG_CCS_PORT0_MASK 0x00000020
    #define USBH_OHCI_STATUS_REG_CCS_PORT0_SHIFT 5
    #define USBH_OHCI_STATUS_REG_CCS_PORT1_MASK 0x00000040
    #define USBH_OHCI_STATUS_REG_CCS_PORT1_SHIFT 6
#define  USBH_OHCI_TRANS_CTRL_REG 0x2018
    #define USBH_OHCI_TRANS_CTRL_REG_MAX_TRANS_MASK 0x000003FF
    #define USBH_OHCI_TRANS_CTRL_REG_MAX_TRANS_SHIFT 0
    #define USBH_OHCI_TRANS_CTRL_REG_MAX_WAIT_MASK 0xFFFF0000
    #define USBH_OHCI_TRANS_CTRL_REG_MAX_WAIT_SHIFT 16
#define  USBH_PHY_CTRL_REG 0x2030
    #define USBH_PHY_POR_MASK 0x00000010
    #define USBH_PHY_POR_SHIFT 4
    #define USBH_PHY_CTRL_REG_USBH_PHY_TX_BIT_STUFF_EN_0_MASK 0x00002000
    #define USBH_PHY_CTRL_REG_USBH_PHY_TX_BIT_STUFF_EN_0_SHIFT 13
    #define USBH_PHY_CTRL_REG_USBH_PHY_TX_BIT_STUFF_EN_H_0_MASK 0x00004000
    #define USBH_PHY_CTRL_REG_USBH_PHY_TX_BIT_STUFF_EN_H_0_SHIFT 14
    #define USBH_PHY_CTRL_REG_USBH_PHY_DM_PULLDOWN_0_MASK 0x00008000
    #define USBH_PHY_CTRL_REG_USBH_PHY_DM_PULLDOWN_0_SHIFT 15
    #define USBH_PHY_CTRL_REG_USBH_PHY_DP_PULLDOWN_0_MASK 0x00010000
    #define USBH_PHY_CTRL_REG_USBH_PHY_DP_PULLDOWN_0_SHIFT 16
    #define USBH_PHY_CTRL_REG_USBH_PHY_WORD_INTERFACE_0_MASK 0x00040000
    #define USBH_PHY_CTRL_REG_USBH_PHY_WORD_INTERFACE_0_SHIFT 18
    #define USBH_PHY_CTRL_REG_USBH_PHY_TX_BIT_STUFF_EN_1_MASK 0x00800000
    #define USBH_PHY_CTRL_REG_USBH_PHY_TX_BIT_STUFF_EN_1_SHIFT 23
    #define USBH_PHY_CTRL_REG_USBH_PHY_TX_BIT_STUFF_EN_H_1_MASK 0x01000000
    #define USBH_PHY_CTRL_REG_USBH_PHY_TX_BIT_STUFF_EN_H_1_SHIFT 24
    #define USBH_PHY_CTRL_REG_USBH_PHY_DM_PULLDOWN_1_MASK 0x02000000
    #define USBH_PHY_CTRL_REG_USBH_PHY_DM_PULLDOWN_1_SHIFT 25
    #define USBH_PHY_CTRL_REG_USBH_PHY_DP_PULLDOWN_1_MASK 0x04000000
    #define USBH_PHY_CTRL_REG_USBH_PHY_DP_PULLDOWN_1_SHIFT 26
    #define USBH_PHY_CTRL_REG_USBH_PHY_WORD_INTERFACE_1_MASK 0x10000000
    #define USBH_PHY_CTRL_REG_USBH_PHY_WORD_INTERFACE_1_SHIFT 28
    #define USBH_PHY_CTRL_REG_USBH_PHY_PORT_RESET_0_MASK 0x20000000
    #define USBH_PHY_CTRL_REG_USBH_PHY_PORT_RESET_0_SHIFT 29
    #define USBH_PHY_CTRL_REG_USBH_PHY_PORT_RESET_1_MASK 0x40000000
    #define USBH_PHY_CTRL_REG_USBH_PHY_PORT_RESET_1_SHIFT 30
#define  USBH_RDAT_REG 0x2014
    #define USBH_RDAT_REG_USBH_RDAT_MASK 0xFFFFFFFF
    #define USBH_RDAT_REG_USBH_RDAT_SHIFT 0
#define  USBH_STATUS_REG 0x201C
    #define USBH_STATUS_REG_MEM_BRIDGE_IDLE_MASK 0x00000001
    #define USBH_STATUS_REG_MEM_BRIDGE_IDLE_SHIFT 0
    #define USBH_STATUS_REG_EHCI_INT_STATUS_MASK 0x00000002
    #define USBH_STATUS_REG_EHCI_INT_STATUS_SHIFT 1
    #define USBH_STATUS_REG_OHCI_INT_STATUS_MASK 0x00000004
    #define USBH_STATUS_REG_OHCI_INT_STATUS_SHIFT 2
    #define USBH_STATUS_REG_OHCI_BRIDGE_INT_MASK 0x00000008
    #define USBH_STATUS_REG_OHCI_BRIDGE_INT_SHIFT 3
    #define USBH_STATUS_REG_EHCI_USB_STATUS_MASK 0x003F0000
    #define USBH_STATUS_REG_EHCI_USB_STATUS_SHIFT 16
    #define USBH_STATUS_REG_EHCI_LPSMC_STATE_MASK 0x03C00000
    #define USBH_STATUS_REG_EHCI_LPSMC_STATE_SHIFT 22
#define  USBH_STRAPS_AND_CFG_REG 0x202C
    #define USBH_STRAPS_AND_CFG_REG_FLADJ_VAL_HOST_MASK 0x0000003F
    #define USBH_STRAPS_AND_CFG_REG_FLADJ_VAL_HOST_SHIFT 0
    #define USBH_STRAPS_AND_CFG_REG_AUTOPPD_ON_OVERCUR_EN_MASK 0x00000040
    #define USBH_STRAPS_AND_CFG_REG_AUTOPPD_ON_OVERCUR_EN_SHIFT 6
    #define USBH_STRAPS_AND_CFG_REG_APP_PRT_OVRCUR_PORT0_MASK 0x00000080
    #define USBH_STRAPS_AND_CFG_REG_APP_PRT_OVRCUR_PORT0_SHIFT 7
    #define USBH_STRAPS_AND_CFG_REG_APP_PRT_OVRCUR_PORT1_MASK 0x00000100
    #define USBH_STRAPS_AND_CFG_REG_APP_PRT_OVRCUR_PORT1_SHIFT 8
    #define USBH_STRAPS_AND_CFG_REG_EHCI_PRT_PWR0_12MHZ_EN_MASK 0x00000200
    #define USBH_STRAPS_AND_CFG_REG_EHCI_PRT_PWR0_12MHZ_EN_SHIFT 9
    #define USBH_STRAPS_AND_CFG_REG_EHCI_PRT_PWR0_60MHZ_EN_MASK 0x00000400
    #define USBH_STRAPS_AND_CFG_REG_EHCI_PRT_PWR0_60MHZ_EN_SHIFT 10
    #define USBH_STRAPS_AND_CFG_REG_EHCI_PRT_PWR1_12MHZ_EN_MASK 0x00000800
    #define USBH_STRAPS_AND_CFG_REG_EHCI_PRT_PWR1_12MHZ_EN_SHIFT 11
    #define USBH_STRAPS_AND_CFG_REG_EHCI_PRT_PWR1_60MHZ_EN_MASK 0x00001000
    #define USBH_STRAPS_AND_CFG_REG_EHCI_PRT_PWR1_60MHZ_EN_SHIFT 12
    #define USBH_STRAPS_AND_CFG_REG_UTMI_BACKWARD_ENB_MASK 0x00002000
    #define USBH_STRAPS_AND_CFG_REG_UTMI_BACKWARD_ENB_SHIFT 13
    #define USBH_STRAPS_AND_CFG_REG_RESUME_UTMI_PLS_DIS_MASK 0x00004000
    #define USBH_STRAPS_AND_CFG_REG_RESUME_UTMI_PLS_DIS_SHIFT 14
#define  USBH_WDAT_REG 0x2010
    #define USBH_WDAT_REG_USBH_WDAT_MASK 0xFFFFFFFF
    #define USBH_WDAT_REG_USBH_WDAT_SHIFT 0
#define  VFE0_ACTIVITY_ADR 0x5528
    #define VFE0_ACTIVITY_ADR_BASE_MASK 0x07FFFFC0
    #define VFE0_ACTIVITY_ADR_BASE_SHIFT 6
#define  VFE0_ACTIVITY_DIV 0x5520
    #define VFE0_ACTIVITY_DIV_VALUE_MASK 0x0000FFFF
    #define VFE0_ACTIVITY_DIV_VALUE_SHIFT 0
#define  VFE0_ACTIVITY_SIZE 0x5524
    #define VFE0_ACTIVITY_SIZE_BUF_SIZE_MASK 0x0000FFF0
    #define VFE0_ACTIVITY_SIZE_BUF_SIZE_SHIFT 4
    #define VFE0_ACTIVITY_SIZE_OUTPUT_MODE_MASK 0x00030000
    #define VFE0_ACTIVITY_SIZE_OUTPUT_MODE_SHIFT 16
#define  VFE0_CR_WR_ADR 0x5624
    #define VFE0_CR_WR_ADR_BASE_MASK 0x07FFE000
    #define VFE0_CR_WR_ADR_BASE_SHIFT 13
#define  VFE0_CTRL 0x5500
    #define VFE0_CTRL_BUF_CNT_MASK 0x0000003F
    #define VFE0_CTRL_BUF_CNT_SHIFT 0
    #define VFE0_CTRL_MODE_MASK 0x00000300
    #define VFE0_CTRL_MODE_SHIFT 8
    #define VFE0_CTRL_HS_ENABLE_MASK 0x00001000
    #define VFE0_CTRL_HS_ENABLE_SHIFT 12
    #define VFE0_CTRL_OUT_MEM_TILE_MASK 0x00002000
    #define VFE0_CTRL_OUT_MEM_TILE_SHIFT 13
    #define VFE0_CTRL_RD_SLICE_CNT_MASK 0x007F0000
    #define VFE0_CTRL_RD_SLICE_CNT_SHIFT 16
    #define VFE0_CTRL_VS_TRUNCATE_MASK 0x00800000
    #define VFE0_CTRL_VS_TRUNCATE_SHIFT 23
    #define VFE0_CTRL_8_BIT_MODE_MASK 0x01000000
    #define VFE0_CTRL_8_BIT_MODE_SHIFT 24
    #define VFE0_CTRL_8_BIT_APPEND_MASK 0x06000000
    #define VFE0_CTRL_8_BIT_APPEND_SHIFT 25
    #define VFE0_CTRL_HS_ROUND_MASK 0x08000000
    #define VFE0_CTRL_HS_ROUND_SHIFT 27
    #define VFE0_CTRL_OUTPUT_IDX_EN_MASK 0x10000000
    #define VFE0_CTRL_OUTPUT_IDX_EN_SHIFT 28
    #define VFE0_CTRL_MEM_TILE_MASK 0x20000000
    #define VFE0_CTRL_MEM_TILE_SHIFT 29
    #define VFE0_CTRL_DROP_FLD_MASK 0x40000000
    #define VFE0_CTRL_DROP_FLD_SHIFT 30
    #define VFE0_CTRL_420_CBCR_MASK 0x80000000
    #define VFE0_CTRL_420_CBCR_SHIFT 31
#define  VFE0_C_WR_ADR 0x551C
    #define VFE0_C_WR_ADR_BASE_MASK 0x07FFE000
    #define VFE0_C_WR_ADR_BASE_SHIFT 13
#define  VFE0_FLTR_CTRL 0x5530
    #define VFE0_FLTR_CTRL_EDGE_THRES_MASK 0x001FFFFF
    #define VFE0_FLTR_CTRL_EDGE_THRES_SHIFT 0
    #define VFE0_FLTR_CTRL_FLTR_SET_MASK 0x60000000
    #define VFE0_FLTR_CTRL_FLTR_SET_SHIFT 29
    #define VFE0_FLTR_CTRL_FLTR_EN_MASK 0x80000000
    #define VFE0_FLTR_CTRL_FLTR_EN_SHIFT 31
#define  VFE0_FLTR_SET 0x552C
    #define VFE0_FLTR_SET_DATA_MASK 0x7FFFFFFF
    #define VFE0_FLTR_SET_DATA_SHIFT 0
#define  VFE0_RD_ADR 0x5514
    #define VFE0_RD_ADR_BASE_MASK 0x07FFFFC0
    #define VFE0_RD_ADR_BASE_SHIFT 6
#define  VFE0_RD_BUF 0x550C
    #define VFE0_RD_BUF_PITCH_MASK 0x00000FF0
    #define VFE0_RD_BUF_PITCH_SHIFT 4
    #define VFE0_RD_BUF_SIZE_MASK 0xFFFF0000
    #define VFE0_RD_BUF_SIZE_SHIFT 16
#define  VFE0_RD_CB_ADR 0x5534
    #define VFE0_RD_CB_ADR_BASE_MASK 0x07FFFFC0
    #define VFE0_RD_CB_ADR_BASE_SHIFT 6
#define  VFE0_RD_CR_ADR 0x5538
    #define VFE0_RD_CR_ADR_BASE_MASK 0x07FFFFC0
    #define VFE0_RD_CR_ADR_BASE_SHIFT 6
#define  VFE0_RD_INFO_ADR 0x5504
    #define VFE0_RD_INFO_ADR_BASE_MASK 0x07FFFFC0
    #define VFE0_RD_INFO_ADR_BASE_SHIFT 6
#define  VFE0_SCL_CTRL_A 0x5618
    #define VFE0_SCL_CTRL_A_PHASES_MASK 0x0000001F
    #define VFE0_SCL_CTRL_A_PHASES_SHIFT 0
    #define VFE0_SCL_CTRL_A_SRC_RES_MASK 0x00007F00
    #define VFE0_SCL_CTRL_A_SRC_RES_SHIFT 8
    #define VFE0_SCL_CTRL_A_DST_RES_MASK 0x007F0000
    #define VFE0_SCL_CTRL_A_DST_RES_SHIFT 16
    #define VFE0_SCL_CTRL_A_DST_WIDTH_UPPER_MASK 0x00800000
    #define VFE0_SCL_CTRL_A_DST_WIDTH_UPPER_SHIFT 23
    #define VFE0_SCL_CTRL_A_IDX_SHIFT_MASK 0x03000000
    #define VFE0_SCL_CTRL_A_IDX_SHIFT_SHIFT 24
    #define VFE0_SCL_CTRL_A_DST_WIDTH_MASK 0xFC000000
    #define VFE0_SCL_CTRL_A_DST_WIDTH_SHIFT 26
#define  VFE0_WR_BUF 0x5510
    #define VFE0_WR_BUF_PITCH_MASK 0x00000FF0
    #define VFE0_WR_BUF_PITCH_SHIFT 4
    #define VFE0_WR_BUF_SIZE_Y_MASK 0x001FF000
    #define VFE0_WR_BUF_SIZE_Y_SHIFT 12
    #define VFE0_WR_BUF_SIZE_C_MASK 0xFF000000
    #define VFE0_WR_BUF_SIZE_C_SHIFT 24
#define  VFE0_WR_INFO_ADR 0x5508
    #define VFE0_WR_INFO_ADR_BASE_MASK 0x07FFFFC0
    #define VFE0_WR_INFO_ADR_BASE_SHIFT 6
#define  VFE0_Y_WR_ADR 0x5518
    #define VFE0_Y_WR_ADR_BASE_MASK 0x07FFE000
    #define VFE0_Y_WR_ADR_BASE_SHIFT 13
#define  VFE1_ACTIVITY_ADR 0x5568
    #define VFE1_ACTIVITY_ADR_BASE_MASK 0x07FFFFC0
    #define VFE1_ACTIVITY_ADR_BASE_SHIFT 6
#define  VFE1_ACTIVITY_DIV 0x5560
    #define VFE1_ACTIVITY_DIV_VALUE_MASK 0x0000FFFF
    #define VFE1_ACTIVITY_DIV_VALUE_SHIFT 0
#define  VFE1_ACTIVITY_SIZE 0x5564
    #define VFE1_ACTIVITY_SIZE_BUF_SIZE_MASK 0x0000FFF0
    #define VFE1_ACTIVITY_SIZE_BUF_SIZE_SHIFT 4
    #define VFE1_ACTIVITY_SIZE_OUTPUT_MODE_MASK 0x00030000
    #define VFE1_ACTIVITY_SIZE_OUTPUT_MODE_SHIFT 16
#define  VFE1_CR_WR_ADR 0x5628
    #define VFE1_CR_WR_ADR_BASE_MASK 0x07FFE000
    #define VFE1_CR_WR_ADR_BASE_SHIFT 13
#define  VFE1_CTRL 0x5540
    #define VFE1_CTRL_BUF_CNT_MASK 0x0000003F
    #define VFE1_CTRL_BUF_CNT_SHIFT 0
    #define VFE1_CTRL_MODE_MASK 0x00000300
    #define VFE1_CTRL_MODE_SHIFT 8
    #define VFE1_CTRL_HS_ENABLE_MASK 0x00001000
    #define VFE1_CTRL_HS_ENABLE_SHIFT 12
    #define VFE1_CTRL_OUT_MEM_TILE_MASK 0x00002000
    #define VFE1_CTRL_OUT_MEM_TILE_SHIFT 13
    #define VFE1_CTRL_RD_SLICE_CNT_MASK 0x007F0000
    #define VFE1_CTRL_RD_SLICE_CNT_SHIFT 16
    #define VFE1_CTRL_VS_TRUNCATE_MASK 0x00800000
    #define VFE1_CTRL_VS_TRUNCATE_SHIFT 23
    #define VFE1_CTRL_8_BIT_MODE_MASK 0x01000000
    #define VFE1_CTRL_8_BIT_MODE_SHIFT 24
    #define VFE1_CTRL_8_BIT_APPEND_MASK 0x06000000
    #define VFE1_CTRL_8_BIT_APPEND_SHIFT 25
    #define VFE1_CTRL_HS_ROUND_MASK 0x08000000
    #define VFE1_CTRL_HS_ROUND_SHIFT 27
    #define VFE1_CTRL_OUTPUT_IDX_EN_MASK 0x10000000
    #define VFE1_CTRL_OUTPUT_IDX_EN_SHIFT 28
    #define VFE1_CTRL_MEM_TILE_MASK 0x20000000
    #define VFE1_CTRL_MEM_TILE_SHIFT 29
    #define VFE1_CTRL_DROP_FLD_MASK 0x40000000
    #define VFE1_CTRL_DROP_FLD_SHIFT 30
    #define VFE1_CTRL_420_CBCR_MASK 0x80000000
    #define VFE1_CTRL_420_CBCR_SHIFT 31
#define  VFE1_C_WR_ADR 0x555C
    #define VFE1_C_WR_ADR_BASE_MASK 0x07FFE000
    #define VFE1_C_WR_ADR_BASE_SHIFT 13
#define  VFE1_FLTR_CTRL 0x5570
    #define VFE1_FLTR_CTRL_EDGE_THRES_MASK 0x001FFFFF
    #define VFE1_FLTR_CTRL_EDGE_THRES_SHIFT 0
    #define VFE1_FLTR_CTRL_FLTR_SET_MASK 0x60000000
    #define VFE1_FLTR_CTRL_FLTR_SET_SHIFT 29
    #define VFE1_FLTR_CTRL_FLTR_EN_MASK 0x80000000
    #define VFE1_FLTR_CTRL_FLTR_EN_SHIFT 31
#define  VFE1_FLTR_SET 0x556C
    #define VFE1_FLTR_SET_DATA_MASK 0x7FFFFFFF
    #define VFE1_FLTR_SET_DATA_SHIFT 0
#define  VFE1_RD_ADR 0x5554
    #define VFE1_RD_ADR_BASE_MASK 0x07FFFFC0
    #define VFE1_RD_ADR_BASE_SHIFT 6
#define  VFE1_RD_BUF 0x554C
    #define VFE1_RD_BUF_PITCH_MASK 0x00000FF0
    #define VFE1_RD_BUF_PITCH_SHIFT 4
    #define VFE1_RD_BUF_SIZE_MASK 0xFFFF0000
    #define VFE1_RD_BUF_SIZE_SHIFT 16
#define  VFE1_RD_CB_ADR 0x5574
    #define VFE1_RD_CB_ADR_BASE_MASK 0x07FFFFC0
    #define VFE1_RD_CB_ADR_BASE_SHIFT 6
#define  VFE1_RD_CR_ADR 0x5578
    #define VFE1_RD_CR_ADR_BASE_MASK 0x07FFFFC0
    #define VFE1_RD_CR_ADR_BASE_SHIFT 6
#define  VFE1_RD_INFO_ADR 0x5544
    #define VFE1_RD_INFO_ADR_BASE_MASK 0x07FFFFC0
    #define VFE1_RD_INFO_ADR_BASE_SHIFT 6
#define  VFE1_SCL_CTRL_A 0x5620
    #define VFE1_SCL_CTRL_A_PHASES_MASK 0x0000001F
    #define VFE1_SCL_CTRL_A_PHASES_SHIFT 0
    #define VFE1_SCL_CTRL_A_SRC_RES_MASK 0x00007F00
    #define VFE1_SCL_CTRL_A_SRC_RES_SHIFT 8
    #define VFE1_SCL_CTRL_A_DST_RES_MASK 0x007F0000
    #define VFE1_SCL_CTRL_A_DST_RES_SHIFT 16
    #define VFE1_SCL_CTRL_A_DST_WIDTH_UPPER_MASK 0x00800000
    #define VFE1_SCL_CTRL_A_DST_WIDTH_UPPER_SHIFT 23
    #define VFE1_SCL_CTRL_A_IDX_SHIFT_MASK 0x03000000
    #define VFE1_SCL_CTRL_A_IDX_SHIFT_SHIFT 24
    #define VFE1_SCL_CTRL_A_DST_WIDTH_MASK 0xFC000000
    #define VFE1_SCL_CTRL_A_DST_WIDTH_SHIFT 26
#define  VFE1_WR_BUF 0x5550
    #define VFE1_WR_BUF_PITCH_MASK 0x00000FF0
    #define VFE1_WR_BUF_PITCH_SHIFT 4
    #define VFE1_WR_BUF_SIZE_Y_MASK 0x001FF000
    #define VFE1_WR_BUF_SIZE_Y_SHIFT 12
    #define VFE1_WR_BUF_SIZE_C_MASK 0xFF000000
    #define VFE1_WR_BUF_SIZE_C_SHIFT 24
#define  VFE1_WR_INFO_ADR 0x5548
    #define VFE1_WR_INFO_ADR_BASE_MASK 0x07FFFFC0
    #define VFE1_WR_INFO_ADR_BASE_SHIFT 6
#define  VFE1_Y_WR_ADR 0x5558
    #define VFE1_Y_WR_ADR_BASE_MASK 0x07FFE000
    #define VFE1_Y_WR_ADR_BASE_SHIFT 13
#define  VFE2_FLTR_SET 0x55AC
    #define VFE2_FLTR_SET_DATA_MASK 0x7FFFFFFF
    #define VFE2_FLTR_SET_DATA_SHIFT 0
#define  VFE3_FLTR_SET 0x55EC
    #define VFE3_FLTR_SET_DATA_MASK 0x7FFFFFFF
    #define VFE3_FLTR_SET_DATA_SHIFT 0
#define  VFE_APPEND_DATA 0x5434
    #define VFE_APPEND_DATA_Y_VAL_MASK 0x000000FF
    #define VFE_APPEND_DATA_Y_VAL_SHIFT 0
    #define VFE_APPEND_DATA_CB_VAL_MASK 0x0000FF00
    #define VFE_APPEND_DATA_CB_VAL_SHIFT 8
    #define VFE_APPEND_DATA_CR_VAL_MASK 0x00FF0000
    #define VFE_APPEND_DATA_CR_VAL_SHIFT 16
#define  VFE_BLEND_DATA 0x541C
    #define EDGE0_THRES_MASK 0x0000000F
    #define EDGE0_THRES_SHIFT 0
    #define EDGE1_THRES_MASK 0x000000F0
    #define EDGE1_THRES_SHIFT 4
    #define EDGE2_THRES_MASK 0x00000F00
    #define EDGE2_THRES_SHIFT 8
    #define EDGE3_THRES_MASK 0x0000F000
    #define EDGE3_THRES_SHIFT 12
#define  VFE_DUMMY_REG 0x542C
    #define VFE_DUMMY_REG_DUMMY_BITS_MASK 0xFFFFFFFF
    #define VFE_DUMMY_REG_DUMMY_BITS_SHIFT 0
#define  VFE_FIFO_CMD 0x5424
    #define SCL_TOP_SRC_MASK 0x0000003F
    #define SCL_TOP_SRC_SHIFT 0
    #define OUTPUT_IDX_0_MASK 0x00000040
    #define OUTPUT_IDX_0_SHIFT 6
    #define OUTPUT_IDX_1_MASK 0x00000080
    #define OUTPUT_IDX_1_SHIFT 7
    #define SCL_BOT_SRC_MASK 0x00003F00
    #define SCL_BOT_SRC_SHIFT 8
    #define OUTPUT_IDX_2_MASK 0x00004000
    #define OUTPUT_IDX_2_SHIFT 14
    #define OUTPUT_IDX_3_MASK 0x00008000
    #define OUTPUT_IDX_3_SHIFT 15
    #define VFE_FIFO_CMD_SLICE_SIZE_MASK 0x007F0000
    #define VFE_FIFO_CMD_SLICE_SIZE_SHIFT 16
    #define OUTPUT_IDX_4_MASK 0x00800000
    #define OUTPUT_IDX_4_SHIFT 23
    #define REPEAT_FLD_MASK 0x03000000
    #define REPEAT_FLD_SHIFT 24
    #define OUTPUT_IDX_5_MASK 0x04000000
    #define OUTPUT_IDX_5_SHIFT 26
    #define VFE_FIFO_CMD_PROG_FRM_MASK 0x10000000
    #define VFE_FIFO_CMD_PROG_FRM_SHIFT 28
    #define VFE_FIFO_CMD_UPDATE_MASK 0x20000000
    #define VFE_FIFO_CMD_UPDATE_SHIFT 29
    #define VFE_FIFO_CMD_STREAM_MASK 0xC0000000
    #define VFE_FIFO_CMD_STREAM_SHIFT 30
#define  VFE_FIFO_FREE 0x5420
    #define VFE_FIFO_FREE_CNT_MASK 0x0000000F
    #define VFE_FIFO_FREE_CNT_SHIFT 0
#define  VFE_HOST_INT_MASK 0x5408
    #define VFE0_HOST_INT_MASK_MASK 0x00000001
    #define VFE0_HOST_INT_MASK_SHIFT 0
    #define VFE1_HOST_INT_MASK_MASK 0x00000002
    #define VFE1_HOST_INT_MASK_SHIFT 1
#define  VFE_INT_CTRL 0x5400
    #define VFE0_INT_EN_MASK 0x000000FF
    #define VFE0_INT_EN_SHIFT 0
    #define VFE1_INT_EN_MASK 0x0000FF00
    #define VFE1_INT_EN_SHIFT 8
#define  VFE_INT_STATUS 0x5404
    #define VFE0_INT_MASK 0x00000001
    #define VFE0_INT_SHIFT 0
    #define VFE1_INT_MASK 0x00000002
    #define VFE1_INT_SHIFT 1
#define  VFE_LIMIT 0x5438
    #define C_UPPER_MASK 0x000000FF
    #define C_UPPER_SHIFT 0
    #define C_LOWER_MASK 0x0000FF00
    #define C_LOWER_SHIFT 8
    #define Y_UPPER_MASK 0x00FF0000
    #define Y_UPPER_SHIFT 16
    #define Y_LOWER_MASK 0xFF000000
    #define Y_LOWER_SHIFT 24
#define  VFE_MEMCLI_ARB 0x5430
    #define COUNT_0_MASK 0x0000003F
    #define COUNT_0_SHIFT 0
    #define COUNT_1_MASK 0x00000FC0
    #define COUNT_1_SHIFT 6
    #define COUNT_2_MASK 0x0003F000
    #define COUNT_2_SHIFT 12
    #define COUNT_3_MASK 0x00FC0000
    #define COUNT_3_SHIFT 18
    #define COUNT_4_MASK 0x3F000000
    #define COUNT_4_SHIFT 24
#define  VFE_MIPS_INT_MASK 0x540C
    #define VFE0_MIPS_INT_MASK_MASK 0x00000001
    #define VFE0_MIPS_INT_MASK_SHIFT 0
    #define VFE1_MIPS_INT_MASK_MASK 0x00000002
    #define VFE1_MIPS_INT_MASK_SHIFT 1
#define  VFE_OUTPUT_IDX 0x5428
    #define VFE0_IDX_MASK 0x0000003F
    #define VFE0_IDX_SHIFT 0
    #define VFE1_IDX_MASK 0x00003F00
    #define VFE1_IDX_SHIFT 8
#define  VFE_SCL_ADR 0x5418
    #define VFE_SCL_ADR_BASE_MASK 0x07FFFFC0
    #define VFE_SCL_ADR_BASE_SHIFT 6
#define  VFE_SCL_BOT 0x5414
    #define VFE_SCL_BOT_DATA_MASK 0x01FFFFFF
    #define VFE_SCL_BOT_DATA_SHIFT 0
#define  VFE_SCL_BUF 0x562C
    #define VFE_SCL_BUF_PITCH_MASK 0x00000FF0
    #define VFE_SCL_BUF_PITCH_SHIFT 4
    #define VFE_SCL_BUF_SIZE_MASK 0xFFFF0000
    #define VFE_SCL_BUF_SIZE_SHIFT 16
#define  VFE_SCL_DATA 0x5604
    #define VFE_SCL_DATA_VALUE_MASK 0xFFFFFFFF
    #define VFE_SCL_DATA_VALUE_SHIFT 0
#define  VFE_SCL_IDX 0x5600
    #define VFE_SCL_IDX_FLD_MASK 0x00000003
    #define VFE_SCL_IDX_FLD_SHIFT 0
    #define VFE_SCL_IDX_ADR_MASK 0x0000003C
    #define VFE_SCL_IDX_ADR_SHIFT 2
    #define INPUT_MASK 0x00000080
    #define INPUT_SHIFT 7
    #define READ_OP_MASK 0x80000000
    #define READ_OP_SHIFT 31
#define  VFE_SCL_TOP 0x5410
    #define VFE_SCL_TOP_DATA_MASK 0x01FFFFFF
    #define VFE_SCL_TOP_DATA_SHIFT 0
#define  VHE0_656_CODE 0x5240
    #define VHE0_656_CODE_Y_COORD_INIT_MASK 0x00000FFF
    #define VHE0_656_CODE_Y_COORD_INIT_SHIFT 0
    #define VHE0_656_CODE_FIRST_CODE_MASK 0x003FF000
    #define VHE0_656_CODE_FIRST_CODE_SHIFT 12
    #define VHE0_656_CODE_SECOND_CODE_MASK 0xFFC00000
    #define VHE0_656_CODE_SECOND_CODE_SHIFT 22
#define  VHE0_656_CODE_CTRL 0x523C
    #define VHE0_656_CODE_CTRL_COUNT_MASK 0x00FFFFFF
    #define VHE0_656_CODE_CTRL_COUNT_SHIFT 0
    #define VHE0_656_CODE_CTRL_FIX_ANC_CODE_MASK 0x10000000
    #define VHE0_656_CODE_CTRL_FIX_ANC_CODE_SHIFT 28
    #define VHE0_656_CODE_CTRL_SECONDARY_CODE_ENABLE_MASK 0x80000000
    #define VHE0_656_CODE_CTRL_SECONDARY_CODE_ENABLE_SHIFT 31
#define  VHE0_656_CODE_SECONDARY 0x5244
    #define VHE0_656_CODE_SECONDARY_Y_COORD_INIT_MASK 0x00000FFF
    #define VHE0_656_CODE_SECONDARY_Y_COORD_INIT_SHIFT 0
    #define VHE0_656_CODE_SECONDARY_FIRST_CODE_MASK 0x003FF000
    #define VHE0_656_CODE_SECONDARY_FIRST_CODE_SHIFT 12
    #define VHE0_656_CODE_SECONDARY_SECOND_CODE_MASK 0xFFC00000
    #define VHE0_656_CODE_SECONDARY_SECOND_CODE_SHIFT 22
#define  VHE0_90KHZ_DEN 0x528C
    #define VHE0_90KHZ_DEN_DEN_MASK 0xFFFFFFFF
    #define VHE0_90KHZ_DEN_DEN_SHIFT 0
#define  VHE0_90KHZ_NUM 0x5288
    #define VHE0_90KHZ_NUM_NUM_MASK 0xFFFFFFFF
    #define VHE0_90KHZ_NUM_NUM_SHIFT 0
#define  VHE0_ACTIVE_X 0x505C
    #define VHE0_ACTIVE_X_END_MASK 0x00000FFF
    #define VHE0_ACTIVE_X_END_SHIFT 0
    #define VHE0_ACTIVE_X_START_MASK 0x0FFF0000
    #define VHE0_ACTIVE_X_START_SHIFT 16
#define  VHE0_ACTIVE_Y_BOT 0x5064
    #define VHE0_ACTIVE_Y_BOT_START_MASK 0x00000FFF
    #define VHE0_ACTIVE_Y_BOT_START_SHIFT 0
    #define VHE0_ACTIVE_Y_BOT_END_MASK 0x0FFF0000
    #define VHE0_ACTIVE_Y_BOT_END_SHIFT 16
#define  VHE0_ACTIVE_Y_TOP 0x5060
    #define VHE0_ACTIVE_Y_TOP_START_MASK 0x00000FFF
    #define VHE0_ACTIVE_Y_TOP_START_SHIFT 0
    #define VHE0_ACTIVE_Y_TOP_END_MASK 0x0FFF0000
    #define VHE0_ACTIVE_Y_TOP_END_SHIFT 16
#define  VHE0_CC_CTRL 0x5074
    #define VHE0_CC_CTRL_CC_EN_MASK 0x00000001
    #define VHE0_CC_CTRL_CC_EN_SHIFT 0
    #define VHE0_CC_CTRL_AUTO_DETECT_MASK 0x00000002
    #define VHE0_CC_CTRL_AUTO_DETECT_SHIFT 1
    #define VHE0_CC_CTRL_CC_FILTER_EN_MASK 0x00000010
    #define VHE0_CC_CTRL_CC_FILTER_EN_SHIFT 4
    #define VHE0_CC_CTRL_START_LOC_MASK 0x000FFF00
    #define VHE0_CC_CTRL_START_LOC_SHIFT 8
    #define VHE0_CC_CTRL_VBI_SAMPLE_EN_MASK 0x80000000
    #define VHE0_CC_CTRL_VBI_SAMPLE_EN_SHIFT 31
#define  VHE0_CC_SAMPLING 0x507C
    #define VHE0_CC_SAMPLING_CC_M_MASK 0x000001FF
    #define VHE0_CC_SAMPLING_CC_M_SHIFT 0
    #define VHE0_CC_SAMPLING_CC_N_MASK 0x01FF0000
    #define VHE0_CC_SAMPLING_CC_N_SHIFT 16
    #define VHE0_CC_SAMPLING_DELTA_MASK 0x70000000
    #define VHE0_CC_SAMPLING_DELTA_SHIFT 28
#define  VHE0_CC_THRES 0x5078
    #define VHE0_CC_THRES_THRES_LOW_MASK 0x000003FF
    #define VHE0_CC_THRES_THRES_LOW_SHIFT 0
    #define VHE0_CC_THRES_THRES_HIGH_MASK 0x03FF0000
    #define VHE0_CC_THRES_THRES_HIGH_SHIFT 16
#define  VHE0_CHROMA_BORDER 0x50B8
    #define VHE0_CHROMA_BORDER_CB_VAL_MASK 0x000003FF
    #define VHE0_CHROMA_BORDER_CB_VAL_SHIFT 0
    #define VHE0_CHROMA_BORDER_CR_VAL_MASK 0x03FF0000
    #define VHE0_CHROMA_BORDER_CR_VAL_SHIFT 16
#define  VHE0_DEN 0x5298
    #define VHE0_DEN_DEN_MASK 0xFFFFFFFF
    #define VHE0_DEN_DEN_SHIFT 0
#define  VHE0_GENLOCK_LOWER 0x52A0
    #define VHE0_GENLOCK_LOWER_GENLOCK_L_MASK 0xFFFFFFFF
    #define VHE0_GENLOCK_LOWER_GENLOCK_L_SHIFT 0
#define  VHE0_GENLOCK_UPPER 0x529C
    #define VHE0_GENLOCK_UPPER_GENLOCK_U_MASK 0x000003FF
    #define VHE0_GENLOCK_UPPER_GENLOCK_U_SHIFT 0
#define  VHE0_INFO_ADR 0x5090
    #define VHE0_INFO_ADR_BASE_MASK 0x07FFFFC0
    #define VHE0_INFO_ADR_BASE_SHIFT 6
#define  VHE0_INPUT_CTRL 0x50A4
    #define VHE0_INPUT_CTRL_INPUT_EN_MASK 0x00000001
    #define VHE0_INPUT_CTRL_INPUT_EN_SHIFT 0
    #define VHE0_INPUT_CTRL_SRC_MASK 0x00000002
    #define VHE0_INPUT_CTRL_SRC_SHIFT 1
    #define VHE0_INPUT_CTRL_BIT_SIZE_MASK 0x00000020
    #define VHE0_INPUT_CTRL_BIT_SIZE_SHIFT 5
    #define VHE0_INPUT_CTRL_CAP_FLD_SEL_MASK 0x000000C0
    #define VHE0_INPUT_CTRL_CAP_FLD_SEL_SHIFT 6
    #define VHE0_INPUT_CTRL_VBI_FLD_SEL_MASK 0x00000300
    #define VHE0_INPUT_CTRL_VBI_FLD_SEL_SHIFT 8
    #define VHE0_INPUT_CTRL_CCIR656_MODE_MASK 0x00000400
    #define VHE0_INPUT_CTRL_CCIR656_MODE_SHIFT 10
    #define VHE0_INPUT_CTRL_BIT_EXTEND_MASK 0x00000800
    #define VHE0_INPUT_CTRL_BIT_EXTEND_SHIFT 11
    #define VHE0_INPUT_CTRL_MEM_LINEAR_MASK 0x00001000
    #define VHE0_INPUT_CTRL_MEM_LINEAR_SHIFT 12
    #define VHE0_INPUT_CTRL_MEM_PACKING_MASK 0x00002000
    #define VHE0_INPUT_CTRL_MEM_PACKING_SHIFT 13
    #define VHE0_INPUT_CTRL_MEM_ROUND_MASK 0x00004000
    #define VHE0_INPUT_CTRL_MEM_ROUND_SHIFT 14
    #define VHE0_INPUT_CTRL_BYPASS_MODE_MASK 0x00008000
    #define VHE0_INPUT_CTRL_BYPASS_MODE_SHIFT 15
    #define VHE0_INPUT_CTRL_PREFETCH_PELS_MASK 0x0FFF0000
    #define VHE0_INPUT_CTRL_PREFETCH_PELS_SHIFT 16
    #define VHE0_INPUT_CTRL_EXT_SYNC_EN_MASK 0x10000000
    #define VHE0_INPUT_CTRL_EXT_SYNC_EN_SHIFT 28
    #define VHE0_INPUT_CTRL_SAMPLE_CLK_EDGE_MASK 0x20000000
    #define VHE0_INPUT_CTRL_SAMPLE_CLK_EDGE_SHIFT 29
#define  VHE0_INPUT_STATUS 0x5230
    #define VHE0_INPUT_STATUS_WADDR_MASK 0x0000000F
    #define VHE0_INPUT_STATUS_WADDR_SHIFT 0
    #define VHE0_INPUT_STATUS_RADDR_MASK 0x00000F00
    #define VHE0_INPUT_STATUS_RADDR_SHIFT 8
    #define VHE0_INPUT_STATUS_EMPTY_MASK 0x00010000
    #define VHE0_INPUT_STATUS_EMPTY_SHIFT 16
    #define VHE0_INPUT_STATUS_FULL_MASK 0x00100000
    #define VHE0_INPUT_STATUS_FULL_SHIFT 20
    #define VHE0_INPUT_STATUS_NO_IN_FIFO_MASK 0x1F000000
    #define VHE0_INPUT_STATUS_NO_IN_FIFO_SHIFT 24
#define  VHE0_LINE_VALID 0x52D4
    #define VHE0_LINE_VALID_TIMEOUT_CNT_MASK 0x00001FFF
    #define VHE0_LINE_VALID_TIMEOUT_CNT_SHIFT 0
    #define VHE0_LINE_VALID_XOR_LV_MASK 0x00010000
    #define VHE0_LINE_VALID_XOR_LV_SHIFT 16
#define  VHE0_LUMA_BORDER 0x50B4
    #define VHE0_LUMA_BORDER_Y_VAL_MASK 0x000003FF
    #define VHE0_LUMA_BORDER_Y_VAL_SHIFT 0
#define  VHE0_NUM 0x5294
    #define VHE0_NUM_NUM_MASK 0xFFFFFFFF
    #define VHE0_NUM_NUM_SHIFT 0
#define  VHE0_RUN_STATUS 0x5234
    #define VHE0_RUN_STATUS_X_COORD_MASK 0x00000FFF
    #define VHE0_RUN_STATUS_X_COORD_SHIFT 0
    #define VHE0_RUN_STATUS_Y_COORD_MASK 0x0FFF0000
    #define VHE0_RUN_STATUS_Y_COORD_SHIFT 16
#define  VHE0_SCL_ADR 0x5084
    #define VHE0_SCL_ADR_BASE_MASK 0x07FFFF80
    #define VHE0_SCL_ADR_BASE_SHIFT 7
#define  VHE0_SCL_BUF 0x5080
    #define VHE0_SCL_BUF_PITCH_MASK 0x00000F00
    #define VHE0_SCL_BUF_PITCH_SHIFT 8
    #define VHE0_SCL_BUF_CNT_MASK 0x0003F000
    #define VHE0_SCL_BUF_CNT_SHIFT 12
    #define VHE0_SCL_BUF_SIZE_TOP_BIT_MASK 0x00040000
    #define VHE0_SCL_BUF_SIZE_TOP_BIT_SHIFT 18
    #define VHE0_SCL_BUF_SIZE_MSB_MASK 0x00080000
    #define VHE0_SCL_BUF_SIZE_MSB_SHIFT 19
    #define VHE0_SCL_BUF_SIZE_MASK 0xFFF00000
    #define VHE0_SCL_BUF_SIZE_SHIFT 20
#define  VHE0_SCL_CB_ADR 0x50AC
    #define VHE0_SCL_CB_ADR_BASE_MASK 0x07FFFF80
    #define VHE0_SCL_CB_ADR_BASE_SHIFT 7
#define  VHE0_SCL_CR_ADR 0x50B0
    #define VHE0_SCL_CR_ADR_BASE_MASK 0x07FFFF80
    #define VHE0_SCL_CR_ADR_BASE_SHIFT 7
#define  VHE0_TBC_SAMPLE 0x5238
    #define VHE0_TBC_SAMPLE_COUNT_MASK 0x00FFFFFF
    #define VHE0_TBC_SAMPLE_COUNT_SHIFT 0
#define  VHE0_TIMESTAMP_CTRL 0x5098
    #define VHE0_TIMESTAMP_CTRL_OFFSET_MASK 0xFFFFFFFF
    #define VHE0_TIMESTAMP_CTRL_OFFSET_SHIFT 0
#define  VHE0_TIMESTAMP_LOWER 0x52C4
    #define VHE0_TIMESTAMP_LOWER_TIMESTAMP_L_MASK 0xFFFFFFFF
    #define VHE0_TIMESTAMP_LOWER_TIMESTAMP_L_SHIFT 0
#define  VHE0_TIMESTAMP_SEL 0x5290
    #define VHE0_TIMESTAMP_SEL_TIMESTAMP_SEL_MASK 0x00000007
    #define VHE0_TIMESTAMP_SEL_TIMESTAMP_SEL_SHIFT 0
#define  VHE0_TIMESTAMP_UPPER 0x52C0
    #define VHE0_TIMESTAMP_UPPER_TIMESTAMP_U_MASK 0x00000001
    #define VHE0_TIMESTAMP_UPPER_TIMESTAMP_U_SHIFT 0
#define  VHE0_VBI_ADR 0x508C
    #define VHE0_VBI_ADR_BASE_MASK 0x07FFFF80
    #define VHE0_VBI_ADR_BASE_SHIFT 7
#define  VHE0_VBI_BUF 0x5088
    #define VHE0_VBI_BUF_PITCH_MASK 0x00000F80
    #define VHE0_VBI_BUF_PITCH_SHIFT 7
    #define VHE0_VBI_BUF_CNT_MASK 0x000FF000
    #define VHE0_VBI_BUF_CNT_SHIFT 12
    #define VHE0_VBI_BUF_SIZE_MASK 0xFFF00000
    #define VHE0_VBI_BUF_SIZE_SHIFT 20
#define  VHE0_VBI_SAMPLE 0x50A8
    #define VHE0_VBI_SAMPLE_MIN_SAMPLE_MASK 0x000003FF
    #define VHE0_VBI_SAMPLE_MIN_SAMPLE_SHIFT 0
    #define VHE0_VBI_SAMPLE_MAX_SAMPLE_MASK 0x03FF0000
    #define VHE0_VBI_SAMPLE_MAX_SAMPLE_SHIFT 16
    #define VHE0_VBI_SAMPLE_SAMPLE_VALID_MASK 0x80000000
    #define VHE0_VBI_SAMPLE_SAMPLE_VALID_SHIFT 31
#define  VHE0_VBI_X 0x5050
    #define VHE0_VBI_X_START_MASK 0x00000FFF
    #define VHE0_VBI_X_START_SHIFT 0
    #define VHE0_VBI_X_END_MASK 0x0FFF0000
    #define VHE0_VBI_X_END_SHIFT 16
#define  VHE0_VBI_Y_BOT 0x5058
    #define VHE0_VBI_Y_BOT_START_MASK 0x00000FFF
    #define VHE0_VBI_Y_BOT_START_SHIFT 0
    #define VHE0_VBI_Y_BOT_END_MASK 0x0FFF0000
    #define VHE0_VBI_Y_BOT_END_SHIFT 16
#define  VHE0_VBI_Y_TOP 0x5054
    #define VHE0_VBI_Y_TOP_START_MASK 0x00000FFF
    #define VHE0_VBI_Y_TOP_START_SHIFT 0
    #define VHE0_VBI_Y_TOP_END_MASK 0x0FFF0000
    #define VHE0_VBI_Y_TOP_END_SHIFT 16
#define  VHE0_VIDEO_X 0x5068
    #define VHE0_VIDEO_X_START_MASK 0x00000FFF
    #define VHE0_VIDEO_X_START_SHIFT 0
    #define VHE0_VIDEO_X_END_MASK 0x0FFF0000
    #define VHE0_VIDEO_X_END_SHIFT 16
#define  VHE0_VIDEO_Y_BOT 0x5070
    #define VHE0_VIDEO_Y_BOT_START_MASK 0x00000FFF
    #define VHE0_VIDEO_Y_BOT_START_SHIFT 0
    #define VHE0_VIDEO_Y_BOT_END_MASK 0x0FFF0000
    #define VHE0_VIDEO_Y_BOT_END_SHIFT 16
#define  VHE0_VIDEO_Y_TOP 0x506C
    #define VHE0_VIDEO_Y_TOP_START_MASK 0x00000FFF
    #define VHE0_VIDEO_Y_TOP_START_SHIFT 0
    #define VHE0_VIDEO_Y_TOP_END_MASK 0x0FFF0000
    #define VHE0_VIDEO_Y_TOP_END_SHIFT 16
#define  VHE0_WAIT_FOR_SAMPLES 0x5248
    #define VHE0_WAIT_FOR_SAMPLES_WAIT_FOR_SAMPLES_MASK 0x00000FFF
    #define VHE0_WAIT_FOR_SAMPLES_WAIT_FOR_SAMPLES_SHIFT 0
#define  VHE1_656_CODE 0x5270
    #define VHE1_656_CODE_Y_COORD_INIT_MASK 0x00000FFF
    #define VHE1_656_CODE_Y_COORD_INIT_SHIFT 0
    #define VHE1_656_CODE_FIRST_CODE_MASK 0x003FF000
    #define VHE1_656_CODE_FIRST_CODE_SHIFT 12
    #define VHE1_656_CODE_SECOND_CODE_MASK 0xFFC00000
    #define VHE1_656_CODE_SECOND_CODE_SHIFT 22
#define  VHE1_656_CODE_CTRL 0x526C
    #define VHE1_656_CODE_CTRL_COUNT_MASK 0x00FFFFFF
    #define VHE1_656_CODE_CTRL_COUNT_SHIFT 0
    #define VHE1_656_CODE_CTRL_FIX_ANC_CODE_MASK 0x10000000
    #define VHE1_656_CODE_CTRL_FIX_ANC_CODE_SHIFT 28
    #define VHE1_656_CODE_CTRL_SECONDARY_CODE_ENABLE_MASK 0x80000000
    #define VHE1_656_CODE_CTRL_SECONDARY_CODE_ENABLE_SHIFT 31
#define  VHE1_656_CODE_SECONDARY 0x5274
    #define VHE1_656_CODE_SECONDARY_Y_COORD_INIT_MASK 0x00000FFF
    #define VHE1_656_CODE_SECONDARY_Y_COORD_INIT_SHIFT 0
    #define VHE1_656_CODE_SECONDARY_FIRST_CODE_MASK 0x003FF000
    #define VHE1_656_CODE_SECONDARY_FIRST_CODE_SHIFT 12
    #define VHE1_656_CODE_SECONDARY_SECOND_CODE_MASK 0xFFC00000
    #define VHE1_656_CODE_SECONDARY_SECOND_CODE_SHIFT 22
#define  VHE1_90KHZ_DEN 0x52A8
    #define VHE1_90KHZ_DEN_DEN_MASK 0xFFFFFFFF
    #define VHE1_90KHZ_DEN_DEN_SHIFT 0
#define  VHE1_90KHZ_NUM 0x52A4
    #define VHE1_90KHZ_NUM_NUM_MASK 0xFFFFFFFF
    #define VHE1_90KHZ_NUM_NUM_SHIFT 0
#define  VHE1_ACTIVE_X 0x50CC
    #define VHE1_ACTIVE_X_END_MASK 0x00000FFF
    #define VHE1_ACTIVE_X_END_SHIFT 0
    #define VHE1_ACTIVE_X_START_MASK 0x0FFF0000
    #define VHE1_ACTIVE_X_START_SHIFT 16
#define  VHE1_ACTIVE_Y_BOT 0x50D4
    #define VHE1_ACTIVE_Y_BOT_START_MASK 0x00000FFF
    #define VHE1_ACTIVE_Y_BOT_START_SHIFT 0
    #define VHE1_ACTIVE_Y_BOT_END_MASK 0x0FFF0000
    #define VHE1_ACTIVE_Y_BOT_END_SHIFT 16
#define  VHE1_ACTIVE_Y_TOP 0x50D0
    #define VHE1_ACTIVE_Y_TOP_START_MASK 0x00000FFF
    #define VHE1_ACTIVE_Y_TOP_START_SHIFT 0
    #define VHE1_ACTIVE_Y_TOP_END_MASK 0x0FFF0000
    #define VHE1_ACTIVE_Y_TOP_END_SHIFT 16
#define  VHE1_CC_CTRL 0x50E4
    #define VHE1_CC_CTRL_CC_EN_MASK 0x00000001
    #define VHE1_CC_CTRL_CC_EN_SHIFT 0
    #define VHE1_CC_CTRL_AUTO_DETECT_MASK 0x00000002
    #define VHE1_CC_CTRL_AUTO_DETECT_SHIFT 1
    #define VHE1_CC_CTRL_CC_FILTER_EN_MASK 0x00000010
    #define VHE1_CC_CTRL_CC_FILTER_EN_SHIFT 4
    #define VHE1_CC_CTRL_START_LOC_MASK 0x000FFF00
    #define VHE1_CC_CTRL_START_LOC_SHIFT 8
    #define VHE1_CC_CTRL_VBI_SAMPLE_EN_MASK 0x80000000
    #define VHE1_CC_CTRL_VBI_SAMPLE_EN_SHIFT 31
#define  VHE1_CC_SAMPLING 0x50EC
    #define VHE1_CC_SAMPLING_CC_M_MASK 0x000001FF
    #define VHE1_CC_SAMPLING_CC_M_SHIFT 0
    #define VHE1_CC_SAMPLING_CC_N_MASK 0x01FF0000
    #define VHE1_CC_SAMPLING_CC_N_SHIFT 16
    #define VHE1_CC_SAMPLING_DELTA_MASK 0x70000000
    #define VHE1_CC_SAMPLING_DELTA_SHIFT 28
#define  VHE1_CC_THRES 0x50E8
    #define VHE1_CC_THRES_THRES_LOW_MASK 0x000003FF
    #define VHE1_CC_THRES_THRES_LOW_SHIFT 0
    #define VHE1_CC_THRES_THRES_HIGH_MASK 0x03FF0000
    #define VHE1_CC_THRES_THRES_HIGH_SHIFT 16
#define  VHE1_CHROMA_BORDER 0x5128
    #define VHE1_CHROMA_BORDER_CB_VAL_MASK 0x000003FF
    #define VHE1_CHROMA_BORDER_CB_VAL_SHIFT 0
    #define VHE1_CHROMA_BORDER_CR_VAL_MASK 0x03FF0000
    #define VHE1_CHROMA_BORDER_CR_VAL_SHIFT 16
#define  VHE1_DEN 0x52B4
    #define VHE1_DEN_DEN_MASK 0xFFFFFFFF
    #define VHE1_DEN_DEN_SHIFT 0
#define  VHE1_GENLOCK_LOWER 0x52BC
    #define VHE1_GENLOCK_LOWER_GENLOCK_L_MASK 0xFFFFFFFF
    #define VHE1_GENLOCK_LOWER_GENLOCK_L_SHIFT 0
#define  VHE1_GENLOCK_UPPER 0x52B8
    #define VHE1_GENLOCK_UPPER_GENLOCK_U_MASK 0x000003FF
    #define VHE1_GENLOCK_UPPER_GENLOCK_U_SHIFT 0
#define  VHE1_INFO_ADR 0x5100
    #define VHE1_INFO_ADR_BASE_MASK 0x07FFFFC0
    #define VHE1_INFO_ADR_BASE_SHIFT 6
#define  VHE1_INPUT_CTRL 0x5114
    #define VHE1_INPUT_CTRL_INPUT_EN_MASK 0x00000001
    #define VHE1_INPUT_CTRL_INPUT_EN_SHIFT 0
    #define VHE1_INPUT_CTRL_SRC_MASK 0x00000002
    #define VHE1_INPUT_CTRL_SRC_SHIFT 1
    #define VHE1_INPUT_CTRL_BIT_SIZE_MASK 0x00000020
    #define VHE1_INPUT_CTRL_BIT_SIZE_SHIFT 5
    #define VHE1_INPUT_CTRL_CAP_FLD_SEL_MASK 0x000000C0
    #define VHE1_INPUT_CTRL_CAP_FLD_SEL_SHIFT 6
    #define VHE1_INPUT_CTRL_VBI_FLD_SEL_MASK 0x00000300
    #define VHE1_INPUT_CTRL_VBI_FLD_SEL_SHIFT 8
    #define VHE1_INPUT_CTRL_CCIR656_MODE_MASK 0x00000400
    #define VHE1_INPUT_CTRL_CCIR656_MODE_SHIFT 10
    #define VHE1_INPUT_CTRL_BIT_EXTEND_MASK 0x00000800
    #define VHE1_INPUT_CTRL_BIT_EXTEND_SHIFT 11
    #define VHE1_INPUT_CTRL_MEM_LINEAR_MASK 0x00001000
    #define VHE1_INPUT_CTRL_MEM_LINEAR_SHIFT 12
    #define VHE1_INPUT_CTRL_MEM_PACKING_MASK 0x00002000
    #define VHE1_INPUT_CTRL_MEM_PACKING_SHIFT 13
    #define VHE1_INPUT_CTRL_MEM_ROUND_MASK 0x00004000
    #define VHE1_INPUT_CTRL_MEM_ROUND_SHIFT 14
    #define VHE1_INPUT_CTRL_BYPASS_MODE_MASK 0x00008000
    #define VHE1_INPUT_CTRL_BYPASS_MODE_SHIFT 15
    #define VHE1_INPUT_CTRL_PREFETCH_PELS_MASK 0x0FFF0000
    #define VHE1_INPUT_CTRL_PREFETCH_PELS_SHIFT 16
    #define VHE1_INPUT_CTRL_EXT_SYNC_EN_MASK 0x10000000
    #define VHE1_INPUT_CTRL_EXT_SYNC_EN_SHIFT 28
    #define VHE1_INPUT_CTRL_SAMPLE_CLK_EDGE_MASK 0x20000000
    #define VHE1_INPUT_CTRL_SAMPLE_CLK_EDGE_SHIFT 29
#define  VHE1_INPUT_STATUS 0x5260
    #define VHE1_INPUT_STATUS_WADDR_MASK 0x0000000F
    #define VHE1_INPUT_STATUS_WADDR_SHIFT 0
    #define VHE1_INPUT_STATUS_RADDR_MASK 0x00000F00
    #define VHE1_INPUT_STATUS_RADDR_SHIFT 8
    #define VHE1_INPUT_STATUS_EMPTY_MASK 0x00010000
    #define VHE1_INPUT_STATUS_EMPTY_SHIFT 16
    #define VHE1_INPUT_STATUS_FULL_MASK 0x00100000
    #define VHE1_INPUT_STATUS_FULL_SHIFT 20
    #define VHE1_INPUT_STATUS_NO_IN_FIFO_MASK 0x1F000000
    #define VHE1_INPUT_STATUS_NO_IN_FIFO_SHIFT 24
#define  VHE1_LINE_VALID 0x52D8
    #define VHE1_LINE_VALID_TIMEOUT_CNT_MASK 0x00001FFF
    #define VHE1_LINE_VALID_TIMEOUT_CNT_SHIFT 0
    #define VHE1_LINE_VALID_XOR_LV_MASK 0x00010000
    #define VHE1_LINE_VALID_XOR_LV_SHIFT 16
#define  VHE1_LUMA_BORDER 0x5124
    #define VHE1_LUMA_BORDER_Y_VAL_MASK 0x000003FF
    #define VHE1_LUMA_BORDER_Y_VAL_SHIFT 0
#define  VHE1_NUM 0x52B0
    #define VHE1_NUM_NUM_MASK 0xFFFFFFFF
    #define VHE1_NUM_NUM_SHIFT 0
#define  VHE1_RUN_STATUS 0x5264
    #define VHE1_RUN_STATUS_X_COORD_MASK 0x00000FFF
    #define VHE1_RUN_STATUS_X_COORD_SHIFT 0
    #define VHE1_RUN_STATUS_Y_COORD_MASK 0x0FFF0000
    #define VHE1_RUN_STATUS_Y_COORD_SHIFT 16
#define  VHE1_SCL_ADR 0x50F4
    #define VHE1_SCL_ADR_BASE_MASK 0x07FFFF80
    #define VHE1_SCL_ADR_BASE_SHIFT 7
#define  VHE1_SCL_BUF 0x50F0
    #define VHE1_SCL_BUF_PITCH_MASK 0x00000F00
    #define VHE1_SCL_BUF_PITCH_SHIFT 8
    #define VHE1_SCL_BUF_CNT_MASK 0x0003F000
    #define VHE1_SCL_BUF_CNT_SHIFT 12
    #define VHE1_SCL_BUF_SIZE_TOP_BIT_MASK 0x00040000
    #define VHE1_SCL_BUF_SIZE_TOP_BIT_SHIFT 18
    #define VHE1_SCL_BUF_SIZE_MSB_MASK 0x00080000
    #define VHE1_SCL_BUF_SIZE_MSB_SHIFT 19
    #define VHE1_SCL_BUF_SIZE_MASK 0xFFF00000
    #define VHE1_SCL_BUF_SIZE_SHIFT 20
#define  VHE1_SCL_CB_ADR 0x511C
    #define VHE1_SCL_CB_ADR_BASE_MASK 0x07FFFF80
    #define VHE1_SCL_CB_ADR_BASE_SHIFT 7
#define  VHE1_SCL_CR_ADR 0x5120
    #define VHE1_SCL_CR_ADR_BASE_MASK 0x07FFFF80
    #define VHE1_SCL_CR_ADR_BASE_SHIFT 7
#define  VHE1_TBC_SAMPLE 0x5268
    #define VHE1_TBC_SAMPLE_COUNT_MASK 0x00FFFFFF
    #define VHE1_TBC_SAMPLE_COUNT_SHIFT 0
#define  VHE1_TIMESTAMP_CTRL 0x5108
    #define VHE1_TIMESTAMP_CTRL_OFFSET_MASK 0xFFFFFFFF
    #define VHE1_TIMESTAMP_CTRL_OFFSET_SHIFT 0
#define  VHE1_TIMESTAMP_LOWER 0x52D0
    #define VHE1_TIMESTAMP_LOWER_TIMESTAMP_L_MASK 0xFFFFFFFF
    #define VHE1_TIMESTAMP_LOWER_TIMESTAMP_L_SHIFT 0
#define  VHE1_TIMESTAMP_SEL 0x52AC
    #define VHE1_TIMESTAMP_SEL_TIMESTAMP_SEL_MASK 0x00000007
    #define VHE1_TIMESTAMP_SEL_TIMESTAMP_SEL_SHIFT 0
#define  VHE1_TIMESTAMP_UPPER 0x52C8
    #define VHE1_TIMESTAMP_UPPER_TIMESTAMP_U_MASK 0x00000001
    #define VHE1_TIMESTAMP_UPPER_TIMESTAMP_U_SHIFT 0
#define  VHE1_VBI_ADR 0x50FC
    #define VHE1_VBI_ADR_BASE_MASK 0x07FFFF80
    #define VHE1_VBI_ADR_BASE_SHIFT 7
#define  VHE1_VBI_BUF 0x50F8
    #define VHE1_VBI_BUF_PITCH_MASK 0x00000F80
    #define VHE1_VBI_BUF_PITCH_SHIFT 7
    #define VHE1_VBI_BUF_CNT_MASK 0x000FF000
    #define VHE1_VBI_BUF_CNT_SHIFT 12
    #define VHE1_VBI_BUF_SIZE_MASK 0xFFF00000
    #define VHE1_VBI_BUF_SIZE_SHIFT 20
#define  VHE1_VBI_SAMPLE 0x5118
    #define VHE1_VBI_SAMPLE_MIN_SAMPLE_MASK 0x000003FF
    #define VHE1_VBI_SAMPLE_MIN_SAMPLE_SHIFT 0
    #define VHE1_VBI_SAMPLE_MAX_SAMPLE_MASK 0x03FF0000
    #define VHE1_VBI_SAMPLE_MAX_SAMPLE_SHIFT 16
    #define VHE1_VBI_SAMPLE_SAMPLE_VALID_MASK 0x80000000
    #define VHE1_VBI_SAMPLE_SAMPLE_VALID_SHIFT 31
#define  VHE1_VBI_X 0x50C0
    #define VHE1_VBI_X_START_MASK 0x00000FFF
    #define VHE1_VBI_X_START_SHIFT 0
    #define VHE1_VBI_X_END_MASK 0x0FFF0000
    #define VHE1_VBI_X_END_SHIFT 16
#define  VHE1_VBI_Y_BOT 0x50C8
    #define VHE1_VBI_Y_BOT_START_MASK 0x00000FFF
    #define VHE1_VBI_Y_BOT_START_SHIFT 0
    #define VHE1_VBI_Y_BOT_END_MASK 0x0FFF0000
    #define VHE1_VBI_Y_BOT_END_SHIFT 16
#define  VHE1_VBI_Y_TOP 0x50C4
    #define VHE1_VBI_Y_TOP_START_MASK 0x00000FFF
    #define VHE1_VBI_Y_TOP_START_SHIFT 0
    #define VHE1_VBI_Y_TOP_END_MASK 0x0FFF0000
    #define VHE1_VBI_Y_TOP_END_SHIFT 16
#define  VHE1_VIDEO_X 0x50D8
    #define VHE1_VIDEO_X_START_MASK 0x00000FFF
    #define VHE1_VIDEO_X_START_SHIFT 0
    #define VHE1_VIDEO_X_END_MASK 0x0FFF0000
    #define VHE1_VIDEO_X_END_SHIFT 16
#define  VHE1_VIDEO_Y_BOT 0x50E0
    #define VHE1_VIDEO_Y_BOT_START_MASK 0x00000FFF
    #define VHE1_VIDEO_Y_BOT_START_SHIFT 0
    #define VHE1_VIDEO_Y_BOT_END_MASK 0x0FFF0000
    #define VHE1_VIDEO_Y_BOT_END_SHIFT 16
#define  VHE1_VIDEO_Y_TOP 0x50DC
    #define VHE1_VIDEO_Y_TOP_START_MASK 0x00000FFF
    #define VHE1_VIDEO_Y_TOP_START_SHIFT 0
    #define VHE1_VIDEO_Y_TOP_END_MASK 0x0FFF0000
    #define VHE1_VIDEO_Y_TOP_END_SHIFT 16
#define  VHE1_WAIT_FOR_SAMPLES 0x5278
    #define VHE1_WAIT_FOR_SAMPLES_WAIT_FOR_SAMPLES_MASK 0x00000FFF
    #define VHE1_WAIT_FOR_SAMPLES_WAIT_FOR_SAMPLES_SHIFT 0
#define  VHE_CORING 0x527C
    #define CB_CR_LOCKED_MASK 0x00000001
    #define CB_CR_LOCKED_SHIFT 0
    #define VHE_CORING_ENABLE_VBI_MASK 0x00000010
    #define VHE_CORING_ENABLE_VBI_SHIFT 4
    #define VHE_CORING_RANGE_MASK 0x001F0000
    #define VHE_CORING_RANGE_SHIFT 16
#define  VHE_CORING_X 0x5284
    #define VHE_CORING_X_START_MASK 0x00000FFF
    #define VHE_CORING_X_START_SHIFT 0
    #define VHE_CORING_X_END_MASK 0x0FFF0000
    #define VHE_CORING_X_END_SHIFT 16
#define  VHE_CTRL 0x5014
    #define SEGMENTS_MASK 0x00000003
    #define SEGMENTS_SHIFT 0
    #define URGENT_THRES_MASK 0x000003F0
    #define URGENT_THRES_SHIFT 4
    #define BYPASS_COUNT_MASK 0x001F0000
    #define BYPASS_COUNT_SHIFT 16
    #define INPUT_TYPE_MASK 0x01000000
    #define INPUT_TYPE_SHIFT 24
    #define VHE_CTRL_DUPLICATE_CODE_MASK 0x02000000
    #define VHE_CTRL_DUPLICATE_CODE_SHIFT 25
    #define LUMA_ORDER_MASK 0x04000000
    #define LUMA_ORDER_SHIFT 26
    #define VHE_CTRL_DDR_MODE_MASK 0x10000000
    #define VHE_CTRL_DDR_MODE_SHIFT 28
    #define DDR_MODE_VHE1_MASK 0x20000000
    #define DDR_MODE_VHE1_SHIFT 29
    #define VHE_CTRL_EXT_SYNC_MODE_MASK 0x40000000
    #define VHE_CTRL_EXT_SYNC_MODE_SHIFT 30
    #define FIRST_PEL_B_MASK 0x80000000
    #define FIRST_PEL_B_SHIFT 31
#define  VHE_DEBUG_REG 0x52E0
    #define VHE_DEBUG_REG_DEBUG_DATA_MASK 0x000FFFFF
    #define VHE_DEBUG_REG_DEBUG_DATA_SHIFT 0
#define  VHE_DUMMY_REG 0x5028
    #define USE_HW_FIELD_FIX_MASK 0x00000004
    #define USE_HW_FIELD_FIX_SHIFT 2
    #define LOCK_INFO_CNT_MASK 0x00000008
    #define LOCK_INFO_CNT_SHIFT 3
    #define DUMP_CC_DEBUG_MASK 0x00000010
    #define DUMP_CC_DEBUG_SHIFT 4
    #define VHE_DUMMY_REG_DUMMY_BITS_MASK 0xFFFFFFE0
    #define VHE_DUMMY_REG_DUMMY_BITS_SHIFT 5
#define  VHE_HOST_INT_MASK 0x500C
    #define VHE0_HOST_INT_MASK_MASK 0x00000001
    #define VHE0_HOST_INT_MASK_SHIFT 0
    #define VHE1_HOST_INT_MASK_MASK 0x00000002
    #define VHE1_HOST_INT_MASK_SHIFT 1
    #define VBI0_HOST_INT_MASK_MASK 0x00010000
    #define VBI0_HOST_INT_MASK_SHIFT 16
    #define VBI1_HOST_INT_MASK_MASK 0x00020000
    #define VBI1_HOST_INT_MASK_SHIFT 17
#define  VHE_INT_CTRL 0x5000
    #define VHE0_INT_EN_MASK 0x000000FF
    #define VHE0_INT_EN_SHIFT 0
    #define VHE1_INT_EN_MASK 0x0000FF00
    #define VHE1_INT_EN_SHIFT 8
#define  VHE_INT_STATUS 0x5008
    #define VHE0_INT_MASK 0x00000001
    #define VHE0_INT_SHIFT 0
    #define VHE1_INT_MASK 0x00000002
    #define VHE1_INT_SHIFT 1
    #define VBI0_INT_MASK 0x00010000
    #define VBI0_INT_SHIFT 16
    #define VBI1_INT_MASK 0x00020000
    #define VBI1_INT_SHIFT 17
#define  VHE_MEMARB_CTRL 0x524C
    #define VHE_MEMARB_CTRL_PF_ARB_DIS_MASK 0x00000001
    #define VHE_MEMARB_CTRL_PF_ARB_DIS_SHIFT 0
    #define VHE_MEMARB_CTRL_ABS_PRIORITY_MASK 0x00000002
    #define VHE_MEMARB_CTRL_ABS_PRIORITY_SHIFT 1
    #define VHE_MEMARB_CTRL_CLI0_TIMER_MASK 0x000000F0
    #define VHE_MEMARB_CTRL_CLI0_TIMER_SHIFT 4
    #define VHE_MEMARB_CTRL_CLI1_TIMER_MASK 0x00000F00
    #define VHE_MEMARB_CTRL_CLI1_TIMER_SHIFT 8
    #define VHE_MEMARB_CTRL_CLI2_TIMER_MASK 0x0000F000
    #define VHE_MEMARB_CTRL_CLI2_TIMER_SHIFT 12
    #define VHE_MEMARB_CTRL_CLI3_TIMER_MASK 0x000F0000
    #define VHE_MEMARB_CTRL_CLI3_TIMER_SHIFT 16
#define  VHE_MIPS_INT_MASK 0x5010
    #define VHE0_MIPS_INT_MASK_MASK 0x00000001
    #define VHE0_MIPS_INT_MASK_SHIFT 0
    #define VHE1_MIPS_INT_MASK_MASK 0x00000002
    #define VHE1_MIPS_INT_MASK_SHIFT 1
    #define VBI0_MIPS_INT_MASK_MASK 0x00010000
    #define VBI0_MIPS_INT_MASK_SHIFT 16
    #define VBI1_MIPS_INT_MASK_MASK 0x00020000
    #define VBI1_MIPS_INT_MASK_SHIFT 17
#define  VHE_OUTPUT_IDX 0x5020
    #define VHE0_IDX_MASK 0x0000007F
    #define VHE0_IDX_SHIFT 0
    #define VHE1_IDX_MASK 0x00007F00
    #define VHE1_IDX_SHIFT 8
#define  VHE_STATUS 0x503C
    #define VHE0_DONE_MASK 0x00000001
    #define VHE0_DONE_SHIFT 0
    #define VHE1_DONE_MASK 0x00000002
    #define VHE1_DONE_SHIFT 1
#define  VHE_TEST_CTRL 0x52DC
    #define TEST_MODE_EN_MASK 0x00000001
    #define TEST_MODE_EN_SHIFT 0
    #define TEST_MODE_SEL_MASK 0x00000070
    #define TEST_MODE_SEL_SHIFT 4
#define  VHE_VBI_IDX 0x5024
    #define VBI0_IDX_MASK 0x000000FF
    #define VBI0_IDX_SHIFT 0
    #define VBI1_IDX_MASK 0x0000FF00
    #define VBI1_IDX_SHIFT 8
#define  VHE_VBI_INT_CTRL 0x5004
    #define VBI0_INT_EN_MASK 0x000000FF
    #define VBI0_INT_EN_SHIFT 0
    #define VBI1_INT_EN_MASK 0x0000FF00
    #define VBI1_INT_EN_SHIFT 8
#define  VHE_Y_CORING 0x5280
    #define Y_CB_CR_LOCKED_MASK 0x00000001
    #define Y_CB_CR_LOCKED_SHIFT 0
    #define VHE_Y_CORING_ENABLE_VBI_MASK 0x00000010
    #define VHE_Y_CORING_ENABLE_VBI_SHIFT 4
    #define VHE_Y_CORING_RANGE_MASK 0x00007F00
    #define VHE_Y_CORING_RANGE_SHIFT 8
    #define VHE_Y_CORING_VALUE_MASK 0x03FF0000
    #define VHE_Y_CORING_VALUE_SHIFT 16
#define  VNE0_BLK_C_MTN_THRESH 0x58B4
    #define VNE0_BLK_C_MTN_THRESH_CB_THRESH_MASK 0x00003FFF
    #define VNE0_BLK_C_MTN_THRESH_CB_THRESH_SHIFT 0
    #define VNE0_BLK_C_MTN_THRESH_CR_THRESH_MASK 0x3FFF0000
    #define VNE0_BLK_C_MTN_THRESH_CR_THRESH_SHIFT 16
#define  VNE0_BLK_Y_MTN_THRESH 0x58B0
    #define VNE0_BLK_Y_MTN_THRESH_Y_THRESH_MASK 0x00003FFF
    #define VNE0_BLK_Y_MTN_THRESH_Y_THRESH_SHIFT 0
#define  VNE0_BUF 0x584C
    #define VNE0_BUF_SRC_SIZE_MASK 0x0000FFFF
    #define VNE0_BUF_SRC_SIZE_SHIFT 0
    #define VNE0_BUF_DST_SIZE_MASK 0xFFFF0000
    #define VNE0_BUF_DST_SIZE_SHIFT 16
#define  VNE0_BUF_PITCH 0x5848
    #define VNE0_BUF_PITCH_SRC_PITCH_MASK 0x00003FE0
    #define VNE0_BUF_PITCH_SRC_PITCH_SHIFT 5
    #define VNE0_BUF_PITCH_DST_PITCH_MASK 0x3FE00000
    #define VNE0_BUF_PITCH_DST_PITCH_SHIFT 21
#define  VNE0_BUF_SIZE 0x5844
    #define VNE0_BUF_SIZE_WIDTH_MASK 0x000007FE
    #define VNE0_BUF_SIZE_WIDTH_SHIFT 1
    #define VNE0_BUF_SIZE_HEIGHT_MASK 0x07FE0000
    #define VNE0_BUF_SIZE_HEIGHT_SHIFT 17
#define  VNE0_CB_COMB_ADR 0x5878
    #define VNE0_CB_COMB_ADR_BASE_MASK 0x7FFFFFC0
    #define VNE0_CB_COMB_ADR_BASE_SHIFT 6
#define  VNE0_CB_CUR_ADR 0x5854
    #define VNE0_CB_CUR_ADR_BASE_MASK 0x7FFFFFC0
    #define VNE0_CB_CUR_ADR_BASE_SHIFT 6
#define  VNE0_CB_DST_ADR 0x5860
    #define VNE0_CB_DST_ADR_BASE_MASK 0x7FFFFFC0
    #define VNE0_CB_DST_ADR_BASE_SHIFT 6
#define  VNE0_CB_MTNFLAG_ADR 0x586C
    #define VNE0_CB_MTNFLAG_ADR_BASE_MASK 0x7FFFFFC0
    #define VNE0_CB_MTNFLAG_ADR_BASE_SHIFT 6
#define  VNE0_COMB_COEF 0x58D8
    #define VNE0_COMB_COEF_INDEX0_MASK 0x00000003
    #define VNE0_COMB_COEF_INDEX0_SHIFT 0
    #define VNE0_COMB_COEF_INDEX1_MASK 0x00000030
    #define VNE0_COMB_COEF_INDEX1_SHIFT 4
    #define VNE0_COMB_COEF_INDEX2_MASK 0x00000300
    #define VNE0_COMB_COEF_INDEX2_SHIFT 8
    #define VNE0_COMB_COEF_CFLAG_THRESH_MASK 0x000F0000
    #define VNE0_COMB_COEF_CFLAG_THRESH_SHIFT 16
#define  VNE0_COMB_FLAG 0x58D4
    #define VNE0_COMB_FLAG_Y_THRESH_MASK 0x00003FFF
    #define VNE0_COMB_FLAG_Y_THRESH_SHIFT 0
    #define VNE0_COMB_FLAG_C_THRESH_MASK 0x3FFF0000
    #define VNE0_COMB_FLAG_C_THRESH_SHIFT 16
#define  VNE0_CR_COMB_ADR 0x587C
    #define VNE0_CR_COMB_ADR_BASE_MASK 0x7FFFFFC0
    #define VNE0_CR_COMB_ADR_BASE_SHIFT 6
#define  VNE0_CR_CUR_ADR 0x5858
    #define VNE0_CR_CUR_ADR_BASE_MASK 0x7FFFFFC0
    #define VNE0_CR_CUR_ADR_BASE_SHIFT 6
#define  VNE0_CR_DST_ADR 0x5864
    #define VNE0_CR_DST_ADR_BASE_MASK 0x7FFFFFC0
    #define VNE0_CR_DST_ADR_BASE_SHIFT 6
#define  VNE0_CR_MTNFLAG_ADR 0x5870
    #define VNE0_CR_MTNFLAG_ADR_BASE_MASK 0x7FFFFFC0
    #define VNE0_CR_MTNFLAG_ADR_BASE_SHIFT 6
#define  VNE0_CTRL 0x5840
    #define VNE0_CTRL_CUR_8_BIT_MASK 0x00000001
    #define VNE0_CTRL_CUR_8_BIT_SHIFT 0
    #define VNE0_CTRL_DST_8_BIT_MASK 0x00000002
    #define VNE0_CTRL_DST_8_BIT_SHIFT 1
    #define VNE0_CTRL_FLD_FORMAT_MASK 0x00000004
    #define VNE0_CTRL_FLD_FORMAT_SHIFT 2
    #define VNE0_CTRL_Y_ONLY_MASK 0x00000010
    #define VNE0_CTRL_Y_ONLY_SHIFT 4
    #define VNE0_CTRL_COMB_DIS_MASK 0x00000020
    #define VNE0_CTRL_COMB_DIS_SHIFT 5
    #define VNE0_CTRL_SF_DIS_MASK 0x00000040
    #define VNE0_CTRL_SF_DIS_SHIFT 6
    #define VNE0_CTRL_TF_DIS_MASK 0x00000080
    #define VNE0_CTRL_TF_DIS_SHIFT 7
    #define VNE0_CTRL_8_TO_10_MASK 0x00000300
    #define VNE0_CTRL_8_TO_10_SHIFT 8
    #define VNE0_CTRL_10_TO_8_MASK 0x00000400
    #define VNE0_CTRL_10_TO_8_SHIFT 10
    #define VNE0_CTRL_FILT_DIS_MASK 0x00000800
    #define VNE0_CTRL_FILT_DIS_SHIFT 11
    #define VNE0_CTRL_ALPHA_EN_MASK 0x00001000
    #define VNE0_CTRL_ALPHA_EN_SHIFT 12
    #define VNE0_CTRL_COMB_Y_DIS_MASK 0x00002000
    #define VNE0_CTRL_COMB_Y_DIS_SHIFT 13
    #define VNE0_CTRL_COMB_C_DIS_MASK 0x00004000
    #define VNE0_CTRL_COMB_C_DIS_SHIFT 14
    #define VNE0_CTRL_BLOCKAGE_MASK 0x00010000
    #define VNE0_CTRL_BLOCKAGE_SHIFT 16
    #define VNE0_CTRL_OUTPUT_DIS_MASK 0x00020000
    #define VNE0_CTRL_OUTPUT_DIS_SHIFT 17
    #define VNE0_CTRL_MF_PITCH_MASK 0x03F00000
    #define VNE0_CTRL_MF_PITCH_SHIFT 20
#define  VNE0_ED_C_THRESH 0x58CC
    #define VNE0_ED_C_THRESH_CB_THRESH_MASK 0x00003FFF
    #define VNE0_ED_C_THRESH_CB_THRESH_SHIFT 0
    #define VNE0_ED_C_THRESH_CR_THRESH_MASK 0x3FFF0000
    #define VNE0_ED_C_THRESH_CR_THRESH_SHIFT 16
#define  VNE0_ED_Y_THRESH 0x58C8
    #define VNE0_ED_Y_THRESH_Y_THRESH_MASK 0x00003FFF
    #define VNE0_ED_Y_THRESH_Y_THRESH_SHIFT 0
#define  VNE0_IIRCOEF_0_7 0x5890
    #define VNE0_IIRCOEF_0_7_INDEX_0_MASK 0x0000000F
    #define VNE0_IIRCOEF_0_7_INDEX_0_SHIFT 0
    #define VNE0_IIRCOEF_0_7_INDEX_1_MASK 0x000000F0
    #define VNE0_IIRCOEF_0_7_INDEX_1_SHIFT 4
    #define VNE0_IIRCOEF_0_7_INDEX_2_MASK 0x00000F00
    #define VNE0_IIRCOEF_0_7_INDEX_2_SHIFT 8
    #define VNE0_IIRCOEF_0_7_INDEX_3_MASK 0x0000F000
    #define VNE0_IIRCOEF_0_7_INDEX_3_SHIFT 12
    #define VNE0_IIRCOEF_0_7_INDEX_4_MASK 0x000F0000
    #define VNE0_IIRCOEF_0_7_INDEX_4_SHIFT 16
    #define VNE0_IIRCOEF_0_7_INDEX_5_MASK 0x00F00000
    #define VNE0_IIRCOEF_0_7_INDEX_5_SHIFT 20
    #define VNE0_IIRCOEF_0_7_INDEX_6_MASK 0x0F000000
    #define VNE0_IIRCOEF_0_7_INDEX_6_SHIFT 24
    #define VNE0_IIRCOEF_0_7_INDEX_7_MASK 0xF0000000
    #define VNE0_IIRCOEF_0_7_INDEX_7_SHIFT 28
#define  VNE0_IIRCOEF_8_16 0x5894
    #define VNE0_IIRCOEF_8_16_INDEX_8_MASK 0x0000000F
    #define VNE0_IIRCOEF_8_16_INDEX_8_SHIFT 0
    #define VNE0_IIRCOEF_8_16_INDEX_9_MASK 0x000000F0
    #define VNE0_IIRCOEF_8_16_INDEX_9_SHIFT 4
    #define VNE0_IIRCOEF_8_16_INDEX_10_MASK 0x00000F00
    #define VNE0_IIRCOEF_8_16_INDEX_10_SHIFT 8
    #define VNE0_IIRCOEF_8_16_INDEX_11_MASK 0x0000F000
    #define VNE0_IIRCOEF_8_16_INDEX_11_SHIFT 12
    #define VNE0_IIRCOEF_8_16_INDEX_12_MASK 0x000F0000
    #define VNE0_IIRCOEF_8_16_INDEX_12_SHIFT 16
    #define VNE0_IIRCOEF_8_16_INDEX_13_MASK 0x00F00000
    #define VNE0_IIRCOEF_8_16_INDEX_13_SHIFT 20
    #define VNE0_IIRCOEF_8_16_INDEX_14_MASK 0x0F000000
    #define VNE0_IIRCOEF_8_16_INDEX_14_SHIFT 24
    #define VNE0_IIRCOEF_8_16_INDEX_15_MASK 0xF0000000
    #define VNE0_IIRCOEF_8_16_INDEX_15_SHIFT 28
#define  VNE0_MD_C_THRESH 0x58C4
    #define VNE0_MD_C_THRESH_CB_THRESH_MASK 0x00003FFF
    #define VNE0_MD_C_THRESH_CB_THRESH_SHIFT 0
    #define VNE0_MD_C_THRESH_CR_THRESH_MASK 0x3FFF0000
    #define VNE0_MD_C_THRESH_CR_THRESH_SHIFT 16
#define  VNE0_MD_Y_THRESH 0x58C0
    #define VNE0_MD_Y_THRESH_Y_THRESH_MASK 0x00003FFF
    #define VNE0_MD_Y_THRESH_Y_THRESH_SHIFT 0
#define  VNE0_NE_CTRL 0x589C
    #define VNE0_NE_CTRL_BLK_HEIGHT_MASK 0x0000000F
    #define VNE0_NE_CTRL_BLK_HEIGHT_SHIFT 0
#define  VNE0_NE_C_BLK 0x58BC
    #define VNE0_NE_C_BLK_CB_BLK_MASK 0x00007FFF
    #define VNE0_NE_C_BLK_CB_BLK_SHIFT 0
    #define VNE0_NE_C_BLK_CR_BLK_MASK 0x7FFF0000
    #define VNE0_NE_C_BLK_CR_BLK_SHIFT 16
#define  VNE0_NE_ENRGY_C_HI 0x58AC
    #define VNE0_NE_ENRGY_C_HI_CB_ENRGY_MASK 0x0000FFFF
    #define VNE0_NE_ENRGY_C_HI_CB_ENRGY_SHIFT 0
    #define VNE0_NE_ENRGY_C_HI_CR_ENRGY_MASK 0xFFFF0000
    #define VNE0_NE_ENRGY_C_HI_CR_ENRGY_SHIFT 16
#define  VNE0_NE_ENRGY_C_LO 0x58A4
    #define VNE0_NE_ENRGY_C_LO_CB_ENRGY_MASK 0x0000FFFF
    #define VNE0_NE_ENRGY_C_LO_CB_ENRGY_SHIFT 0
    #define VNE0_NE_ENRGY_C_LO_CR_ENRGY_MASK 0xFFFF0000
    #define VNE0_NE_ENRGY_C_LO_CR_ENRGY_SHIFT 16
#define  VNE0_NE_ENRGY_Y_HI 0x58A8
    #define VNE0_NE_ENRGY_Y_HI_Y_ENRGY_MASK 0x0000FFFF
    #define VNE0_NE_ENRGY_Y_HI_Y_ENRGY_SHIFT 0
#define  VNE0_NE_ENRGY_Y_LO 0x58A0
    #define VNE0_NE_ENRGY_Y_LO_Y_ENRGY_MASK 0x0000FFFF
    #define VNE0_NE_ENRGY_Y_LO_Y_ENRGY_SHIFT 0
#define  VNE0_NE_INFO_ADR 0x5880
    #define VNE0_NE_INFO_ADR_BASE_MASK 0x7FFFFFC0
    #define VNE0_NE_INFO_ADR_BASE_SHIFT 6
#define  VNE0_NE_Y_BLK 0x58B8
    #define VNE0_NE_Y_BLK_Y_BLK_MASK 0x00007FFF
    #define VNE0_NE_Y_BLK_Y_BLK_SHIFT 0
#define  VNE0_RD_INFO_ADR 0x5884
    #define VNE0_RD_INFO_ADR_BASE_MASK 0x7FFFFFC0
    #define VNE0_RD_INFO_ADR_BASE_SHIFT 6
#define  VNE0_SPATCOEF 0x5898
    #define VNE0_SPATCOEF_INDEX_0_MASK 0x0000003F
    #define VNE0_SPATCOEF_INDEX_0_SHIFT 0
    #define VNE0_SPATCOEF_INDEX_1_MASK 0x00003F00
    #define VNE0_SPATCOEF_INDEX_1_SHIFT 8
    #define VNE0_SPATCOEF_INDEX_2_MASK 0x003F0000
    #define VNE0_SPATCOEF_INDEX_2_SHIFT 16
    #define VNE0_SPATCOEF_INDEX_MAX_MASK 0xF0000000
    #define VNE0_SPATCOEF_INDEX_MAX_SHIFT 28
#define  VNE0_SPTL_MTN 0x58D0
    #define VNE0_SPTL_MTN_SAD_THRESH_MASK 0x00001FFF
    #define VNE0_SPTL_MTN_SAD_THRESH_SHIFT 0
    #define VNE0_SPTL_MTN_Y_RATIO0_MASK 0x00030000
    #define VNE0_SPTL_MTN_Y_RATIO0_SHIFT 16
    #define VNE0_SPTL_MTN_Y_RATIO1_MASK 0x000C0000
    #define VNE0_SPTL_MTN_Y_RATIO1_SHIFT 18
    #define VNE0_SPTL_MTN_Y_RATIO2_MASK 0x00300000
    #define VNE0_SPTL_MTN_Y_RATIO2_SHIFT 20
    #define VNE0_SPTL_MTN_C_RATIO0_MASK 0x03000000
    #define VNE0_SPTL_MTN_C_RATIO0_SHIFT 24
    #define VNE0_SPTL_MTN_C_RATIO1_MASK 0x0C000000
    #define VNE0_SPTL_MTN_C_RATIO1_SHIFT 26
    #define VNE0_SPTL_MTN_C_RATIO2_MASK 0x30000000
    #define VNE0_SPTL_MTN_C_RATIO2_SHIFT 28
#define  VNE0_TMP_ADR 0x588C
    #define VNE0_TMP_ADR_BASE_MASK 0x7FFFFFC0
    #define VNE0_TMP_ADR_BASE_SHIFT 6
#define  VNE0_WR_INFO_ADR 0x5888
    #define VNE0_WR_INFO_ADR_BASE_MASK 0x7FFFFFC0
    #define VNE0_WR_INFO_ADR_BASE_SHIFT 6
#define  VNE0_Y_COMB_ADR 0x5874
    #define VNE0_Y_COMB_ADR_BASE_MASK 0x7FFFFFC0
    #define VNE0_Y_COMB_ADR_BASE_SHIFT 6
#define  VNE0_Y_CUR_ADR 0x5850
    #define VNE0_Y_CUR_ADR_BASE_MASK 0x7FFFFFC0
    #define VNE0_Y_CUR_ADR_BASE_SHIFT 6
#define  VNE0_Y_DST_ADR 0x585C
    #define VNE0_Y_DST_ADR_BASE_MASK 0x7FFFFFC0
    #define VNE0_Y_DST_ADR_BASE_SHIFT 6
#define  VNE0_Y_MTNFLAG_ADR 0x5868
    #define VNE0_Y_MTNFLAG_ADR_BASE_MASK 0x7FFFFFC0
    #define VNE0_Y_MTNFLAG_ADR_BASE_SHIFT 6
#define  VNE1_BLK_C_MTN_THRESH 0x59B4
    #define VNE1_BLK_C_MTN_THRESH_CB_THRESH_MASK 0x00003FFF
    #define VNE1_BLK_C_MTN_THRESH_CB_THRESH_SHIFT 0
    #define VNE1_BLK_C_MTN_THRESH_CR_THRESH_MASK 0x3FFF0000
    #define VNE1_BLK_C_MTN_THRESH_CR_THRESH_SHIFT 16
#define  VNE1_BLK_Y_MTN_THRESH 0x59B0
    #define VNE1_BLK_Y_MTN_THRESH_Y_THRESH_MASK 0x00003FFF
    #define VNE1_BLK_Y_MTN_THRESH_Y_THRESH_SHIFT 0
#define  VNE1_BUF 0x594C
    #define VNE1_BUF_SRC_SIZE_MASK 0x0000FFFF
    #define VNE1_BUF_SRC_SIZE_SHIFT 0
    #define VNE1_BUF_DST_SIZE_MASK 0xFFFF0000
    #define VNE1_BUF_DST_SIZE_SHIFT 16
#define  VNE1_BUF_PITCH 0x5948
    #define VNE1_BUF_PITCH_SRC_PITCH_MASK 0x00003FE0
    #define VNE1_BUF_PITCH_SRC_PITCH_SHIFT 5
    #define VNE1_BUF_PITCH_DST_PITCH_MASK 0x3FE00000
    #define VNE1_BUF_PITCH_DST_PITCH_SHIFT 21
#define  VNE1_BUF_SIZE 0x5944
    #define VNE1_BUF_SIZE_WIDTH_MASK 0x000007FE
    #define VNE1_BUF_SIZE_WIDTH_SHIFT 1
    #define VNE1_BUF_SIZE_HEIGHT_MASK 0x07FE0000
    #define VNE1_BUF_SIZE_HEIGHT_SHIFT 17
#define  VNE1_CB_COMB_ADR 0x5978
    #define VNE1_CB_COMB_ADR_BASE_MASK 0x7FFFFFC0
    #define VNE1_CB_COMB_ADR_BASE_SHIFT 6
#define  VNE1_CB_CUR_ADR 0x5954
    #define VNE1_CB_CUR_ADR_BASE_MASK 0x7FFFFFC0
    #define VNE1_CB_CUR_ADR_BASE_SHIFT 6
#define  VNE1_CB_DST_ADR 0x5960
    #define VNE1_CB_DST_ADR_BASE_MASK 0x7FFFFFC0
    #define VNE1_CB_DST_ADR_BASE_SHIFT 6
#define  VNE1_CB_MTNFLAG_ADR 0x596C
    #define VNE1_CB_MTNFLAG_ADR_BASE_MASK 0x7FFFFFC0
    #define VNE1_CB_MTNFLAG_ADR_BASE_SHIFT 6
#define  VNE1_COMB_COEF 0x59D8
    #define VNE1_COMB_COEF_INDEX0_MASK 0x00000003
    #define VNE1_COMB_COEF_INDEX0_SHIFT 0
    #define VNE1_COMB_COEF_INDEX1_MASK 0x00000030
    #define VNE1_COMB_COEF_INDEX1_SHIFT 4
    #define VNE1_COMB_COEF_INDEX2_MASK 0x00000300
    #define VNE1_COMB_COEF_INDEX2_SHIFT 8
    #define VNE1_COMB_COEF_CFLAG_THRESH_MASK 0x000F0000
    #define VNE1_COMB_COEF_CFLAG_THRESH_SHIFT 16
#define  VNE1_COMB_FLAG 0x59D4
    #define VNE1_COMB_FLAG_Y_THRESH_MASK 0x00003FFF
    #define VNE1_COMB_FLAG_Y_THRESH_SHIFT 0
    #define VNE1_COMB_FLAG_C_THRESH_MASK 0x3FFF0000
    #define VNE1_COMB_FLAG_C_THRESH_SHIFT 16
#define  VNE1_CR_COMB_ADR 0x597C
    #define VNE1_CR_COMB_ADR_BASE_MASK 0x7FFFFFC0
    #define VNE1_CR_COMB_ADR_BASE_SHIFT 6
#define  VNE1_CR_CUR_ADR 0x5958
    #define VNE1_CR_CUR_ADR_BASE_MASK 0x7FFFFFC0
    #define VNE1_CR_CUR_ADR_BASE_SHIFT 6
#define  VNE1_CR_DST_ADR 0x5964
    #define VNE1_CR_DST_ADR_BASE_MASK 0x7FFFFFC0
    #define VNE1_CR_DST_ADR_BASE_SHIFT 6
#define  VNE1_CR_MTNFLAG_ADR 0x5970
    #define VNE1_CR_MTNFLAG_ADR_BASE_MASK 0x7FFFFFC0
    #define VNE1_CR_MTNFLAG_ADR_BASE_SHIFT 6
#define  VNE1_CTRL 0x5940
    #define VNE1_CTRL_CUR_8_BIT_MASK 0x00000001
    #define VNE1_CTRL_CUR_8_BIT_SHIFT 0
    #define VNE1_CTRL_DST_8_BIT_MASK 0x00000002
    #define VNE1_CTRL_DST_8_BIT_SHIFT 1
    #define VNE1_CTRL_FLD_FORMAT_MASK 0x00000004
    #define VNE1_CTRL_FLD_FORMAT_SHIFT 2
    #define VNE1_CTRL_Y_ONLY_MASK 0x00000010
    #define VNE1_CTRL_Y_ONLY_SHIFT 4
    #define VNE1_CTRL_COMB_DIS_MASK 0x00000020
    #define VNE1_CTRL_COMB_DIS_SHIFT 5
    #define VNE1_CTRL_SF_DIS_MASK 0x00000040
    #define VNE1_CTRL_SF_DIS_SHIFT 6
    #define VNE1_CTRL_TF_DIS_MASK 0x00000080
    #define VNE1_CTRL_TF_DIS_SHIFT 7
    #define VNE1_CTRL_8_TO_10_MASK 0x00000300
    #define VNE1_CTRL_8_TO_10_SHIFT 8
    #define VNE1_CTRL_10_TO_8_MASK 0x00000400
    #define VNE1_CTRL_10_TO_8_SHIFT 10
    #define VNE1_CTRL_FILT_DIS_MASK 0x00000800
    #define VNE1_CTRL_FILT_DIS_SHIFT 11
    #define VNE1_CTRL_ALPHA_EN_MASK 0x00001000
    #define VNE1_CTRL_ALPHA_EN_SHIFT 12
    #define VNE1_CTRL_COMB_Y_DIS_MASK 0x00002000
    #define VNE1_CTRL_COMB_Y_DIS_SHIFT 13
    #define VNE1_CTRL_COMB_C_DIS_MASK 0x00004000
    #define VNE1_CTRL_COMB_C_DIS_SHIFT 14
    #define VNE1_CTRL_BLOCKAGE_MASK 0x00010000
    #define VNE1_CTRL_BLOCKAGE_SHIFT 16
    #define VNE1_CTRL_OUTPUT_DIS_MASK 0x00020000
    #define VNE1_CTRL_OUTPUT_DIS_SHIFT 17
    #define VNE1_CTRL_MF_PITCH_MASK 0x03F00000
    #define VNE1_CTRL_MF_PITCH_SHIFT 20
#define  VNE1_ED_C_THRESH 0x59CC
    #define VNE1_ED_C_THRESH_CB_THRESH_MASK 0x00003FFF
    #define VNE1_ED_C_THRESH_CB_THRESH_SHIFT 0
    #define VNE1_ED_C_THRESH_CR_THRESH_MASK 0x3FFF0000
    #define VNE1_ED_C_THRESH_CR_THRESH_SHIFT 16
#define  VNE1_ED_Y_THRESH 0x59C8
    #define VNE1_ED_Y_THRESH_Y_THRESH_MASK 0x00003FFF
    #define VNE1_ED_Y_THRESH_Y_THRESH_SHIFT 0
#define  VNE1_IIRCOEF_0_7 0x5990
    #define VNE1_IIRCOEF_0_7_INDEX_0_MASK 0x0000000F
    #define VNE1_IIRCOEF_0_7_INDEX_0_SHIFT 0
    #define VNE1_IIRCOEF_0_7_INDEX_1_MASK 0x000000F0
    #define VNE1_IIRCOEF_0_7_INDEX_1_SHIFT 4
    #define VNE1_IIRCOEF_0_7_INDEX_2_MASK 0x00000F00
    #define VNE1_IIRCOEF_0_7_INDEX_2_SHIFT 8
    #define VNE1_IIRCOEF_0_7_INDEX_3_MASK 0x0000F000
    #define VNE1_IIRCOEF_0_7_INDEX_3_SHIFT 12
    #define VNE1_IIRCOEF_0_7_INDEX_4_MASK 0x000F0000
    #define VNE1_IIRCOEF_0_7_INDEX_4_SHIFT 16
    #define VNE1_IIRCOEF_0_7_INDEX_5_MASK 0x00F00000
    #define VNE1_IIRCOEF_0_7_INDEX_5_SHIFT 20
    #define VNE1_IIRCOEF_0_7_INDEX_6_MASK 0x0F000000
    #define VNE1_IIRCOEF_0_7_INDEX_6_SHIFT 24
    #define VNE1_IIRCOEF_0_7_INDEX_7_MASK 0xF0000000
    #define VNE1_IIRCOEF_0_7_INDEX_7_SHIFT 28
#define  VNE1_IIRCOEF_8_16 0x5994
    #define VNE1_IIRCOEF_8_16_INDEX_8_MASK 0x0000000F
    #define VNE1_IIRCOEF_8_16_INDEX_8_SHIFT 0
    #define VNE1_IIRCOEF_8_16_INDEX_9_MASK 0x000000F0
    #define VNE1_IIRCOEF_8_16_INDEX_9_SHIFT 4
    #define VNE1_IIRCOEF_8_16_INDEX_10_MASK 0x00000F00
    #define VNE1_IIRCOEF_8_16_INDEX_10_SHIFT 8
    #define VNE1_IIRCOEF_8_16_INDEX_11_MASK 0x0000F000
    #define VNE1_IIRCOEF_8_16_INDEX_11_SHIFT 12
    #define VNE1_IIRCOEF_8_16_INDEX_12_MASK 0x000F0000
    #define VNE1_IIRCOEF_8_16_INDEX_12_SHIFT 16
    #define VNE1_IIRCOEF_8_16_INDEX_13_MASK 0x00F00000
    #define VNE1_IIRCOEF_8_16_INDEX_13_SHIFT 20
    #define VNE1_IIRCOEF_8_16_INDEX_14_MASK 0x0F000000
    #define VNE1_IIRCOEF_8_16_INDEX_14_SHIFT 24
    #define VNE1_IIRCOEF_8_16_INDEX_15_MASK 0xF0000000
    #define VNE1_IIRCOEF_8_16_INDEX_15_SHIFT 28
#define  VNE1_MD_C_THRESH 0x59C4
    #define VNE1_MD_C_THRESH_CB_THRESH_MASK 0x00003FFF
    #define VNE1_MD_C_THRESH_CB_THRESH_SHIFT 0
    #define VNE1_MD_C_THRESH_CR_THRESH_MASK 0x3FFF0000
    #define VNE1_MD_C_THRESH_CR_THRESH_SHIFT 16
#define  VNE1_MD_Y_THRESH 0x59C0
    #define VNE1_MD_Y_THRESH_Y_THRESH_MASK 0x00003FFF
    #define VNE1_MD_Y_THRESH_Y_THRESH_SHIFT 0
#define  VNE1_NE_CTRL 0x599C
    #define VNE1_NE_CTRL_BLK_HEIGHT_MASK 0x0000000F
    #define VNE1_NE_CTRL_BLK_HEIGHT_SHIFT 0
#define  VNE1_NE_C_BLK 0x59BC
    #define VNE1_NE_C_BLK_CB_BLK_MASK 0x00007FFF
    #define VNE1_NE_C_BLK_CB_BLK_SHIFT 0
    #define VNE1_NE_C_BLK_CR_BLK_MASK 0x7FFF0000
    #define VNE1_NE_C_BLK_CR_BLK_SHIFT 16
#define  VNE1_NE_ENRGY_C_HI 0x59AC
    #define VNE1_NE_ENRGY_C_HI_CB_ENRGY_MASK 0x0000FFFF
    #define VNE1_NE_ENRGY_C_HI_CB_ENRGY_SHIFT 0
    #define VNE1_NE_ENRGY_C_HI_CR_ENRGY_MASK 0xFFFF0000
    #define VNE1_NE_ENRGY_C_HI_CR_ENRGY_SHIFT 16
#define  VNE1_NE_ENRGY_C_LO 0x59A4
    #define VNE1_NE_ENRGY_C_LO_CB_ENRGY_MASK 0x0000FFFF
    #define VNE1_NE_ENRGY_C_LO_CB_ENRGY_SHIFT 0
    #define VNE1_NE_ENRGY_C_LO_CR_ENRGY_MASK 0xFFFF0000
    #define VNE1_NE_ENRGY_C_LO_CR_ENRGY_SHIFT 16
#define  VNE1_NE_ENRGY_Y_HI 0x59A8
    #define VNE1_NE_ENRGY_Y_HI_Y_ENRGY_MASK 0x0000FFFF
    #define VNE1_NE_ENRGY_Y_HI_Y_ENRGY_SHIFT 0
#define  VNE1_NE_ENRGY_Y_LO 0x59A0
    #define VNE1_NE_ENRGY_Y_LO_Y_ENRGY_MASK 0x0000FFFF
    #define VNE1_NE_ENRGY_Y_LO_Y_ENRGY_SHIFT 0
#define  VNE1_NE_INFO_ADR 0x5980
    #define VNE1_NE_INFO_ADR_BASE_MASK 0x7FFFFFC0
    #define VNE1_NE_INFO_ADR_BASE_SHIFT 6
#define  VNE1_NE_Y_BLK 0x59B8
    #define VNE1_NE_Y_BLK_Y_BLK_MASK 0x00007FFF
    #define VNE1_NE_Y_BLK_Y_BLK_SHIFT 0
#define  VNE1_RD_INFO_ADR 0x5984
    #define VNE1_RD_INFO_ADR_BASE_MASK 0x7FFFFFC0
    #define VNE1_RD_INFO_ADR_BASE_SHIFT 6
#define  VNE1_SPATCOEF 0x5998
    #define VNE1_SPATCOEF_INDEX_0_MASK 0x0000003F
    #define VNE1_SPATCOEF_INDEX_0_SHIFT 0
    #define VNE1_SPATCOEF_INDEX_1_MASK 0x00003F00
    #define VNE1_SPATCOEF_INDEX_1_SHIFT 8
    #define VNE1_SPATCOEF_INDEX_2_MASK 0x003F0000
    #define VNE1_SPATCOEF_INDEX_2_SHIFT 16
    #define VNE1_SPATCOEF_INDEX_MAX_MASK 0xF0000000
    #define VNE1_SPATCOEF_INDEX_MAX_SHIFT 28
#define  VNE1_SPTL_MTN 0x59D0
    #define VNE1_SPTL_MTN_SAD_THRESH_MASK 0x00001FFF
    #define VNE1_SPTL_MTN_SAD_THRESH_SHIFT 0
    #define VNE1_SPTL_MTN_Y_RATIO0_MASK 0x00030000
    #define VNE1_SPTL_MTN_Y_RATIO0_SHIFT 16
    #define VNE1_SPTL_MTN_Y_RATIO1_MASK 0x000C0000
    #define VNE1_SPTL_MTN_Y_RATIO1_SHIFT 18
    #define VNE1_SPTL_MTN_Y_RATIO2_MASK 0x00300000
    #define VNE1_SPTL_MTN_Y_RATIO2_SHIFT 20
    #define VNE1_SPTL_MTN_C_RATIO0_MASK 0x03000000
    #define VNE1_SPTL_MTN_C_RATIO0_SHIFT 24
    #define VNE1_SPTL_MTN_C_RATIO1_MASK 0x0C000000
    #define VNE1_SPTL_MTN_C_RATIO1_SHIFT 26
    #define VNE1_SPTL_MTN_C_RATIO2_MASK 0x30000000
    #define VNE1_SPTL_MTN_C_RATIO2_SHIFT 28
#define  VNE1_TMP_ADR 0x598C
    #define VNE1_TMP_ADR_BASE_MASK 0x7FFFFFC0
    #define VNE1_TMP_ADR_BASE_SHIFT 6
#define  VNE1_WR_INFO_ADR 0x5988
    #define VNE1_WR_INFO_ADR_BASE_MASK 0x7FFFFFC0
    #define VNE1_WR_INFO_ADR_BASE_SHIFT 6
#define  VNE1_Y_COMB_ADR 0x5974
    #define VNE1_Y_COMB_ADR_BASE_MASK 0x7FFFFFC0
    #define VNE1_Y_COMB_ADR_BASE_SHIFT 6
#define  VNE1_Y_CUR_ADR 0x5950
    #define VNE1_Y_CUR_ADR_BASE_MASK 0x7FFFFFC0
    #define VNE1_Y_CUR_ADR_BASE_SHIFT 6
#define  VNE1_Y_DST_ADR 0x595C
    #define VNE1_Y_DST_ADR_BASE_MASK 0x7FFFFFC0
    #define VNE1_Y_DST_ADR_BASE_SHIFT 6
#define  VNE1_Y_MTNFLAG_ADR 0x5968
    #define VNE1_Y_MTNFLAG_ADR_BASE_MASK 0x7FFFFFC0
    #define VNE1_Y_MTNFLAG_ADR_BASE_SHIFT 6
#define  VNE_DEBUG_STAT 0x5820
    #define VNE_DEBUG_STAT_DEBUG_BUS_MASK 0x000FFFFF
    #define VNE_DEBUG_STAT_DEBUG_BUS_SHIFT 0
#define  VNE_DUMMY_REG 0x5830
    #define VNE_DUMMY_REG_DUMMY_BITS_MASK 0xFFFFFFFF
    #define VNE_DUMMY_REG_DUMMY_BITS_SHIFT 0
#define  VNE_FIFO_CMD 0x5810
    #define VNE_FIFO_CMD_FLD_CUR_IDX_MASK 0x0000000F
    #define VNE_FIFO_CMD_FLD_CUR_IDX_SHIFT 0
    #define VNE_FIFO_CMD_FLD_FWD_IDX_MASK 0x000000F0
    #define VNE_FIFO_CMD_FLD_FWD_IDX_SHIFT 4
    #define VNE_FIFO_CMD_FLD_FFD_IDX_MASK 0x00000F00
    #define VNE_FIFO_CMD_FLD_FFD_IDX_SHIFT 8
    #define VNE_FIFO_CMD_FLD_PRV_IDX_MASK 0x0000F000
    #define VNE_FIFO_CMD_FLD_PRV_IDX_SHIFT 12
    #define VNE_FIFO_CMD_FLD_DST_IDX_MASK 0x000F0000
    #define VNE_FIFO_CMD_FLD_DST_IDX_SHIFT 16
    #define VNE_FIFO_CMD_MF_SRC_IDX_MASK 0x00700000
    #define VNE_FIFO_CMD_MF_SRC_IDX_SHIFT 20
    #define VNE_FIFO_CMD_MF_DST_IDX_MASK 0x03800000
    #define VNE_FIFO_CMD_MF_DST_IDX_SHIFT 23
    #define VNE_FIFO_CMD_COMB_IDX_MASK 0x0C000000
    #define VNE_FIFO_CMD_COMB_IDX_SHIFT 26
    #define VNE_FIFO_CMD_MFLAG_INIT_MASK 0x10000000
    #define VNE_FIFO_CMD_MFLAG_INIT_SHIFT 28
    #define VNE_FIFO_CMD_UPDATE_MASK 0x20000000
    #define VNE_FIFO_CMD_UPDATE_SHIFT 29
    #define VNE_FIFO_CMD_STREAM_MASK 0xC0000000
    #define VNE_FIFO_CMD_STREAM_SHIFT 30
#define  VNE_HOST_INT_MASK 0x5808
    #define VNE0_HOST_INT_MASK_MASK 0x00000001
    #define VNE0_HOST_INT_MASK_SHIFT 0
    #define VNE1_HOST_INT_MASK_MASK 0x00000002
    #define VNE1_HOST_INT_MASK_SHIFT 1
#define  VNE_INT_CTRL 0x5800
    #define VNE0_INT_EN_MASK 0x000000FF
    #define VNE0_INT_EN_SHIFT 0
    #define VNE1_INT_EN_MASK 0x0000FF00
    #define VNE1_INT_EN_SHIFT 8
#define  VNE_INT_STATUS 0x5804
    #define VNE0_INT_MASK 0x00000001
    #define VNE0_INT_SHIFT 0
    #define VNE1_INT_MASK 0x00000002
    #define VNE1_INT_SHIFT 1
#define  VNE_MIPS_INT_MASK 0x580C
    #define VNE0_MIPS_INT_MASK_MASK 0x00000001
    #define VNE0_MIPS_INT_MASK_SHIFT 0
    #define VNE1_MIPS_INT_MASK_MASK 0x00000002
    #define VNE1_MIPS_INT_MASK_SHIFT 1
#define  VNE_PWR_CTRL 0x5818
    #define VNE_RST_SOFT_MASK 0x00000001
    #define VNE_RST_SOFT_SHIFT 0
    #define VNE_PWR_CTRL_CF_FLUSH_MASK 0x00000100
    #define VNE_PWR_CTRL_CF_FLUSH_SHIFT 8
    #define VNE_PWR_CTRL_READ_ACCEL_MASK 0x00010000
    #define VNE_PWR_CTRL_READ_ACCEL_SHIFT 16
#define  VNE_STATUS 0x5814
    #define VNE_STATUS_FIFO_FREE_MASK 0x0000001F
    #define VNE_STATUS_FIFO_FREE_SHIFT 0
    #define VNE_STATUS_STRM0_BUSY_MASK 0x00000100
    #define VNE_STATUS_STRM0_BUSY_SHIFT 8
    #define STRM1_BUSY_MASK 0x00000200
    #define STRM1_BUSY_SHIFT 9
    #define VNE_STATUS_STRM0_IDX_MASK 0x000F0000
    #define VNE_STATUS_STRM0_IDX_SHIFT 16
    #define STRM1_IDX_MASK 0x00F00000
    #define STRM1_IDX_SHIFT 20
    #define VNE_BUSY_MASK 0x80000000
    #define VNE_BUSY_SHIFT 31
#define  VNH0_BLK_C_MTN_THRESH 0x9CB4
    #define VNH0_BLK_C_MTN_THRESH_CB_THRESH_MASK 0x00003FFF
    #define VNH0_BLK_C_MTN_THRESH_CB_THRESH_SHIFT 0
    #define VNH0_BLK_C_MTN_THRESH_CR_THRESH_MASK 0x3FFF0000
    #define VNH0_BLK_C_MTN_THRESH_CR_THRESH_SHIFT 16
#define  VNH0_BLK_Y_MTN_THRESH 0x9CB0
    #define VNH0_BLK_Y_MTN_THRESH_Y_THRESH_MASK 0x00003FFF
    #define VNH0_BLK_Y_MTN_THRESH_Y_THRESH_SHIFT 0
#define  VNH0_BUF 0x9C4C
    #define VNH0_BUF_SRC_SIZE_MASK 0x00007FFF
    #define VNH0_BUF_SRC_SIZE_SHIFT 0
    #define VNH0_BUF_DST_SIZE_MASK 0x7FFF0000
    #define VNH0_BUF_DST_SIZE_SHIFT 16
#define  VNH0_BUF_PITCH 0x9C48
    #define VNH0_BUF_PITCH_SRC_PITCH_MASK 0x00003FE0
    #define VNH0_BUF_PITCH_SRC_PITCH_SHIFT 5
    #define VNH0_BUF_PITCH_DST_PITCH_MASK 0x3FE00000
    #define VNH0_BUF_PITCH_DST_PITCH_SHIFT 21
#define  VNH0_BUF_SIZE 0x9C44
    #define VNH0_BUF_SIZE_WIDTH_MASK 0x000007FE
    #define VNH0_BUF_SIZE_WIDTH_SHIFT 1
    #define VNH0_BUF_SIZE_HEIGHT_MASK 0x07FE0000
    #define VNH0_BUF_SIZE_HEIGHT_SHIFT 17
#define  VNH0_CB_8BIT_ADR 0x9CE4
    #define VNH0_CB_8BIT_ADR_BASE_MASK 0x7FFFFFC0
    #define VNH0_CB_8BIT_ADR_BASE_SHIFT 6
#define  VNH0_CB_COMB_ADR 0x9C78
    #define VNH0_CB_COMB_ADR_BASE_MASK 0x7FFFFFC0
    #define VNH0_CB_COMB_ADR_BASE_SHIFT 6
#define  VNH0_CB_CUR_ADR 0x9C54
    #define VNH0_CB_CUR_ADR_BASE_MASK 0x7FFFFFC0
    #define VNH0_CB_CUR_ADR_BASE_SHIFT 6
#define  VNH0_CB_DST_ADR 0x9C60
    #define VNH0_CB_DST_ADR_BASE_MASK 0x7FFFFFC0
    #define VNH0_CB_DST_ADR_BASE_SHIFT 6
#define  VNH0_CB_MTNFLAG_ADR 0x9C6C
    #define VNH0_CB_MTNFLAG_ADR_BASE_MASK 0x7FFFFFC0
    #define VNH0_CB_MTNFLAG_ADR_BASE_SHIFT 6
#define  VNH0_COMB_COEF 0x9CD8
    #define VNH0_COMB_COEF_INDEX0_MASK 0x00000003
    #define VNH0_COMB_COEF_INDEX0_SHIFT 0
    #define VNH0_COMB_COEF_INDEX1_MASK 0x00000030
    #define VNH0_COMB_COEF_INDEX1_SHIFT 4
    #define VNH0_COMB_COEF_INDEX2_MASK 0x00000300
    #define VNH0_COMB_COEF_INDEX2_SHIFT 8
    #define VNH0_COMB_COEF_CFLAG_THRESH_MASK 0x000F0000
    #define VNH0_COMB_COEF_CFLAG_THRESH_SHIFT 16
#define  VNH0_COMB_FLAG 0x9CD4
    #define VNH0_COMB_FLAG_Y_THRESH_MASK 0x00003FFF
    #define VNH0_COMB_FLAG_Y_THRESH_SHIFT 0
    #define VNH0_COMB_FLAG_C_THRESH_MASK 0x3FFF0000
    #define VNH0_COMB_FLAG_C_THRESH_SHIFT 16
#define  VNH0_CR_8BIT_ADR 0x9CE8
    #define VNH0_CR_8BIT_ADR_BASE_MASK 0x7FFFFFC0
    #define VNH0_CR_8BIT_ADR_BASE_SHIFT 6
#define  VNH0_CR_COMB_ADR 0x9C7C
    #define VNH0_CR_COMB_ADR_BASE_MASK 0x7FFFFFC0
    #define VNH0_CR_COMB_ADR_BASE_SHIFT 6
#define  VNH0_CR_CUR_ADR 0x9C58
    #define VNH0_CR_CUR_ADR_BASE_MASK 0x7FFFFFC0
    #define VNH0_CR_CUR_ADR_BASE_SHIFT 6
#define  VNH0_CR_DST_ADR 0x9C64
    #define VNH0_CR_DST_ADR_BASE_MASK 0x7FFFFFC0
    #define VNH0_CR_DST_ADR_BASE_SHIFT 6
#define  VNH0_CR_MTNFLAG_ADR 0x9C70
    #define VNH0_CR_MTNFLAG_ADR_BASE_MASK 0x7FFFFFC0
    #define VNH0_CR_MTNFLAG_ADR_BASE_SHIFT 6
#define  VNH0_CTRL 0x9C40
    #define VNH0_CTRL_CUR_8_BIT_MASK 0x00000001
    #define VNH0_CTRL_CUR_8_BIT_SHIFT 0
    #define VNH0_CTRL_DST_8_BIT_MASK 0x00000002
    #define VNH0_CTRL_DST_8_BIT_SHIFT 1
    #define VNH0_CTRL_FLD_FORMAT_MASK 0x00000004
    #define VNH0_CTRL_FLD_FORMAT_SHIFT 2
    #define VNH0_CTRL_Y_ONLY_MASK 0x00000010
    #define VNH0_CTRL_Y_ONLY_SHIFT 4
    #define VNH0_CTRL_COMB_DIS_MASK 0x00000020
    #define VNH0_CTRL_COMB_DIS_SHIFT 5
    #define VNH0_CTRL_SF_DIS_MASK 0x00000040
    #define VNH0_CTRL_SF_DIS_SHIFT 6
    #define VNH0_CTRL_TF_DIS_MASK 0x00000080
    #define VNH0_CTRL_TF_DIS_SHIFT 7
    #define V8_TO_10_MASK 0x00000300
    #define V8_TO_10_SHIFT 8
    #define V10_TO_8_MASK 0x00000400
    #define V10_TO_8_SHIFT 10
    #define VNH0_CTRL_FILT_DIS_MASK 0x00000800
    #define VNH0_CTRL_FILT_DIS_SHIFT 11
    #define VNH0_CTRL_ALPHA_EN_MASK 0x00001000
    #define VNH0_CTRL_ALPHA_EN_SHIFT 12
    #define VNH0_CTRL_COMB_Y_DIS_MASK 0x00002000
    #define VNH0_CTRL_COMB_Y_DIS_SHIFT 13
    #define VNH0_CTRL_COMB_C_DIS_MASK 0x00004000
    #define VNH0_CTRL_COMB_C_DIS_SHIFT 14
    #define SIMUL_8BIT_EN_MASK 0x00008000
    #define SIMUL_8BIT_EN_SHIFT 15
    #define VNH0_CTRL_BLOCKAGE_MASK 0x00010000
    #define VNH0_CTRL_BLOCKAGE_SHIFT 16
    #define VNH0_CTRL_MF_PITCH_MASK 0x03F00000
    #define VNH0_CTRL_MF_PITCH_SHIFT 20
#define  VNH0_ED_C_THRESH 0x9CCC
    #define VNH0_ED_C_THRESH_CB_THRESH_MASK 0x00003FFF
    #define VNH0_ED_C_THRESH_CB_THRESH_SHIFT 0
    #define VNH0_ED_C_THRESH_CR_THRESH_MASK 0x3FFF0000
    #define VNH0_ED_C_THRESH_CR_THRESH_SHIFT 16
#define  VNH0_ED_Y_THRESH 0x9CC8
    #define VNH0_ED_Y_THRESH_Y_THRESH_MASK 0x00003FFF
    #define VNH0_ED_Y_THRESH_Y_THRESH_SHIFT 0
#define  VNH0_IIRCOEF_0_7 0x9C90
    #define VNH0_IIRCOEF_0_7_INDEX_0_MASK 0x0000000F
    #define VNH0_IIRCOEF_0_7_INDEX_0_SHIFT 0
    #define VNH0_IIRCOEF_0_7_INDEX_1_MASK 0x000000F0
    #define VNH0_IIRCOEF_0_7_INDEX_1_SHIFT 4
    #define VNH0_IIRCOEF_0_7_INDEX_2_MASK 0x00000F00
    #define VNH0_IIRCOEF_0_7_INDEX_2_SHIFT 8
    #define VNH0_IIRCOEF_0_7_INDEX_3_MASK 0x0000F000
    #define VNH0_IIRCOEF_0_7_INDEX_3_SHIFT 12
    #define VNH0_IIRCOEF_0_7_INDEX_4_MASK 0x000F0000
    #define VNH0_IIRCOEF_0_7_INDEX_4_SHIFT 16
    #define VNH0_IIRCOEF_0_7_INDEX_5_MASK 0x00F00000
    #define VNH0_IIRCOEF_0_7_INDEX_5_SHIFT 20
    #define VNH0_IIRCOEF_0_7_INDEX_6_MASK 0x0F000000
    #define VNH0_IIRCOEF_0_7_INDEX_6_SHIFT 24
    #define VNH0_IIRCOEF_0_7_INDEX_7_MASK 0xF0000000
    #define VNH0_IIRCOEF_0_7_INDEX_7_SHIFT 28
#define  VNH0_IIRCOEF_8_16 0x9C94
    #define VNH0_IIRCOEF_8_16_INDEX_8_MASK 0x0000000F
    #define VNH0_IIRCOEF_8_16_INDEX_8_SHIFT 0
    #define VNH0_IIRCOEF_8_16_INDEX_9_MASK 0x000000F0
    #define VNH0_IIRCOEF_8_16_INDEX_9_SHIFT 4
    #define VNH0_IIRCOEF_8_16_INDEX_10_MASK 0x00000F00
    #define VNH0_IIRCOEF_8_16_INDEX_10_SHIFT 8
    #define VNH0_IIRCOEF_8_16_INDEX_11_MASK 0x0000F000
    #define VNH0_IIRCOEF_8_16_INDEX_11_SHIFT 12
    #define VNH0_IIRCOEF_8_16_INDEX_12_MASK 0x000F0000
    #define VNH0_IIRCOEF_8_16_INDEX_12_SHIFT 16
    #define VNH0_IIRCOEF_8_16_INDEX_13_MASK 0x00F00000
    #define VNH0_IIRCOEF_8_16_INDEX_13_SHIFT 20
    #define VNH0_IIRCOEF_8_16_INDEX_14_MASK 0x0F000000
    #define VNH0_IIRCOEF_8_16_INDEX_14_SHIFT 24
    #define VNH0_IIRCOEF_8_16_INDEX_15_MASK 0xF0000000
    #define VNH0_IIRCOEF_8_16_INDEX_15_SHIFT 28
#define  VNH0_MD_C_THRESH 0x9CC4
    #define VNH0_MD_C_THRESH_CB_THRESH_MASK 0x00003FFF
    #define VNH0_MD_C_THRESH_CB_THRESH_SHIFT 0
    #define VNH0_MD_C_THRESH_CR_THRESH_MASK 0x3FFF0000
    #define VNH0_MD_C_THRESH_CR_THRESH_SHIFT 16
#define  VNH0_MD_Y_THRESH 0x9CC0
    #define VNH0_MD_Y_THRESH_Y_THRESH_MASK 0x00003FFF
    #define VNH0_MD_Y_THRESH_Y_THRESH_SHIFT 0
#define  VNH0_NE_CTRL 0x9C9C
    #define VNH0_NE_CTRL_BLK_HEIGHT_MASK 0x0000000F
    #define VNH0_NE_CTRL_BLK_HEIGHT_SHIFT 0
#define  VNH0_NE_C_BLK 0x9CBC
    #define VNH0_NE_C_BLK_CB_BLK_MASK 0x00007FFF
    #define VNH0_NE_C_BLK_CB_BLK_SHIFT 0
    #define VNH0_NE_C_BLK_CR_BLK_MASK 0x7FFF0000
    #define VNH0_NE_C_BLK_CR_BLK_SHIFT 16
#define  VNH0_NE_ENRGY_C_HI 0x9CAC
    #define VNH0_NE_ENRGY_C_HI_CB_ENRGY_MASK 0x0000FFFF
    #define VNH0_NE_ENRGY_C_HI_CB_ENRGY_SHIFT 0
    #define VNH0_NE_ENRGY_C_HI_CR_ENRGY_MASK 0xFFFF0000
    #define VNH0_NE_ENRGY_C_HI_CR_ENRGY_SHIFT 16
#define  VNH0_NE_ENRGY_C_LO 0x9CA4
    #define VNH0_NE_ENRGY_C_LO_CB_ENRGY_MASK 0x0000FFFF
    #define VNH0_NE_ENRGY_C_LO_CB_ENRGY_SHIFT 0
    #define VNH0_NE_ENRGY_C_LO_CR_ENRGY_MASK 0xFFFF0000
    #define VNH0_NE_ENRGY_C_LO_CR_ENRGY_SHIFT 16
#define  VNH0_NE_ENRGY_Y_HI 0x9CA8
    #define VNH0_NE_ENRGY_Y_HI_Y_ENRGY_MASK 0x0000FFFF
    #define VNH0_NE_ENRGY_Y_HI_Y_ENRGY_SHIFT 0
#define  VNH0_NE_ENRGY_Y_LO 0x9CA0
    #define VNH0_NE_ENRGY_Y_LO_Y_ENRGY_MASK 0x0000FFFF
    #define VNH0_NE_ENRGY_Y_LO_Y_ENRGY_SHIFT 0
#define  VNH0_NE_INFO_ADR 0x9C80
    #define VNH0_NE_INFO_ADR_BASE_MASK 0x7FFFFFC0
    #define VNH0_NE_INFO_ADR_BASE_SHIFT 6
#define  VNH0_NE_Y_BLK 0x9CB8
    #define VNH0_NE_Y_BLK_Y_BLK_MASK 0x00007FFF
    #define VNH0_NE_Y_BLK_Y_BLK_SHIFT 0
#define  VNH0_RD_INFO_ADR 0x9C84
    #define VNH0_RD_INFO_ADR_BASE_MASK 0x7FFFFFC0
    #define VNH0_RD_INFO_ADR_BASE_SHIFT 6
#define  VNH0_S8B_BUF 0x9CF0
    #define S8B_SIZE_MASK 0x00007FFF
    #define S8B_SIZE_SHIFT 0
#define  VNH0_S8B_PITCH 0x9CEC
    #define S8B_PITCH_MASK 0x00000FE0
    #define S8B_PITCH_SHIFT 5
#define  VNH0_SPATCOEF 0x9C98
    #define VNH0_SPATCOEF_INDEX_0_MASK 0x0000003F
    #define VNH0_SPATCOEF_INDEX_0_SHIFT 0
    #define VNH0_SPATCOEF_INDEX_1_MASK 0x00003F00
    #define VNH0_SPATCOEF_INDEX_1_SHIFT 8
    #define VNH0_SPATCOEF_INDEX_2_MASK 0x003F0000
    #define VNH0_SPATCOEF_INDEX_2_SHIFT 16
    #define VNH0_SPATCOEF_INDEX_MAX_MASK 0xF0000000
    #define VNH0_SPATCOEF_INDEX_MAX_SHIFT 28
#define  VNH0_SPTL_MTN 0x9CD0
    #define VNH0_SPTL_MTN_SAD_THRESH_MASK 0x00001FFF
    #define VNH0_SPTL_MTN_SAD_THRESH_SHIFT 0
    #define VNH0_SPTL_MTN_Y_RATIO0_MASK 0x00030000
    #define VNH0_SPTL_MTN_Y_RATIO0_SHIFT 16
    #define VNH0_SPTL_MTN_Y_RATIO1_MASK 0x000C0000
    #define VNH0_SPTL_MTN_Y_RATIO1_SHIFT 18
    #define VNH0_SPTL_MTN_Y_RATIO2_MASK 0x00300000
    #define VNH0_SPTL_MTN_Y_RATIO2_SHIFT 20
    #define VNH0_SPTL_MTN_C_RATIO0_MASK 0x03000000
    #define VNH0_SPTL_MTN_C_RATIO0_SHIFT 24
    #define VNH0_SPTL_MTN_C_RATIO1_MASK 0x0C000000
    #define VNH0_SPTL_MTN_C_RATIO1_SHIFT 26
    #define VNH0_SPTL_MTN_C_RATIO2_MASK 0x30000000
    #define VNH0_SPTL_MTN_C_RATIO2_SHIFT 28
#define  VNH0_TMP_ADR 0x9C8C
    #define VNH0_TMP_ADR_BASE_MASK 0x7FFFFFC0
    #define VNH0_TMP_ADR_BASE_SHIFT 6
#define  VNH0_WR_INFO_ADR 0x9C88
    #define VNH0_WR_INFO_ADR_BASE_MASK 0x7FFFFFC0
    #define VNH0_WR_INFO_ADR_BASE_SHIFT 6
#define  VNH0_Y_8BIT_ADR 0x9CE0
    #define VNH0_Y_8BIT_ADR_BASE_MASK 0x7FFFFFC0
    #define VNH0_Y_8BIT_ADR_BASE_SHIFT 6
#define  VNH0_Y_COMB_ADR 0x9C74
    #define VNH0_Y_COMB_ADR_BASE_MASK 0x7FFFFFC0
    #define VNH0_Y_COMB_ADR_BASE_SHIFT 6
#define  VNH0_Y_CUR_ADR 0x9C50
    #define VNH0_Y_CUR_ADR_BASE_MASK 0x7FFFFFC0
    #define VNH0_Y_CUR_ADR_BASE_SHIFT 6
#define  VNH0_Y_DST_ADR 0x9C5C
    #define VNH0_Y_DST_ADR_BASE_MASK 0x7FFFFFC0
    #define VNH0_Y_DST_ADR_BASE_SHIFT 6
#define  VNH0_Y_MTNFLAG_ADR 0x9C68
    #define VNH0_Y_MTNFLAG_ADR_BASE_MASK 0x7FFFFFC0
    #define VNH0_Y_MTNFLAG_ADR_BASE_SHIFT 6
#define  VNH_DEBUG_STAT 0x9C20
    #define VNH_DEBUG_STAT_DEBUG_BUS_MASK 0x000FFFFF
    #define VNH_DEBUG_STAT_DEBUG_BUS_SHIFT 0
#define  VNH_DUMMY_REG 0x9C30
    #define VNH_DUMMY_REG_DUMMY_BITS_MASK 0xFFFFFFFF
    #define VNH_DUMMY_REG_DUMMY_BITS_SHIFT 0
#define  VNH_FIFO_CMD 0x9C10
    #define VNH_FIFO_CMD_FLD_CUR_IDX_MASK 0x0000000F
    #define VNH_FIFO_CMD_FLD_CUR_IDX_SHIFT 0
    #define VNH_FIFO_CMD_FLD_FWD_IDX_MASK 0x000000F0
    #define VNH_FIFO_CMD_FLD_FWD_IDX_SHIFT 4
    #define VNH_FIFO_CMD_FLD_FFD_IDX_MASK 0x00000F00
    #define VNH_FIFO_CMD_FLD_FFD_IDX_SHIFT 8
    #define VNH_FIFO_CMD_FLD_PRV_IDX_MASK 0x0000F000
    #define VNH_FIFO_CMD_FLD_PRV_IDX_SHIFT 12
    #define VNH_FIFO_CMD_FLD_DST_IDX_MASK 0x000F0000
    #define VNH_FIFO_CMD_FLD_DST_IDX_SHIFT 16
    #define VNH_FIFO_CMD_MF_SRC_IDX_MASK 0x00700000
    #define VNH_FIFO_CMD_MF_SRC_IDX_SHIFT 20
    #define VNH_FIFO_CMD_MF_DST_IDX_MASK 0x03800000
    #define VNH_FIFO_CMD_MF_DST_IDX_SHIFT 23
    #define VNH_FIFO_CMD_COMB_IDX_MASK 0x0C000000
    #define VNH_FIFO_CMD_COMB_IDX_SHIFT 26
    #define VNH_FIFO_CMD_MFLAG_INIT_MASK 0x10000000
    #define VNH_FIFO_CMD_MFLAG_INIT_SHIFT 28
    #define VNH_FIFO_CMD_UPDATE_MASK 0x20000000
    #define VNH_FIFO_CMD_UPDATE_SHIFT 29
#define  VNH_FIFO_CMD1 0x9CDC
    #define FLD_S8B_IDX_MASK 0x0000000F
    #define FLD_S8B_IDX_SHIFT 0
    #define VNH_FIFO_CMD1_TILE_MODE_MASK 0x00000030
    #define VNH_FIFO_CMD1_TILE_MODE_SHIFT 4
#define  VNH_INT_CTRL 0x9C00
    #define VNH0_INT_EN_MASK 0x000000FF
    #define VNH0_INT_EN_SHIFT 0
#define  VNH_INT_MASK 0x9C08
    #define VNH0_INT_MASK_MASK 0x00000001
    #define VNH0_INT_MASK_SHIFT 0
#define  VNH_INT_STATUS 0x9C04
    #define VNH0_INT_MASK 0x00000001
    #define VNH0_INT_SHIFT 0
#define  VNH_PWR_CTRL 0x9C18
    #define VNH_RST_SOFT_MASK 0x00000001
    #define VNH_RST_SOFT_SHIFT 0
    #define VNH_PWR_CTRL_CF_FLUSH_MASK 0x00000100
    #define VNH_PWR_CTRL_CF_FLUSH_SHIFT 8
    #define VNH_PWR_CTRL_READ_ACCEL_MASK 0x00010000
    #define VNH_PWR_CTRL_READ_ACCEL_SHIFT 16
#define  VNH_STATUS 0x9C14
    #define VNH_STATUS_FIFO_FREE_MASK 0x0000001F
    #define VNH_STATUS_FIFO_FREE_SHIFT 0
    #define VNH_STATUS_STRM0_BUSY_MASK 0x00000100
    #define VNH_STATUS_STRM0_BUSY_SHIFT 8
    #define VNH_STATUS_STRM0_IDX_MASK 0x000F0000
    #define VNH_STATUS_STRM0_IDX_SHIFT 16
    #define VNH_BUSY_MASK 0x80000000
    #define VNH_BUSY_SHIFT 31
#define  WDT_RESET 0x0598
    #define WDT_RESET_TIMEOUT_MASK 0xFFFFFFFF
    #define WDT_RESET_TIMEOUT_SHIFT 0
#define  WDT_TIMER0 0x0590
    #define WDT_TIMER0_TIMEOUT_MASK 0xFFFFFFFF
    #define WDT_TIMER0_TIMEOUT_SHIFT 0
#define  WDT_TIMER1 0x0594
    #define WDT_TIMER1_TIMEOUT_MASK 0xFFFFFFFF
    #define WDT_TIMER1_TIMEOUT_SHIFT 0
#endif
