#ifndef JAGUAR_H
#define JAGUAR_H

#define  AHB_REG_CTRL 0xD000
    #define SATA_REG_ADDR_MASK 0x00000FFF
    #define SATA_REG_ADDR_SHIFT 0
    #define SATA0_HSEL_MASK 0x00001000
    #define SATA0_HSEL_SHIFT 12
    #define SATA1_HSEL_MASK 0x00002000
    #define SATA1_HSEL_SHIFT 13
    #define DMA_HSEL_MASK 0x00004000
    #define DMA_HSEL_SHIFT 14
    #define AHB_REG_CTRL_WOP_MASK 0x80000000
    #define AHB_REG_CTRL_WOP_SHIFT 31
#define  AHB_REG_RDAT 0xD00C
    #define AHB_REG_RDAT_DATA_MASK 0xFFFFFFFF
    #define AHB_REG_RDAT_DATA_SHIFT 0
#define  AHB_REG_STATUS 0xD004
    #define SATA_CSR_BUSY_MASK 0x00000001
    #define SATA_CSR_BUSY_SHIFT 0
    #define SATA_CSR_ERR_MASK 0x00000002
    #define SATA_CSR_ERR_SHIFT 1
#define  AHB_REG_WDAT 0xD008
    #define AHB_REG_WDAT_DATA_MASK 0xFFFFFFFF
    #define AHB_REG_WDAT_DATA_SHIFT 0
#define  BKD0_STATUS 0xA140
    #define BKD0_STATUS_DONE_MASK 0x00000001
    #define BKD0_STATUS_DONE_SHIFT 0
    #define BKD0_STATUS_DIP_END_MASK 0x07FFFFFC
    #define BKD0_STATUS_DIP_END_SHIFT 2
    #define BKD0_STATUS_ERROR_MASK 0xF0000000
    #define BKD0_STATUS_ERROR_SHIFT 28
#define  BKD0_TRIG 0xA13C
    #define BKD0_TRIG_INTRA_MASK 0x00000001
    #define BKD0_TRIG_INTRA_SHIFT 0
    #define BKD0_TRIG_CBP_MASK 0xFC000000
    #define BKD0_TRIG_CBP_SHIFT 26
#define  BKD1_STATUS 0xA540
    #define BKD1_STATUS_DONE_MASK 0x00000001
    #define BKD1_STATUS_DONE_SHIFT 0
    #define BKD1_STATUS_DIP_END_MASK 0x07FFFFFC
    #define BKD1_STATUS_DIP_END_SHIFT 2
    #define BKD1_STATUS_ERROR_MASK 0xF0000000
    #define BKD1_STATUS_ERROR_SHIFT 28
#define  BKD1_TRIG 0xA53C
    #define BKD1_TRIG_INTRA_MASK 0x00000001
    #define BKD1_TRIG_INTRA_SHIFT 0
    #define BKD1_TRIG_CBP_MASK 0xFC000000
    #define BKD1_TRIG_CBP_SHIFT 26
#define  BOOT_CTRL_ADDR 0x10C0
    #define BOOT_ADDR_MASK 0x00FFFFFF
    #define BOOT_ADDR_SHIFT 0
    #define BOOT_OPCODE_MASK 0xFF000000
    #define BOOT_OPCODE_SHIFT 24
#define  BOOT_CTRL_CFG 0x10BC
    #define BOOT_REQ_MASK 0x00000001
    #define BOOT_REQ_SHIFT 0
    #define BOOT_IDLE_MASK 0x00000002
    #define BOOT_IDLE_SHIFT 1
    #define BOOT_ADDR_SIZE_MASK 0x0000000C
    #define BOOT_ADDR_SIZE_SHIFT 2
#define  CCSPI_HOST_READY_EN 0x10D8
    #define CCSPI_HOST_READY_EN_MASK 0x00000001
    #define CCSPI_HOST_READY_EN_SHIFT 0
#define  CCSPI_OPTIONS 0x10E4
    #define CCSPI_ALLOW_RX_PKT_WO_CR_MASK 0x00000001
    #define CCSPI_ALLOW_RX_PKT_WO_CR_SHIFT 0
    #define CCSPI_ALLOW_RX_PKT_WO_HR_MASK 0x00000002
    #define CCSPI_ALLOW_RX_PKT_WO_HR_SHIFT 1
#define  CCSPI_PORT_CTRL 0x10DC
    #define CCSPI_PORT_CTRL_MASK 0x00000001
    #define CCSPI_PORT_CTRL_SHIFT 0
#define  CCSPI_QB_TIMEOUT 0x10E0
    #define CCSPI_QB_TIMEOUT_LIMIT_MASK 0x0000FFFF
    #define CCSPI_QB_TIMEOUT_LIMIT_SHIFT 0
    #define CCSPI_QB_TIMEOUT_ENABLE_MASK 0x00010000
    #define CCSPI_QB_TIMEOUT_ENABLE_SHIFT 16
#define  CCSPI_RX_ADDR 0x10D4
    #define CCSPI_RX_PACKET_TOP_ADDR_MASK 0x00FFFFFF
    #define CCSPI_RX_PACKET_TOP_ADDR_SHIFT 0
#define  CCSPI_RX_STATUS 0x10D0
    #define CCSPI_RX_PACKET_SIZE_MASK 0x00001FFF
    #define CCSPI_RX_PACKET_SIZE_SHIFT 0
    #define CCSPI_RX_PACKET_FIRST_MASK 0x00002000
    #define CCSPI_RX_PACKET_FIRST_SHIFT 13
    #define CCSPI_RX_PACKET_LAST_MASK 0x00004000
    #define CCSPI_RX_PACKET_LAST_SHIFT 14
    #define CCSPI_RX_PACKET_CHANNEL_MASK 0x00008000
    #define CCSPI_RX_PACKET_CHANNEL_SHIFT 15
    #define CCSPI_MCARD_ERROR_MASK 0x00010000
    #define CCSPI_MCARD_ERROR_SHIFT 16
    #define CCSPI_MCARD_DATA_AVAILABLE_MASK 0x00020000
    #define CCSPI_MCARD_DATA_AVAILABLE_SHIFT 17
    #define CCSPI_MCARD_FIRST_PACKET_MASK 0x00040000
    #define CCSPI_MCARD_FIRST_PACKET_SHIFT 18
    #define CCSPI_MCARD_LAST_PACKET_MASK 0x00080000
    #define CCSPI_MCARD_LAST_PACKET_SHIFT 19
    #define CCSPI_MCARD_EXTENDED_CHANNEL_MASK 0x00100000
    #define CCSPI_MCARD_EXTENDED_CHANNEL_SHIFT 20
    #define CCSPI_MCARD_READY_MASK 0x00200000
    #define CCSPI_MCARD_READY_SHIFT 21
    #define CCSPI_HOST_ERROR_MASK 0x00400000
    #define CCSPI_HOST_ERROR_SHIFT 22
    #define CCSPI_HOST_DATA_AVAILABLE_MASK 0x00800000
    #define CCSPI_HOST_DATA_AVAILABLE_SHIFT 23
    #define CCSPI_HOST_FIRST_PACKET_MASK 0x01000000
    #define CCSPI_HOST_FIRST_PACKET_SHIFT 24
    #define CCSPI_HOST_LAST_PACKET_MASK 0x02000000
    #define CCSPI_HOST_LAST_PACKET_SHIFT 25
    #define CCSPI_HOST_EXTENDED_CHANNEL_MASK 0x04000000
    #define CCSPI_HOST_EXTENDED_CHANNEL_SHIFT 26
    #define CCSPI_HOST_READY_MASK 0x08000000
    #define CCSPI_HOST_READY_SHIFT 27
#define  CCSPI_TX_ADDR 0x10CC
    #define CCSPI_TX_PACKET_TOP_ADDR_MASK 0x00FFFFFF
    #define CCSPI_TX_PACKET_TOP_ADDR_SHIFT 0
#define  CCSPI_TX_CONTROL 0x10C8
    #define CCSPI_TX_PACKET_SIZE_MASK 0x00001FFF
    #define CCSPI_TX_PACKET_SIZE_SHIFT 0
    #define CCSPI_TX_PACKET_FIRST_MASK 0x00002000
    #define CCSPI_TX_PACKET_FIRST_SHIFT 13
    #define CCSPI_TX_PACKET_LAST_MASK 0x00004000
    #define CCSPI_TX_PACKET_LAST_SHIFT 14
    #define CCSPI_TX_PACKET_CHANNEL_MASK 0x00008000
    #define CCSPI_TX_PACKET_CHANNEL_SHIFT 15
#define  CG_BLK_CLK_STOP0 0x0130
    #define DMA_MCLK_STOP_MASK 0x00000001
    #define DMA_MCLK_STOP_SHIFT 0
    #define DMA_SCLK_STOP_MASK 0x00000002
    #define DMA_SCLK_STOP_SHIFT 1
    #define TSD_MCLK_STOP_MASK 0x00000004
    #define TSD_MCLK_STOP_SHIFT 2
    #define TSD_SCLK_STOP_MASK 0x00000008
    #define TSD_SCLK_STOP_SHIFT 3
    #define TSD_DCLK_STOP_MASK 0x00000010
    #define TSD_DCLK_STOP_SHIFT 4
    #define MPP_ENC_MCLK_STOP_MASK 0x00000020
    #define MPP_ENC_MCLK_STOP_SHIFT 5
    #define MPP_ENC_ECLK_STOP_MASK 0x00000040
    #define MPP_ENC_ECLK_STOP_SHIFT 6
    #define MPP_DEC_MCLK_STOP_MASK 0x00000080
    #define MPP_DEC_MCLK_STOP_SHIFT 7
    #define MPP_DEC_ECLK_STOP_MASK 0x00000100
    #define MPP_DEC_ECLK_STOP_SHIFT 8
    #define VHE_MCLK_STOP_MASK 0x00000200
    #define VHE_MCLK_STOP_SHIFT 9
    #define VHE_SCLK_STOP_MASK 0x00000400
    #define VHE_SCLK_STOP_SHIFT 10
    #define VHE_HCLK_STOP_MASK 0x00000800
    #define VHE_HCLK_STOP_SHIFT 11
    #define VFE_MCLK_STOP_MASK 0x00001000
    #define VFE_MCLK_STOP_SHIFT 12
    #define VFE_SCLK_STOP_MASK 0x00002000
    #define VFE_SCLK_STOP_SHIFT 13
    #define VNE_SCLK_STOP_MASK 0x00004000
    #define VNE_SCLK_STOP_SHIFT 14
    #define PROC0_MCLK_STOP_MASK 0x00010000
    #define PROC0_MCLK_STOP_SHIFT 16
    #define PROC0_SCLK_STOP_MASK 0x00020000
    #define PROC0_SCLK_STOP_SHIFT 17
    #define PROC1_MCLK_STOP_MASK 0x00040000
    #define PROC1_MCLK_STOP_SHIFT 18
    #define PROC1_SCLK_STOP_MASK 0x00080000
    #define PROC1_SCLK_STOP_SHIFT 19
    #define PROC2_MCLK_STOP_MASK 0x00100000
    #define PROC2_MCLK_STOP_SHIFT 20
    #define PROC2_SCLK_STOP_MASK 0x00200000
    #define PROC2_SCLK_STOP_SHIFT 21
    #define PROC3_MCLK_STOP_MASK 0x00400000
    #define PROC3_MCLK_STOP_SHIFT 22
    #define PROC3_SCLK_STOP_MASK 0x00800000
    #define PROC3_SCLK_STOP_SHIFT 23
    #define PROC4_MCLK_STOP_MASK 0x01000000
    #define PROC4_MCLK_STOP_SHIFT 24
    #define PROC4_SCLK_STOP_MASK 0x02000000
    #define PROC4_SCLK_STOP_SHIFT 25
#define  CG_BLK_CLK_STOP1 0x0134
    #define USBD_MCLK_STOP_MASK 0x00000001
    #define USBD_MCLK_STOP_SHIFT 0
    #define USBH_MCLK_STOP_MASK 0x00000004
    #define USBH_MCLK_STOP_SHIFT 2
    #define USBH_SCLK_STOP_MASK 0x00000008
    #define USBH_SCLK_STOP_SHIFT 3
    #define ETH0_MCLK_STOP_MASK 0x00000010
    #define ETH0_MCLK_STOP_SHIFT 4
    #define ETH0_SCLK_STOP_MASK 0x00000020
    #define ETH0_SCLK_STOP_SHIFT 5
    #define ETH1_MCLK_STOP_MASK 0x00000040
    #define ETH1_MCLK_STOP_SHIFT 6
    #define ETH1_SCLK_STOP_MASK 0x00000080
    #define ETH1_SCLK_STOP_SHIFT 7
    #define HBI_MCLK_STOP_MASK 0x00000100
    #define HBI_MCLK_STOP_SHIFT 8
    #define HBI_SCLK_STOP_MASK 0x00000200
    #define HBI_SCLK_STOP_SHIFT 9
    #define SATA_MCLK_STOP_MASK 0x00000800
    #define SATA_MCLK_STOP_SHIFT 11
    #define DVE_MCLK_STOP_MASK 0x00010000
    #define DVE_MCLK_STOP_SHIFT 16
    #define DVE_SCLK_STOP_MASK 0x00020000
    #define DVE_SCLK_STOP_SHIFT 17
    #define SPDIFRX_MCLK_STOP_MASK 0x00040000
    #define SPDIFRX_MCLK_STOP_SHIFT 18
    #define SPDIFRX_SCLK_STOP_MASK 0x00080000
    #define SPDIFRX_SCLK_STOP_SHIFT 19
    #define SPDIFRX_VCLK_STOP_MASK 0x00100000
    #define SPDIFRX_VCLK_STOP_SHIFT 20
    #define I2STX0_MCLK_STOP_MASK 0x00200000
    #define I2STX0_MCLK_STOP_SHIFT 21
    #define I2STX0_SCLK_STOP_MASK 0x00400000
    #define I2STX0_SCLK_STOP_SHIFT 22
    #define SPDIFTX0_MCLK_STOP_MASK 0x00800000
    #define SPDIFTX0_MCLK_STOP_SHIFT 23
    #define SPDIFTX0_SCLK_STOP_MASK 0x01000000
    #define SPDIFTX0_SCLK_STOP_SHIFT 24
#define  CG_CLK_SRC_EN0 0x0120
    #define MCLK_SRC_EN_MASK 0x00000001
    #define MCLK_SRC_EN_SHIFT 0
    #define SCLK_SRC_EN_MASK 0x00000002
    #define SCLK_SRC_EN_SHIFT 1
    #define SEQCLK_SRC_EN_MASK 0x00000004
    #define SEQCLK_SRC_EN_SHIFT 2
    #define MRCLK_SRC_EN_MASK 0x00000020
    #define MRCLK_SRC_EN_SHIFT 5
    #define XCLK_SRC_EN_MASK 0x00000040
    #define XCLK_SRC_EN_SHIFT 6
    #define BCLK_SRC_EN_MASK 0x00000080
    #define BCLK_SRC_EN_SHIFT 7
    #define DCLK_SRC_EN_MASK 0x00000100
    #define DCLK_SRC_EN_SHIFT 8
    #define ACLK_SRC_EN_MASK 0x00000200
    #define ACLK_SRC_EN_SHIFT 9
    #define ECLK_SRC_EN_MASK 0x00000400
    #define ECLK_SRC_EN_SHIFT 10
    #define VCLK_SRC_EN_MASK 0x00000800
    #define VCLK_SRC_EN_SHIFT 11
    #define CCLK_SRC_EN_MASK 0x00001000
    #define CCLK_SRC_EN_SHIFT 12
    #define UCLK_SRC_EN_MASK 0x00002000
    #define UCLK_SRC_EN_SHIFT 13
    #define HUECLK_SRC_EN_MASK 0x00004000
    #define HUECLK_SRC_EN_SHIFT 14
    #define GVPCLK_SRC_EN_MASK 0x00008000
    #define GVPCLK_SRC_EN_SHIFT 15
    #define GVDCLK_SRC_EN_MASK 0x00010000
    #define GVDCLK_SRC_EN_SHIFT 16
    #define PROC0CLK_SRC_EN_MASK 0x00020000
    #define PROC0CLK_SRC_EN_SHIFT 17
    #define PROC1CLK_SRC_EN_MASK 0x00040000
    #define PROC1CLK_SRC_EN_SHIFT 18
    #define PROC2CLK_SRC_EN_MASK 0x00080000
    #define PROC2CLK_SRC_EN_SHIFT 19
    #define PROC3CLK_SRC_EN_MASK 0x00100000
    #define PROC3CLK_SRC_EN_SHIFT 20
    #define PROC4CLK_SRC_EN_MASK 0x00200000
    #define PROC4CLK_SRC_EN_SHIFT 21
    #define VOCLK_SRC_EN_MASK 0x00400000
    #define VOCLK_SRC_EN_SHIFT 22
    #define I2STX0CLK_SRC_EN_MASK 0x00800000
    #define I2STX0CLK_SRC_EN_SHIFT 23
    #define SPDIFTX0CLK_SRC_EN_MASK 0x01000000
    #define SPDIFTX0CLK_SRC_EN_SHIFT 24
    #define I2SSYSCLK_SRC_EN_MASK 0x02000000
    #define I2SSYSCLK_SRC_EN_SHIFT 25
#define  CG_CLK_SRC_EN1 0x0124
    #define I2SXTL_CLR_MASK 0x10000000
    #define I2SXTL_CLR_SHIFT 28
    #define I2SXTL_CKE_MASK 0x20000000
    #define I2SXTL_CKE_SHIFT 29
    #define XTL_CLR_MASK 0x40000000
    #define XTL_CLR_SHIFT 30
    #define XTL_CKE_MASK 0x80000000
    #define XTL_CKE_SHIFT 31
#define  CG_CLK_SRC_SEL0 0x0140
    #define SEQCLK_SRC_SEL_MASK 0x000000FF
    #define SEQCLK_SRC_SEL_SHIFT 0
#define  CG_CLK_SRC_SEL1 0x0144
    #define MCLK_SRC_SEL_MASK 0x000000FF
    #define MCLK_SRC_SEL_SHIFT 0
    #define SCLK_SRC_SEL_MASK 0x0000FF00
    #define SCLK_SRC_SEL_SHIFT 8
    #define MRCLK_SRC_SEL_MASK 0x00FF0000
    #define MRCLK_SRC_SEL_SHIFT 16
#define  CG_CLK_SRC_SEL2 0x0148
    #define XCLK_SRC_SEL_MASK 0x000000FF
    #define XCLK_SRC_SEL_SHIFT 0
    #define BCLK_SRC_SEL_MASK 0x0000FF00
    #define BCLK_SRC_SEL_SHIFT 8
    #define DCLK_SRC_SEL_MASK 0x00FF0000
    #define DCLK_SRC_SEL_SHIFT 16
    #define ACLK_SRC_SEL_MASK 0xFF000000
    #define ACLK_SRC_SEL_SHIFT 24
#define  CG_CLK_SRC_SEL3 0x014C
    #define ECLK_SRC_SEL_MASK 0x000000FF
    #define ECLK_SRC_SEL_SHIFT 0
    #define VCLK_SRC_SEL_MASK 0x0000FF00
    #define VCLK_SRC_SEL_SHIFT 8
    #define CCLK_SRC_SEL_MASK 0x00FF0000
    #define CCLK_SRC_SEL_SHIFT 16
    #define UCLK_SRC_SEL_MASK 0xFF000000
    #define UCLK_SRC_SEL_SHIFT 24
#define  CG_CLK_SRC_SEL4 0x0150
    #define HUECLK_SRC_SEL_MASK 0x000000FF
    #define HUECLK_SRC_SEL_SHIFT 0
    #define GVPCLK_SRC_SEL_MASK 0x0000FF00
    #define GVPCLK_SRC_SEL_SHIFT 8
    #define GVDCLK_SRC_SEL_MASK 0x00FF0000
    #define GVDCLK_SRC_SEL_SHIFT 16
#define  CG_CLK_SRC_SEL5 0x0154
    #define PROC0CLK_SRC_SEL_MASK 0x000000FF
    #define PROC0CLK_SRC_SEL_SHIFT 0
    #define PROC1CLK_SRC_SEL_MASK 0x0000FF00
    #define PROC1CLK_SRC_SEL_SHIFT 8
#define  CG_CLK_SRC_SEL6 0x0158
    #define PROC2CLK_SRC_SEL_MASK 0x000000FF
    #define PROC2CLK_SRC_SEL_SHIFT 0
    #define PROC3CLK_SRC_SEL_MASK 0x0000FF00
    #define PROC3CLK_SRC_SEL_SHIFT 8
    #define PROC4CLK_SRC_SEL_MASK 0x00FF0000
    #define PROC4CLK_SRC_SEL_SHIFT 16
#define  CG_CLK_SRC_SEL7 0x015C
    #define VOCLK_SRC_SEL_MASK 0x0000000F
    #define VOCLK_SRC_SEL_SHIFT 0
    #define I2SSYSCLK_SRC_SEL_MASK 0x0000F000
    #define I2SSYSCLK_SRC_SEL_SHIFT 12
#define  CG_CLK_SRC_SEL8 0x0160
    #define I2STX0CLK_SRC_SEL_MASK 0x0000000F
    #define I2STX0CLK_SRC_SEL_SHIFT 0
    #define SPDIFTX0CLK_SRC_SEL_MASK 0x000F0000
    #define SPDIFTX0CLK_SRC_SEL_SHIFT 16
#define  CG_CLK_SRC_SEL9 0x0164
#define  CG_CLK_STOP0 0x0128
    #define MCLK_STOP_MASK 0x00000001
    #define MCLK_STOP_SHIFT 0
    #define SEQ0CLK_STOP_MASK 0x00000004
    #define SEQ0CLK_STOP_SHIFT 2
    #define SEQ1CLK_STOP_MASK 0x00000008
    #define SEQ1CLK_STOP_SHIFT 3
    #define SEQ2CLK_STOP_MASK 0x00000010
    #define SEQ2CLK_STOP_SHIFT 4
    #define MRCLK_STOP_MASK 0x00000020
    #define MRCLK_STOP_SHIFT 5
    #define XCLK_STOP_MASK 0x00000040
    #define XCLK_STOP_SHIFT 6
    #define BCLK_STOP_MASK 0x00000080
    #define BCLK_STOP_SHIFT 7
    #define DCLK_STOP_MASK 0x00000100
    #define DCLK_STOP_SHIFT 8
    #define ACLK_STOP_MASK 0x00000200
    #define ACLK_STOP_SHIFT 9
    #define ECLK_STOP_MASK 0x00000400
    #define ECLK_STOP_SHIFT 10
    #define VCLK_STOP_MASK 0x00000800
    #define VCLK_STOP_SHIFT 11
    #define CCLK_STOP_MASK 0x00001000
    #define CCLK_STOP_SHIFT 12
    #define UCLK_STOP_MASK 0x00002000
    #define UCLK_STOP_SHIFT 13
    #define HUECLK_STOP_MASK 0x00004000
    #define HUECLK_STOP_SHIFT 14
    #define GVPCLK_STOP_MASK 0x00008000
    #define GVPCLK_STOP_SHIFT 15
    #define GVDCLK_STOP_MASK 0x00010000
    #define GVDCLK_STOP_SHIFT 16
    #define PROC0CLK_STOP_MASK 0x00020000
    #define PROC0CLK_STOP_SHIFT 17
    #define PROC1CLK_STOP_MASK 0x00040000
    #define PROC1CLK_STOP_SHIFT 18
    #define PROC2CLK_STOP_MASK 0x00080000
    #define PROC2CLK_STOP_SHIFT 19
    #define PROC3CLK_STOP_MASK 0x00100000
    #define PROC3CLK_STOP_SHIFT 20
    #define PROC4CLK_STOP_MASK 0x00200000
    #define PROC4CLK_STOP_SHIFT 21
    #define VOCLK_STOP_MASK 0x00400000
    #define VOCLK_STOP_SHIFT 22
    #define I2STX0CLK_STOP_MASK 0x00800000
    #define I2STX0CLK_STOP_SHIFT 23
    #define SPDIFTX0CLK_STOP_MASK 0x01000000
    #define SPDIFTX0CLK_STOP_SHIFT 24
    #define I2SSYSCLK_STOP_MASK 0x02000000
    #define I2SSYSCLK_STOP_SHIFT 25
    #define VHE_INPUT0_EN_MASK 0x40000000
    #define VHE_INPUT0_EN_SHIFT 30
    #define VHE_INPUT1_EN_MASK 0x80000000
    #define VHE_INPUT1_EN_SHIFT 31
#define  CG_DBUS_CLK_SEL 0x0090
    #define DBCLK0_SEL_MASK 0x000000FF
    #define DBCLK0_SEL_SHIFT 0
    #define DBCLK1_SEL_MASK 0x0000FF00
    #define DBCLK1_SEL_SHIFT 8
#define  CG_DFT 0x0110
    #define REG_TRIG_DIS_MASK 0x00000001
    #define REG_TRIG_DIS_SHIFT 0
    #define TEST_CNT_STOP_MASK 0x40000000
    #define TEST_CNT_STOP_SHIFT 30
    #define TEST_CNT_START_MASK 0x80000000
    #define TEST_CNT_START_SHIFT 31
#define  CG_DUMMY_REG 0x00FC
    #define CG_DUMMY_REG_DUMMY_BITS_MASK 0xFFFFFFFF
    #define CG_DUMMY_REG_DUMMY_BITS_SHIFT 0
#define  CG_IP_PHY_CLK_CTRL 0x0104    
#define  CG_DYNAMIC_BLK_STOP 0x0068
    #define VNE_VCLK_GATE_MASK 0x00001000
    #define VNE_VCLK_GATE_SHIFT 12
    #define VNE_MCLK_GATE_MASK 0x00002000
    #define VNE_MCLK_GATE_SHIFT 13
#define  CG_GENLOCK_CTRL 0x0084
    #define CG_GENLOCK_CTRL_VHE0_CLR_CNT_MASK 0x00000001
    #define CG_GENLOCK_CTRL_VHE0_CLR_CNT_SHIFT 0
    #define CG_GENLOCK_CTRL_VHE1_CLR_CNT_MASK 0x00000002
    #define CG_GENLOCK_CTRL_VHE1_CLR_CNT_SHIFT 1
    #define CG_GENLOCK_CTRL_I2S0_CLR_CNT_MASK 0x00000004
    #define CG_GENLOCK_CTRL_I2S0_CLR_CNT_SHIFT 2
    #define CG_GENLOCK_CTRL_I2S1_CLR_CNT_MASK 0x00000008
    #define CG_GENLOCK_CTRL_I2S1_CLR_CNT_SHIFT 3
    #define CG_GENLOCK_CTRL_SPDIF_RX_CLR_CNT_MASK 0x00000010
    #define CG_GENLOCK_CTRL_SPDIF_RX_CLR_CNT_SHIFT 4
    #define CG_GENLOCK_CTRL_DVE_CLR_CNT_MASK 0x00000020
    #define CG_GENLOCK_CTRL_DVE_CLR_CNT_SHIFT 5
    #define I2S_TX_CLR_CNT_MASK 0x00000040
    #define I2S_TX_CLR_CNT_SHIFT 6
    #define SPDIF_TX_CLR_CNT_MASK 0x00000080
    #define SPDIF_TX_CLR_CNT_SHIFT 7
    #define TSD_CLR_CNT_MASK 0x00000100
    #define TSD_CLR_CNT_SHIFT 8
    #define CG_GENLOCK_CTRL_VHE0_EN_CNT_MASK 0x00000400
    #define CG_GENLOCK_CTRL_VHE0_EN_CNT_SHIFT 10
    #define CG_GENLOCK_CTRL_VHE1_EN_CNT_MASK 0x00000800
    #define CG_GENLOCK_CTRL_VHE1_EN_CNT_SHIFT 11
    #define CG_GENLOCK_CTRL_I2S0_EN_CNT_MASK 0x00001000
    #define CG_GENLOCK_CTRL_I2S0_EN_CNT_SHIFT 12
    #define CG_GENLOCK_CTRL_I2S1_EN_CNT_MASK 0x00002000
    #define CG_GENLOCK_CTRL_I2S1_EN_CNT_SHIFT 13
    #define CG_GENLOCK_CTRL_SPDIF_RX_EN_CNT_MASK 0x00004000
    #define CG_GENLOCK_CTRL_SPDIF_RX_EN_CNT_SHIFT 14
    #define CG_GENLOCK_CTRL_DVE_EN_CNT_MASK 0x00008000
    #define CG_GENLOCK_CTRL_DVE_EN_CNT_SHIFT 15
    #define I2S_TX_EN_CNT_MASK 0x00010000
    #define I2S_TX_EN_CNT_SHIFT 16
    #define TSD_EN_CNT_MASK 0x00020000
    #define TSD_EN_CNT_SHIFT 17
    #define SPDIF_TX_EN_CNT_MASK 0x00040000
    #define SPDIF_TX_EN_CNT_SHIFT 18
    #define VHE0_SAMPLE_CNT_MASK 0x00100000
    #define VHE0_SAMPLE_CNT_SHIFT 20
    #define VHE1_SAMPLE_CNT_MASK 0x00200000
    #define VHE1_SAMPLE_CNT_SHIFT 21
    #define I2S0_SAMPLE_CNT_MASK 0x00400000
    #define I2S0_SAMPLE_CNT_SHIFT 22
    #define I2S1_SAMPLE_CNT_MASK 0x00800000
    #define I2S1_SAMPLE_CNT_SHIFT 23
    #define SPDIF_RX_SAMPLE_CNT_MASK 0x01000000
    #define SPDIF_RX_SAMPLE_CNT_SHIFT 24
    #define CG_GENLOCK_CTRL_DVE_SAMPLE_CNT_MASK 0x02000000
    #define CG_GENLOCK_CTRL_DVE_SAMPLE_CNT_SHIFT 25
    #define I2S_TX_SAMPLE_CNT_MASK 0x04000000
    #define I2S_TX_SAMPLE_CNT_SHIFT 26
    #define SPDIF_TX_SAMPLE_CNT_MASK 0x08000000
    #define SPDIF_TX_SAMPLE_CNT_SHIFT 27
    #define TSD_SAMPLE_CNT_MASK 0x10000000
    #define TSD_SAMPLE_CNT_SHIFT 28
#define  CG_GENLOCK_PCR_CTRL 0x008C
    #define CG_GENLOCK_PCR_CTRL_DVE_CLR_CNT_MASK 0x00000001
    #define CG_GENLOCK_PCR_CTRL_DVE_CLR_CNT_SHIFT 0
    #define CG_GENLOCK_PCR_CTRL_DVE_EN_CNT_MASK 0x00000100
    #define CG_GENLOCK_PCR_CTRL_DVE_EN_CNT_SHIFT 8
    #define CG_GENLOCK_PCR_CTRL_DVE_SAMPLE_CNT_MASK 0x00010000
    #define CG_GENLOCK_PCR_CTRL_DVE_SAMPLE_CNT_SHIFT 16
#define  CG_I2SSYSCLK_FREQ 0x01A0
    #define I2SSYSCLK_DIV_MASK 0x0000000E
    #define I2SSYSCLK_DIV_SHIFT 1
    #define I2SSYSCLK_DIV_SEL_MASK 0x00010000
    #define I2SSYSCLK_DIV_SEL_SHIFT 16
    #define I2SSYSCLK_DIV_RST_MASK 0x01000000
    #define I2SSYSCLK_DIV_RST_SHIFT 24
#define  CG_I2STX0CLK_FREQ 0x0180
    #define I2STX0CLK_DIV_MASK 0x000003FE
    #define I2STX0CLK_DIV_SHIFT 1
    #define I2STX0CLK_DIV_SEL_MASK 0x000F0000
    #define I2STX0CLK_DIV_SEL_SHIFT 16
    #define I2STX0CLK_DIV_RST_MASK 0x01000000
    #define I2STX0CLK_DIV_RST_SHIFT 24
#define  CG_LPCLK_CTRL 0x0070
    #define LPCLK_DIV_MASK 0x000003FE
    #define LPCLK_DIV_SHIFT 1
    #define LPCLK_SRC_SEL_MASK 0x00010000
    #define LPCLK_SRC_SEL_SHIFT 16
    #define LPCLK_RST_MASK 0x01000000
    #define LPCLK_RST_SHIFT 24
#define  CG_MCIF_RESET 0x0108
    #define MCIF_RING1_RESET_MASK 0x00000002
    #define MCIF_RING1_RESET_SHIFT 1
    #define MCIF_RING2_RESET_MASK 0x00000004
    #define MCIF_RING2_RESET_SHIFT 2
    #define MCIF_RING3_RESET_MASK 0x00000008
    #define MCIF_RING3_RESET_SHIFT 3
    #define MCIF_RING4_RESET_MASK 0x00000010
    #define MCIF_RING4_RESET_SHIFT 4
#define  CG_MODDIV_CTRL 0x02A8
    #define CG_MODDIV_CTRL_RESET_MASK 0x00000001
    #define CG_MODDIV_CTRL_RESET_SHIFT 0
    #define CG_MODDIV_CTRL_ENABLE_MASK 0x00000002
    #define CG_MODDIV_CTRL_ENABLE_SHIFT 1
#define  CG_MODDIV_DEN 0x02A4
    #define MODDIV_DEN_MASK 0x03FFFFFF
    #define MODDIV_DEN_SHIFT 0
#define  CG_MODDIV_NUM 0x02A0
    #define MODDIV_NUM_MASK 0x003FFFFF
    #define MODDIV_NUM_SHIFT 0
#define  CG_PLL0_CTRL 0x0208
    #define CG_PLL0_CTRL_ENABLE_MASK 0x00000001
    #define CG_PLL0_CTRL_ENABLE_SHIFT 0
    #define CG_PLL0_CTRL_LOOP_INIT_MASK 0x00000002
    #define CG_PLL0_CTRL_LOOP_INIT_SHIFT 1
    #define CG_PLL0_CTRL_REFCLK_SEL_MASK 0x0000000C
    #define CG_PLL0_CTRL_REFCLK_SEL_SHIFT 2
    #define CG_PLL0_CTRL_FILTER_IBIAS_IDN_MASK 0x00000010
    #define CG_PLL0_CTRL_FILTER_IBIAS_IDN_SHIFT 4
    #define CG_PLL0_CTRL_FILTER_IBIAS_IUP_MASK 0x00000020
    #define CG_PLL0_CTRL_FILTER_IBIAS_IUP_SHIFT 5
    #define CG_PLL0_CTRL_FILTER_PCASC_IDN_MASK 0x00000040
    #define CG_PLL0_CTRL_FILTER_PCASC_IDN_SHIFT 6
    #define CG_PLL0_CTRL_FILTER_PCASC_IUP_MASK 0x00000080
    #define CG_PLL0_CTRL_FILTER_PCASC_IUP_SHIFT 7
    #define CG_PLL0_CTRL_FILTER_NCASC_IDN_MASK 0x00000100
    #define CG_PLL0_CTRL_FILTER_NCASC_IDN_SHIFT 8
    #define CG_PLL0_CTRL_FILTER_NCASC_IUP_MASK 0x00000200
    #define CG_PLL0_CTRL_FILTER_NCASC_IUP_SHIFT 9
    #define CG_PLL0_CTRL_LFSR_ENABLE_MASK 0x00000800
    #define CG_PLL0_CTRL_LFSR_ENABLE_SHIFT 11
    #define CG_PLL0_CTRL_ICPHALF_MASK 0x00001000
    #define CG_PLL0_CTRL_ICPHALF_SHIFT 12
    #define CG_PLL0_CTRL_ICP2X_MASK 0x00002000
    #define CG_PLL0_CTRL_ICP2X_SHIFT 13
    #define CG_PLL0_CTRL_SELFBIAS_MASK 0x00008000
    #define CG_PLL0_CTRL_SELFBIAS_SHIFT 15
    #define CG_PLL0_CTRL_VAG_OA_IBIAS_IDN_MASK 0x00010000
    #define CG_PLL0_CTRL_VAG_OA_IBIAS_IDN_SHIFT 16
    #define CG_PLL0_CTRL_VAG_OA_IBIAS_IUP_MASK 0x00020000
    #define CG_PLL0_CTRL_VAG_OA_IBIAS_IUP_SHIFT 17
    #define CG_PLL0_CTRL_VAG_OA_PCASC_IDN_MASK 0x00040000
    #define CG_PLL0_CTRL_VAG_OA_PCASC_IDN_SHIFT 18
    #define CG_PLL0_CTRL_VAG_OA_PCASC_IUP_MASK 0x00080000
    #define CG_PLL0_CTRL_VAG_OA_PCASC_IUP_SHIFT 19
    #define CG_PLL0_CTRL_VAG_OA_NCASC_IDN_MASK 0x00100000
    #define CG_PLL0_CTRL_VAG_OA_NCASC_IDN_SHIFT 20
    #define CG_PLL0_CTRL_VAG_OA_NCASC_IUP_MASK 0x00200000
    #define CG_PLL0_CTRL_VAG_OA_NCASC_IUP_SHIFT 21
    #define CG_PLL0_CTRL_PFD_SEL_MASK 0x01000000
    #define CG_PLL0_CTRL_PFD_SEL_SHIFT 24
    #define CG_PLL0_CTRL_FRAC_ENABLE_MASK 0x02000000
    #define CG_PLL0_CTRL_FRAC_ENABLE_SHIFT 25
    #define CG_PLL0_CTRL_CONT_LOCK_MON_MASK 0x04000000
    #define CG_PLL0_CTRL_CONT_LOCK_MON_SHIFT 26
    #define CG_PLL0_CTRL_TSTSEL_MASK 0x70000000
    #define CG_PLL0_CTRL_TSTSEL_SHIFT 28
#define  CG_PLL0_FREQ 0x0200
    #define CG_PLL0_FREQ_FB_DIV_FRAC_MASK 0x000FFFFF
    #define CG_PLL0_FREQ_FB_DIV_FRAC_SHIFT 0
    #define CG_PLL0_FREQ_FB_DIV_INT_MASK 0x00F00000
    #define CG_PLL0_FREQ_FB_DIV_INT_SHIFT 20
    #define CG_PLL0_FREQ_PRE_DIV_MASK 0x01000000
    #define CG_PLL0_FREQ_PRE_DIV_SHIFT 24
#define  CG_PLL1_CTRL 0x0218
    #define CG_PLL1_CTRL_ENABLE_MASK 0x00000001
    #define CG_PLL1_CTRL_ENABLE_SHIFT 0
    #define CG_PLL1_CTRL_LOOP_INIT_MASK 0x00000002
    #define CG_PLL1_CTRL_LOOP_INIT_SHIFT 1
    #define CG_PLL1_CTRL_REFCLK_SEL_MASK 0x0000000C
    #define CG_PLL1_CTRL_REFCLK_SEL_SHIFT 2
    #define CG_PLL1_CTRL_FILTER_IBIAS_IDN_MASK 0x00000010
    #define CG_PLL1_CTRL_FILTER_IBIAS_IDN_SHIFT 4
    #define CG_PLL1_CTRL_FILTER_IBIAS_IUP_MASK 0x00000020
    #define CG_PLL1_CTRL_FILTER_IBIAS_IUP_SHIFT 5
    #define CG_PLL1_CTRL_FILTER_PCASC_IDN_MASK 0x00000040
    #define CG_PLL1_CTRL_FILTER_PCASC_IDN_SHIFT 6
    #define CG_PLL1_CTRL_FILTER_PCASC_IUP_MASK 0x00000080
    #define CG_PLL1_CTRL_FILTER_PCASC_IUP_SHIFT 7
    #define CG_PLL1_CTRL_FILTER_NCASC_IDN_MASK 0x00000100
    #define CG_PLL1_CTRL_FILTER_NCASC_IDN_SHIFT 8
    #define CG_PLL1_CTRL_FILTER_NCASC_IUP_MASK 0x00000200
    #define CG_PLL1_CTRL_FILTER_NCASC_IUP_SHIFT 9
    #define CG_PLL1_CTRL_LFSR_ENABLE_MASK 0x00000800
    #define CG_PLL1_CTRL_LFSR_ENABLE_SHIFT 11
    #define CG_PLL1_CTRL_ICPHALF_MASK 0x00001000
    #define CG_PLL1_CTRL_ICPHALF_SHIFT 12
    #define CG_PLL1_CTRL_ICP2X_MASK 0x00002000
    #define CG_PLL1_CTRL_ICP2X_SHIFT 13
    #define CG_PLL1_CTRL_SELFBIAS_MASK 0x00008000
    #define CG_PLL1_CTRL_SELFBIAS_SHIFT 15
    #define CG_PLL1_CTRL_VAG_OA_IBIAS_IDN_MASK 0x00010000
    #define CG_PLL1_CTRL_VAG_OA_IBIAS_IDN_SHIFT 16
    #define CG_PLL1_CTRL_VAG_OA_IBIAS_IUP_MASK 0x00020000
    #define CG_PLL1_CTRL_VAG_OA_IBIAS_IUP_SHIFT 17
    #define CG_PLL1_CTRL_VAG_OA_PCASC_IDN_MASK 0x00040000
    #define CG_PLL1_CTRL_VAG_OA_PCASC_IDN_SHIFT 18
    #define CG_PLL1_CTRL_VAG_OA_PCASC_IUP_MASK 0x00080000
    #define CG_PLL1_CTRL_VAG_OA_PCASC_IUP_SHIFT 19
    #define CG_PLL1_CTRL_VAG_OA_NCASC_IDN_MASK 0x00100000
    #define CG_PLL1_CTRL_VAG_OA_NCASC_IDN_SHIFT 20
    #define CG_PLL1_CTRL_VAG_OA_NCASC_IUP_MASK 0x00200000
    #define CG_PLL1_CTRL_VAG_OA_NCASC_IUP_SHIFT 21
    #define CG_PLL1_CTRL_PFD_SEL_MASK 0x01000000
    #define CG_PLL1_CTRL_PFD_SEL_SHIFT 24
    #define CG_PLL1_CTRL_FRAC_ENABLE_MASK 0x02000000
    #define CG_PLL1_CTRL_FRAC_ENABLE_SHIFT 25
    #define CG_PLL1_CTRL_CONT_LOCK_MON_MASK 0x04000000
    #define CG_PLL1_CTRL_CONT_LOCK_MON_SHIFT 26
    #define CG_PLL1_CTRL_TSTSEL_MASK 0x70000000
    #define CG_PLL1_CTRL_TSTSEL_SHIFT 28
#define  CG_PLL1_FREQ 0x0210
    #define CG_PLL1_FREQ_FB_DIV_FRAC_MASK 0x000FFFFF
    #define CG_PLL1_FREQ_FB_DIV_FRAC_SHIFT 0
    #define CG_PLL1_FREQ_FB_DIV_INT_MASK 0x00F00000
    #define CG_PLL1_FREQ_FB_DIV_INT_SHIFT 20
    #define CG_PLL1_FREQ_PRE_DIV_MASK 0x01000000
    #define CG_PLL1_FREQ_PRE_DIV_SHIFT 24
#define  CG_PLL2_CTRL 0x0228
    #define CG_PLL2_CTRL_ENABLE_MASK 0x00000001
    #define CG_PLL2_CTRL_ENABLE_SHIFT 0
    #define CG_PLL2_CTRL_LOOP_INIT_MASK 0x00000002
    #define CG_PLL2_CTRL_LOOP_INIT_SHIFT 1
    #define CG_PLL2_CTRL_REFCLK_SEL_MASK 0x0000000C
    #define CG_PLL2_CTRL_REFCLK_SEL_SHIFT 2
    #define CG_PLL2_CTRL_FILTER_IBIAS_IDN_MASK 0x00000010
    #define CG_PLL2_CTRL_FILTER_IBIAS_IDN_SHIFT 4
    #define CG_PLL2_CTRL_FILTER_IBIAS_IUP_MASK 0x00000020
    #define CG_PLL2_CTRL_FILTER_IBIAS_IUP_SHIFT 5
    #define CG_PLL2_CTRL_FILTER_PCASC_IDN_MASK 0x00000040
    #define CG_PLL2_CTRL_FILTER_PCASC_IDN_SHIFT 6
    #define CG_PLL2_CTRL_FILTER_PCASC_IUP_MASK 0x00000080
    #define CG_PLL2_CTRL_FILTER_PCASC_IUP_SHIFT 7
    #define CG_PLL2_CTRL_FILTER_NCASC_IDN_MASK 0x00000100
    #define CG_PLL2_CTRL_FILTER_NCASC_IDN_SHIFT 8
    #define CG_PLL2_CTRL_FILTER_NCASC_IUP_MASK 0x00000200
    #define CG_PLL2_CTRL_FILTER_NCASC_IUP_SHIFT 9
    #define CG_PLL2_CTRL_LFSR_ENABLE_MASK 0x00000800
    #define CG_PLL2_CTRL_LFSR_ENABLE_SHIFT 11
    #define CG_PLL2_CTRL_ICPHALF_MASK 0x00001000
    #define CG_PLL2_CTRL_ICPHALF_SHIFT 12
    #define CG_PLL2_CTRL_ICP2X_MASK 0x00002000
    #define CG_PLL2_CTRL_ICP2X_SHIFT 13
    #define CG_PLL2_CTRL_SELFBIAS_MASK 0x00008000
    #define CG_PLL2_CTRL_SELFBIAS_SHIFT 15
    #define CG_PLL2_CTRL_VAG_OA_IBIAS_IDN_MASK 0x00010000
    #define CG_PLL2_CTRL_VAG_OA_IBIAS_IDN_SHIFT 16
    #define CG_PLL2_CTRL_VAG_OA_IBIAS_IUP_MASK 0x00020000
    #define CG_PLL2_CTRL_VAG_OA_IBIAS_IUP_SHIFT 17
    #define CG_PLL2_CTRL_VAG_OA_PCASC_IDN_MASK 0x00040000
    #define CG_PLL2_CTRL_VAG_OA_PCASC_IDN_SHIFT 18
    #define CG_PLL2_CTRL_VAG_OA_PCASC_IUP_MASK 0x00080000
    #define CG_PLL2_CTRL_VAG_OA_PCASC_IUP_SHIFT 19
    #define CG_PLL2_CTRL_VAG_OA_NCASC_IDN_MASK 0x00100000
    #define CG_PLL2_CTRL_VAG_OA_NCASC_IDN_SHIFT 20
    #define CG_PLL2_CTRL_VAG_OA_NCASC_IUP_MASK 0x00200000
    #define CG_PLL2_CTRL_VAG_OA_NCASC_IUP_SHIFT 21
    #define CG_PLL2_CTRL_PFD_SEL_MASK 0x01000000
    #define CG_PLL2_CTRL_PFD_SEL_SHIFT 24
    #define CG_PLL2_CTRL_FRAC_ENABLE_MASK 0x02000000
    #define CG_PLL2_CTRL_FRAC_ENABLE_SHIFT 25
    #define CG_PLL2_CTRL_CONT_LOCK_MON_MASK 0x04000000
    #define CG_PLL2_CTRL_CONT_LOCK_MON_SHIFT 26
    #define CG_PLL2_CTRL_TSTSEL_MASK 0x70000000
    #define CG_PLL2_CTRL_TSTSEL_SHIFT 28
#define  CG_PLL2_FREQ 0x0220
    #define CG_PLL2_FREQ_FB_DIV_FRAC_MASK 0x000FFFFF
    #define CG_PLL2_FREQ_FB_DIV_FRAC_SHIFT 0
    #define CG_PLL2_FREQ_FB_DIV_INT_MASK 0x00F00000
    #define CG_PLL2_FREQ_FB_DIV_INT_SHIFT 20
    #define CG_PLL2_FREQ_PRE_DIV_MASK 0x01000000
    #define CG_PLL2_FREQ_PRE_DIV_SHIFT 24
#define  CG_PLL3_CTRL 0x0238
    #define CG_PLL3_CTRL_ENABLE_MASK 0x00000001
    #define CG_PLL3_CTRL_ENABLE_SHIFT 0
    #define CG_PLL3_CTRL_LOOP_INIT_MASK 0x00000002
    #define CG_PLL3_CTRL_LOOP_INIT_SHIFT 1
    #define CG_PLL3_CTRL_REFCLK_SEL_MASK 0x0000000C
    #define CG_PLL3_CTRL_REFCLK_SEL_SHIFT 2
    #define CG_PLL3_CTRL_FILTER_IBIAS_IDN_MASK 0x00000010
    #define CG_PLL3_CTRL_FILTER_IBIAS_IDN_SHIFT 4
    #define CG_PLL3_CTRL_FILTER_IBIAS_IUP_MASK 0x00000020
    #define CG_PLL3_CTRL_FILTER_IBIAS_IUP_SHIFT 5
    #define CG_PLL3_CTRL_FILTER_PCASC_IDN_MASK 0x00000040
    #define CG_PLL3_CTRL_FILTER_PCASC_IDN_SHIFT 6
    #define CG_PLL3_CTRL_FILTER_PCASC_IUP_MASK 0x00000080
    #define CG_PLL3_CTRL_FILTER_PCASC_IUP_SHIFT 7
    #define CG_PLL3_CTRL_FILTER_NCASC_IDN_MASK 0x00000100
    #define CG_PLL3_CTRL_FILTER_NCASC_IDN_SHIFT 8
    #define CG_PLL3_CTRL_FILTER_NCASC_IUP_MASK 0x00000200
    #define CG_PLL3_CTRL_FILTER_NCASC_IUP_SHIFT 9
    #define CG_PLL3_CTRL_LFSR_ENABLE_MASK 0x00000800
    #define CG_PLL3_CTRL_LFSR_ENABLE_SHIFT 11
    #define CG_PLL3_CTRL_ICPHALF_MASK 0x00001000
    #define CG_PLL3_CTRL_ICPHALF_SHIFT 12
    #define CG_PLL3_CTRL_ICP2X_MASK 0x00002000
    #define CG_PLL3_CTRL_ICP2X_SHIFT 13
    #define CG_PLL3_CTRL_SELFBIAS_MASK 0x00008000
    #define CG_PLL3_CTRL_SELFBIAS_SHIFT 15
    #define CG_PLL3_CTRL_VAG_OA_IBIAS_IDN_MASK 0x00010000
    #define CG_PLL3_CTRL_VAG_OA_IBIAS_IDN_SHIFT 16
    #define CG_PLL3_CTRL_VAG_OA_IBIAS_IUP_MASK 0x00020000
    #define CG_PLL3_CTRL_VAG_OA_IBIAS_IUP_SHIFT 17
    #define CG_PLL3_CTRL_VAG_OA_PCASC_IDN_MASK 0x00040000
    #define CG_PLL3_CTRL_VAG_OA_PCASC_IDN_SHIFT 18
    #define CG_PLL3_CTRL_VAG_OA_PCASC_IUP_MASK 0x00080000
    #define CG_PLL3_CTRL_VAG_OA_PCASC_IUP_SHIFT 19
    #define CG_PLL3_CTRL_VAG_OA_NCASC_IDN_MASK 0x00100000
    #define CG_PLL3_CTRL_VAG_OA_NCASC_IDN_SHIFT 20
    #define CG_PLL3_CTRL_VAG_OA_NCASC_IUP_MASK 0x00200000
    #define CG_PLL3_CTRL_VAG_OA_NCASC_IUP_SHIFT 21
    #define CG_PLL3_CTRL_PFD_SEL_MASK 0x01000000
    #define CG_PLL3_CTRL_PFD_SEL_SHIFT 24
    #define CG_PLL3_CTRL_FRAC_ENABLE_MASK 0x02000000
    #define CG_PLL3_CTRL_FRAC_ENABLE_SHIFT 25
    #define CG_PLL3_CTRL_CONT_LOCK_MON_MASK 0x04000000
    #define CG_PLL3_CTRL_CONT_LOCK_MON_SHIFT 26
    #define CG_PLL3_CTRL_TSTSEL_MASK 0x70000000
    #define CG_PLL3_CTRL_TSTSEL_SHIFT 28
#define  CG_PLL3_FREQ 0x0230
    #define CG_PLL3_FREQ_FB_DIV_FRAC_MASK 0x000FFFFF
    #define CG_PLL3_FREQ_FB_DIV_FRAC_SHIFT 0
    #define CG_PLL3_FREQ_FB_DIV_INT_MASK 0x00F00000
    #define CG_PLL3_FREQ_FB_DIV_INT_SHIFT 20
    #define CG_PLL3_FREQ_PRE_DIV_MASK 0x01000000
    #define CG_PLL3_FREQ_PRE_DIV_SHIFT 24
#define  CG_PLL4_CTRL 0x0248
    #define CG_PLL4_CTRL_ENABLE_MASK 0x00000001
    #define CG_PLL4_CTRL_ENABLE_SHIFT 0
    #define CG_PLL4_CTRL_LOOP_INIT_MASK 0x00000002
    #define CG_PLL4_CTRL_LOOP_INIT_SHIFT 1
    #define CG_PLL4_CTRL_REFCLK_SEL_MASK 0x0000000C
    #define CG_PLL4_CTRL_REFCLK_SEL_SHIFT 2
    #define CG_PLL4_CTRL_FILTER_IBIAS_IDN_MASK 0x00000010
    #define CG_PLL4_CTRL_FILTER_IBIAS_IDN_SHIFT 4
    #define CG_PLL4_CTRL_FILTER_IBIAS_IUP_MASK 0x00000020
    #define CG_PLL4_CTRL_FILTER_IBIAS_IUP_SHIFT 5
    #define CG_PLL4_CTRL_FILTER_PCASC_IDN_MASK 0x00000040
    #define CG_PLL4_CTRL_FILTER_PCASC_IDN_SHIFT 6
    #define CG_PLL4_CTRL_FILTER_PCASC_IUP_MASK 0x00000080
    #define CG_PLL4_CTRL_FILTER_PCASC_IUP_SHIFT 7
    #define CG_PLL4_CTRL_FILTER_NCASC_IDN_MASK 0x00000100
    #define CG_PLL4_CTRL_FILTER_NCASC_IDN_SHIFT 8
    #define CG_PLL4_CTRL_FILTER_NCASC_IUP_MASK 0x00000200
    #define CG_PLL4_CTRL_FILTER_NCASC_IUP_SHIFT 9
    #define CG_PLL4_CTRL_LFSR_ENABLE_MASK 0x00000800
    #define CG_PLL4_CTRL_LFSR_ENABLE_SHIFT 11
    #define CG_PLL4_CTRL_ICPHALF_MASK 0x00001000
    #define CG_PLL4_CTRL_ICPHALF_SHIFT 12
    #define CG_PLL4_CTRL_ICP2X_MASK 0x00002000
    #define CG_PLL4_CTRL_ICP2X_SHIFT 13
    #define CG_PLL4_CTRL_SELFBIAS_MASK 0x00008000
    #define CG_PLL4_CTRL_SELFBIAS_SHIFT 15
    #define CG_PLL4_CTRL_VAG_OA_IBIAS_IDN_MASK 0x00010000
    #define CG_PLL4_CTRL_VAG_OA_IBIAS_IDN_SHIFT 16
    #define CG_PLL4_CTRL_VAG_OA_IBIAS_IUP_MASK 0x00020000
    #define CG_PLL4_CTRL_VAG_OA_IBIAS_IUP_SHIFT 17
    #define CG_PLL4_CTRL_VAG_OA_PCASC_IDN_MASK 0x00040000
    #define CG_PLL4_CTRL_VAG_OA_PCASC_IDN_SHIFT 18
    #define CG_PLL4_CTRL_VAG_OA_PCASC_IUP_MASK 0x00080000
    #define CG_PLL4_CTRL_VAG_OA_PCASC_IUP_SHIFT 19
    #define CG_PLL4_CTRL_VAG_OA_NCASC_IDN_MASK 0x00100000
    #define CG_PLL4_CTRL_VAG_OA_NCASC_IDN_SHIFT 20
    #define CG_PLL4_CTRL_VAG_OA_NCASC_IUP_MASK 0x00200000
    #define CG_PLL4_CTRL_VAG_OA_NCASC_IUP_SHIFT 21
    #define CG_PLL4_CTRL_PFD_SEL_MASK 0x01000000
    #define CG_PLL4_CTRL_PFD_SEL_SHIFT 24
    #define CG_PLL4_CTRL_FRAC_ENABLE_MASK 0x02000000
    #define CG_PLL4_CTRL_FRAC_ENABLE_SHIFT 25
    #define CG_PLL4_CTRL_CONT_LOCK_MON_MASK 0x04000000
    #define CG_PLL4_CTRL_CONT_LOCK_MON_SHIFT 26
    #define CG_PLL4_CTRL_TSTSEL_MASK 0x70000000
    #define CG_PLL4_CTRL_TSTSEL_SHIFT 28
#define  CG_PLL4_FREQ 0x0240
    #define CG_PLL4_FREQ_FB_DIV_FRAC_MASK 0x000FFFFF
    #define CG_PLL4_FREQ_FB_DIV_FRAC_SHIFT 0
    #define CG_PLL4_FREQ_FB_DIV_INT_MASK 0x00F00000
    #define CG_PLL4_FREQ_FB_DIV_INT_SHIFT 20
    #define CG_PLL4_FREQ_PRE_DIV_MASK 0x01000000
    #define CG_PLL4_FREQ_PRE_DIV_SHIFT 24
#define  CG_PLL5_CTRL 0x0258
    #define CG_PLL5_CTRL_ENABLE_MASK 0x00000001
    #define CG_PLL5_CTRL_ENABLE_SHIFT 0
    #define CG_PLL5_CTRL_LOOP_INIT_MASK 0x00000002
    #define CG_PLL5_CTRL_LOOP_INIT_SHIFT 1
    #define CG_PLL5_CTRL_REFCLK_SEL_MASK 0x0000000C
    #define CG_PLL5_CTRL_REFCLK_SEL_SHIFT 2
    #define CG_PLL5_CTRL_FILTER_IBIAS_IDN_MASK 0x00000010
    #define CG_PLL5_CTRL_FILTER_IBIAS_IDN_SHIFT 4
    #define CG_PLL5_CTRL_FILTER_IBIAS_IUP_MASK 0x00000020
    #define CG_PLL5_CTRL_FILTER_IBIAS_IUP_SHIFT 5
    #define CG_PLL5_CTRL_FILTER_PCASC_IDN_MASK 0x00000040
    #define CG_PLL5_CTRL_FILTER_PCASC_IDN_SHIFT 6
    #define CG_PLL5_CTRL_FILTER_PCASC_IUP_MASK 0x00000080
    #define CG_PLL5_CTRL_FILTER_PCASC_IUP_SHIFT 7
    #define CG_PLL5_CTRL_FILTER_NCASC_IDN_MASK 0x00000100
    #define CG_PLL5_CTRL_FILTER_NCASC_IDN_SHIFT 8
    #define CG_PLL5_CTRL_FILTER_NCASC_IUP_MASK 0x00000200
    #define CG_PLL5_CTRL_FILTER_NCASC_IUP_SHIFT 9
    #define CG_PLL5_CTRL_LFSR_ENABLE_MASK 0x00000800
    #define CG_PLL5_CTRL_LFSR_ENABLE_SHIFT 11
    #define CG_PLL5_CTRL_ICPHALF_MASK 0x00001000
    #define CG_PLL5_CTRL_ICPHALF_SHIFT 12
    #define CG_PLL5_CTRL_ICP2X_MASK 0x00002000
    #define CG_PLL5_CTRL_ICP2X_SHIFT 13
    #define CG_PLL5_CTRL_SELFBIAS_MASK 0x00008000
    #define CG_PLL5_CTRL_SELFBIAS_SHIFT 15
    #define CG_PLL5_CTRL_VAG_OA_IBIAS_IDN_MASK 0x00010000
    #define CG_PLL5_CTRL_VAG_OA_IBIAS_IDN_SHIFT 16
    #define CG_PLL5_CTRL_VAG_OA_IBIAS_IUP_MASK 0x00020000
    #define CG_PLL5_CTRL_VAG_OA_IBIAS_IUP_SHIFT 17
    #define CG_PLL5_CTRL_VAG_OA_PCASC_IDN_MASK 0x00040000
    #define CG_PLL5_CTRL_VAG_OA_PCASC_IDN_SHIFT 18
    #define CG_PLL5_CTRL_VAG_OA_PCASC_IUP_MASK 0x00080000
    #define CG_PLL5_CTRL_VAG_OA_PCASC_IUP_SHIFT 19
    #define CG_PLL5_CTRL_VAG_OA_NCASC_IDN_MASK 0x00100000
    #define CG_PLL5_CTRL_VAG_OA_NCASC_IDN_SHIFT 20
    #define CG_PLL5_CTRL_VAG_OA_NCASC_IUP_MASK 0x00200000
    #define CG_PLL5_CTRL_VAG_OA_NCASC_IUP_SHIFT 21
    #define CG_PLL5_CTRL_PFD_SEL_MASK 0x01000000
    #define CG_PLL5_CTRL_PFD_SEL_SHIFT 24
    #define CG_PLL5_CTRL_FRAC_ENABLE_MASK 0x02000000
    #define CG_PLL5_CTRL_FRAC_ENABLE_SHIFT 25
    #define CG_PLL5_CTRL_CONT_LOCK_MON_MASK 0x04000000
    #define CG_PLL5_CTRL_CONT_LOCK_MON_SHIFT 26
    #define CG_PLL5_CTRL_TSTSEL_MASK 0x70000000
    #define CG_PLL5_CTRL_TSTSEL_SHIFT 28
#define  CG_PLL5_FREQ 0x0250
    #define CG_PLL5_FREQ_FB_DIV_FRAC_MASK 0x000FFFFF
    #define CG_PLL5_FREQ_FB_DIV_FRAC_SHIFT 0
    #define CG_PLL5_FREQ_FB_DIV_INT_MASK 0x00F00000
    #define CG_PLL5_FREQ_FB_DIV_INT_SHIFT 20
    #define CG_PLL5_FREQ_PRE_DIV_MASK 0x01000000
    #define CG_PLL5_FREQ_PRE_DIV_SHIFT 24
#define  CG_PLL6_CTRL 0x0268
    #define CG_PLL6_CTRL_ENABLE_MASK 0x00000001
    #define CG_PLL6_CTRL_ENABLE_SHIFT 0
    #define CG_PLL6_CTRL_LOOP_INIT_MASK 0x00000002
    #define CG_PLL6_CTRL_LOOP_INIT_SHIFT 1
    #define CG_PLL6_CTRL_REFCLK_SEL_MASK 0x0000000C
    #define CG_PLL6_CTRL_REFCLK_SEL_SHIFT 2
    #define CG_PLL6_CTRL_FILTER_IBIAS_IDN_MASK 0x00000010
    #define CG_PLL6_CTRL_FILTER_IBIAS_IDN_SHIFT 4
    #define CG_PLL6_CTRL_FILTER_IBIAS_IUP_MASK 0x00000020
    #define CG_PLL6_CTRL_FILTER_IBIAS_IUP_SHIFT 5
    #define CG_PLL6_CTRL_FILTER_PCASC_IDN_MASK 0x00000040
    #define CG_PLL6_CTRL_FILTER_PCASC_IDN_SHIFT 6
    #define CG_PLL6_CTRL_FILTER_PCASC_IUP_MASK 0x00000080
    #define CG_PLL6_CTRL_FILTER_PCASC_IUP_SHIFT 7
    #define CG_PLL6_CTRL_FILTER_NCASC_IDN_MASK 0x00000100
    #define CG_PLL6_CTRL_FILTER_NCASC_IDN_SHIFT 8
    #define CG_PLL6_CTRL_FILTER_NCASC_IUP_MASK 0x00000200
    #define CG_PLL6_CTRL_FILTER_NCASC_IUP_SHIFT 9
    #define CG_PLL6_CTRL_LFSR_ENABLE_MASK 0x00000800
    #define CG_PLL6_CTRL_LFSR_ENABLE_SHIFT 11
    #define CG_PLL6_CTRL_ICPHALF_MASK 0x00001000
    #define CG_PLL6_CTRL_ICPHALF_SHIFT 12
    #define CG_PLL6_CTRL_ICP2X_MASK 0x00002000
    #define CG_PLL6_CTRL_ICP2X_SHIFT 13
    #define CG_PLL6_CTRL_SELFBIAS_MASK 0x00008000
    #define CG_PLL6_CTRL_SELFBIAS_SHIFT 15
    #define CG_PLL6_CTRL_VAG_OA_IBIAS_IDN_MASK 0x00010000
    #define CG_PLL6_CTRL_VAG_OA_IBIAS_IDN_SHIFT 16
    #define CG_PLL6_CTRL_VAG_OA_IBIAS_IUP_MASK 0x00020000
    #define CG_PLL6_CTRL_VAG_OA_IBIAS_IUP_SHIFT 17
    #define CG_PLL6_CTRL_VAG_OA_PCASC_IDN_MASK 0x00040000
    #define CG_PLL6_CTRL_VAG_OA_PCASC_IDN_SHIFT 18
    #define CG_PLL6_CTRL_VAG_OA_PCASC_IUP_MASK 0x00080000
    #define CG_PLL6_CTRL_VAG_OA_PCASC_IUP_SHIFT 19
    #define CG_PLL6_CTRL_VAG_OA_NCASC_IDN_MASK 0x00100000
    #define CG_PLL6_CTRL_VAG_OA_NCASC_IDN_SHIFT 20
    #define CG_PLL6_CTRL_VAG_OA_NCASC_IUP_MASK 0x00200000
    #define CG_PLL6_CTRL_VAG_OA_NCASC_IUP_SHIFT 21
    #define CG_PLL6_CTRL_PFD_SEL_MASK 0x01000000
    #define CG_PLL6_CTRL_PFD_SEL_SHIFT 24
    #define CG_PLL6_CTRL_FRAC_ENABLE_MASK 0x02000000
    #define CG_PLL6_CTRL_FRAC_ENABLE_SHIFT 25
    #define CG_PLL6_CTRL_CONT_LOCK_MON_MASK 0x04000000
    #define CG_PLL6_CTRL_CONT_LOCK_MON_SHIFT 26
    #define CG_PLL6_CTRL_TSTSEL_MASK 0x70000000
    #define CG_PLL6_CTRL_TSTSEL_SHIFT 28
#define  CG_PLL6_FREQ 0x0260
    #define CG_PLL6_FREQ_FB_DIV_FRAC_MASK 0x000FFFFF
    #define CG_PLL6_FREQ_FB_DIV_FRAC_SHIFT 0
    #define CG_PLL6_FREQ_FB_DIV_INT_MASK 0x00F00000
    #define CG_PLL6_FREQ_FB_DIV_INT_SHIFT 20
    #define CG_PLL6_FREQ_PRE_DIV_MASK 0x01000000
    #define CG_PLL6_FREQ_PRE_DIV_SHIFT 24
#define  CG_PLL7_CTRL 0x0278
    #define CG_PLL7_CTRL_ENABLE_MASK 0x00000001
    #define CG_PLL7_CTRL_ENABLE_SHIFT 0
    #define CG_PLL7_CTRL_LOOP_INIT_MASK 0x00000002
    #define CG_PLL7_CTRL_LOOP_INIT_SHIFT 1
    #define CG_PLL7_CTRL_REFCLK_SEL_MASK 0x0000000C
    #define CG_PLL7_CTRL_REFCLK_SEL_SHIFT 2
    #define CG_PLL7_CTRL_FILTER_IBIAS_IDN_MASK 0x00000010
    #define CG_PLL7_CTRL_FILTER_IBIAS_IDN_SHIFT 4
    #define CG_PLL7_CTRL_FILTER_IBIAS_IUP_MASK 0x00000020
    #define CG_PLL7_CTRL_FILTER_IBIAS_IUP_SHIFT 5
    #define CG_PLL7_CTRL_FILTER_PCASC_IDN_MASK 0x00000040
    #define CG_PLL7_CTRL_FILTER_PCASC_IDN_SHIFT 6
    #define CG_PLL7_CTRL_FILTER_PCASC_IUP_MASK 0x00000080
    #define CG_PLL7_CTRL_FILTER_PCASC_IUP_SHIFT 7
    #define CG_PLL7_CTRL_FILTER_NCASC_IDN_MASK 0x00000100
    #define CG_PLL7_CTRL_FILTER_NCASC_IDN_SHIFT 8
    #define CG_PLL7_CTRL_FILTER_NCASC_IUP_MASK 0x00000200
    #define CG_PLL7_CTRL_FILTER_NCASC_IUP_SHIFT 9
    #define CG_PLL7_CTRL_LFSR_ENABLE_MASK 0x00000800
    #define CG_PLL7_CTRL_LFSR_ENABLE_SHIFT 11
    #define CG_PLL7_CTRL_ICPHALF_MASK 0x00001000
    #define CG_PLL7_CTRL_ICPHALF_SHIFT 12
    #define CG_PLL7_CTRL_ICP2X_MASK 0x00002000
    #define CG_PLL7_CTRL_ICP2X_SHIFT 13
    #define CG_PLL7_CTRL_SELFBIAS_MASK 0x00008000
    #define CG_PLL7_CTRL_SELFBIAS_SHIFT 15
    #define CG_PLL7_CTRL_VAG_OA_IBIAS_IDN_MASK 0x00010000
    #define CG_PLL7_CTRL_VAG_OA_IBIAS_IDN_SHIFT 16
    #define CG_PLL7_CTRL_VAG_OA_IBIAS_IUP_MASK 0x00020000
    #define CG_PLL7_CTRL_VAG_OA_IBIAS_IUP_SHIFT 17
    #define CG_PLL7_CTRL_VAG_OA_PCASC_IDN_MASK 0x00040000
    #define CG_PLL7_CTRL_VAG_OA_PCASC_IDN_SHIFT 18
    #define CG_PLL7_CTRL_VAG_OA_PCASC_IUP_MASK 0x00080000
    #define CG_PLL7_CTRL_VAG_OA_PCASC_IUP_SHIFT 19
    #define CG_PLL7_CTRL_VAG_OA_NCASC_IDN_MASK 0x00100000
    #define CG_PLL7_CTRL_VAG_OA_NCASC_IDN_SHIFT 20
    #define CG_PLL7_CTRL_VAG_OA_NCASC_IUP_MASK 0x00200000
    #define CG_PLL7_CTRL_VAG_OA_NCASC_IUP_SHIFT 21
    #define CG_PLL7_CTRL_PFD_SEL_MASK 0x01000000
    #define CG_PLL7_CTRL_PFD_SEL_SHIFT 24
    #define CG_PLL7_CTRL_FRAC_ENABLE_MASK 0x02000000
    #define CG_PLL7_CTRL_FRAC_ENABLE_SHIFT 25
    #define CG_PLL7_CTRL_CONT_LOCK_MON_MASK 0x04000000
    #define CG_PLL7_CTRL_CONT_LOCK_MON_SHIFT 26
    #define CG_PLL7_CTRL_TSTSEL_MASK 0x70000000
    #define CG_PLL7_CTRL_TSTSEL_SHIFT 28
#define  CG_PLL7_FREQ 0x0270
    #define CG_PLL7_FREQ_FB_DIV_FRAC_MASK 0x000FFFFF
    #define CG_PLL7_FREQ_FB_DIV_FRAC_SHIFT 0
    #define CG_PLL7_FREQ_FB_DIV_INT_MASK 0x00F00000
    #define CG_PLL7_FREQ_FB_DIV_INT_SHIFT 20
    #define CG_PLL7_FREQ_PRE_DIV_MASK 0x01000000
    #define CG_PLL7_FREQ_PRE_DIV_SHIFT 24
#define  CG_PLL_MISC_CTRL0 0x01E8
    #define CG_PLL_MISC_CTRL0_RESET_MASK 0x00000001
    #define CG_PLL_MISC_CTRL0_RESET_SHIFT 0
    #define BG_PD_MASK 0x00000002
    #define BG_PD_SHIFT 1
    #define REG_ENABLE_MASK 0x00000004
    #define REG_ENABLE_SHIFT 2
    #define BGCORE_NBIAS_IDN_MASK 0x00000010
    #define BGCORE_NBIAS_IDN_SHIFT 4
    #define BGCORE_NBIAS_IUP_MASK 0x00000020
    #define BGCORE_NBIAS_IUP_SHIFT 5
    #define BGCORE_PCASC_IDN_MASK 0x00000040
    #define BGCORE_PCASC_IDN_SHIFT 6
    #define BGCORE_PCASC_IUP_MASK 0x00000080
    #define BGCORE_PCASC_IUP_SHIFT 7
    #define BGRG_NBIAS_IDN_MASK 0x00000100
    #define BGRG_NBIAS_IDN_SHIFT 8
    #define BGRG_NBIAS_IUP_MASK 0x00000200
    #define BGRG_NBIAS_IUP_SHIFT 9
    #define BGRG_PCASC_IDN_MASK 0x00000400
    #define BGRG_PCASC_IDN_SHIFT 10
    #define BGRG_PCASC_IUP_MASK 0x00000800
    #define BGRG_PCASC_IUP_SHIFT 11
    #define CHIP_RES_MASK 0x00001000
    #define CHIP_RES_SHIFT 12
    #define VTREF_PD_MASK 0x00002000
    #define VTREF_PD_SHIFT 13
    #define VTREF_PWL_PD_MASK 0x00004000
    #define VTREF_PWL_PD_SHIFT 14
    #define REG_IBIAS_IDN_MASK 0x00010000
    #define REG_IBIAS_IDN_SHIFT 16
    #define REG_IBIAS_IUP_MASK 0x00020000
    #define REG_IBIAS_IUP_SHIFT 17
    #define REG_PCASC_IDN_MASK 0x00040000
    #define REG_PCASC_IDN_SHIFT 18
    #define REG_PCASC_IUP_MASK 0x00080000
    #define REG_PCASC_IUP_SHIFT 19
    #define CG_PLL_MISC_CTRL0_TSTSEL_MASK 0xFF000000
    #define CG_PLL_MISC_CTRL0_TSTSEL_SHIFT 24
#define  CG_PLL_STATUS0 0x01E0
    #define PLL0_LOCK_MASK 0x00000001
    #define PLL0_LOCK_SHIFT 0
    #define PLL1_LOCK_MASK 0x00000002
    #define PLL1_LOCK_SHIFT 1
    #define PLL2_LOCK_MASK 0x00000004
    #define PLL2_LOCK_SHIFT 2
    #define PLL3_LOCK_MASK 0x00000008
    #define PLL3_LOCK_SHIFT 3
    #define PLL4_LOCK_MASK 0x00000010
    #define PLL4_LOCK_SHIFT 4
    #define PLL5_LOCK_MASK 0x00000020
    #define PLL5_LOCK_SHIFT 5
    #define PLL6_LOCK_MASK 0x00000040
    #define PLL6_LOCK_SHIFT 6
    #define PLL7_LOCK_MASK 0x00000080
    #define PLL7_LOCK_SHIFT 7
#define  CG_PWM_CTRL 0x02C4
    #define PWMCLK_SRC_SEL_MASK 0x00F00000
    #define PWMCLK_SRC_SEL_SHIFT 20
    #define PWM_RST_MASK 0x01000000
    #define PWM_RST_SHIFT 24
#define  CG_PWM_DC 0x02C0
    #define PWM_PULSE_LO_CNT_MASK 0x00000FFF
    #define PWM_PULSE_LO_CNT_SHIFT 0
    #define PWM_PULSE_HI_CNT_MASK 0x0FFF0000
    #define PWM_PULSE_HI_CNT_SHIFT 16
#define  CG_REG_GATE_CTRL 0x0008
    #define VFE_VCLK_GATE_MASK 0x80000000
    #define VFE_VCLK_GATE_SHIFT 31
#define  CG_RESET_REG 0x0000
    #define DMA_RESET_MASK 0x00000002
    #define DMA_RESET_SHIFT 1
    #define TSD_RESET_MASK 0x00000004
    #define TSD_RESET_SHIFT 2
    #define DVE_RESET_MASK 0x00000008
    #define DVE_RESET_SHIFT 3
    #define MC_RESET_MASK 0x00000010
    #define MC_RESET_SHIFT 4
    #define SATA_RESET_MASK 0x00000080
    #define SATA_RESET_SHIFT 7
    #define PPC_RESET_MASK 0x00000200
    #define PPC_RESET_SHIFT 9
    #define RSA_RESET_MASK 0x00000400
    #define RSA_RESET_SHIFT 10
    #define MPP_RESET_MASK 0x00001000
    #define MPP_RESET_SHIFT 12
    #define I2S_RESET_MASK 0x00002000
    #define I2S_RESET_SHIFT 13
    #define VHE_RESET_MASK 0x00004000
    #define VHE_RESET_SHIFT 14
    #define VFE_RESET_MASK 0x00008000
    #define VFE_RESET_SHIFT 15
    #define VNE_RESET_MASK 0x00010000
    #define VNE_RESET_SHIFT 16
    #define GVP_RESET_MASK 0x00020000
    #define GVP_RESET_SHIFT 17
    #define PROC0_RESET_MASK 0x00040000
    #define PROC0_RESET_SHIFT 18
    #define PROC1_RESET_MASK 0x00080000
    #define PROC1_RESET_SHIFT 19
    #define PROC2_RESET_MASK 0x00100000
    #define PROC2_RESET_SHIFT 20
    #define PROC3_RESET_MASK 0x00200000
    #define PROC3_RESET_SHIFT 21
    #define PROC4_RESET_MASK 0x00400000
    #define PROC4_RESET_SHIFT 22
    #define USBH_RESET_MASK 0x00800000
    #define USBH_RESET_SHIFT 23
    #define ETH0_RESET_MASK 0x01000000
    #define ETH0_RESET_SHIFT 24
    #define ETH1_RESET_MASK 0x02000000
    #define ETH1_RESET_SHIFT 25
    #define USBD_RESET_MASK 0x04000000
    #define USBD_RESET_SHIFT 26
    #define GVD_RESET_MASK 0x08000000
    #define GVD_RESET_SHIFT 27
    #define DSCL_RESET_MASK 0x10000000
    #define DSCL_RESET_SHIFT 28
    #define SPDIF_TX_RESET_MASK 0x20000000
    #define SPDIF_TX_RESET_SHIFT 29
    #define SPDIF_RX_RESET_MASK 0x40000000
    #define SPDIF_RX_RESET_SHIFT 30
    #define I2S_TX_RESET_MASK 0x80000000
    #define I2S_TX_RESET_SHIFT 31
#define  CG_SPDIFTX0CLK_FREQ 0x0190
    #define SPDIFTX0CLK_DIV_MASK 0x000003FE
    #define SPDIFTX0CLK_DIV_SHIFT 1
    #define SPDIFTX0CLK_DIV_SEL_MASK 0x000F0000
    #define SPDIFTX0CLK_DIV_SEL_SHIFT 16
    #define SPDIFTX0CLK_DIV_RST_MASK 0x01000000
    #define SPDIFTX0CLK_DIV_RST_SHIFT 24
#define  CG_SYSTEM_CNT 0x00F8
    #define SYSTEM_CNT_MASK 0xFFFFFFFF
    #define SYSTEM_CNT_SHIFT 0
#define  CG_TIMESTAMP_CTRL 0x0080
    #define CG_TIMESTAMP_CTRL_VHE0_CLR_CNT_MASK 0x00000001
    #define CG_TIMESTAMP_CTRL_VHE0_CLR_CNT_SHIFT 0
    #define CG_TIMESTAMP_CTRL_VHE1_CLR_CNT_MASK 0x00000002
    #define CG_TIMESTAMP_CTRL_VHE1_CLR_CNT_SHIFT 1
    #define CG_TIMESTAMP_CTRL_I2S0_CLR_CNT_MASK 0x00000004
    #define CG_TIMESTAMP_CTRL_I2S0_CLR_CNT_SHIFT 2
    #define CG_TIMESTAMP_CTRL_I2S1_CLR_CNT_MASK 0x00000008
    #define CG_TIMESTAMP_CTRL_I2S1_CLR_CNT_SHIFT 3
    #define CG_TIMESTAMP_CTRL_SPDIF_RX_CLR_CNT_MASK 0x00000010
    #define CG_TIMESTAMP_CTRL_SPDIF_RX_CLR_CNT_SHIFT 4
    #define CG_TIMESTAMP_CTRL_VHE0_EN_CNT_MASK 0x00000100
    #define CG_TIMESTAMP_CTRL_VHE0_EN_CNT_SHIFT 8
    #define CG_TIMESTAMP_CTRL_VHE1_EN_CNT_MASK 0x00000200
    #define CG_TIMESTAMP_CTRL_VHE1_EN_CNT_SHIFT 9
    #define CG_TIMESTAMP_CTRL_I2S0_EN_CNT_MASK 0x00000400
    #define CG_TIMESTAMP_CTRL_I2S0_EN_CNT_SHIFT 10
    #define CG_TIMESTAMP_CTRL_I2S1_EN_CNT_MASK 0x00000800
    #define CG_TIMESTAMP_CTRL_I2S1_EN_CNT_SHIFT 11
    #define CG_TIMESTAMP_CTRL_SPDIF_RX_EN_CNT_MASK 0x00001000
    #define CG_TIMESTAMP_CTRL_SPDIF_RX_EN_CNT_SHIFT 12
#define  DEBUG_BUS_CTRL 0x0438
    #define BUS_SEL_MASK 0x0000003F
    #define BUS_SEL_SHIFT 0
    #define MUX_SEL_MASK 0x00007F00
    #define MUX_SEL_SHIFT 8
    #define DC_SEL_MASK 0x00070000
    #define DC_SEL_SHIFT 16
    #define BUS_OUT_EN_MASK 0x02000000
    #define BUS_OUT_EN_SHIFT 25
#define  DEBUG_BUS_WATCH 0x10F8
    #define DEBUG_BUS_WATCH_MASK 0xFFFFFFFF
    #define DEBUG_BUS_WATCH_SHIFT 0
#define  DEC0_DIP_ADR 0xA120
    #define DEC0_DIP_ADR_BASE_MASK 0x07FFFFFC
    #define DEC0_DIP_ADR_BASE_SHIFT 2
#define  DEC0_DIP_LIMIT 0xA094
    #define DEC0_DIP_LIMIT_BASE_MASK 0x07FFFFFC
    #define DEC0_DIP_LIMIT_BASE_SHIFT 2
    #define DEC0_DIP_LIMIT_LIMIT_EN_MASK 0x80000000
    #define DEC0_DIP_LIMIT_LIMIT_EN_SHIFT 31
#define  DEC1_DIP_ADR 0xA520
    #define DEC1_DIP_ADR_BASE_MASK 0x07FFFFFC
    #define DEC1_DIP_ADR_BASE_SHIFT 2
#define  DEC1_DIP_LIMIT 0xA494
    #define DEC1_DIP_LIMIT_BASE_MASK 0x07FFFFFC
    #define DEC1_DIP_LIMIT_BASE_SHIFT 2
    #define DEC1_DIP_LIMIT_LIMIT_EN_MASK 0x80000000
    #define DEC1_DIP_LIMIT_LIMIT_EN_SHIFT 31
#define  DEC_ARB_CTRL 0x74AC
    #define DIP_TIMER_MASK 0x0000000F
    #define DIP_TIMER_SHIFT 0
    #define MSCMVF_TIMER_MASK 0x000000F0
    #define MSCMVF_TIMER_SHIFT 4
    #define MSCREF_TIMER_MASK 0x00000F00
    #define MSCREF_TIMER_SHIFT 8
    #define SCLR_TIMER_MASK 0x0000F000
    #define SCLR_TIMER_SHIFT 12
    #define MSCRFM_TIMER_MASK 0x000F0000
    #define MSCRFM_TIMER_SHIFT 16
    #define SCLW_TIMER_MASK 0x00F00000
    #define SCLW_TIMER_SHIFT 20
    #define SCLW_BOT_TIMER_MASK 0x0F000000
    #define SCLW_BOT_TIMER_SHIFT 24
#define  DEC_BWD_C_ADR 0x7380
    #define DEC_BWD_C_ADR_BASE_MASK 0x0FFFE000
    #define DEC_BWD_C_ADR_BASE_SHIFT 13
#define  DEC_BWD_Y_ADR 0x737C
    #define DEC_BWD_Y_ADR_BASE_MASK 0x0FFFE000
    #define DEC_BWD_Y_ADR_BASE_SHIFT 13
#define  DEC_CTRL 0x735C
    #define DEC_CTRL_MISMATCH_MASK 0x00000003
    #define DEC_CTRL_MISMATCH_SHIFT 0
    #define DEC_CTRL_SCAN_ORDER_MASK 0x0000000C
    #define DEC_CTRL_SCAN_ORDER_SHIFT 2
    #define DEC_CTRL_DC_SCALE_MASK 0x00000030
    #define DEC_CTRL_DC_SCALE_SHIFT 4
    #define DEC_CTRL_QSCALE_METHOD_MASK 0x00000040
    #define DEC_CTRL_QSCALE_METHOD_SHIFT 6
    #define DEC_CTRL_SATURATE_MASK 0x00000F00
    #define DEC_CTRL_SATURATE_SHIFT 8
#define  DEC_FWD_C_ADR 0x7378
    #define DEC_FWD_C_ADR_BASE_MASK 0x0FFFE000
    #define DEC_FWD_C_ADR_BASE_SHIFT 13
#define  DEC_FWD_Y_ADR 0x7374
    #define DEC_FWD_Y_ADR_BASE_MASK 0x0FFFE000
    #define DEC_FWD_Y_ADR_BASE_SHIFT 13
#define  DEC_MVA_ADR 0x7384
    #define DEC_MVA_ADR_BASE_MASK 0x0FFFFC00
    #define DEC_MVA_ADR_BASE_SHIFT 10
#define  DEC_PICT_INFO 0x7350
    #define DEC_PICT_INFO_PICT_TYPE_MASK 0x00000003
    #define DEC_PICT_INFO_PICT_TYPE_SHIFT 0
    #define DEC_PICT_INFO_PICT_STRUCT_MASK 0x0000000C
    #define DEC_PICT_INFO_PICT_STRUCT_SHIFT 2
    #define DEC_PICT_INFO_MPEG_FRMT_MASK 0x00000030
    #define DEC_PICT_INFO_MPEG_FRMT_SHIFT 4
    #define DEC_PICT_INFO_SECOND_FLD_MASK 0x80000000
    #define DEC_PICT_INFO_SECOND_FLD_SHIFT 31
#define  DEC_PICT_SIZE 0x7354
    #define DEC_PICT_SIZE_SLICE_SIZE_MASK 0x0000007F
    #define DEC_PICT_SIZE_SLICE_SIZE_SHIFT 0
    #define DEC_PICT_SIZE_SLICE_CNT_MASK 0x00007F00
    #define DEC_PICT_SIZE_SLICE_CNT_SHIFT 8
#define  DEC_QMATRIX_0_3_INTRA 0x7100
    #define DEC_QM0_INT_MASK 0x000000FF
    #define DEC_QM0_INT_SHIFT 0
    #define DEC_QM1_INT_MASK 0x0000FF00
    #define DEC_QM1_INT_SHIFT 8
    #define DEC_QM2_INT_MASK 0x00FF0000
    #define DEC_QM2_INT_SHIFT 16
    #define DEC_QM3_INT_MASK 0xFF000000
    #define DEC_QM3_INT_SHIFT 24
#define  DEC_QMATRIX_0_3_NONINT 0x7140
    #define DEC_QM0_NONINT_MASK 0x000000FF
    #define DEC_QM0_NONINT_SHIFT 0
    #define DEC_QM1_NONINT_MASK 0x0000FF00
    #define DEC_QM1_NONINT_SHIFT 8
    #define DEC_QM2_NONINT_MASK 0x00FF0000
    #define DEC_QM2_NONINT_SHIFT 16
    #define DEC_QM3_NONINT_MASK 0xFF000000
    #define DEC_QM3_NONINT_SHIFT 24
#define  DEC_QMATRIX_12_15_INTRA 0x710C
    #define DEC_QM12_INT_MASK 0x000000FF
    #define DEC_QM12_INT_SHIFT 0
    #define DEC_QM13_INT_MASK 0x0000FF00
    #define DEC_QM13_INT_SHIFT 8
    #define DEC_QM14_INT_MASK 0x00FF0000
    #define DEC_QM14_INT_SHIFT 16
    #define DEC_QM15_INT_MASK 0xFF000000
    #define DEC_QM15_INT_SHIFT 24
#define  DEC_QMATRIX_12_15_NONINT 0x714C
    #define DEC_QM12_NONINT_MASK 0x000000FF
    #define DEC_QM12_NONINT_SHIFT 0
    #define DEC_QM13_NONINT_MASK 0x0000FF00
    #define DEC_QM13_NONINT_SHIFT 8
    #define DEC_QM14_NONINT_MASK 0x00FF0000
    #define DEC_QM14_NONINT_SHIFT 16
    #define DEC_QM15_NONINT_MASK 0xFF000000
    #define DEC_QM15_NONINT_SHIFT 24
#define  DEC_QMATRIX_16_19_INTRA 0x7110
    #define DEC_QM16_INT_MASK 0x000000FF
    #define DEC_QM16_INT_SHIFT 0
    #define DEC_QM17_INT_MASK 0x0000FF00
    #define DEC_QM17_INT_SHIFT 8
    #define DEC_QM18_INT_MASK 0x00FF0000
    #define DEC_QM18_INT_SHIFT 16
    #define DEC_QM19_INT_MASK 0xFF000000
    #define DEC_QM19_INT_SHIFT 24
#define  DEC_QMATRIX_16_19_NONINT 0x7150
    #define DEC_QM16_NONINT_MASK 0x000000FF
    #define DEC_QM16_NONINT_SHIFT 0
    #define DEC_QM17_NONINT_MASK 0x0000FF00
    #define DEC_QM17_NONINT_SHIFT 8
    #define DEC_QM18_NONINT_MASK 0x00FF0000
    #define DEC_QM18_NONINT_SHIFT 16
    #define DEC_QM19_NONINT_MASK 0xFF000000
    #define DEC_QM19_NONINT_SHIFT 24
#define  DEC_QMATRIX_20_23_INTRA 0x7114
    #define DEC_QM20_INT_MASK 0x000000FF
    #define DEC_QM20_INT_SHIFT 0
    #define DEC_QM21_INT_MASK 0x0000FF00
    #define DEC_QM21_INT_SHIFT 8
    #define DEC_QM22_INT_MASK 0x00FF0000
    #define DEC_QM22_INT_SHIFT 16
    #define DEC_QM23_INT_MASK 0xFF000000
    #define DEC_QM23_INT_SHIFT 24
#define  DEC_QMATRIX_20_23_NONINT 0x7154
    #define DEC_QM20_NONINT_MASK 0x000000FF
    #define DEC_QM20_NONINT_SHIFT 0
    #define DEC_QM21_NONINT_MASK 0x0000FF00
    #define DEC_QM21_NONINT_SHIFT 8
    #define DEC_QM22_NONINT_MASK 0x00FF0000
    #define DEC_QM22_NONINT_SHIFT 16
    #define DEC_QM23_NONINT_MASK 0xFF000000
    #define DEC_QM23_NONINT_SHIFT 24
#define  DEC_QMATRIX_24_27_INTRA 0x7118
    #define DEC_QM24_INT_MASK 0x000000FF
    #define DEC_QM24_INT_SHIFT 0
    #define DEC_QM25_INT_MASK 0x0000FF00
    #define DEC_QM25_INT_SHIFT 8
    #define DEC_QM26_INT_MASK 0x00FF0000
    #define DEC_QM26_INT_SHIFT 16
    #define DEC_QM27_INT_MASK 0xFF000000
    #define DEC_QM27_INT_SHIFT 24
#define  DEC_QMATRIX_24_27_NONINT 0x7158
    #define DEC_QM24_NONINT_MASK 0x000000FF
    #define DEC_QM24_NONINT_SHIFT 0
    #define DEC_QM25_NONINT_MASK 0x0000FF00
    #define DEC_QM25_NONINT_SHIFT 8
    #define DEC_QM26_NONINT_MASK 0x00FF0000
    #define DEC_QM26_NONINT_SHIFT 16
    #define DEC_QM27_NONINT_MASK 0xFF000000
    #define DEC_QM27_NONINT_SHIFT 24
#define  DEC_QMATRIX_28_31_INTRA 0x711C
    #define DEC_QM28_INT_MASK 0x000000FF
    #define DEC_QM28_INT_SHIFT 0
    #define DEC_QM29_INT_MASK 0x0000FF00
    #define DEC_QM29_INT_SHIFT 8
    #define DEC_QM30_INT_MASK 0x00FF0000
    #define DEC_QM30_INT_SHIFT 16
    #define DEC_QM31_INT_MASK 0xFF000000
    #define DEC_QM31_INT_SHIFT 24
#define  DEC_QMATRIX_28_31_NONINT 0x715C
    #define DEC_QM28_NONINT_MASK 0x000000FF
    #define DEC_QM28_NONINT_SHIFT 0
    #define DEC_QM29_NONINT_MASK 0x0000FF00
    #define DEC_QM29_NONINT_SHIFT 8
    #define DEC_QM30_NONINT_MASK 0x00FF0000
    #define DEC_QM30_NONINT_SHIFT 16
    #define DEC_QM31_NONINT_MASK 0xFF000000
    #define DEC_QM31_NONINT_SHIFT 24
#define  DEC_QMATRIX_32_35_INTRA 0x7120
    #define DEC_QM32_INT_MASK 0x000000FF
    #define DEC_QM32_INT_SHIFT 0
    #define DEC_QM33_INT_MASK 0x0000FF00
    #define DEC_QM33_INT_SHIFT 8
    #define DEC_QM34_INT_MASK 0x00FF0000
    #define DEC_QM34_INT_SHIFT 16
    #define DEC_QM35_INT_MASK 0xFF000000
    #define DEC_QM35_INT_SHIFT 24
#define  DEC_QMATRIX_32_35_NONINT 0x7160
    #define DEC_QM32_NONINT_MASK 0x000000FF
    #define DEC_QM32_NONINT_SHIFT 0
    #define DEC_QM33_NONINT_MASK 0x0000FF00
    #define DEC_QM33_NONINT_SHIFT 8
    #define DEC_QM34_NONINT_MASK 0x00FF0000
    #define DEC_QM34_NONINT_SHIFT 16
    #define DEC_QM35_NONINT_MASK 0xFF000000
    #define DEC_QM35_NONINT_SHIFT 24
#define  DEC_QMATRIX_36_39_INTRA 0x7124
    #define DEC_QM36_INT_MASK 0x000000FF
    #define DEC_QM36_INT_SHIFT 0
    #define DEC_QM37_INT_MASK 0x0000FF00
    #define DEC_QM37_INT_SHIFT 8
    #define DEC_QM38_INT_MASK 0x00FF0000
    #define DEC_QM38_INT_SHIFT 16
    #define DEC_QM39_INT_MASK 0xFF000000
    #define DEC_QM39_INT_SHIFT 24
#define  DEC_QMATRIX_36_39_NONINT 0x7164
    #define DEC_QM36_NONINT_MASK 0x000000FF
    #define DEC_QM36_NONINT_SHIFT 0
    #define DEC_QM37_NONINT_MASK 0x0000FF00
    #define DEC_QM37_NONINT_SHIFT 8
    #define DEC_QM38_NONINT_MASK 0x00FF0000
    #define DEC_QM38_NONINT_SHIFT 16
    #define DEC_QM39_NONINT_MASK 0xFF000000
    #define DEC_QM39_NONINT_SHIFT 24
#define  DEC_QMATRIX_40_43_INTRA 0x7128
    #define DEC_QM40_INT_MASK 0x000000FF
    #define DEC_QM40_INT_SHIFT 0
    #define DEC_QM41_INT_MASK 0x0000FF00
    #define DEC_QM41_INT_SHIFT 8
    #define DEC_QM42_INT_MASK 0x00FF0000
    #define DEC_QM42_INT_SHIFT 16
    #define DEC_QM43_INT_MASK 0xFF000000
    #define DEC_QM43_INT_SHIFT 24
#define  DEC_QMATRIX_40_43_NONINT 0x7168
    #define DEC_QM40_NONINT_MASK 0x000000FF
    #define DEC_QM40_NONINT_SHIFT 0
    #define DEC_QM41_NONINT_MASK 0x0000FF00
    #define DEC_QM41_NONINT_SHIFT 8
    #define DEC_QM42_NONINT_MASK 0x00FF0000
    #define DEC_QM42_NONINT_SHIFT 16
    #define DEC_QM43_NONINT_MASK 0xFF000000
    #define DEC_QM43_NONINT_SHIFT 24
#define  DEC_QMATRIX_44_47_INTRA 0x712C
    #define DEC_QM44_INT_MASK 0x000000FF
    #define DEC_QM44_INT_SHIFT 0
    #define DEC_QM45_INT_MASK 0x0000FF00
    #define DEC_QM45_INT_SHIFT 8
    #define DEC_QM46_INT_MASK 0x00FF0000
    #define DEC_QM46_INT_SHIFT 16
    #define DEC_QM47_INT_MASK 0xFF000000
    #define DEC_QM47_INT_SHIFT 24
#define  DEC_QMATRIX_44_47_NONINT 0x716C
    #define DEC_QM44_NONINT_MASK 0x000000FF
    #define DEC_QM44_NONINT_SHIFT 0
    #define DEC_QM45_NONINT_MASK 0x0000FF00
    #define DEC_QM45_NONINT_SHIFT 8
    #define DEC_QM46_NONINT_MASK 0x00FF0000
    #define DEC_QM46_NONINT_SHIFT 16
    #define DEC_QM47_NONINT_MASK 0xFF000000
    #define DEC_QM47_NONINT_SHIFT 24
#define  DEC_QMATRIX_48_51_INTRA 0x7130
    #define DEC_QM48_INT_MASK 0x000000FF
    #define DEC_QM48_INT_SHIFT 0
    #define DEC_QM49_INT_MASK 0x0000FF00
    #define DEC_QM49_INT_SHIFT 8
    #define DEC_QM50_INT_MASK 0x00FF0000
    #define DEC_QM50_INT_SHIFT 16
    #define DEC_QM51_INT_MASK 0xFF000000
    #define DEC_QM51_INT_SHIFT 24
#define  DEC_QMATRIX_48_51_NONINT 0x7170
    #define DEC_QM48_NONINT_MASK 0x000000FF
    #define DEC_QM48_NONINT_SHIFT 0
    #define DEC_QM49_NONINT_MASK 0x0000FF00
    #define DEC_QM49_NONINT_SHIFT 8
    #define DEC_QM50_NONINT_MASK 0x00FF0000
    #define DEC_QM50_NONINT_SHIFT 16
    #define DEC_QM51_NONINT_MASK 0xFF000000
    #define DEC_QM51_NONINT_SHIFT 24
#define  DEC_QMATRIX_4_7_INTRA 0x7104
    #define DEC_QM4_INT_MASK 0x000000FF
    #define DEC_QM4_INT_SHIFT 0
    #define DEC_QM5_INT_MASK 0x0000FF00
    #define DEC_QM5_INT_SHIFT 8
    #define DEC_QM6_INT_MASK 0x00FF0000
    #define DEC_QM6_INT_SHIFT 16
    #define DEC_QM7_INT_MASK 0xFF000000
    #define DEC_QM7_INT_SHIFT 24
#define  DEC_QMATRIX_4_7_NONINT 0x7144
    #define DEC_QM4_NONINT_MASK 0x000000FF
    #define DEC_QM4_NONINT_SHIFT 0
    #define DEC_QM5_NONINT_MASK 0x0000FF00
    #define DEC_QM5_NONINT_SHIFT 8
    #define DEC_QM6_NONINT_MASK 0x00FF0000
    #define DEC_QM6_NONINT_SHIFT 16
    #define DEC_QM7_NONINT_MASK 0xFF000000
    #define DEC_QM7_NONINT_SHIFT 24
#define  DEC_QMATRIX_52_55_INTRA 0x7134
    #define DEC_QM52_INT_MASK 0x000000FF
    #define DEC_QM52_INT_SHIFT 0
    #define DEC_QM53_INT_MASK 0x0000FF00
    #define DEC_QM53_INT_SHIFT 8
    #define DEC_QM54_INT_MASK 0x00FF0000
    #define DEC_QM54_INT_SHIFT 16
    #define DEC_QM55_INT_MASK 0xFF000000
    #define DEC_QM55_INT_SHIFT 24
#define  DEC_QMATRIX_52_55_NONINT 0x7174
    #define DEC_QM52_NONINT_MASK 0x000000FF
    #define DEC_QM52_NONINT_SHIFT 0
    #define DEC_QM53_NONINT_MASK 0x0000FF00
    #define DEC_QM53_NONINT_SHIFT 8
    #define DEC_QM54_NONINT_MASK 0x00FF0000
    #define DEC_QM54_NONINT_SHIFT 16
    #define DEC_QM55_NONINT_MASK 0xFF000000
    #define DEC_QM55_NONINT_SHIFT 24
#define  DEC_QMATRIX_56_59_INTRA 0x7138
    #define DEC_QM56_INT_MASK 0x000000FF
    #define DEC_QM56_INT_SHIFT 0
    #define DEC_QM57_INT_MASK 0x0000FF00
    #define DEC_QM57_INT_SHIFT 8
    #define DEC_QM58_INT_MASK 0x00FF0000
    #define DEC_QM58_INT_SHIFT 16
    #define DEC_QM59_INT_MASK 0xFF000000
    #define DEC_QM59_INT_SHIFT 24
#define  DEC_QMATRIX_56_59_NONINT 0x7178
    #define DEC_QM56_NONINT_MASK 0x000000FF
    #define DEC_QM56_NONINT_SHIFT 0
    #define DEC_QM57_NONINT_MASK 0x0000FF00
    #define DEC_QM57_NONINT_SHIFT 8
    #define DEC_QM58_NONINT_MASK 0x00FF0000
    #define DEC_QM58_NONINT_SHIFT 16
    #define DEC_QM59_NONINT_MASK 0xFF000000
    #define DEC_QM59_NONINT_SHIFT 24
#define  DEC_QMATRIX_60_63_INTRA 0x713C
    #define DEC_QM60_INT_MASK 0x000000FF
    #define DEC_QM60_INT_SHIFT 0
    #define DEC_QM61_INT_MASK 0x0000FF00
    #define DEC_QM61_INT_SHIFT 8
    #define DEC_QM62_INT_MASK 0x00FF0000
    #define DEC_QM62_INT_SHIFT 16
    #define DEC_QM63_INT_MASK 0xFF000000
    #define DEC_QM63_INT_SHIFT 24
#define  DEC_QMATRIX_60_63_NONINT 0x717C
    #define DEC_QM60_NONINT_MASK 0x000000FF
    #define DEC_QM60_NONINT_SHIFT 0
    #define DEC_QM61_NONINT_MASK 0x0000FF00
    #define DEC_QM61_NONINT_SHIFT 8
    #define DEC_QM62_NONINT_MASK 0x00FF0000
    #define DEC_QM62_NONINT_SHIFT 16
    #define DEC_QM63_NONINT_MASK 0xFF000000
    #define DEC_QM63_NONINT_SHIFT 24
#define  DEC_QMATRIX_8_11_INTRA 0x7108
    #define DEC_QM8_INT_MASK 0x000000FF
    #define DEC_QM8_INT_SHIFT 0
    #define DEC_QM9_INT_MASK 0x0000FF00
    #define DEC_QM9_INT_SHIFT 8
    #define DEC_QM10_INT_MASK 0x00FF0000
    #define DEC_QM10_INT_SHIFT 16
    #define DEC_QM11_INT_MASK 0xFF000000
    #define DEC_QM11_INT_SHIFT 24
#define  DEC_QMATRIX_8_11_NONINT 0x7148
    #define DEC_QM8_NONINT_MASK 0x000000FF
    #define DEC_QM8_NONINT_SHIFT 0
    #define DEC_QM9_NONINT_MASK 0x0000FF00
    #define DEC_QM9_NONINT_SHIFT 8
    #define DEC_QM10_NONINT_MASK 0x00FF0000
    #define DEC_QM10_NONINT_SHIFT 16
    #define DEC_QM11_NONINT_MASK 0xFF000000
    #define DEC_QM11_NONINT_SHIFT 24
#define  DEC_RUNLEVEL 0x7300
    #define DEC_RUNLEVEL_LEVEL_MASK 0x00007FFF
    #define DEC_RUNLEVEL_LEVEL_SHIFT 0
    #define DEC_RUNLEVEL_LEVEL_SIGN_MASK 0x00008000
    #define DEC_RUNLEVEL_LEVEL_SIGN_SHIFT 15
    #define DEC_RUNLEVEL_RUN_MASK 0x007F0000
    #define DEC_RUNLEVEL_RUN_SHIFT 16
    #define LAST_MASK 0x00800000
    #define LAST_SHIFT 23
#define  DEC_SURF_SIZE 0x7358
    #define DEC_SURF_SIZE_PITCH_MASK 0x00000FC0
    #define DEC_SURF_SIZE_PITCH_SHIFT 6
#define  DIP_CTRL 0x7040
    #define EN_MASK 0x00000001
    #define EN_SHIFT 0
#define  DIP_FETCHER_ADR_A 0x7000
    #define BASE_A_MASK 0x0FFFFFF0
    #define BASE_A_SHIFT 4
#define  DIP_FETCHER_ADR_B 0x7008
    #define BASE_B_MASK 0x0FFFFFF0
    #define BASE_B_SHIFT 4
#define  DIP_FETCHER_ADR_C 0x7010
    #define BASE_C_MASK 0x0FFFFFF0
    #define BASE_C_SHIFT 4
#define  DIP_FETCHER_ADR_D 0x7018
    #define BASE_D_MASK 0x0FFFFFF0
    #define BASE_D_SHIFT 4
#define  DIP_FETCHER_CNT_A 0x7004
    #define CNT_A_MASK 0x000FFFFF
    #define CNT_A_SHIFT 0
#define  DIP_FETCHER_CNT_B 0x700C
    #define CNT_B_MASK 0x000FFFFF
    #define CNT_B_SHIFT 0
#define  DIP_FETCHER_CNT_C 0x7014
    #define CNT_C_MASK 0x000FFFFF
    #define CNT_C_SHIFT 0
#define  DIP_FETCHER_CNT_D 0x701C
    #define CNT_D_MASK 0x000FFFFF
    #define CNT_D_SHIFT 0
#define  DIP_HOST_INT_MASK 0x7058
    #define DIP_HOST_INT_MASK_INT_EN_FETCH_A_DONE_MASK 0x00000001
    #define DIP_HOST_INT_MASK_INT_EN_FETCH_A_DONE_SHIFT 0
    #define DIP_HOST_INT_MASK_INT_EN_FETCH_B_DONE_MASK 0x00000002
    #define DIP_HOST_INT_MASK_INT_EN_FETCH_B_DONE_SHIFT 1
    #define DIP_HOST_INT_MASK_INT_EN_FETCH_C_DONE_MASK 0x00000004
    #define DIP_HOST_INT_MASK_INT_EN_FETCH_C_DONE_SHIFT 2
    #define DIP_HOST_INT_MASK_INT_EN_FETCH_D_DONE_MASK 0x00000008
    #define DIP_HOST_INT_MASK_INT_EN_FETCH_D_DONE_SHIFT 3
    #define DIP_HOST_INT_MASK_INT_EN_MPP_INT_MASK 0x00000010
    #define DIP_HOST_INT_MASK_INT_EN_MPP_INT_SHIFT 4
#define  DIP_INT_STATUS 0x7054
    #define FETCH_A_DONE_MASK 0x00000001
    #define FETCH_A_DONE_SHIFT 0
    #define FETCH_B_DONE_MASK 0x00000002
    #define FETCH_B_DONE_SHIFT 1
    #define FETCH_C_DONE_MASK 0x00000004
    #define FETCH_C_DONE_SHIFT 2
    #define FETCH_D_DONE_MASK 0x00000008
    #define FETCH_D_DONE_SHIFT 3
    #define DIP_INT_STATUS_MPP_INT_MASK 0x00000010
    #define DIP_INT_STATUS_MPP_INT_SHIFT 4
#define  DIP_MIPS_INT_MASK 0x705C
    #define DIP_MIPS_INT_MASK_INT_EN_FETCH_A_DONE_MASK 0x00000001
    #define DIP_MIPS_INT_MASK_INT_EN_FETCH_A_DONE_SHIFT 0
    #define DIP_MIPS_INT_MASK_INT_EN_FETCH_B_DONE_MASK 0x00000002
    #define DIP_MIPS_INT_MASK_INT_EN_FETCH_B_DONE_SHIFT 1
    #define DIP_MIPS_INT_MASK_INT_EN_FETCH_C_DONE_MASK 0x00000004
    #define DIP_MIPS_INT_MASK_INT_EN_FETCH_C_DONE_SHIFT 2
    #define DIP_MIPS_INT_MASK_INT_EN_FETCH_D_DONE_MASK 0x00000008
    #define DIP_MIPS_INT_MASK_INT_EN_FETCH_D_DONE_SHIFT 3
    #define DIP_MIPS_INT_MASK_INT_EN_MPP_INT_MASK 0x00000010
    #define DIP_MIPS_INT_MASK_INT_EN_MPP_INT_SHIFT 4
#define  DIP_STATUS 0x7060
    #define FETCH_ACTIVE_CNT_MASK 0x000FFFFF
    #define FETCH_ACTIVE_CNT_SHIFT 0
    #define FETCH_CHA_VALID_MASK 0x00100000
    #define FETCH_CHA_VALID_SHIFT 20
    #define FETCH_CHB_VALID_MASK 0x00200000
    #define FETCH_CHB_VALID_SHIFT 21
    #define FETCH_CHC_VALID_MASK 0x00400000
    #define FETCH_CHC_VALID_SHIFT 22
    #define FETCH_CHD_VALID_MASK 0x00800000
    #define FETCH_CHD_VALID_SHIFT 23
    #define FETCH_CHA_ACTIVE_MASK 0x01000000
    #define FETCH_CHA_ACTIVE_SHIFT 24
    #define FETCH_CHB_ACTIVE_MASK 0x02000000
    #define FETCH_CHB_ACTIVE_SHIFT 25
    #define FETCH_CHC_ACTIVE_MASK 0x04000000
    #define FETCH_CHC_ACTIVE_SHIFT 26
    #define FETCH_CHD_ACTIVE_MASK 0x08000000
    #define FETCH_CHD_ACTIVE_SHIFT 27
    #define FETCH_BUSY_MASK 0x10000000
    #define FETCH_BUSY_SHIFT 28
    #define MICRO_BUSY_MASK 0x20000000
    #define MICRO_BUSY_SHIFT 29
#define  DMA_ACTIVE_CMD 0x0C30
    #define DMA_ACTIVE_CMD_BYTECNT_MASK 0x0000FFFF
    #define DMA_ACTIVE_CMD_BYTECNT_SHIFT 0
    #define DMA_ACTIVE_CMD_ENCRYPT_TYPE_SEL_MASK 0x00070000
    #define DMA_ACTIVE_CMD_ENCRYPT_TYPE_SEL_SHIFT 16
    #define EXTENDED_MASK 0x00080000
    #define EXTENDED_SHIFT 19
    #define DMA_ACTIVE_CMD_ENCRYPT_EN_MASK 0x00300000
    #define DMA_ACTIVE_CMD_ENCRYPT_EN_SHIFT 20
    #define DMA_ACTIVE_CMD_STREAMCIPHER_START_MASK 0x00400000
    #define DMA_ACTIVE_CMD_STREAMCIPHER_START_SHIFT 22
    #define DMA_ACTIVE_CMD_FILL_MODE_MASK 0x00800000
    #define DMA_ACTIVE_CMD_FILL_MODE_SHIFT 23
    #define DMA_ACTIVE_CMD_SRCSPACE_MASK 0x01000000
    #define DMA_ACTIVE_CMD_SRCSPACE_SHIFT 24
    #define DMA_ACTIVE_CMD_DSTSPACE_MASK 0x02000000
    #define DMA_ACTIVE_CMD_DSTSPACE_SHIFT 25
    #define DMA_ACTIVE_CMD_SWAP_MASK 0x0C000000
    #define DMA_ACTIVE_CMD_SWAP_SHIFT 26
    #define DMA_ACTIVE_CMD_INTHOST_MASK 0x10000000
    #define DMA_ACTIVE_CMD_INTHOST_SHIFT 28
    #define DMA_ACTIVE_CMD_INTMIPS_MASK 0x20000000
    #define DMA_ACTIVE_CMD_INTMIPS_SHIFT 29
    #define PREEMPTED_MASK 0x40000000
    #define PREEMPTED_SHIFT 30
    #define EOL_MASK 0x80000000
    #define EOL_SHIFT 31
#define  DMA_ACTIVE_DESCRIPTOR 0x0C38
    #define DMA_ACTIVE_DESCRIPTOR_BASE_MASK 0x0FFFFFF8
    #define DMA_ACTIVE_DESCRIPTOR_BASE_SHIFT 3
    #define READING_MASK 0x10000000
    #define READING_SHIFT 28
#define  DMA_CRC_STATUS 0x0CC0
    #define CRC_VALUE_MASK 0xFFFFFFFF
    #define CRC_VALUE_SHIFT 0
#define  DMA_DIRECT_DMACMD_A 0x0C90
    #define DMA_DIRECT_DMACMD_A_BYTECNT_MASK 0x0000FFFF
    #define DMA_DIRECT_DMACMD_A_BYTECNT_SHIFT 0
    #define DMA_DIRECT_DMACMD_A_ENCRYPT_TYPE_SEL_MASK 0x00070000
    #define DMA_DIRECT_DMACMD_A_ENCRYPT_TYPE_SEL_SHIFT 16
    #define DMA_DIRECT_DMACMD_A_ENCRYPT_EN_MASK 0x00300000
    #define DMA_DIRECT_DMACMD_A_ENCRYPT_EN_SHIFT 20
    #define DMA_DIRECT_DMACMD_A_STREAMCIPHER_START_MASK 0x00400000
    #define DMA_DIRECT_DMACMD_A_STREAMCIPHER_START_SHIFT 22
    #define DMA_DIRECT_DMACMD_A_FILL_MODE_MASK 0x00800000
    #define DMA_DIRECT_DMACMD_A_FILL_MODE_SHIFT 23
    #define DMA_DIRECT_DMACMD_A_SRCSPACE_MASK 0x01000000
    #define DMA_DIRECT_DMACMD_A_SRCSPACE_SHIFT 24
    #define DMA_DIRECT_DMACMD_A_DSTSPACE_MASK 0x02000000
    #define DMA_DIRECT_DMACMD_A_DSTSPACE_SHIFT 25
    #define DMA_DIRECT_DMACMD_A_SWAP_MASK 0x0C000000
    #define DMA_DIRECT_DMACMD_A_SWAP_SHIFT 26
    #define DMA_DIRECT_DMACMD_A_INTHOST_MASK 0x10000000
    #define DMA_DIRECT_DMACMD_A_INTHOST_SHIFT 28
    #define DMA_DIRECT_DMACMD_A_INTMIPS_MASK 0x20000000
    #define DMA_DIRECT_DMACMD_A_INTMIPS_SHIFT 29
    #define DMA_DIRECT_DMACMD_A_URGENT_MASK 0x40000000
    #define DMA_DIRECT_DMACMD_A_URGENT_SHIFT 30
#define  DMA_DIRECT_DMACMD_B 0x0CB0
    #define DMA_DIRECT_DMACMD_B_BYTECNT_MASK 0x0000FFFF
    #define DMA_DIRECT_DMACMD_B_BYTECNT_SHIFT 0
    #define DMA_DIRECT_DMACMD_B_ENCRYPT_TYPE_SEL_MASK 0x00070000
    #define DMA_DIRECT_DMACMD_B_ENCRYPT_TYPE_SEL_SHIFT 16
    #define DMA_DIRECT_DMACMD_B_ENCRYPT_EN_MASK 0x00300000
    #define DMA_DIRECT_DMACMD_B_ENCRYPT_EN_SHIFT 20
    #define DMA_DIRECT_DMACMD_B_STREAMCIPHER_START_MASK 0x00400000
    #define DMA_DIRECT_DMACMD_B_STREAMCIPHER_START_SHIFT 22
    #define DMA_DIRECT_DMACMD_B_FILL_MODE_MASK 0x00800000
    #define DMA_DIRECT_DMACMD_B_FILL_MODE_SHIFT 23
    #define DMA_DIRECT_DMACMD_B_SRCSPACE_MASK 0x01000000
    #define DMA_DIRECT_DMACMD_B_SRCSPACE_SHIFT 24
    #define DMA_DIRECT_DMACMD_B_DSTSPACE_MASK 0x02000000
    #define DMA_DIRECT_DMACMD_B_DSTSPACE_SHIFT 25
    #define DMA_DIRECT_DMACMD_B_SWAP_MASK 0x0C000000
    #define DMA_DIRECT_DMACMD_B_SWAP_SHIFT 26
    #define DMA_DIRECT_DMACMD_B_INTHOST_MASK 0x10000000
    #define DMA_DIRECT_DMACMD_B_INTHOST_SHIFT 28
    #define DMA_DIRECT_DMACMD_B_INTMIPS_MASK 0x20000000
    #define DMA_DIRECT_DMACMD_B_INTMIPS_SHIFT 29
    #define DMA_DIRECT_DMACMD_B_URGENT_MASK 0x40000000
    #define DMA_DIRECT_DMACMD_B_URGENT_SHIFT 30
#define  DMA_DIRECT_DMACW_A 0x0C94
    #define DMA_DIRECT_DMACW_A_CW0_INDEX_MASK 0x0000003F
    #define DMA_DIRECT_DMACW_A_CW0_INDEX_SHIFT 0
    #define DMA_DIRECT_DMACW_A_DES_S0_CTRL_MASK 0x00000040
    #define DMA_DIRECT_DMACW_A_DES_S0_CTRL_SHIFT 6
    #define DMA_DIRECT_DMACW_A_DES_S0_MODE_MASK 0x00000080
    #define DMA_DIRECT_DMACW_A_DES_S0_MODE_SHIFT 7
    #define DMA_DIRECT_DMACW_A_INPUT_DWORD_SWAP_MASK 0x00400000
    #define DMA_DIRECT_DMACW_A_INPUT_DWORD_SWAP_SHIFT 22
    #define DMA_DIRECT_DMACW_A_OUTPUT_DWORD_SWAP_MASK 0x00800000
    #define DMA_DIRECT_DMACW_A_OUTPUT_DWORD_SWAP_SHIFT 23
    #define DMA_DIRECT_DMACW_A_IV_INDEX_MASK 0x3F000000
    #define DMA_DIRECT_DMACW_A_IV_INDEX_SHIFT 24
    #define DMA_DIRECT_DMACW_A_DEBUG_MODE_MASK 0x80000000
    #define DMA_DIRECT_DMACW_A_DEBUG_MODE_SHIFT 31
#define  DMA_DIRECT_DMACW_B 0x0CB4
    #define DMA_DIRECT_DMACW_B_CW0_INDEX_MASK 0x0000003F
    #define DMA_DIRECT_DMACW_B_CW0_INDEX_SHIFT 0
    #define DMA_DIRECT_DMACW_B_DES_S0_CTRL_MASK 0x00000040
    #define DMA_DIRECT_DMACW_B_DES_S0_CTRL_SHIFT 6
    #define DMA_DIRECT_DMACW_B_DES_S0_MODE_MASK 0x00000080
    #define DMA_DIRECT_DMACW_B_DES_S0_MODE_SHIFT 7
    #define DMA_DIRECT_DMACW_B_INPUT_DWORD_SWAP_MASK 0x00400000
    #define DMA_DIRECT_DMACW_B_INPUT_DWORD_SWAP_SHIFT 22
    #define DMA_DIRECT_DMACW_B_OUTPUT_DWORD_SWAP_MASK 0x00800000
    #define DMA_DIRECT_DMACW_B_OUTPUT_DWORD_SWAP_SHIFT 23
    #define DMA_DIRECT_DMACW_B_IV_INDEX_MASK 0x3F000000
    #define DMA_DIRECT_DMACW_B_IV_INDEX_SHIFT 24
    #define DMA_DIRECT_DMACW_B_DEBUG_MODE_MASK 0x80000000
    #define DMA_DIRECT_DMACW_B_DEBUG_MODE_SHIFT 31
#define  DMA_DIRECT_LDST_A 0x0C88
    #define DMA_DIRECT_LDST_A_BASE_MASK 0xFFFFFFFF
    #define DMA_DIRECT_LDST_A_BASE_SHIFT 0
#define  DMA_DIRECT_LDST_B 0x0CA8
    #define DMA_DIRECT_LDST_B_BASE_MASK 0xFFFFFFFF
    #define DMA_DIRECT_LDST_B_BASE_SHIFT 0
#define  DMA_DIRECT_LSRC_A 0x0C80
    #define DMA_DIRECT_LSRC_A_BASE_MASK 0xFFFFFFFF
    #define DMA_DIRECT_LSRC_A_BASE_SHIFT 0
#define  DMA_DIRECT_LSRC_B 0x0CA0
    #define DMA_DIRECT_LSRC_B_BASE_MASK 0xFFFFFFFF
    #define DMA_DIRECT_LSRC_B_BASE_SHIFT 0
#define  DMA_DIRECT_UDST_A 0x0C8C
    #define DMA_DIRECT_UDST_A_BASE_MASK 0xFFFFFFFF
    #define DMA_DIRECT_UDST_A_BASE_SHIFT 0
#define  DMA_DIRECT_UDST_B 0x0CAC
    #define DMA_DIRECT_UDST_B_BASE_MASK 0xFFFFFFFF
    #define DMA_DIRECT_UDST_B_BASE_SHIFT 0
#define  DMA_DIRECT_USRC_A 0x0C84
    #define DMA_DIRECT_USRC_A_BASE_MASK 0xFFFFFFFF
    #define DMA_DIRECT_USRC_A_BASE_SHIFT 0
#define  DMA_DIRECT_USRC_B 0x0CA4
    #define DMA_DIRECT_USRC_B_BASE_MASK 0xFFFFFFFF
    #define DMA_DIRECT_USRC_B_BASE_SHIFT 0
#define  DMA_DQ_PTR0 0x0C00
    #define DMA_DQ_PTR0_BASE_MASK 0x0FFFFFF0
    #define DMA_DQ_PTR0_BASE_SHIFT 4
#define  DMA_DQ_PTR1 0x0C04
    #define DMA_DQ_PTR1_BASE_MASK 0x0FFFFFF0
    #define DMA_DQ_PTR1_BASE_SHIFT 4
#define  DMA_DUMMY_REG 0x0C7C
    #define DMA_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define DMA_DUMMY_REG_DATA_SHIFT 0
#define  DMA_HOST_INT_MASK 0x0C54
    #define DMA_HOST_INT_MASK_INT_EN_XFER_DONE0_MASK 0x00000001
    #define DMA_HOST_INT_MASK_INT_EN_XFER_DONE0_SHIFT 0
    #define DMA_HOST_INT_MASK_INT_EN_XFER_DONE1_MASK 0x00000002
    #define DMA_HOST_INT_MASK_INT_EN_XFER_DONE1_SHIFT 1
    #define DMA_HOST_INT_MASK_INT_EN_XFER_DONEA_MASK 0x00000004
    #define DMA_HOST_INT_MASK_INT_EN_XFER_DONEA_SHIFT 2
    #define DMA_HOST_INT_MASK_INT_EN_XFER_DONEB_MASK 0x00000008
    #define DMA_HOST_INT_MASK_INT_EN_XFER_DONEB_SHIFT 3
#define  DMA_HOST_INT_STATUS 0x0C50
    #define DMA_HOST_INT_STATUS_XFER_DONE0_MASK 0x00000001
    #define DMA_HOST_INT_STATUS_XFER_DONE0_SHIFT 0
    #define DMA_HOST_INT_STATUS_XFER_DONE1_MASK 0x00000002
    #define DMA_HOST_INT_STATUS_XFER_DONE1_SHIFT 1
    #define DMA_HOST_INT_STATUS_XFER_DONEA_MASK 0x00000004
    #define DMA_HOST_INT_STATUS_XFER_DONEA_SHIFT 2
    #define DMA_HOST_INT_STATUS_XFER_DONEB_MASK 0x00000008
    #define DMA_HOST_INT_STATUS_XFER_DONEB_SHIFT 3
#define  DMA_MIPS_INT_MASK 0x0C5C
    #define DMA_MIPS_INT_MASK_INT_EN_XFER_DONE0_MASK 0x00000001
    #define DMA_MIPS_INT_MASK_INT_EN_XFER_DONE0_SHIFT 0
    #define DMA_MIPS_INT_MASK_INT_EN_XFER_DONE1_MASK 0x00000002
    #define DMA_MIPS_INT_MASK_INT_EN_XFER_DONE1_SHIFT 1
    #define DMA_MIPS_INT_MASK_INT_EN_XFER_DONEA_MASK 0x00000004
    #define DMA_MIPS_INT_MASK_INT_EN_XFER_DONEA_SHIFT 2
    #define DMA_MIPS_INT_MASK_INT_EN_XFER_DONEB_MASK 0x00000008
    #define DMA_MIPS_INT_MASK_INT_EN_XFER_DONEB_SHIFT 3
#define  DMA_MIPS_INT_STATUS 0x0C58
    #define DMA_MIPS_INT_STATUS_XFER_DONE0_MASK 0x00000001
    #define DMA_MIPS_INT_STATUS_XFER_DONE0_SHIFT 0
    #define DMA_MIPS_INT_STATUS_XFER_DONE1_MASK 0x00000002
    #define DMA_MIPS_INT_STATUS_XFER_DONE1_SHIFT 1
    #define DMA_MIPS_INT_STATUS_XFER_DONEA_MASK 0x00000004
    #define DMA_MIPS_INT_STATUS_XFER_DONEA_SHIFT 2
    #define DMA_MIPS_INT_STATUS_XFER_DONEB_MASK 0x00000008
    #define DMA_MIPS_INT_STATUS_XFER_DONEB_SHIFT 3
#define  DMA_STATUS 0x0C34
    #define INDIRECT0_MASK 0x00000001
    #define INDIRECT0_SHIFT 0
    #define INDIRECT1_MASK 0x00000002
    #define INDIRECT1_SHIFT 1
    #define DIRECT_A_MASK 0x00000004
    #define DIRECT_A_SHIFT 2
    #define DIRECT_B_MASK 0x00000008
    #define DIRECT_B_SHIFT 3
    #define ERR_INDIRECT0_MASK 0x00000010
    #define ERR_INDIRECT0_SHIFT 4
    #define ERR_INDIRECT1_MASK 0x00000020
    #define ERR_INDIRECT1_SHIFT 5
    #define ERR_DIRECT_A_MASK 0x00000040
    #define ERR_DIRECT_A_SHIFT 6
    #define ERR_DIRECT_B_MASK 0x00000080
    #define ERR_DIRECT_B_SHIFT 7
    #define INDIRECT0_CURRENT_MASK 0x00000100
    #define INDIRECT0_CURRENT_SHIFT 8
    #define INDIRECT1_CURRENT_MASK 0x00000200
    #define INDIRECT1_CURRENT_SHIFT 9
    #define DIRECT_A_CURRENT_MASK 0x00000400
    #define DIRECT_A_CURRENT_SHIFT 10
    #define DIRECT_B_CURRENT_MASK 0x00000800
    #define DIRECT_B_CURRENT_SHIFT 11
#define  DQS_CLK_CTRL 0x74CC
    #define DQS_ECLK_GATE_EN_MASK 0x00000001
    #define DQS_ECLK_GATE_EN_SHIFT 0
    #define DQS_MCLK_GATE_EN_MASK 0x00000002
    #define DQS_MCLK_GATE_EN_SHIFT 1
    #define RFM_ECLK_GATE_EN_MASK 0x00000004
    #define RFM_ECLK_GATE_EN_SHIFT 2
    #define RFM_MCLK_GATE_EN_MASK 0x00000008
    #define RFM_MCLK_GATE_EN_SHIFT 3
    #define DQS_PASS_GATE_EN_MASK 0x00000010
    #define DQS_PASS_GATE_EN_SHIFT 4
    #define RCB_ECLK_GATE_EN_MASK 0x00000020
    #define RCB_ECLK_GATE_EN_SHIFT 5
    #define OSF_MAIN_GATE_EN_MASK 0x00000040
    #define OSF_MAIN_GATE_EN_SHIFT 6
    #define OSF_MPG4_GATE_EN_MASK 0x00000080
    #define OSF_MPG4_GATE_EN_SHIFT 7
#define  DQS_DUMMY_REG 0x72E0
    #define DQS_DUMMY_REG_DUMMY_MASK 0xFFFFFFFF
    #define DQS_DUMMY_REG_DUMMY_SHIFT 0
#define  DQS_STAT_MUX 0x7298
    #define DQS_STAT_MUX_STAT_MUX_MASK 0x0000001F
    #define DQS_STAT_MUX_STAT_MUX_SHIFT 0
#define  DQS_STAT_MUX_RB 0x7294
    #define DQS_STAT_MUX_RB_STAT_RB_MASK 0xFFFFFFFF
    #define DQS_STAT_MUX_RB_STAT_RB_SHIFT 0
#define  DSCL_BOT_CR_WR_ADR 0x5C48
    #define DSCL_BOT_CR_WR_ADR_BASE_MASK 0x0FFFE000
    #define DSCL_BOT_CR_WR_ADR_BASE_SHIFT 13
#define  DSCL_BOT_C_WR_ADR 0x5C44
    #define DSCL_BOT_C_WR_ADR_BASE_MASK 0x0FFFE000
    #define DSCL_BOT_C_WR_ADR_BASE_SHIFT 13
#define  DSCL_BOT_Y_WR_ADR 0x5C40
    #define DSCL_BOT_Y_WR_ADR_BASE_MASK 0x0FFFE000
    #define DSCL_BOT_Y_WR_ADR_BASE_SHIFT 13
#define  DSCL_CR_RD_ADR 0x5C3C
    #define DSCL_CR_RD_ADR_BASE_MASK 0x0FFFE000
    #define DSCL_CR_RD_ADR_BASE_SHIFT 13
#define  DSCL_CR_WR_ADR 0x5C38
    #define DSCL_CR_WR_ADR_BASE_MASK 0x0FFFE000
    #define DSCL_CR_WR_ADR_BASE_SHIFT 13
#define  DSCL_C_RD_ADR 0x5C34
    #define DSCL_C_RD_ADR_BASE_MASK 0x0FFFE000
    #define DSCL_C_RD_ADR_BASE_SHIFT 13
#define  DSCL_C_WR_ADR 0x5C2C
    #define DSCL_C_WR_ADR_BASE_MASK 0x0FFFE000
    #define DSCL_C_WR_ADR_BASE_SHIFT 13
#define  DSCL_DUMMY_REG 0x5CF0
    #define DSCL_DUMMY_REG_DUMMY_MASK 0x00000001
    #define DSCL_DUMMY_REG_DUMMY_SHIFT 0
#define  DSCL_HORI_CTRL 0x5C20
    #define DSCL_HORI_CTRL_SCALE_EN_MASK 0x00000001
    #define DSCL_HORI_CTRL_SCALE_EN_SHIFT 0
    #define DSCL_HORI_CTRL_UCODE_VCNT_MASK 0x0000007E
    #define DSCL_HORI_CTRL_UCODE_VCNT_SHIFT 1
    #define DSCL_HORI_CTRL_INV_DIV_MASK 0xFFFF0000
    #define DSCL_HORI_CTRL_INV_DIV_SHIFT 16
#define  DSCL_HORI_UCODE 0x5C04
    #define DSCL_HORI_UCODE_HORI0_UCODE_MASK 0x000000FF
    #define DSCL_HORI_UCODE_HORI0_UCODE_SHIFT 0
    #define DSCL_HORI_UCODE_HORI1_UCODE_MASK 0x0000FF00
    #define DSCL_HORI_UCODE_HORI1_UCODE_SHIFT 8
    #define DSCL_HORI_UCODE_HORI2_UCODE_MASK 0x00FF0000
    #define DSCL_HORI_UCODE_HORI2_UCODE_SHIFT 16
    #define DSCL_HORI_UCODE_HORI3_UCODE_MASK 0xFF000000
    #define DSCL_HORI_UCODE_HORI3_UCODE_SHIFT 24
#define  DSCL_INT 0x5C54
    #define DSCL_INTERRUPT_MASK 0x00000001
    #define DSCL_INTERRUPT_SHIFT 0
#define  DSCL_INT_CTRL 0x5C58
    #define DSCL_INT_MIPS_EN_MASK 0x00000001
    #define DSCL_INT_MIPS_EN_SHIFT 0
    #define DSCL_INT_HOST_EN_MASK 0x00000002
    #define DSCL_INT_HOST_EN_SHIFT 1
#define  DSCL_PICT_RD_SIZE 0x5C14
    #define DSCL_PICT_RD_SIZE_SLICE_RD_SIZE_MASK 0x0000007F
    #define DSCL_PICT_RD_SIZE_SLICE_RD_SIZE_SHIFT 0
    #define DSCL_PICT_RD_SIZE_SLICE_RD_CNT_MASK 0x00007F00
    #define DSCL_PICT_RD_SIZE_SLICE_RD_CNT_SHIFT 8
#define  DSCL_PICT_WR_SIZE 0x5C18
    #define DSCL_PICT_WR_SIZE_SLICE_WR_SIZE_MASK 0x0000007F
    #define DSCL_PICT_WR_SIZE_SLICE_WR_SIZE_SHIFT 0
    #define DSCL_PICT_WR_SIZE_SLICE_WR_CNT_MASK 0x00007F00
    #define DSCL_PICT_WR_SIZE_SLICE_WR_CNT_SHIFT 8
#define  DSCL_SURF_RD_SIZE 0x5C50
    #define DSCL_RD_PITCH_MASK 0x00000FC0
    #define DSCL_RD_PITCH_SHIFT 6
#define  DSCL_SURF_WR_SIZE 0x5C1C
    #define DSCL_WR_PITCH_MASK 0x00000FC0
    #define DSCL_WR_PITCH_SHIFT 6
#define  DSCL_TRIG 0x5C10
    #define DSCL_TRIG_COLBITS_OVERRIDE_MASK 0x00000001
    #define DSCL_TRIG_COLBITS_OVERRIDE_SHIFT 0
    #define DSCL_TRIG_COLBITS_RD_VALUE_MASK 0x000000F0
    #define DSCL_TRIG_COLBITS_RD_VALUE_SHIFT 4
    #define DSCL_TRIG_COLBITS_WR_VALUE_MASK 0x00000F00
    #define DSCL_TRIG_COLBITS_WR_VALUE_SHIFT 8
    #define DSCL_TRIG_FORCE_RD_ONLY_MASK 0x00010000
    #define DSCL_TRIG_FORCE_RD_ONLY_SHIFT 16
    #define DSCL_TRIG_FIELD_SCALE_MASK 0x00100000
    #define DSCL_TRIG_FIELD_SCALE_SHIFT 20
    #define DSCL_TRIG_RD_8X8_MASK 0x00800000
    #define DSCL_TRIG_RD_8X8_SHIFT 23
    #define DSCL_TRIG_RD_LINEAR_MASK 0x01000000
    #define DSCL_TRIG_RD_LINEAR_SHIFT 24
    #define DSCL_TRIG_WR_LINEAR_MASK 0x02000000
    #define DSCL_TRIG_WR_LINEAR_SHIFT 25
    #define DSCL_TRIG_SCL_EN_MASK 0x10000000
    #define DSCL_TRIG_SCL_EN_SHIFT 28
    #define DSCL_TRIG_SKIP_FLD_EN_MASK 0x40000000
    #define DSCL_TRIG_SKIP_FLD_EN_SHIFT 30
    #define DSCL_TRIG_FLD_SEL_MASK 0x80000000
    #define DSCL_TRIG_FLD_SEL_SHIFT 31
#define  DSCL_UCODE_IDX 0x5C00
    #define DSCL_UCODE_IDX_HORI_IDX_MASK 0x0000000F
    #define DSCL_UCODE_IDX_HORI_IDX_SHIFT 0
    #define DSCL_UCODE_IDX_VERT_IDX_MASK 0x000F0000
    #define DSCL_UCODE_IDX_VERT_IDX_SHIFT 16
    #define DSCL_UCODE_IDX_VERT_BOT_IDX_MASK 0x00F00000
    #define DSCL_UCODE_IDX_VERT_BOT_IDX_SHIFT 20
#define  DSCL_VAR_ADR 0x5C60
    #define DSCL_VAR_ADR_BASE_MASK 0x0FFFFFC0
    #define DSCL_VAR_ADR_BASE_SHIFT 6
#define  DSCL_VAR_CTRL 0x5C5C
    #define DSCL_VAR_EN_MASK 0x00000001
    #define DSCL_VAR_EN_SHIFT 0
    #define DSCL_VAR_FLD_DIS_MASK 0x00000002
    #define DSCL_VAR_FLD_DIS_SHIFT 1
#define  DSCL_VERT_BOT_CTRL 0x5C4C
    #define DSCL_VERT_BOT_CTRL_SCALE_EN_MASK 0x00000001
    #define DSCL_VERT_BOT_CTRL_SCALE_EN_SHIFT 0
    #define DSCL_VERT_BOT_CTRL_UCODE_VCNT_MASK 0x0000007E
    #define DSCL_VERT_BOT_CTRL_UCODE_VCNT_SHIFT 1
    #define DSCL_VERT_BOT_CTRL_INV_DIV_MASK 0xFFFF0000
    #define DSCL_VERT_BOT_CTRL_INV_DIV_SHIFT 16
#define  DSCL_VERT_BOT_UCODE 0x5C0C
    #define DSCL_VERT_BOT_UCODE_VERT0_BOT_UCODE_MASK 0x000000FF
    #define DSCL_VERT_BOT_UCODE_VERT0_BOT_UCODE_SHIFT 0
    #define DSCL_VERT_BOT_UCODE_VERT1_BOT_UCODE_MASK 0x0000FF00
    #define DSCL_VERT_BOT_UCODE_VERT1_BOT_UCODE_SHIFT 8
    #define DSCL_VERT_BOT_UCODE_VERT2_BOT_UCODE_MASK 0x00FF0000
    #define DSCL_VERT_BOT_UCODE_VERT2_BOT_UCODE_SHIFT 16
    #define DSCL_VERT_BOT_UCODE_VERT3_BOT_UCODE_MASK 0xFF000000
    #define DSCL_VERT_BOT_UCODE_VERT3_BOT_UCODE_SHIFT 24
#define  DSCL_VERT_CTRL 0x5C24
    #define DSCL_VERT_CTRL_SCALE_EN_MASK 0x00000001
    #define DSCL_VERT_CTRL_SCALE_EN_SHIFT 0
    #define DSCL_VERT_CTRL_UCODE_VCNT_MASK 0x0000007E
    #define DSCL_VERT_CTRL_UCODE_VCNT_SHIFT 1
    #define DSCL_VERT_CTRL_INV_DIV_MASK 0xFFFF0000
    #define DSCL_VERT_CTRL_INV_DIV_SHIFT 16
#define  DSCL_VERT_UCODE 0x5C08
    #define DSCL_VERT_UCODE_VERT0_UCODE_MASK 0x000000FF
    #define DSCL_VERT_UCODE_VERT0_UCODE_SHIFT 0
    #define DSCL_VERT_UCODE_VERT1_UCODE_MASK 0x0000FF00
    #define DSCL_VERT_UCODE_VERT1_UCODE_SHIFT 8
    #define DSCL_VERT_UCODE_VERT2_UCODE_MASK 0x00FF0000
    #define DSCL_VERT_UCODE_VERT2_UCODE_SHIFT 16
    #define DSCL_VERT_UCODE_VERT3_UCODE_MASK 0xFF000000
    #define DSCL_VERT_UCODE_VERT3_UCODE_SHIFT 24
#define  DSCL_Y_RD_ADR 0x5C30
    #define DSCL_Y_RD_ADR_BASE_MASK 0x0FFFE000
    #define DSCL_Y_RD_ADR_BASE_SHIFT 13
#define  DSCL_Y_WR_ADR 0x5C28
    #define DSCL_Y_WR_ADR_BASE_MASK 0x0FFFE000
    #define DSCL_Y_WR_ADR_BASE_SHIFT 13
#define  DVE_ACTIVE_X 0x4044
    #define DVE_ACTIVE_X_START_MASK 0x00001FFF
    #define DVE_ACTIVE_X_START_SHIFT 0
    #define DVE_ACTIVE_X_END_MASK 0x1FFF0000
    #define DVE_ACTIVE_X_END_SHIFT 16
#define  DVE_AV_X 0x4050
    #define EAV_START_MASK 0x00001FFF
    #define EAV_START_SHIFT 0
    #define SAV_START_MASK 0x1FFF0000
    #define SAV_START_SHIFT 16
#define  DVE_BOT_ACTIVE_Y 0x4038
    #define DVE_BOT_ACTIVE_Y_START_MASK 0x00000FFF
    #define DVE_BOT_ACTIVE_Y_START_SHIFT 0
    #define DVE_BOT_ACTIVE_Y_END_MASK 0x0FFF0000
    #define DVE_BOT_ACTIVE_Y_END_SHIFT 16
#define  DVE_BOT_DE_X 0x407C
    #define DVE_BOT_DE_X_START_MASK 0x00001FFF
    #define DVE_BOT_DE_X_START_SHIFT 0
    #define DVE_BOT_DE_X_END_MASK 0x1FFF0000
    #define DVE_BOT_DE_X_END_SHIFT 16
#define  DVE_BOT_DE_Y 0x4074
    #define DVE_BOT_DE_Y_START_MASK 0x00000FFF
    #define DVE_BOT_DE_Y_START_SHIFT 0
    #define DVE_BOT_DE_Y_END_MASK 0x0FFF0000
    #define DVE_BOT_DE_Y_END_SHIFT 16
#define  DVE_BOT_VBI_Y 0x4030
    #define DVE_BOT_VBI_Y_START_MASK 0x00000FFF
    #define DVE_BOT_VBI_Y_START_SHIFT 0
    #define DVE_BOT_VBI_Y_END_MASK 0x0FFF0000
    #define DVE_BOT_VBI_Y_END_SHIFT 16
#define  DVE_BOT_VIDEO_Y 0x4040
    #define DVE_BOT_VIDEO_Y_START_MASK 0x00000FFF
    #define DVE_BOT_VIDEO_Y_START_SHIFT 0
    #define DVE_BOT_VIDEO_Y_END_MASK 0x0FFF0000
    #define DVE_BOT_VIDEO_Y_END_SHIFT 16
#define  DVE_BOT_VSYNC_X 0x4060
    #define DVE_BOT_VSYNC_X_START_MASK 0x00001FFF
    #define DVE_BOT_VSYNC_X_START_SHIFT 0
    #define DVE_BOT_VSYNC_X_END_MASK 0x1FFF0000
    #define DVE_BOT_VSYNC_X_END_SHIFT 16
#define  DVE_BOT_VSYNC_Y 0x4058
    #define DVE_BOT_VSYNC_Y_START_MASK 0x00000FFF
    #define DVE_BOT_VSYNC_Y_START_SHIFT 0
    #define DVE_BOT_VSYNC_Y_END_MASK 0x0FFF0000
    #define DVE_BOT_VSYNC_Y_END_SHIFT 16
#define  DVE_BUF_STATUS 0x4104
    #define CB_FREE_ENTRIES_MASK 0x000000FF
    #define CB_FREE_ENTRIES_SHIFT 0
    #define CR_FREE_ENTRIES_MASK 0x0000FF00
    #define CR_FREE_ENTRIES_SHIFT 8
    #define YVBI_FREE_ENTRIES_MASK 0x01FF0000
    #define YVBI_FREE_ENTRIES_SHIFT 16
#define  DVE_CB_ADR 0x40BC
    #define DVE_CB_ADR_BASE_MASK 0x0FFFFFC0
    #define DVE_CB_ADR_BASE_SHIFT 6
#define  DVE_CHROMA_LIMIT 0x40EC
    #define DVE_CHROMA_LIMIT_UPPER_THRES_MASK 0x000003FF
    #define DVE_CHROMA_LIMIT_UPPER_THRES_SHIFT 0
    #define DVE_CHROMA_LIMIT_LOWER_THRES_MASK 0x03FF0000
    #define DVE_CHROMA_LIMIT_LOWER_THRES_SHIFT 16
#define  DVE_CMD_FIFO 0x4018
    #define DVE_CMD_FIFO_TOP_IDX_MASK 0x0000003F
    #define DVE_CMD_FIFO_TOP_IDX_SHIFT 0
    #define DVE_CMD_FIFO_FLD_SEL_MASK 0x000000C0
    #define DVE_CMD_FIFO_FLD_SEL_SHIFT 6
    #define DVE_CMD_FIFO_BOT_IDX_MASK 0x00003F00
    #define DVE_CMD_FIFO_BOT_IDX_SHIFT 8
    #define DVE_CMD_FIFO_VBI_FLD_SEL_MASK 0x0000C000
    #define DVE_CMD_FIFO_VBI_FLD_SEL_SHIFT 14
    #define DVE_CMD_FIFO_VBI_TOP_IDX_MASK 0x007F0000
    #define DVE_CMD_FIFO_VBI_TOP_IDX_SHIFT 16
    #define DVE_CMD_FIFO_VBI_BOT_IDX_MASK 0x7F000000
    #define DVE_CMD_FIFO_VBI_BOT_IDX_SHIFT 24
    #define DVE_CMD_FIFO_UPDATE_MASK 0x80000000
    #define DVE_CMD_FIFO_UPDATE_SHIFT 31
#define  DVE_CR_ADR 0x40C0
    #define DVE_CR_ADR_BASE_MASK 0x0FFFFFC0
    #define DVE_CR_ADR_BASE_SHIFT 6
#define  DVE_CTRL 0x4010
    #define INPUT_BIT_SIZE_MASK 0x00000001
    #define INPUT_BIT_SIZE_SHIFT 0
    #define INPUT_422_MASK 0x00000002
    #define INPUT_422_SHIFT 1
    #define MEM_FORMAT_MASK 0x0000000C
    #define MEM_FORMAT_SHIFT 2
    #define EXTEND_8BIT_MASK 0x00000010
    #define EXTEND_8BIT_SHIFT 4
    #define OUTPUT_BIT_SIZE_MASK 0x00000020
    #define OUTPUT_BIT_SIZE_SHIFT 5
    #define OUT_CLK_EDGE_MASK 0x00000040
    #define OUT_CLK_EDGE_SHIFT 6
    #define DVE_CTRL_DUPLICATE_CODE_MASK 0x00000080
    #define DVE_CTRL_DUPLICATE_CODE_SHIFT 7
    #define OUTPUT_TYPE_MASK 0x00000300
    #define OUTPUT_TYPE_SHIFT 8
    #define EMPTY_FIFO_MODE_MASK 0x00000C00
    #define EMPTY_FIFO_MODE_SHIFT 10
    #define FIELD_POLARITY_MASK 0x00001000
    #define FIELD_POLARITY_SHIFT 12
    #define VSYNC_POLARITY_MASK 0x00002000
    #define VSYNC_POLARITY_SHIFT 13
    #define HSYNC_POLARITY_MASK 0x00004000
    #define HSYNC_POLARITY_SHIFT 14
    #define DE_POLARITY_MASK 0x00008000
    #define DE_POLARITY_SHIFT 15
    #define HS_BANK_MASK 0x00010000
    #define HS_BANK_SHIFT 16
    #define COL_CONV_EN_MASK 0x00020000
    #define COL_CONV_EN_SHIFT 17
    #define COL_CONV_SEL_MASK 0x000C0000
    #define COL_CONV_SEL_SHIFT 18
    #define EXT_SYNC_MODE_MASK 0x00100000
    #define EXT_SYNC_MODE_SHIFT 20
    #define AV_VSYNC_POLARITY_MASK 0x01000000
    #define AV_VSYNC_POLARITY_SHIFT 24
    #define AV_FIELD_POLARITY_MASK 0x02000000
    #define AV_FIELD_POLARITY_SHIFT 25
    #define PROG_TO_INTLCD_MODE_MASK 0x04000000
    #define PROG_TO_INTLCD_MODE_SHIFT 26
    #define MEM_PACKED_MASK 0x10000000
    #define MEM_PACKED_SHIFT 28
#define  DVE_CURR_CMD 0x4024
    #define DVE_CURR_CMD_TOP_IDX_MASK 0x0000003F
    #define DVE_CURR_CMD_TOP_IDX_SHIFT 0
    #define DVE_CURR_CMD_FLD_SEL_MASK 0x000000C0
    #define DVE_CURR_CMD_FLD_SEL_SHIFT 6
    #define DVE_CURR_CMD_BOT_IDX_MASK 0x00003F00
    #define DVE_CURR_CMD_BOT_IDX_SHIFT 8
    #define DVE_CURR_CMD_VBI_FLD_SEL_MASK 0x0000C000
    #define DVE_CURR_CMD_VBI_FLD_SEL_SHIFT 14
    #define DVE_CURR_CMD_VBI_TOP_IDX_MASK 0x007F0000
    #define DVE_CURR_CMD_VBI_TOP_IDX_SHIFT 16
    #define DVE_CURR_CMD_VBI_BOT_IDX_MASK 0x7F000000
    #define DVE_CURR_CMD_VBI_BOT_IDX_SHIFT 24
    #define DVE_CURR_CMD_UPDATE_MASK 0x80000000
    #define DVE_CURR_CMD_UPDATE_SHIFT 31
#define  DVE_C_ADR 0x40AC
    #define DVE_C_ADR_BASE_MASK 0x0FFFFFC0
    #define DVE_C_ADR_BASE_SHIFT 6
#define  DVE_DEFAULT_CHROMA 0x4094
    #define DVE_DEFAULT_CHROMA_CB_VAL_MASK 0x000003FF
    #define DVE_DEFAULT_CHROMA_CB_VAL_SHIFT 0
    #define DVE_DEFAULT_CHROMA_CR_VAL_MASK 0x03FF0000
    #define DVE_DEFAULT_CHROMA_CR_VAL_SHIFT 16
#define  DVE_DEFAULT_LUMA 0x4090
    #define DVE_DEFAULT_LUMA_Y_VAL_MASK 0x000003FF
    #define DVE_DEFAULT_LUMA_Y_VAL_SHIFT 0
#define  DVE_DEN 0x4124
    #define DVE_DEN_DEN_MASK 0xFFFFFFFF
    #define DVE_DEN_DEN_SHIFT 0
#define  DVE_DUMMY_REG 0x4100
    #define DVE_DUMMY_REG_DUMMY_BITS_MASK 0xFFFFFFFF
    #define DVE_DUMMY_REG_DUMMY_BITS_SHIFT 0
#define  DVE_FIELD_X 0x406C
    #define DVE_FIELD_X_FO_START_MASK 0x00001FFF
    #define DVE_FIELD_X_FO_START_SHIFT 0
    #define DVE_FIELD_X_FE_START_MASK 0x1FFF0000
    #define DVE_FIELD_X_FE_START_SHIFT 16
#define  DVE_FIELD_Y 0x4068
    #define DVE_FIELD_Y_FO_START_MASK 0x00000FFF
    #define DVE_FIELD_Y_FO_START_SHIFT 0
    #define DVE_FIELD_Y_FE_START_MASK 0x0FFF0000
    #define DVE_FIELD_Y_FE_START_SHIFT 16
#define  DVE_FIFO_STATUS 0x401C
    #define DVE_FIFO_STATUS_FREE_ENTRIES_MASK 0x0000001F
    #define DVE_FIFO_STATUS_FREE_ENTRIES_SHIFT 0
    #define CURR_IDX_MASK 0x00000F00
    #define CURR_IDX_SHIFT 8
    #define DVE_FIFO_STATUS_FRM_CNT_MASK 0x000FF000
    #define DVE_FIFO_STATUS_FRM_CNT_SHIFT 12
#define  DVE_FRAME_SIZE 0x4028
    #define H_TOTAL_MASK 0x00001FFF
    #define H_TOTAL_SHIFT 0
    #define V_TOTAL_MASK 0x0FFF0000
    #define V_TOTAL_SHIFT 16
#define  DVE_GENLOCK_LOWER 0x412C
    #define DVE_GENLOCK_LOWER_GENLOCK_L_MASK 0xFFFFFFFF
    #define DVE_GENLOCK_LOWER_GENLOCK_L_SHIFT 0
#define  DVE_GENLOCK_PCR_LOWER 0x40FC
    #define GENLOCK_PCR_L_MASK 0xFFFFFFFF
    #define GENLOCK_PCR_L_SHIFT 0
#define  DVE_GENLOCK_PCR_UPPER 0x40F8
    #define GENLOCK_PCR_U_MASK 0x000003FF
    #define GENLOCK_PCR_U_SHIFT 0
#define  DVE_GENLOCK_UPPER 0x4128
    #define DVE_GENLOCK_UPPER_GENLOCK_U_MASK 0x000003FF
    #define DVE_GENLOCK_UPPER_GENLOCK_U_SHIFT 0
#define  DVE_HBLANK_CHROMA 0x4084
    #define DVE_HBLANK_CHROMA_CB_VAL_MASK 0x000003FF
    #define DVE_HBLANK_CHROMA_CB_VAL_SHIFT 0
    #define DVE_HBLANK_CHROMA_CR_VAL_MASK 0x03FF0000
    #define DVE_HBLANK_CHROMA_CR_VAL_SHIFT 16
#define  DVE_HBLANK_LUMA 0x4080
    #define DVE_HBLANK_LUMA_Y_VAL_MASK 0x000003FF
    #define DVE_HBLANK_LUMA_Y_VAL_SHIFT 0
#define  DVE_HOST_INT_MASK 0x4008
    #define DVE_HOST_INT_MASK_MASK 0x00000001
    #define DVE_HOST_INT_MASK_SHIFT 0
#define  DVE_HSCAL_CHROMA_CTRL 0x40DC
    #define DVE_HSCAL_CHROMA_CTRL_PHASES_MASK 0x0000001F
    #define DVE_HSCAL_CHROMA_CTRL_PHASES_SHIFT 0
    #define DVE_HSCAL_CHROMA_CTRL_SRC_RES_MASK 0x00007F00
    #define DVE_HSCAL_CHROMA_CTRL_SRC_RES_SHIFT 8
    #define DVE_HSCAL_CHROMA_CTRL_DST_RES_MASK 0x007F0000
    #define DVE_HSCAL_CHROMA_CTRL_DST_RES_SHIFT 16
    #define DVE_HSCAL_CHROMA_CTRL_IDX_SHIFT_MASK 0x03000000
    #define DVE_HSCAL_CHROMA_CTRL_IDX_SHIFT_SHIFT 24
#define  DVE_HSCAL_CHROMA_DATA 0x40E4
    #define DVE_HSCAL_CHROMA_DATA_COEF_MASK 0xFFFFFFFF
    #define DVE_HSCAL_CHROMA_DATA_COEF_SHIFT 0
#define  DVE_HSCAL_CHROMA_IDX 0x40E0
    #define DVE_HSCAL_CHROMA_IDX_FLD_MASK 0x00000003
    #define DVE_HSCAL_CHROMA_IDX_FLD_SHIFT 0
    #define DVE_HSCAL_CHROMA_IDX_ADR_MASK 0x000000F0
    #define DVE_HSCAL_CHROMA_IDX_ADR_SHIFT 4
    #define DVE_HSCAL_CHROMA_IDX_BANK_MASK 0x00000100
    #define DVE_HSCAL_CHROMA_IDX_BANK_SHIFT 8
#define  DVE_HSCAL_LUMA_CTRL 0x40D0
    #define DVE_HSCAL_LUMA_CTRL_PHASES_MASK 0x0000001F
    #define DVE_HSCAL_LUMA_CTRL_PHASES_SHIFT 0
    #define DVE_HSCAL_LUMA_CTRL_SRC_RES_MASK 0x00007F00
    #define DVE_HSCAL_LUMA_CTRL_SRC_RES_SHIFT 8
    #define DVE_HSCAL_LUMA_CTRL_DST_RES_MASK 0x007F0000
    #define DVE_HSCAL_LUMA_CTRL_DST_RES_SHIFT 16
    #define DVE_HSCAL_LUMA_CTRL_IDX_SHIFT_MASK 0x03000000
    #define DVE_HSCAL_LUMA_CTRL_IDX_SHIFT_SHIFT 24
#define  DVE_HSCAL_LUMA_DATA 0x40D8
    #define DVE_HSCAL_LUMA_DATA_COEF_MASK 0xFFFFFFFF
    #define DVE_HSCAL_LUMA_DATA_COEF_SHIFT 0
#define  DVE_HSCAL_LUMA_IDX 0x40D4
    #define DVE_HSCAL_LUMA_IDX_FLD_MASK 0x00000003
    #define DVE_HSCAL_LUMA_IDX_FLD_SHIFT 0
    #define DVE_HSCAL_LUMA_IDX_ADR_MASK 0x000000F0
    #define DVE_HSCAL_LUMA_IDX_ADR_SHIFT 4
    #define DVE_HSCAL_LUMA_IDX_BANK_MASK 0x00000100
    #define DVE_HSCAL_LUMA_IDX_BANK_SHIFT 8
#define  DVE_HSYNC_X 0x4064
    #define DVE_HSYNC_X_START_MASK 0x00001FFF
    #define DVE_HSYNC_X_START_SHIFT 0
    #define DVE_HSYNC_X_END_MASK 0x1FFF0000
    #define DVE_HSYNC_X_END_SHIFT 16
#define  DVE_INT_CTRL 0x4000
    #define DVE_INT_EN_MASK 0x000000FF
    #define DVE_INT_EN_SHIFT 0
#define  DVE_INT_STATUS 0x4004
    #define DVE_INT_STATUS_DVE_INT_MASK 0x00000001
    #define DVE_INT_STATUS_DVE_INT_SHIFT 0
    #define FRM_CNT_RST_MASK 0x00000010
    #define FRM_CNT_RST_SHIFT 4
#define  DVE_LUMA_LIMIT 0x40E8
    #define DVE_LUMA_LIMIT_UPPER_THRES_MASK 0x000003FF
    #define DVE_LUMA_LIMIT_UPPER_THRES_SHIFT 0
    #define DVE_LUMA_LIMIT_LOWER_THRES_MASK 0x03FF0000
    #define DVE_LUMA_LIMIT_LOWER_THRES_SHIFT 16
#define  DVE_MIPS_INT_MASK 0x400C
    #define DVE_MIPS_INT_MASK_MASK 0x00000001
    #define DVE_MIPS_INT_MASK_SHIFT 0
#define  DVE_NUM 0x4120
    #define DVE_NUM_NUM_MASK 0xFFFFFFFF
    #define DVE_NUM_NUM_SHIFT 0
#define  DVE_OUTPUT_CLK_CTRL 0x4130
    #define DVE_OUTPUT_CLK_CTRL_DDR_MODE_MASK 0x00000001
    #define DVE_OUTPUT_CLK_CTRL_DDR_MODE_SHIFT 0
    #define DDR_CLK_POLARITY_MASK 0x00000010
    #define DDR_CLK_POLARITY_SHIFT 4
    #define STOP_OUT_CLK_MASK 0x80000000
    #define STOP_OUT_CLK_SHIFT 31
#define  DVE_OUTPUT_SEL 0x4140
    #define VODATA_9_0_SEL_MASK 0x00000003
    #define VODATA_9_0_SEL_SHIFT 0
    #define VODATA_19_10_SEL_MASK 0x00000300
    #define VODATA_19_10_SEL_SHIFT 8
    #define VODATA_29_20_SEL_MASK 0x00030000
    #define VODATA_29_20_SEL_SHIFT 16
#define  DVE_OUT_STATUS 0x4020
    #define DVE_OUT_STATUS_X_COORD_MASK 0x00001FFF
    #define DVE_OUT_STATUS_X_COORD_SHIFT 0
    #define DVE_OUT_STATUS_Y_COORD_MASK 0x01FFE000
    #define DVE_OUT_STATUS_Y_COORD_SHIFT 13
    #define FRM_STATE_MASK 0xFE000000
    #define FRM_STATE_SHIFT 25
#define  DVE_PACKED_ORDER 0x4014
    #define Y_BYTE_SEL_MASK 0x00000003
    #define Y_BYTE_SEL_SHIFT 0
    #define CB_BYTE_SEL_MASK 0x00000030
    #define CB_BYTE_SEL_SHIFT 4
    #define CR_BYTE_SEL_MASK 0x00000300
    #define CR_BYTE_SEL_SHIFT 8
#define  DVE_PCR_DEN 0x40F4
    #define DVE_PCR_DEN_DEN_MASK 0x0000FFFF
    #define DVE_PCR_DEN_DEN_SHIFT 0
#define  DVE_PCR_NUM 0x40F0
    #define DVE_PCR_NUM_NUM_MASK 0x0000FFFF
    #define DVE_PCR_NUM_NUM_SHIFT 0
#define  DVE_PLANAR_BUF 0x4098
    #define DVE_PLANAR_BUF_PITCH_MASK 0x00001FE0
    #define DVE_PLANAR_BUF_PITCH_SHIFT 5
    #define DVE_PLANAR_BUF_SIZE_MASK 0x7FFF0000
    #define DVE_PLANAR_BUF_SIZE_SHIFT 16
#define  DVE_PLANAR_SAMPLES 0x409C
    #define DVE_PLANAR_SAMPLES_WIDTH_MASK 0x00000FFF
    #define DVE_PLANAR_SAMPLES_WIDTH_SHIFT 0
#define  DVE_REQ_STATUS 0x4108
    #define C_REQ_WAIT_MASK 0x00000001
    #define C_REQ_WAIT_SHIFT 0
    #define Y_REQ_WAIT_MASK 0x00000010
    #define Y_REQ_WAIT_SHIFT 4
    #define VBI_REQ_WAIT_MASK 0x00000100
    #define VBI_REQ_WAIT_SHIFT 8
    #define MEM_RCLI_RDY_MASK 0x00001000
    #define MEM_RCLI_RDY_SHIFT 12
#define  DVE_TILED_BUF 0x40A0
    #define DVE_TILED_BUF_PITCH_MASK 0x00000FF0
    #define DVE_TILED_BUF_PITCH_SHIFT 4
    #define DVE_TILED_BUF_SIZE_Y_MASK 0x001FF000
    #define DVE_TILED_BUF_SIZE_Y_SHIFT 12
    #define DVE_TILED_BUF_SIZE_C_MASK 0xFF000000
    #define DVE_TILED_BUF_SIZE_C_SHIFT 24
#define  DVE_TILED_SAMPLES 0x40A4
    #define DVE_TILED_SAMPLES_WIDTH_MASK 0x00000FFF
    #define DVE_TILED_SAMPLES_WIDTH_SHIFT 0
#define  DVE_TOP_ACTIVE_Y 0x4034
    #define DVE_TOP_ACTIVE_Y_START_MASK 0x00000FFF
    #define DVE_TOP_ACTIVE_Y_START_SHIFT 0
    #define DVE_TOP_ACTIVE_Y_END_MASK 0x0FFF0000
    #define DVE_TOP_ACTIVE_Y_END_SHIFT 16
#define  DVE_TOP_DE_X 0x4078
    #define DVE_TOP_DE_X_START_MASK 0x00001FFF
    #define DVE_TOP_DE_X_START_SHIFT 0
    #define DVE_TOP_DE_X_END_MASK 0x1FFF0000
    #define DVE_TOP_DE_X_END_SHIFT 16
#define  DVE_TOP_DE_Y 0x4070
    #define DVE_TOP_DE_Y_START_MASK 0x00000FFF
    #define DVE_TOP_DE_Y_START_SHIFT 0
    #define DVE_TOP_DE_Y_END_MASK 0x0FFF0000
    #define DVE_TOP_DE_Y_END_SHIFT 16
#define  DVE_TOP_VBI_Y 0x402C
    #define DVE_TOP_VBI_Y_START_MASK 0x00000FFF
    #define DVE_TOP_VBI_Y_START_SHIFT 0
    #define DVE_TOP_VBI_Y_END_MASK 0x0FFF0000
    #define DVE_TOP_VBI_Y_END_SHIFT 16
#define  DVE_TOP_VIDEO_Y 0x403C
    #define DVE_TOP_VIDEO_Y_START_MASK 0x00000FFF
    #define DVE_TOP_VIDEO_Y_START_SHIFT 0
    #define DVE_TOP_VIDEO_Y_END_MASK 0x0FFF0000
    #define DVE_TOP_VIDEO_Y_END_SHIFT 16
#define  DVE_TOP_VSYNC_X 0x405C
    #define DVE_TOP_VSYNC_X_START_MASK 0x00001FFF
    #define DVE_TOP_VSYNC_X_START_SHIFT 0
    #define DVE_TOP_VSYNC_X_END_MASK 0x1FFF0000
    #define DVE_TOP_VSYNC_X_END_SHIFT 16
#define  DVE_TOP_VSYNC_Y 0x4054
    #define DVE_TOP_VSYNC_Y_START_MASK 0x00000FFF
    #define DVE_TOP_VSYNC_Y_START_SHIFT 0
    #define DVE_TOP_VSYNC_Y_END_MASK 0x0FFF0000
    #define DVE_TOP_VSYNC_Y_END_SHIFT 16
#define  DVE_VBI_ADR 0x40B8
    #define DVE_VBI_ADR_BASE_MASK 0x0FFFFFC0
    #define DVE_VBI_ADR_BASE_SHIFT 6
#define  DVE_VBI_BUF 0x40B0
    #define DVE_VBI_BUF_PITCH_MASK 0x00000FE0
    #define DVE_VBI_BUF_PITCH_SHIFT 5
    #define DVE_VBI_BUF_SIZE_MASK 0x0FFF0000
    #define DVE_VBI_BUF_SIZE_SHIFT 16
#define  DVE_VBI_SAMPLES 0x40B4
    #define DVE_VBI_SAMPLES_WIDTH_MASK 0x00000FFF
    #define DVE_VBI_SAMPLES_WIDTH_SHIFT 0
#define  DVE_VBI_X 0x404C
    #define DVE_VBI_X_START_MASK 0x00001FFF
    #define DVE_VBI_X_START_SHIFT 0
    #define DVE_VBI_X_END_MASK 0x1FFF0000
    #define DVE_VBI_X_END_SHIFT 16
#define  DVE_VFILT_BOT0 0x4118
    #define DVE_VFILT_BOT0_COEF_MASK 0x7FFFFFFF
    #define DVE_VFILT_BOT0_COEF_SHIFT 0
#define  DVE_VFILT_BOT1 0x411C
    #define DVE_VFILT_BOT1_COEF_MASK 0x7FFFFFFF
    #define DVE_VFILT_BOT1_COEF_SHIFT 0
#define  DVE_VFILT_CTRL 0x410C
    #define VCNT_INIT_FRAC_MASK 0x00000001
    #define VCNT_INIT_FRAC_SHIFT 0
    #define VCNT_INIT_MASK 0x00003FFE
    #define VCNT_INIT_SHIFT 1
    #define VCNT_INCR_FRAC_MASK 0x00010000
    #define VCNT_INCR_FRAC_SHIFT 16
    #define VCNT_INCR_MASK 0x00020000
    #define VCNT_INCR_SHIFT 17
#define  DVE_VFILT_TOP0 0x4110
    #define DVE_VFILT_TOP0_COEF_MASK 0x7FFFFFFF
    #define DVE_VFILT_TOP0_COEF_SHIFT 0
#define  DVE_VFILT_TOP1 0x4114
    #define DVE_VFILT_TOP1_COEF_MASK 0x7FFFFFFF
    #define DVE_VFILT_TOP1_COEF_SHIFT 0
#define  DVE_VIDEO_BORDER_CHROMA 0x408C
    #define DVE_VIDEO_BORDER_CHROMA_CB_VAL_MASK 0x000003FF
    #define DVE_VIDEO_BORDER_CHROMA_CB_VAL_SHIFT 0
    #define DVE_VIDEO_BORDER_CHROMA_CR_VAL_MASK 0x03FF0000
    #define DVE_VIDEO_BORDER_CHROMA_CR_VAL_SHIFT 16
#define  DVE_VIDEO_BORDER_LUMA 0x4088
    #define DVE_VIDEO_BORDER_LUMA_Y_VAL_MASK 0x000003FF
    #define DVE_VIDEO_BORDER_LUMA_Y_VAL_SHIFT 0
#define  DVE_VIDEO_X 0x4048
    #define DVE_VIDEO_X_START_MASK 0x00001FFF
    #define DVE_VIDEO_X_START_SHIFT 0
    #define DVE_VIDEO_X_END_MASK 0x1FFF0000
    #define DVE_VIDEO_X_END_SHIFT 16
#define  DVE_Y_ADR 0x40A8
    #define DVE_Y_ADR_BASE_MASK 0x0FFFFFC0
    #define DVE_Y_ADR_BASE_SHIFT 6
#define  DVO_CTRL 0x6090
    #define DATAMODE_MASK 0x00000001
    #define DATAMODE_SHIFT 0
    #define CLK_INV_MASK 0x00000004
    #define CLK_INV_SHIFT 2
    #define CLK_STOP_MASK 0x00000008
    #define CLK_STOP_SHIFT 3
    #define INCR_DIS_MASK 0x00000010
    #define INCR_DIS_SHIFT 4
    #define DVO_VALID_HIGH_MASK 0x00000040
    #define DVO_VALID_HIGH_SHIFT 6
    #define CLK_MASK 0x00000380
    #define CLK_SHIFT 7
    #define NULL_STUFF_MASK 0x00001000
    #define NULL_STUFF_SHIFT 12
    #define DROP_HEADER_MASK 0x00004000
    #define DROP_HEADER_SHIFT 14
    #define SYNC_DUR_MASK 0x00008000
    #define SYNC_DUR_SHIFT 15
    #define PAR_RATE_MASK 0x07FF0000
    #define PAR_RATE_SHIFT 16
    #define DVO_CTRL_DUMMY_MASK 0xF8000000
    #define DVO_CTRL_DUMMY_SHIFT 27
#define  DVO_INCR_PCR_CID 0x60A8
    #define DVO_INCR_PCR_CID_PCR_CID0_MASK 0x0000001F
    #define DVO_INCR_PCR_CID_PCR_CID0_SHIFT 0
    #define DVO_INCR_PCR_CID_PCR_CID1_MASK 0x00001F00
    #define DVO_INCR_PCR_CID_PCR_CID1_SHIFT 8
    #define DVO_INCR_PCR_CID_PCR_CID2_MASK 0x001F0000
    #define DVO_INCR_PCR_CID_PCR_CID2_SHIFT 16
    #define DVO_INCR_PCR_CID_PCR_CID3_MASK 0x1F000000
    #define DVO_INCR_PCR_CID_PCR_CID3_SHIFT 24
#define  DVO_PCR_INCR_ADR 0x60D0
    #define PCR_INCR_ADR_MASK 0x00000007
    #define PCR_INCR_ADR_SHIFT 0
#define  DVO_PCR_INCR_DATA_L 0x60D4
    #define PCR_INCR_DATA_L_MASK 0xFFFFFFFF
    #define PCR_INCR_DATA_L_SHIFT 0
#define  DVO_PCR_INCR_DATA_U 0x60D8
    #define PCR_INCR_DATA_U_MASK 0x00000001
    #define PCR_INCR_DATA_U_SHIFT 0
    #define PCR_INCR_DATA_RD_VALID_MASK 0x80000000
    #define PCR_INCR_DATA_RD_VALID_SHIFT 31
#define  DVO_PCR_LATCHED_ADR 0x60E0
    #define PCR_LATCHED_ADR_MASK 0x00000007
    #define PCR_LATCHED_ADR_SHIFT 0
#define  DVO_PCR_LATCHED_DATA_L 0x60E4
    #define PCR_LATCHED_DATA_L_MASK 0xFFFFFFFF
    #define PCR_LATCHED_DATA_L_SHIFT 0
#define  DVO_PCR_LATCHED_DATA_U 0x60E8
    #define PCR_LATCHED_DATA_U_MASK 0x00000001
    #define PCR_LATCHED_DATA_U_SHIFT 0
    #define PCR_LATCHED_DATA_RD_VALID_MASK 0x80000000
    #define PCR_LATCHED_DATA_RD_VALID_SHIFT 31
#define  DVO_PCR_PID0_1 0x6094
    #define PCR_PID0_MASK 0x00001FFF
    #define PCR_PID0_SHIFT 0
    #define PCR_STR0_MASK 0x00002000
    #define PCR_STR0_SHIFT 13
    #define PCR_PID1_MASK 0x1FFF0000
    #define PCR_PID1_SHIFT 16
    #define PCR_STR1_MASK 0x20000000
    #define PCR_STR1_SHIFT 29
#define  DVO_PCR_PID2_3 0x6098
    #define PCR_PID2_MASK 0x00001FFF
    #define PCR_PID2_SHIFT 0
    #define PCR_STR2_MASK 0x00002000
    #define PCR_STR2_SHIFT 13
    #define PCR_PID3_MASK 0x1FFF0000
    #define PCR_PID3_SHIFT 16
    #define PCR_STR3_MASK 0x20000000
    #define PCR_STR3_SHIFT 29
#define  DVO_RTP_PCR_CID 0x60AC
    #define DVO_RTP_PCR_CID_PCR_CID0_MASK 0x0000001F
    #define DVO_RTP_PCR_CID_PCR_CID0_SHIFT 0
    #define DVO_RTP_PCR_CID_PCR_CID1_MASK 0x00001F00
    #define DVO_RTP_PCR_CID_PCR_CID1_SHIFT 8
    #define DVO_RTP_PCR_CID_PCR_CID2_MASK 0x001F0000
    #define DVO_RTP_PCR_CID_PCR_CID2_SHIFT 16
    #define DVO_RTP_PCR_CID_PCR_CID3_MASK 0x1F000000
    #define DVO_RTP_PCR_CID_PCR_CID3_SHIFT 24
#define  ENC_BWD_C_ADR 0x7410
    #define ENC_BWD_C_ADR_BASE_MASK 0x0FFFE000
    #define ENC_BWD_C_ADR_BASE_SHIFT 13
#define  ENC_BWD_Y_ADR 0x740C
    #define ENC_BWD_Y_ADR_BASE_MASK 0x0FFFE000
    #define ENC_BWD_Y_ADR_BASE_SHIFT 13
#define  ENC_CANDIDATE_COUNT 0x72C0
    #define ENC_CANDIDATE_COUNT_VALUE_MASK 0x0001FFFF
    #define ENC_CANDIDATE_COUNT_VALUE_SHIFT 0
#define  ENC_CTRL 0x73F0
    #define ENC_CTRL_MISMATCH_MASK 0x00000001
    #define ENC_CTRL_MISMATCH_SHIFT 0
    #define ENC_CTRL_SCAN_ORDER_MASK 0x0000000C
    #define ENC_CTRL_SCAN_ORDER_SHIFT 2
    #define ENC_CTRL_DC_SCALE_MASK 0x00000030
    #define ENC_CTRL_DC_SCALE_SHIFT 4
    #define ENC_CTRL_QSCALE_METHOD_MASK 0x00000040
    #define ENC_CTRL_QSCALE_METHOD_SHIFT 6
    #define ENC_CTRL_QSCALE_TYPE_MASK 0x00000080
    #define ENC_CTRL_QSCALE_TYPE_SHIFT 7
    #define ENC_CTRL_SATURATE_MASK 0x00000F00
    #define ENC_CTRL_SATURATE_SHIFT 8
    #define RFM_DIS_MASK 0x00010000
    #define RFM_DIS_SHIFT 16
#define  ENC_CUR_C_ADR 0x7400
    #define ENC_CUR_C_ADR_BASE_MASK 0x0FFFE000
    #define ENC_CUR_C_ADR_BASE_SHIFT 13
#define  ENC_CUR_C_BOT_ADR 0x7420
    #define ENC_CUR_C_BOT_ADR_BASE_MASK 0x0FFFE000
    #define ENC_CUR_C_BOT_ADR_BASE_SHIFT 13
#define  ENC_CUR_Y_ADR 0x73FC
    #define ENC_CUR_Y_ADR_BASE_MASK 0x0FFFE000
    #define ENC_CUR_Y_ADR_BASE_SHIFT 13
#define  ENC_CUR_Y_BOT_ADR 0x741C
    #define ENC_CUR_Y_BOT_ADR_BASE_MASK 0x0FFFE000
    #define ENC_CUR_Y_BOT_ADR_BASE_SHIFT 13
#define  ENC_FULL_COUNT 0x72C8
    #define ENC_FULL_COUNT_VALUE_MASK 0x00003FFF
    #define ENC_FULL_COUNT_VALUE_SHIFT 0
#define  ENC_FWD_C_ADR 0x7408
    #define ENC_FWD_C_ADR_BASE_MASK 0x0FFFE000
    #define ENC_FWD_C_ADR_BASE_SHIFT 13
#define  ENC_FWD_Y_ADR 0x7404
    #define ENC_FWD_Y_ADR_BASE_MASK 0x0FFFE000
    #define ENC_FWD_Y_ADR_BASE_SHIFT 13
#define  ENC_INTRA_COUNT 0x72B8
    #define ENC_INTRA_COUNT_VALUE_MASK 0x00003FFF
    #define ENC_INTRA_COUNT_VALUE_SHIFT 0
#define  ENC_MVA_ADR 0x7414
    #define ENC_MVA_ADR_BASE_MASK 0x0FFFFC00
    #define ENC_MVA_ADR_BASE_SHIFT 10
#define  ENC_MVA_IDX_ADR 0x7418
    #define ENC_MVA_IDX_ADR_BASE_MASK 0x0FFFFC00
    #define ENC_MVA_IDX_ADR_BASE_SHIFT 10
#define  ENC_MV_SCALE 0x73EC
    #define ENC_MV_SCALE_MV_SCL_X_MASK 0x0000FFFF
    #define ENC_MV_SCALE_MV_SCL_X_SHIFT 0
    #define ENC_MV_SCALE_MV_SCL_Y_MASK 0xFFFF0000
    #define ENC_MV_SCALE_MV_SCL_Y_SHIFT 16
#define  ENC_PART_COUNT 0x72C4
    #define ENC_PART_COUNT_VALUE_MASK 0x00003FFF
    #define ENC_PART_COUNT_VALUE_SHIFT 0
#define  ENC_PICT_INFO 0x73E0
    #define ENC_PICT_INFO_PICT_TYPE_MASK 0x00000003
    #define ENC_PICT_INFO_PICT_TYPE_SHIFT 0
    #define ENC_PICT_INFO_PICT_STRUCT_MASK 0x0000000C
    #define ENC_PICT_INFO_PICT_STRUCT_SHIFT 2
    #define ENC_PICT_INFO_MPEG_FRMT_MASK 0x00000030
    #define ENC_PICT_INFO_MPEG_FRMT_SHIFT 4
    #define CHROMA_ROUNDING_MASK 0x00000040
    #define CHROMA_ROUNDING_SHIFT 6
    #define ENC_PICT_INFO_SECOND_FLD_MASK 0x80000000
    #define ENC_PICT_INFO_SECOND_FLD_SHIFT 31
#define  ENC_PICT_SIZE 0x73E4
    #define ENC_PICT_SIZE_SLICE_SIZE_MASK 0x0000007F
    #define ENC_PICT_SIZE_SLICE_SIZE_SHIFT 0
    #define ENC_PICT_SIZE_SLICE_CNT_MASK 0x00007F00
    #define ENC_PICT_SIZE_SLICE_CNT_SHIFT 8
#define  ENC_QMATRIX_0_3_INTRA 0x7180
    #define ENC_QM0_INT_MASK 0x000000FF
    #define ENC_QM0_INT_SHIFT 0
    #define ENC_QM1_INT_MASK 0x0000FF00
    #define ENC_QM1_INT_SHIFT 8
    #define ENC_QM2_INT_MASK 0x00FF0000
    #define ENC_QM2_INT_SHIFT 16
    #define ENC_QM3_INT_MASK 0xFF000000
    #define ENC_QM3_INT_SHIFT 24
#define  ENC_QMATRIX_0_3_NONINT 0x71C0
    #define ENC_QM0_NONINT_MASK 0x000000FF
    #define ENC_QM0_NONINT_SHIFT 0
    #define ENC_QM1_NONINT_MASK 0x0000FF00
    #define ENC_QM1_NONINT_SHIFT 8
    #define ENC_QM2_NONINT_MASK 0x00FF0000
    #define ENC_QM2_NONINT_SHIFT 16
    #define ENC_QM3_NONINT_MASK 0xFF000000
    #define ENC_QM3_NONINT_SHIFT 24
#define  ENC_QMATRIX_12_15_INTRA 0x718C
    #define ENC_QM12_INT_MASK 0x000000FF
    #define ENC_QM12_INT_SHIFT 0
    #define ENC_QM13_INT_MASK 0x0000FF00
    #define ENC_QM13_INT_SHIFT 8
    #define ENC_QM14_INT_MASK 0x00FF0000
    #define ENC_QM14_INT_SHIFT 16
    #define ENC_QM15_INT_MASK 0xFF000000
    #define ENC_QM15_INT_SHIFT 24
#define  ENC_QMATRIX_12_15_NONINT 0x71CC
    #define ENC_QM12_NONINT_MASK 0x000000FF
    #define ENC_QM12_NONINT_SHIFT 0
    #define ENC_QM13_NONINT_MASK 0x0000FF00
    #define ENC_QM13_NONINT_SHIFT 8
    #define ENC_QM14_NONINT_MASK 0x00FF0000
    #define ENC_QM14_NONINT_SHIFT 16
    #define ENC_QM15_NONINT_MASK 0xFF000000
    #define ENC_QM15_NONINT_SHIFT 24
#define  ENC_QMATRIX_16_19_INTRA 0x7190
    #define ENC_QM16_INT_MASK 0x000000FF
    #define ENC_QM16_INT_SHIFT 0
    #define ENC_QM17_INT_MASK 0x0000FF00
    #define ENC_QM17_INT_SHIFT 8
    #define ENC_QM18_INT_MASK 0x00FF0000
    #define ENC_QM18_INT_SHIFT 16
    #define ENC_QM19_INT_MASK 0xFF000000
    #define ENC_QM19_INT_SHIFT 24
#define  ENC_QMATRIX_16_19_NONINT 0x71D0
    #define ENC_QM16_NONINT_MASK 0x000000FF
    #define ENC_QM16_NONINT_SHIFT 0
    #define ENC_QM17_NONINT_MASK 0x0000FF00
    #define ENC_QM17_NONINT_SHIFT 8
    #define ENC_QM18_NONINT_MASK 0x00FF0000
    #define ENC_QM18_NONINT_SHIFT 16
    #define ENC_QM19_NONINT_MASK 0xFF000000
    #define ENC_QM19_NONINT_SHIFT 24
#define  ENC_QMATRIX_20_23_INTRA 0x7194
    #define ENC_QM20_INT_MASK 0x000000FF
    #define ENC_QM20_INT_SHIFT 0
    #define ENC_QM21_INT_MASK 0x0000FF00
    #define ENC_QM21_INT_SHIFT 8
    #define ENC_QM22_INT_MASK 0x00FF0000
    #define ENC_QM22_INT_SHIFT 16
    #define ENC_QM23_INT_MASK 0xFF000000
    #define ENC_QM23_INT_SHIFT 24
#define  ENC_QMATRIX_20_23_NONINT 0x71D4
    #define ENC_QM20_NONINT_MASK 0x000000FF
    #define ENC_QM20_NONINT_SHIFT 0
    #define ENC_QM21_NONINT_MASK 0x0000FF00
    #define ENC_QM21_NONINT_SHIFT 8
    #define ENC_QM22_NONINT_MASK 0x00FF0000
    #define ENC_QM22_NONINT_SHIFT 16
    #define ENC_QM23_NONINT_MASK 0xFF000000
    #define ENC_QM23_NONINT_SHIFT 24
#define  ENC_QMATRIX_24_27_INTRA 0x7198
    #define ENC_QM24_INT_MASK 0x000000FF
    #define ENC_QM24_INT_SHIFT 0
    #define ENC_QM25_INT_MASK 0x0000FF00
    #define ENC_QM25_INT_SHIFT 8
    #define ENC_QM26_INT_MASK 0x00FF0000
    #define ENC_QM26_INT_SHIFT 16
    #define ENC_QM27_INT_MASK 0xFF000000
    #define ENC_QM27_INT_SHIFT 24
#define  ENC_QMATRIX_24_27_NONINT 0x71D8
    #define ENC_QM24_NONINT_MASK 0x000000FF
    #define ENC_QM24_NONINT_SHIFT 0
    #define ENC_QM25_NONINT_MASK 0x0000FF00
    #define ENC_QM25_NONINT_SHIFT 8
    #define ENC_QM26_NONINT_MASK 0x00FF0000
    #define ENC_QM26_NONINT_SHIFT 16
    #define ENC_QM27_NONINT_MASK 0xFF000000
    #define ENC_QM27_NONINT_SHIFT 24
#define  ENC_QMATRIX_28_31_INTRA 0x719C
    #define ENC_QM28_INT_MASK 0x000000FF
    #define ENC_QM28_INT_SHIFT 0
    #define ENC_QM29_INT_MASK 0x0000FF00
    #define ENC_QM29_INT_SHIFT 8
    #define ENC_QM30_INT_MASK 0x00FF0000
    #define ENC_QM30_INT_SHIFT 16
    #define ENC_QM31_INT_MASK 0xFF000000
    #define ENC_QM31_INT_SHIFT 24
#define  ENC_QMATRIX_28_31_NONINT 0x71DC
    #define ENC_QM28_NONINT_MASK 0x000000FF
    #define ENC_QM28_NONINT_SHIFT 0
    #define ENC_QM29_NONINT_MASK 0x0000FF00
    #define ENC_QM29_NONINT_SHIFT 8
    #define ENC_QM30_NONINT_MASK 0x00FF0000
    #define ENC_QM30_NONINT_SHIFT 16
    #define ENC_QM31_NONINT_MASK 0xFF000000
    #define ENC_QM31_NONINT_SHIFT 24
#define  ENC_QMATRIX_32_35_INTRA 0x71A0
    #define ENC_QM32_INT_MASK 0x000000FF
    #define ENC_QM32_INT_SHIFT 0
    #define ENC_QM33_INT_MASK 0x0000FF00
    #define ENC_QM33_INT_SHIFT 8
    #define ENC_QM34_INT_MASK 0x00FF0000
    #define ENC_QM34_INT_SHIFT 16
    #define ENC_QM35_INT_MASK 0xFF000000
    #define ENC_QM35_INT_SHIFT 24
#define  ENC_QMATRIX_32_35_NONINT 0x71E0
    #define ENC_QM32_NONINT_MASK 0x000000FF
    #define ENC_QM32_NONINT_SHIFT 0
    #define ENC_QM33_NONINT_MASK 0x0000FF00
    #define ENC_QM33_NONINT_SHIFT 8
    #define ENC_QM34_NONINT_MASK 0x00FF0000
    #define ENC_QM34_NONINT_SHIFT 16
    #define ENC_QM35_NONINT_MASK 0xFF000000
    #define ENC_QM35_NONINT_SHIFT 24
#define  ENC_QMATRIX_36_39_INTRA 0x71A4
    #define ENC_QM36_INT_MASK 0x000000FF
    #define ENC_QM36_INT_SHIFT 0
    #define ENC_QM37_INT_MASK 0x0000FF00
    #define ENC_QM37_INT_SHIFT 8
    #define ENC_QM38_INT_MASK 0x00FF0000
    #define ENC_QM38_INT_SHIFT 16
    #define ENC_QM39_INT_MASK 0xFF000000
    #define ENC_QM39_INT_SHIFT 24
#define  ENC_QMATRIX_36_39_NONINT 0x71E4
    #define ENC_QM36_NONINT_MASK 0x000000FF
    #define ENC_QM36_NONINT_SHIFT 0
    #define ENC_QM37_NONINT_MASK 0x0000FF00
    #define ENC_QM37_NONINT_SHIFT 8
    #define ENC_QM38_NONINT_MASK 0x00FF0000
    #define ENC_QM38_NONINT_SHIFT 16
    #define ENC_QM39_NONINT_MASK 0xFF000000
    #define ENC_QM39_NONINT_SHIFT 24
#define  ENC_QMATRIX_40_43_INTRA 0x71A8
    #define ENC_QM40_INT_MASK 0x000000FF
    #define ENC_QM40_INT_SHIFT 0
    #define ENC_QM41_INT_MASK 0x0000FF00
    #define ENC_QM41_INT_SHIFT 8
    #define ENC_QM42_INT_MASK 0x00FF0000
    #define ENC_QM42_INT_SHIFT 16
    #define ENC_QM43_INT_MASK 0xFF000000
    #define ENC_QM43_INT_SHIFT 24
#define  ENC_QMATRIX_40_43_NONINT 0x71E8
    #define ENC_QM40_NONINT_MASK 0x000000FF
    #define ENC_QM40_NONINT_SHIFT 0
    #define ENC_QM41_NONINT_MASK 0x0000FF00
    #define ENC_QM41_NONINT_SHIFT 8
    #define ENC_QM42_NONINT_MASK 0x00FF0000
    #define ENC_QM42_NONINT_SHIFT 16
    #define ENC_QM43_NONINT_MASK 0xFF000000
    #define ENC_QM43_NONINT_SHIFT 24
#define  ENC_QMATRIX_44_47_INTRA 0x71AC
    #define ENC_QM44_INT_MASK 0x000000FF
    #define ENC_QM44_INT_SHIFT 0
    #define ENC_QM45_INT_MASK 0x0000FF00
    #define ENC_QM45_INT_SHIFT 8
    #define ENC_QM46_INT_MASK 0x00FF0000
    #define ENC_QM46_INT_SHIFT 16
    #define ENC_QM47_INT_MASK 0xFF000000
    #define ENC_QM47_INT_SHIFT 24
#define  ENC_QMATRIX_44_47_NONINT 0x71EC
    #define ENC_QM44_NONINT_MASK 0x000000FF
    #define ENC_QM44_NONINT_SHIFT 0
    #define ENC_QM45_NONINT_MASK 0x0000FF00
    #define ENC_QM45_NONINT_SHIFT 8
    #define ENC_QM46_NONINT_MASK 0x00FF0000
    #define ENC_QM46_NONINT_SHIFT 16
    #define ENC_QM47_NONINT_MASK 0xFF000000
    #define ENC_QM47_NONINT_SHIFT 24
#define  ENC_QMATRIX_48_51_INTRA 0x71B0
    #define ENC_QM48_INT_MASK 0x000000FF
    #define ENC_QM48_INT_SHIFT 0
    #define ENC_QM49_INT_MASK 0x0000FF00
    #define ENC_QM49_INT_SHIFT 8
    #define ENC_QM50_INT_MASK 0x00FF0000
    #define ENC_QM50_INT_SHIFT 16
    #define ENC_QM51_INT_MASK 0xFF000000
    #define ENC_QM51_INT_SHIFT 24
#define  ENC_QMATRIX_48_51_NONINT 0x71F0
    #define ENC_QM48_NONINT_MASK 0x000000FF
    #define ENC_QM48_NONINT_SHIFT 0
    #define ENC_QM49_NONINT_MASK 0x0000FF00
    #define ENC_QM49_NONINT_SHIFT 8
    #define ENC_QM50_NONINT_MASK 0x00FF0000
    #define ENC_QM50_NONINT_SHIFT 16
    #define ENC_QM51_NONINT_MASK 0xFF000000
    #define ENC_QM51_NONINT_SHIFT 24
#define  ENC_QMATRIX_4_7_INTRA 0x7184
    #define ENC_QM4_INT_MASK 0x000000FF
    #define ENC_QM4_INT_SHIFT 0
    #define ENC_QM5_INT_MASK 0x0000FF00
    #define ENC_QM5_INT_SHIFT 8
    #define ENC_QM6_INT_MASK 0x00FF0000
    #define ENC_QM6_INT_SHIFT 16
    #define ENC_QM7_INT_MASK 0xFF000000
    #define ENC_QM7_INT_SHIFT 24
#define  ENC_QMATRIX_4_7_NONINT 0x71C4
    #define ENC_QM4_NONINT_MASK 0x000000FF
    #define ENC_QM4_NONINT_SHIFT 0
    #define ENC_QM5_NONINT_MASK 0x0000FF00
    #define ENC_QM5_NONINT_SHIFT 8
    #define ENC_QM6_NONINT_MASK 0x00FF0000
    #define ENC_QM6_NONINT_SHIFT 16
    #define ENC_QM7_NONINT_MASK 0xFF000000
    #define ENC_QM7_NONINT_SHIFT 24
#define  ENC_QMATRIX_52_55_INTRA 0x71B4
    #define ENC_QM52_INT_MASK 0x000000FF
    #define ENC_QM52_INT_SHIFT 0
    #define ENC_QM53_INT_MASK 0x0000FF00
    #define ENC_QM53_INT_SHIFT 8
    #define ENC_QM54_INT_MASK 0x00FF0000
    #define ENC_QM54_INT_SHIFT 16
    #define ENC_QM55_INT_MASK 0xFF000000
    #define ENC_QM55_INT_SHIFT 24
#define  ENC_QMATRIX_52_55_NONINT 0x71F4
    #define ENC_QM52_NONINT_MASK 0x000000FF
    #define ENC_QM52_NONINT_SHIFT 0
    #define ENC_QM53_NONINT_MASK 0x0000FF00
    #define ENC_QM53_NONINT_SHIFT 8
    #define ENC_QM54_NONINT_MASK 0x00FF0000
    #define ENC_QM54_NONINT_SHIFT 16
    #define ENC_QM55_NONINT_MASK 0xFF000000
    #define ENC_QM55_NONINT_SHIFT 24
#define  ENC_QMATRIX_56_59_INTRA 0x71B8
    #define ENC_QM56_INT_MASK 0x000000FF
    #define ENC_QM56_INT_SHIFT 0
    #define ENC_QM57_INT_MASK 0x0000FF00
    #define ENC_QM57_INT_SHIFT 8
    #define ENC_QM58_INT_MASK 0x00FF0000
    #define ENC_QM58_INT_SHIFT 16
    #define ENC_QM59_INT_MASK 0xFF000000
    #define ENC_QM59_INT_SHIFT 24
#define  ENC_QMATRIX_56_59_NONINT 0x71F8
    #define ENC_QM56_NONINT_MASK 0x000000FF
    #define ENC_QM56_NONINT_SHIFT 0
    #define ENC_QM57_NONINT_MASK 0x0000FF00
    #define ENC_QM57_NONINT_SHIFT 8
    #define ENC_QM58_NONINT_MASK 0x00FF0000
    #define ENC_QM58_NONINT_SHIFT 16
    #define ENC_QM59_NONINT_MASK 0xFF000000
    #define ENC_QM59_NONINT_SHIFT 24
#define  ENC_QMATRIX_60_63_INTRA 0x71BC
    #define ENC_QM60_INT_MASK 0x000000FF
    #define ENC_QM60_INT_SHIFT 0
    #define ENC_QM61_INT_MASK 0x0000FF00
    #define ENC_QM61_INT_SHIFT 8
    #define ENC_QM62_INT_MASK 0x00FF0000
    #define ENC_QM62_INT_SHIFT 16
    #define ENC_QM63_INT_MASK 0xFF000000
    #define ENC_QM63_INT_SHIFT 24
#define  ENC_QMATRIX_60_63_NONINT 0x71FC
    #define ENC_QM60_NONINT_MASK 0x000000FF
    #define ENC_QM60_NONINT_SHIFT 0
    #define ENC_QM61_NONINT_MASK 0x0000FF00
    #define ENC_QM61_NONINT_SHIFT 8
    #define ENC_QM62_NONINT_MASK 0x00FF0000
    #define ENC_QM62_NONINT_SHIFT 16
    #define ENC_QM63_NONINT_MASK 0xFF000000
    #define ENC_QM63_NONINT_SHIFT 24
#define  ENC_QMATRIX_8_11_INTRA 0x7188
    #define ENC_QM8_INT_MASK 0x000000FF
    #define ENC_QM8_INT_SHIFT 0
    #define ENC_QM9_INT_MASK 0x0000FF00
    #define ENC_QM9_INT_SHIFT 8
    #define ENC_QM10_INT_MASK 0x00FF0000
    #define ENC_QM10_INT_SHIFT 16
    #define ENC_QM11_INT_MASK 0xFF000000
    #define ENC_QM11_INT_SHIFT 24
#define  ENC_QMATRIX_8_11_NONINT 0x71C8
    #define ENC_QM8_NONINT_MASK 0x000000FF
    #define ENC_QM8_NONINT_SHIFT 0
    #define ENC_QM9_NONINT_MASK 0x0000FF00
    #define ENC_QM9_NONINT_SHIFT 8
    #define ENC_QM10_NONINT_MASK 0x00FF0000
    #define ENC_QM10_NONINT_SHIFT 16
    #define ENC_QM11_NONINT_MASK 0xFF000000
    #define ENC_QM11_NONINT_SHIFT 24
#define  ENC_RARB_CTRL 0x74B0
    #define ENC_RARB_CTRL_CL0_TIMER_MASK 0x0000000F
    #define ENC_RARB_CTRL_CL0_TIMER_SHIFT 0
    #define ENC_RARB_CTRL_CL1_TIMER_MASK 0x000000F0
    #define ENC_RARB_CTRL_CL1_TIMER_SHIFT 4
    #define ENC_RARB_CTRL_CL2_TIMER_MASK 0x00000F00
    #define ENC_RARB_CTRL_CL2_TIMER_SHIFT 8
    #define ENC_RARB_CTRL_CL3_TIMER_MASK 0x0000F000
    #define ENC_RARB_CTRL_CL3_TIMER_SHIFT 12
    #define ENC_RARB_CTRL_CL4_TIMER_MASK 0x000F0000
    #define ENC_RARB_CTRL_CL4_TIMER_SHIFT 16
    #define ENC_RARB_CTRL_CL5_TIMER_MASK 0x00F00000
    #define ENC_RARB_CTRL_CL5_TIMER_SHIFT 20
    #define ENC_RARB_CTRL_CL6_TIMER_MASK 0x0F000000
    #define ENC_RARB_CTRL_CL6_TIMER_SHIFT 24
    #define ENC_RARB_CTRL_CL7_TIMER_MASK 0xF0000000
    #define ENC_RARB_CTRL_CL7_TIMER_SHIFT 28
#define  ENC_STATION_COUNT 0x72BC
    #define ENC_STATION_COUNT_VALUE_MASK 0x00003FFF
    #define ENC_STATION_COUNT_VALUE_SHIFT 0
#define  ENC_SURF_SIZE 0x73E8
    #define ENC_SURF_SIZE_PITCH_MASK 0x00000FC0
    #define ENC_SURF_SIZE_PITCH_SHIFT 6
#define  ENC_WARB_CTRL 0x74B4
    #define ENC_WARB_CTRL_CL0_TIMER_MASK 0x0000000F
    #define ENC_WARB_CTRL_CL0_TIMER_SHIFT 0
    #define ENC_WARB_CTRL_CL1_TIMER_MASK 0x000000F0
    #define ENC_WARB_CTRL_CL1_TIMER_SHIFT 4
    #define ENC_WARB_CTRL_CL2_TIMER_MASK 0x00000F00
    #define ENC_WARB_CTRL_CL2_TIMER_SHIFT 8
#define  ENGCTRL_CUR_ADR 0x7094
    #define ENGCTRL_CUR_BASE_MASK 0x00000FFC
    #define ENGCTRL_CUR_BASE_SHIFT 2
#define  ENGCTRL_CUR_DATA 0x7098
    #define ENGCTRL_CUR_DATA_MASK 0xFFFFFFFF
    #define ENGCTRL_CUR_DATA_SHIFT 0
#define  ENGCTRL_REG_CHAIN 0x709C
    #define REGBUS_SETTLE_SEL_MASK 0x00000007
    #define REGBUS_SETTLE_SEL_SHIFT 0
#define  ETH_CSR_CTRL_REG 0x2800
    #define ETH_CSR_CTRL_REG_ADDR_MASK 0x00001FFC
    #define ETH_CSR_CTRL_REG_ADDR_SHIFT 2
    #define ETH_CSR_CTRL_REG_WOP_MASK 0x80000000
    #define ETH_CSR_CTRL_REG_WOP_SHIFT 31
#define  ETH_CSR_CTRL_REG1 0x2C00
    #define ADDR1_MASK 0x00001FFC
    #define ADDR1_SHIFT 2
    #define WOP1_MASK 0x80000000
    #define WOP1_SHIFT 31
#define  ETH_CTRL_REG 0x2810
    #define ETH_CTRL_REG_RESETN_MASK 0x00000001
    #define ETH_CTRL_REG_RESETN_SHIFT 0
    #define TX_NEGEDGE_MASK 0x00000002
    #define TX_NEGEDGE_SHIFT 1
    #define RX_NEGEDGE_MASK 0x00000004
    #define RX_NEGEDGE_SHIFT 2
    #define SBD_FLOWCTRL_MASK 0x00000008
    #define SBD_FLOWCTRL_SHIFT 3
    #define ETH_CTRL_REG_EXT_MEM_ARB_TIMER_MASK 0x000000F0
    #define ETH_CTRL_REG_EXT_MEM_ARB_TIMER_SHIFT 4
#define  ETH_CTRL_REG1 0x2C10
    #define RESETN1_MASK 0x00000001
    #define RESETN1_SHIFT 0
    #define TX_NEGEDGE1_MASK 0x00000002
    #define TX_NEGEDGE1_SHIFT 1
    #define RX_NEGEDGE1_MASK 0x00000004
    #define RX_NEGEDGE1_SHIFT 2
    #define SBD_FLOWCTRL1_MASK 0x00000008
    #define SBD_FLOWCTRL1_SHIFT 3
    #define EXT_MEM_ARB_TIMER1_MASK 0x000000F0
    #define EXT_MEM_ARB_TIMER1_SHIFT 4
#define  ETH_DUMMY_REG 0x2820
    #define ETH_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define ETH_DUMMY_REG_DATA_SHIFT 0
#define  ETH_DUMMY_REG1 0x2C20
    #define ETH_DUMMY_REG1_DATA_MASK 0xFFFFFFFF
    #define ETH_DUMMY_REG1_DATA_SHIFT 0
#define  ETH_HOST_INT_MASK_REG 0x2818
    #define ETH_HOST_INT_MASK_REG_PMT_INTR_EN_MASK 0x00000001
    #define ETH_HOST_INT_MASK_REG_PMT_INTR_EN_SHIFT 0
    #define ETH_HOST_INT_MASK_REG_SBD_INTR_EN_MASK 0x00000002
    #define ETH_HOST_INT_MASK_REG_SBD_INTR_EN_SHIFT 1
#define  ETH_HOST_INT_MASK_REG1 0x2C18
    #define ETH_HOST_INT_MASK_REG1_PMT_INTR_EN1_MASK 0x00000001
    #define ETH_HOST_INT_MASK_REG1_PMT_INTR_EN1_SHIFT 0
    #define ETH_HOST_INT_MASK_REG1_SBD_INTR_EN1_MASK 0x00000002
    #define ETH_HOST_INT_MASK_REG1_SBD_INTR_EN1_SHIFT 1
#define  ETH_INT_STATUS_REG 0x2814
    #define PMT_INTR_STATUS_MASK 0x00000001
    #define PMT_INTR_STATUS_SHIFT 0
    #define SBD_INTR_STATUS_MASK 0x00000002
    #define SBD_INTR_STATUS_SHIFT 1
#define  ETH_INT_STATUS_REG1 0x2C14
    #define PMT_INTR_STATUS1_MASK 0x00000001
    #define PMT_INTR_STATUS1_SHIFT 0
    #define SBD_INTR_STATUS1_MASK 0x00000002
    #define SBD_INTR_STATUS1_SHIFT 1
#define  ETH_MIPS_INT_MASK_REG 0x281C
    #define ETH_MIPS_INT_MASK_REG_PMT_INTR_EN_MASK 0x00000001
    #define ETH_MIPS_INT_MASK_REG_PMT_INTR_EN_SHIFT 0
    #define ETH_MIPS_INT_MASK_REG_SBD_INTR_EN_MASK 0x00000002
    #define ETH_MIPS_INT_MASK_REG_SBD_INTR_EN_SHIFT 1
#define  ETH_MIPS_INT_MASK_REG1 0x2C1C
    #define ETH_MIPS_INT_MASK_REG1_PMT_INTR_EN1_MASK 0x00000001
    #define ETH_MIPS_INT_MASK_REG1_PMT_INTR_EN1_SHIFT 0
    #define ETH_MIPS_INT_MASK_REG1_SBD_INTR_EN1_MASK 0x00000002
    #define ETH_MIPS_INT_MASK_REG1_SBD_INTR_EN1_SHIFT 1
#define  ETH_RDAT_REG 0x280C
    #define READ_MASK 0xFFFFFFFF
    #define READ_SHIFT 0
#define  ETH_RDAT_REG1 0x2C0C
    #define READ1_MASK 0xFFFFFFFF
    #define READ1_SHIFT 0
#define  ETH_STATUS_REG 0x2804
    #define CSR_BUSY_MASK 0x00000001
    #define CSR_BUSY_SHIFT 0
#define  ETH_STATUS_REG1 0x2C04
    #define CSR_BUSY1_MASK 0x00000001
    #define CSR_BUSY1_SHIFT 0
#define  ETH_WDAT_REG 0x2808
    #define WRITE_MASK 0xFFFFFFFF
    #define WRITE_SHIFT 0
#define  ETH_WDAT_REG1 0x2C08
    #define WRITE_DATA1_MASK 0xFFFFFFFF
    #define WRITE_DATA1_SHIFT 0
#define  GPIO_A_CTRL 0xFC0C
    #define GPIO_A_CTRL_HOST_INT_MASK_MASK 0x00000001
    #define GPIO_A_CTRL_HOST_INT_MASK_SHIFT 0
    #define GPIO_A_CTRL_MIPS_INT_MASK_MASK 0x00000002
    #define GPIO_A_CTRL_MIPS_INT_MASK_SHIFT 1
    #define GPIO_A_CTRL_GPIO_MODE_SEL_MASK 0xE0000000
    #define GPIO_A_CTRL_GPIO_MODE_SEL_SHIFT 29
#define  GPIO_A_IN 0xFC00
    #define GPIO_A_IN_GPIO_IN_MASK 0xFFFFFFFF
    #define GPIO_A_IN_GPIO_IN_SHIFT 0
#define  GPIO_A_OE 0xFC08
    #define GPIO_A_OE_GPIO_OE_MASK 0xFFFFFFFF
    #define GPIO_A_OE_GPIO_OE_SHIFT 0
#define  GPIO_A_OUT 0xFC04
    #define GPIO_A_OUT_GPIO_OUT_MASK 0xFFFFFFFF
    #define GPIO_A_OUT_GPIO_OUT_SHIFT 0
#define  GPIO_B_CTRL 0xFC1C
    #define GPIO_B_CTRL_HOST_INT_MASK_MASK 0x00000001
    #define GPIO_B_CTRL_HOST_INT_MASK_SHIFT 0
    #define GPIO_B_CTRL_MIPS_INT_MASK_MASK 0x00000002
    #define GPIO_B_CTRL_MIPS_INT_MASK_SHIFT 1
    #define GPIO_B_CTRL_GPIO_MODE_SEL_MASK 0x80000000
    #define GPIO_B_CTRL_GPIO_MODE_SEL_SHIFT 31
#define  GPIO_B_IN 0xFC10
    #define GPIO_B_IN_GPIO_IN_MASK 0x0000FFFF
    #define GPIO_B_IN_GPIO_IN_SHIFT 0
#define  GPIO_B_OE 0xFC18
    #define GPIO_B_OE_GPIO_OE_MASK 0x0000FFFF
    #define GPIO_B_OE_GPIO_OE_SHIFT 0
#define  GPIO_B_OUT 0xFC14
    #define GPIO_B_OUT_GPIO_OUT_MASK 0x0000FFFF
    #define GPIO_B_OUT_GPIO_OUT_SHIFT 0
#define  GPIO_C_CTRL 0xFC2C
    #define GPIO_C_CTRL_HOST_INT_MASK_MASK 0x00000001
    #define GPIO_C_CTRL_HOST_INT_MASK_SHIFT 0
    #define GPIO_C_CTRL_MIPS_INT_MASK_MASK 0x00000002
    #define GPIO_C_CTRL_MIPS_INT_MASK_SHIFT 1
    #define GPIO_C_CTRL_GPIO_MODE_SEL_MASK 0x80000000
    #define GPIO_C_CTRL_GPIO_MODE_SEL_SHIFT 31
#define  GPIO_C_IN 0xFC20
    #define GPIO_C_IN_GPIO_IN_MASK 0x0000FFFF
    #define GPIO_C_IN_GPIO_IN_SHIFT 0
#define  GPIO_C_OE 0xFC28
    #define GPIO_C_OE_GPIO_OE_MASK 0x0000FFFF
    #define GPIO_C_OE_GPIO_OE_SHIFT 0
#define  GPIO_C_OUT 0xFC24
    #define GPIO_C_OUT_GPIO_OUT_MASK 0x0000FFFF
    #define GPIO_C_OUT_GPIO_OUT_SHIFT 0
#define  GPIO_DEDICATED_IN 0x1108
    #define GPIO_DEDICATED_IN0_MASK 0x00000001
    #define GPIO_DEDICATED_IN0_SHIFT 0
    #define GPIO_DEDICATED_IN1_MASK 0x00000002
    #define GPIO_DEDICATED_IN1_SHIFT 1
    #define GPIO_DEDICATED_IN2_MASK 0x00000004
    #define GPIO_DEDICATED_IN2_SHIFT 2
    #define GPIO_DEDICATED_IN3_MASK 0x00000008
    #define GPIO_DEDICATED_IN3_SHIFT 3
    #define GPIO_DEDICATED_IN4_MASK 0x00000010
    #define GPIO_DEDICATED_IN4_SHIFT 4
    #define GPIO_DEDICATED_IN5_MASK 0x00000020
    #define GPIO_DEDICATED_IN5_SHIFT 5
    #define GPIO_DEDICATED_IN6_MASK 0x00000040
    #define GPIO_DEDICATED_IN6_SHIFT 6
    #define GPIO_DEDICATED_IN7_MASK 0x00000080
    #define GPIO_DEDICATED_IN7_SHIFT 7
#define  GPIO_DEDICATED_OUT 0x1100
    #define GPIO_DEDICATED_OUT0_MASK 0x00000001
    #define GPIO_DEDICATED_OUT0_SHIFT 0
    #define GPIO_DEDICATED_OUT1_MASK 0x00000002
    #define GPIO_DEDICATED_OUT1_SHIFT 1
    #define GPIO_DEDICATED_OUT2_MASK 0x00000004
    #define GPIO_DEDICATED_OUT2_SHIFT 2
    #define GPIO_DEDICATED_OUT3_MASK 0x00000008
    #define GPIO_DEDICATED_OUT3_SHIFT 3
    #define GPIO_DEDICATED_OUT4_MASK 0x00000010
    #define GPIO_DEDICATED_OUT4_SHIFT 4
    #define GPIO_DEDICATED_OUT5_MASK 0x00000020
    #define GPIO_DEDICATED_OUT5_SHIFT 5
    #define GPIO_DEDICATED_OUT6_MASK 0x00000040
    #define GPIO_DEDICATED_OUT6_SHIFT 6
    #define GPIO_DEDICATED_OUT7_MASK 0x00000080
    #define GPIO_DEDICATED_OUT7_SHIFT 7
#define  GPIO_DEDICATED_OUTEN 0x1104
    #define GPIO_DEDICATED_OUTEN0_MASK 0x00000001
    #define GPIO_DEDICATED_OUTEN0_SHIFT 0
    #define GPIO_DEDICATED_OUTEN1_MASK 0x00000002
    #define GPIO_DEDICATED_OUTEN1_SHIFT 1
    #define GPIO_DEDICATED_OUTEN2_MASK 0x00000004
    #define GPIO_DEDICATED_OUTEN2_SHIFT 2
    #define GPIO_DEDICATED_OUTEN3_MASK 0x00000008
    #define GPIO_DEDICATED_OUTEN3_SHIFT 3
    #define GPIO_DEDICATED_OUTEN4_MASK 0x00000010
    #define GPIO_DEDICATED_OUTEN4_SHIFT 4
    #define GPIO_DEDICATED_OUTEN5_MASK 0x00000020
    #define GPIO_DEDICATED_OUTEN5_SHIFT 5
    #define GPIO_DEDICATED_OUTEN6_MASK 0x00000040
    #define GPIO_DEDICATED_OUTEN6_SHIFT 6
    #define GPIO_DEDICATED_OUTEN7_MASK 0x00000080
    #define GPIO_DEDICATED_OUTEN7_SHIFT 7
#define  GPIO_D_CTRL 0xFC3C
    #define GPIO_D_CTRL_HOST_INT_MASK_MASK 0x00000001
    #define GPIO_D_CTRL_HOST_INT_MASK_SHIFT 0
    #define GPIO_D_CTRL_MIPS_INT_MASK_MASK 0x00000002
    #define GPIO_D_CTRL_MIPS_INT_MASK_SHIFT 1
    #define GPIO_D_CTRL_GPIO_MODE_SEL_MASK 0x80000000
    #define GPIO_D_CTRL_GPIO_MODE_SEL_SHIFT 31
#define  GPIO_D_IN 0xFC30
    #define GPIO_D_IN_GPIO_IN_MASK 0x000003FF
    #define GPIO_D_IN_GPIO_IN_SHIFT 0
#define  GPIO_D_OE 0xFC38
    #define GPIO_D_OE_GPIO_OE_MASK 0x000003FF
    #define GPIO_D_OE_GPIO_OE_SHIFT 0
#define  GPIO_D_OUT 0xFC34
    #define GPIO_D_OUT_GPIO_OUT_MASK 0x000003FF
    #define GPIO_D_OUT_GPIO_OUT_SHIFT 0
#define  GPIO_E_CTRL 0xFC4C
    #define GPIO_E_CTRL_HOST_INT_MASK_MASK 0x00000001
    #define GPIO_E_CTRL_HOST_INT_MASK_SHIFT 0
    #define GPIO_E_CTRL_MIPS_INT_MASK_MASK 0x00000002
    #define GPIO_E_CTRL_MIPS_INT_MASK_SHIFT 1
    #define GPIO_E_CTRL_GPIO_MODE_SEL_MASK 0x80000000
    #define GPIO_E_CTRL_GPIO_MODE_SEL_SHIFT 31
#define  GPIO_E_IN 0xFC40
    #define GPIO_E_IN_GPIO_IN_MASK 0x000003FF
    #define GPIO_E_IN_GPIO_IN_SHIFT 0
#define  GPIO_E_OE 0xFC48
    #define GPIO_E_OE_GPIO_OE_MASK 0x000003FF
    #define GPIO_E_OE_GPIO_OE_SHIFT 0
#define  GPIO_E_OUT 0xFC44
    #define GPIO_E_OUT_GPIO_OUT_MASK 0x000003FF
    #define GPIO_E_OUT_GPIO_OUT_SHIFT 0
#define  GPIO_F_CTRL 0xFC5C
    #define GPIO_F_CTRL_HOST_INT_MASK_MASK 0x00000001
    #define GPIO_F_CTRL_HOST_INT_MASK_SHIFT 0
    #define GPIO_F_CTRL_MIPS_INT_MASK_MASK 0x00000002
    #define GPIO_F_CTRL_MIPS_INT_MASK_SHIFT 1
    #define GPIO_F_CTRL_GPIO_MODE_SEL_MASK 0x80000000
    #define GPIO_F_CTRL_GPIO_MODE_SEL_SHIFT 31
#define  GPIO_F_IN 0xFC50
    #define GPIO_F_IN_GPIO_IN_MASK 0x000003FF
    #define GPIO_F_IN_GPIO_IN_SHIFT 0
#define  GPIO_F_OE 0xFC58
    #define GPIO_F_OE_GPIO_OE_MASK 0x000003FF
    #define GPIO_F_OE_GPIO_OE_SHIFT 0
#define  GPIO_F_OUT 0xFC54
    #define GPIO_F_OUT_GPIO_OUT_MASK 0x000003FF
    #define GPIO_F_OUT_GPIO_OUT_SHIFT 0
#define  GPIO_G_CTRL 0xFC6C
    #define GPIO_G_CTRL_HOST_INT_MASK_MASK 0x00000001
    #define GPIO_G_CTRL_HOST_INT_MASK_SHIFT 0
    #define GPIO_G_CTRL_MIPS_INT_MASK_MASK 0x00000002
    #define GPIO_G_CTRL_MIPS_INT_MASK_SHIFT 1
    #define GPIO_G_CTRL_GPIO_MODE_SEL_MASK 0x80000000
    #define GPIO_G_CTRL_GPIO_MODE_SEL_SHIFT 31
#define  GPIO_G_IN 0xFC60
    #define GPIO_G_IN_GPIO_IN_MASK 0x000003FF
    #define GPIO_G_IN_GPIO_IN_SHIFT 0
#define  GPIO_G_OE 0xFC68
    #define GPIO_G_OE_GPIO_OE_MASK 0x000003FF
    #define GPIO_G_OE_GPIO_OE_SHIFT 0
#define  GPIO_G_OUT 0xFC64
    #define GPIO_G_OUT_GPIO_OUT_MASK 0x000003FF
    #define GPIO_G_OUT_GPIO_OUT_SHIFT 0
#define  GPIO_H_CTRL 0xFC7C
    #define GPIO_H_CTRL_HOST_INT_MASK_MASK 0x00000001
    #define GPIO_H_CTRL_HOST_INT_MASK_SHIFT 0
    #define GPIO_H_CTRL_MIPS_INT_MASK_MASK 0x00000002
    #define GPIO_H_CTRL_MIPS_INT_MASK_SHIFT 1
    #define GPIO_H_CTRL_GPIO_MODE_SEL_MASK 0x80000000
    #define GPIO_H_CTRL_GPIO_MODE_SEL_SHIFT 31
#define  GPIO_H_IN 0xFC70
    #define GPIO_H_IN_GPIO_IN_MASK 0xFFFFFFFF
    #define GPIO_H_IN_GPIO_IN_SHIFT 0
#define  GPIO_H_OE 0xFC78
    #define GPIO_H_OE_GPIO_OE_MASK 0xFFFFFFFF
    #define GPIO_H_OE_GPIO_OE_SHIFT 0
#define  GPIO_H_OUT 0xFC74
    #define GPIO_H_OUT_GPIO_OUT_MASK 0xFFFFFFFF
    #define GPIO_H_OUT_GPIO_OUT_SHIFT 0
#define  GPIO_I_CTRL 0xFC8C
    #define GPIO_I_CTRL_HOST_INT_MASK_MASK 0x00000001
    #define GPIO_I_CTRL_HOST_INT_MASK_SHIFT 0
    #define GPIO_I_CTRL_MIPS_INT_MASK_MASK 0x00000002
    #define GPIO_I_CTRL_MIPS_INT_MASK_SHIFT 1
    #define GPIO_I_CTRL_GPIO_MODE_SEL_MASK 0xFF000000
    #define GPIO_I_CTRL_GPIO_MODE_SEL_SHIFT 24
#define  GPIO_I_IN 0xFC80
    #define GPIO_I_IN_GPIO_IN_MASK 0x0001FFFF
    #define GPIO_I_IN_GPIO_IN_SHIFT 0
#define  GPIO_I_OE 0xFC88
    #define GPIO_I_OE_GPIO_OE_MASK 0x0001FFFF
    #define GPIO_I_OE_GPIO_OE_SHIFT 0
#define  GPIO_I_OUT 0xFC84
    #define GPIO_I_OUT_GPIO_OUT_MASK 0x0001FFFF
    #define GPIO_I_OUT_GPIO_OUT_SHIFT 0
#define  GPIO_J_CTRL 0xFC9C
    #define GPIO_J_CTRL_HOST_INT_MASK_MASK 0x00000001
    #define GPIO_J_CTRL_HOST_INT_MASK_SHIFT 0
    #define GPIO_J_CTRL_MIPS_INT_MASK_MASK 0x00000002
    #define GPIO_J_CTRL_MIPS_INT_MASK_SHIFT 1
    #define GPIO_J_CTRL_GPIO_MODE_SEL_MASK 0xC0000000
    #define GPIO_J_CTRL_GPIO_MODE_SEL_SHIFT 30
#define  GPIO_J_IN 0xFC90
    #define GPIO_J_IN_GPIO_IN_MASK 0x0000003F
    #define GPIO_J_IN_GPIO_IN_SHIFT 0
#define  GPIO_J_OE 0xFC98
    #define GPIO_J_OE_GPIO_OE_MASK 0x0000003F
    #define GPIO_J_OE_GPIO_OE_SHIFT 0
#define  GPIO_J_OUT 0xFC94
    #define GPIO_J_OUT_GPIO_OUT_MASK 0x0000003F
    #define GPIO_J_OUT_GPIO_OUT_SHIFT 0
#define  GVD_CMD_FIFO_0 0x8810
    #define GVD_CMD_FIFO_0_DATA_MASK 0xFFFFFFFF
    #define GVD_CMD_FIFO_0_DATA_SHIFT 0
#define  GVD_CMD_FIFO_1 0x8814
    #define GVD_CMD_FIFO_1_VALUE_MASK 0x1FFFFFFF
    #define GVD_CMD_FIFO_1_VALUE_SHIFT 0
    #define GVD_CMD_MASK 0xE0000000
    #define GVD_CMD_SHIFT 29
#define  GVD_CMD_REGISTER 0x881C
    #define GVD_CMD_REGISTER_DATA_MASK 0xFFFFFFFF
    #define GVD_CMD_REGISTER_DATA_SHIFT 0
#define  GVD_CMD_STATUS 0x8818
    #define GVD_CMD_STATUS_FIFO_FREE_MASK 0x0000001F
    #define GVD_CMD_STATUS_FIFO_FREE_SHIFT 0
    #define GVD_DCP_BUSY_MASK 0x80000000
    #define GVD_DCP_BUSY_SHIFT 31
#define  GVD_CTRL 0x883C
    #define GVD_SETTLE_MASK 0x00000007
    #define GVD_SETTLE_SHIFT 0
#define  GVD_DBK_C0_OFFSET 0x894C
    #define GVD_DBK_C0_OFFSET_ALPHA_C0_OFFSET_DIV2_MASK 0x0000000F
    #define GVD_DBK_C0_OFFSET_ALPHA_C0_OFFSET_DIV2_SHIFT 0
    #define GVD_DBK_C0_OFFSET_BETA_C0_OFFSET_DIV2_MASK 0x00000F00
    #define GVD_DBK_C0_OFFSET_BETA_C0_OFFSET_DIV2_SHIFT 8
#define  GVD_DBK_CHROMA_QP_INDEX_OFFSET 0x8950
    #define GVD_DBK_CHROMA_QP_INDEX_OFFSET_CHROMA_QP_INDEX_OFFSET_MASK 0x0000001F
    #define GVD_DBK_CHROMA_QP_INDEX_OFFSET_CHROMA_QP_INDEX_OFFSET_SHIFT 0
    #define SECOND_CHROMA_QP_INDEX_OFFSET_MASK 0x00001F00
    #define SECOND_CHROMA_QP_INDEX_OFFSET_SHIFT 8
#define  GVD_DBK_CTRL 0x8944
    #define GVD_DBK_CTRL_DBK_BYPASS_MASK 0x00000001
    #define GVD_DBK_CTRL_DBK_BYPASS_SHIFT 0
    #define GVD_DBK_CTRL_DBK_DISABLE_MASK 0x00000002
    #define GVD_DBK_CTRL_DBK_DISABLE_SHIFT 1
    #define GVD_DBK_CTRL_DBK_REF_INDEX_MASK 0x00001F00
    #define GVD_DBK_CTRL_DBK_REF_INDEX_SHIFT 8
#define  GVD_DBK_DBG 0x8960
    #define GVD_DBK_DBG_DATA_MASK 0xFFFFFFFF
    #define GVD_DBK_DBG_DATA_SHIFT 0
#define  GVD_DBK_DBG_CTRL 0x895C
    #define GVD_DBK_DBG_CTRL_SEL_MASK 0x0000003F
    #define GVD_DBK_DBG_CTRL_SEL_SHIFT 0
    #define GVD_DBK_DBG_CTRL_MUX_MASK 0x00000F00
    #define GVD_DBK_DBG_CTRL_MUX_SHIFT 8
#define  GVD_DBK_DSQA0_LOAD 0x8954
    #define GVD_DBK_DSQA0_LOAD_DATA_MASK 0xFFFFFFFF
    #define GVD_DBK_DSQA0_LOAD_DATA_SHIFT 0
#define  GVD_DBK_DSQA1_LOAD 0x8958
    #define GVD_DBK_DSQA1_LOAD_DATA_MASK 0xFFFFFFFF
    #define GVD_DBK_DSQA1_LOAD_DATA_SHIFT 0
#define  GVD_DBK_START_MB 0x8940
    #define GVD_DBK_START_MB_START_MB_X_MASK 0x000000FF
    #define GVD_DBK_START_MB_START_MB_X_SHIFT 0
    #define GVD_DBK_START_MB_START_MB_Y_MASK 0x00007F00
    #define GVD_DBK_START_MB_START_MB_Y_SHIFT 8
#define  GVD_DBK_STATUS 0x8948
    #define GVD_DBK_STATUS_DBK_BUSY_MASK 0x00000001
    #define GVD_DBK_STATUS_DBK_BUSY_SHIFT 0
#define  GVD_DEBUG 0x8840
    #define GVD_DEBUG_DEBUG_MASK 0x000FFFFF
    #define GVD_DEBUG_DEBUG_SHIFT 0
#define  GVD_DMC_STATUS 0x88F0
    #define GVD_DMC_STATUS_MB_CNT_MASK 0x0007FFFF
    #define GVD_DMC_STATUS_MB_CNT_SHIFT 0
#define  GVD_EDC_BB_POP 0x8B9C
    #define BB_POP_MASK 0x0000000F
    #define BB_POP_SHIFT 0
#define  GVD_EDC_BB_STATUS 0x8B98
    #define BB_DAT_MASK 0x00FFFFFF
    #define BB_DAT_SHIFT 0
    #define BB_CNT_MASK 0x3F000000
    #define BB_CNT_SHIFT 24
#define  GVD_EDC_CMD 0x8B80
    #define GVD_EDC_CMD_SLICE_COUNT_MASK 0x000000FF
    #define GVD_EDC_CMD_SLICE_COUNT_SHIFT 0
#define  GVD_EDC_CONFIG 0x8B88
    #define BYTE_ALIGN_MASK 0x00000001
    #define BYTE_ALIGN_SHIFT 0
    #define BIT_ALIGN_MASK 0x00000002
    #define BIT_ALIGN_SHIFT 1
    #define PPS_CFG_MASK 0x0000000C
    #define PPS_CFG_SHIFT 2
    #define SPS_CFG_MASK 0x00000030
    #define SPS_CFG_SHIFT 4
    #define PTR_CFG_MASK 0x00000040
    #define PTR_CFG_SHIFT 6
    #define CONTINUE_MASK 0x00000100
    #define CONTINUE_SHIFT 8
    #define SLICES_ONLY_MASK 0x00000200
    #define SLICES_ONLY_SHIFT 9
    #define START_CODE_ONLY_MASK 0x00000400
    #define START_CODE_ONLY_SHIFT 10
    #define DISABLE_UVLC_END_MASK 0x00000800
    #define DISABLE_UVLC_END_SHIFT 11
    #define CTRL_FAST_MASK 0x00001000
    #define CTRL_FAST_SHIFT 12
    #define SELECT_MAX_FIFO_MASK 0x00002000
    #define SELECT_MAX_FIFO_SHIFT 13
    #define BB_DISABLE_PTR_WRAP_MASK 0x00004000
    #define BB_DISABLE_PTR_WRAP_SHIFT 14
    #define RBSP_SLOW_MASK 0x00008000
    #define RBSP_SLOW_SHIFT 15
    #define RBSP_LAST_MB_MASK 0x00010000
    #define RBSP_LAST_MB_SHIFT 16
    #define DISABLE_FORCE_EPB_MASK 0x00020000
    #define DISABLE_FORCE_EPB_SHIFT 17
    #define DISABLE_SC_GIVEUP_MASK 0x00040000
    #define DISABLE_SC_GIVEUP_SHIFT 18
    #define DISABLE_SC_FORCE_POP_MASK 0x00080000
    #define DISABLE_SC_FORCE_POP_SHIFT 19
    #define DISABLE_BB_BIT_PULL_MASK 0x00100000
    #define DISABLE_BB_BIT_PULL_SHIFT 20
    #define DISABLE_BB_PCM_PULL_MASK 0x00200000
    #define DISABLE_BB_PCM_PULL_SHIFT 21
    #define NOSTOP_ON_RPTR_MASK 0x00400000
    #define NOSTOP_ON_RPTR_SHIFT 22
    #define RUN_CABAC_TEST_MASK 0x00800000
    #define RUN_CABAC_TEST_SHIFT 23
    #define NOFLUSH_SLICE_CONT_MASK 0x01000000
    #define NOFLUSH_SLICE_CONT_SHIFT 24
    #define INPUT_END_MODE_MASK 0x02000000
    #define INPUT_END_MODE_SHIFT 25
    #define CONT_ON_IL_ERR_MASK 0x04000000
    #define CONT_ON_IL_ERR_SHIFT 26
    #define CONT_ON_SC_ERR_MASK 0x08000000
    #define CONT_ON_SC_ERR_SHIFT 27
    #define CONT_ON_MB_ERR_MASK 0x10000000
    #define CONT_ON_MB_ERR_SHIFT 28
    #define CONT_ON_PPSSPS_ERR_MASK 0x20000000
    #define CONT_ON_PPSSPS_ERR_SHIFT 29
    #define CONT_ON_BB_ERR_MASK 0x40000000
    #define CONT_ON_BB_ERR_SHIFT 30
    #define CONT_ON_OTHER_ERR_MASK 0x80000000
    #define CONT_ON_OTHER_ERR_SHIFT 31
#define  GVD_EDC_CONFIG2 0x8BB4
    #define EPB_COUNT_MODE_MASK 0x00000001
    #define EPB_COUNT_MODE_SHIFT 0
    #define RBSP_VERIFY_EPB_MASK 0x00000006
    #define RBSP_VERIFY_EPB_SHIFT 1
    #define RBSP_VERIFY_MODE_MASK 0x00000008
    #define RBSP_VERIFY_MODE_SHIFT 3
    #define BB_CONSERVATIVE_MASK 0x00000040
    #define BB_CONSERVATIVE_SHIFT 6
    #define BB_CONSERVATIVE_END_MASK 0x00000080
    #define BB_CONSERVATIVE_END_SHIFT 7
    #define DISABLE_STOP_ON_ID_MASK 0x00000100
    #define DISABLE_STOP_ON_ID_SHIFT 8
    #define STOP_ON_ID_MODE_MASK 0x00000200
    #define STOP_ON_ID_MODE_SHIFT 9
    #define NAL_MODE_MASK 0x00003000
    #define NAL_MODE_SHIFT 12
    #define REF_IDX_MODE_MASK 0x00004000
    #define REF_IDX_MODE_SHIFT 14
    #define MVD_OF_MODE_MASK 0x00008000
    #define MVD_OF_MODE_SHIFT 15
    #define MCI_ENABLE_MASK 0x00010000
    #define MCI_ENABLE_SHIFT 16
    #define MCI_DISABLE_MASK 0x00020000
    #define MCI_DISABLE_SHIFT 17
    #define SYNTAX_STATUS_MUX_MASK 0x001C0000
    #define SYNTAX_STATUS_MUX_SHIFT 18
#define  GVD_EDC_CTRL_STATUS 0x8B8C
    #define CURR_MB_ADR_MASK 0x00007FFF
    #define CURR_MB_ADR_SHIFT 0
    #define GVD_EDC_CTRL_STATUS_SLICE_COUNT_MASK 0x03FF0000
    #define GVD_EDC_CTRL_STATUS_SLICE_COUNT_SHIFT 16
#define  GVD_EDC_DUMMY 0x8BF0
    #define GVD_EDC_DUMMY_DATA_MASK 0xFFFFFFFF
    #define GVD_EDC_DUMMY_DATA_SHIFT 0
#define  GVD_EDC_ERR_DISABLE1 0x8BA4
    #define ERR_DISABLE1_MASK 0xFFFFFFFF
    #define ERR_DISABLE1_SHIFT 0
#define  GVD_EDC_ERR_DISABLE2 0x8BA8
    #define ERR_DISABLE2_MASK 0xFFFFFFFF
    #define ERR_DISABLE2_SHIFT 0
#define  GVD_EDC_INPUT_RB_BASE 0x8B30
    #define GVD_EDC_INPUT_RB_BASE_ADDR_MASK 0x0FFFFFC0
    #define GVD_EDC_INPUT_RB_BASE_ADDR_SHIFT 6
#define  GVD_EDC_INPUT_RB_CTRL 0x8B34
    #define GVD_EDC_INPUT_RB_CTRL_SIZE_MASK 0x01FFFFC0
    #define GVD_EDC_INPUT_RB_CTRL_SIZE_SHIFT 6
#define  GVD_EDC_INPUT_RB_RPTR 0x8B38
    #define GVD_EDC_INPUT_RB_RPTR_OFFSET_MASK 0x01FFFFFF
    #define GVD_EDC_INPUT_RB_RPTR_OFFSET_SHIFT 0
#define  GVD_EDC_INPUT_RB_RPTR_MEM 0x8B28
    #define GVD_EDC_INPUT_RB_RPTR_MEM_OFFSET_MASK 0x01FFFFFF
    #define GVD_EDC_INPUT_RB_RPTR_MEM_OFFSET_SHIFT 0
#define  GVD_EDC_INPUT_RB_WPTR 0x8B3C
    #define GVD_EDC_INPUT_RB_WPTR_OFFSET_MASK 0x01FFFFFF
    #define GVD_EDC_INPUT_RB_WPTR_OFFSET_SHIFT 0
    #define GVD_EDC_INPUT_RB_WPTR_END_FLAG_MASK 0x80000000
    #define GVD_EDC_INPUT_RB_WPTR_END_FLAG_SHIFT 31
#define  GVD_EDC_INT 0x8B94
    #define INT_PARSE_ERR_MASK 0x00000001
    #define INT_PARSE_ERR_SHIFT 0
    #define INT_FINISHED_MASK 0x00000002
    #define INT_FINISHED_SHIFT 1
    #define INT_INPUT_STALL_MASK 0x00000004
    #define INT_INPUT_STALL_SHIFT 2
    #define INT_OUTPUT_STALL_MASK 0x00000008
    #define INT_OUTPUT_STALL_SHIFT 3
    #define INT_SYNTAX_ERR_MASK 0x00000010
    #define INT_SYNTAX_ERR_SHIFT 4
#define  GVD_EDC_INT_MASK 0x8B90
    #define INT_MASK_PARSE_ERR_MASK 0x00000001
    #define INT_MASK_PARSE_ERR_SHIFT 0
    #define INT_MASK_FINISHED_MASK 0x00000002
    #define INT_MASK_FINISHED_SHIFT 1
    #define INT_MASK_INPUT_STALL_MASK 0x00000004
    #define INT_MASK_INPUT_STALL_SHIFT 2
    #define INT_MASK_OUTPUT_STALL_MASK 0x00000008
    #define INT_MASK_OUTPUT_STALL_SHIFT 3
    #define INT_MASK_SYNTAX_ERR_MASK 0x00000010
    #define INT_MASK_SYNTAX_ERR_SHIFT 4
#define  GVD_EDC_MBH_BASE_WPTR 0x8B00
    #define GVD_EDC_MBH_BASE_WPTR_DATA_MASK 0x0FFFFFF8
    #define GVD_EDC_MBH_BASE_WPTR_DATA_SHIFT 3
#define  GVD_EDC_MVD_RB_BASE 0x8B08
    #define GVD_EDC_MVD_RB_BASE_ADDR_MASK 0x0FFFFFC0
    #define GVD_EDC_MVD_RB_BASE_ADDR_SHIFT 6
#define  GVD_EDC_MVD_RB_CTRL 0x8B0C
    #define GVD_EDC_MVD_RB_CTRL_SIZE_MASK 0x03FFFFC0
    #define GVD_EDC_MVD_RB_CTRL_SIZE_SHIFT 6
#define  GVD_EDC_MVD_RB_RPTR 0x8B14
    #define GVD_EDC_MVD_RB_RPTR_OFFSET_MASK 0x03FFFFFC
    #define GVD_EDC_MVD_RB_RPTR_OFFSET_SHIFT 2
#define  GVD_EDC_MVD_RB_WPTR 0x8B10
    #define GVD_EDC_MVD_RB_WPTR_OFFSET_MASK 0x03FFFFFC
    #define GVD_EDC_MVD_RB_WPTR_OFFSET_SHIFT 2
#define  GVD_EDC_PPS_INFO_BASE 0x8B44
    #define GVD_EDC_PPS_INFO_BASE_ADDR_MASK 0x0FFFFFF8
    #define GVD_EDC_PPS_INFO_BASE_ADDR_SHIFT 3
#define  GVD_EDC_RESET 0x8BB0
    #define RESET_SYNTAX_MASK 0x00000001
    #define RESET_SYNTAX_SHIFT 0
    #define RESET_SYNTAX_FIFO_MASK 0x00000002
    #define RESET_SYNTAX_FIFO_SHIFT 1
    #define RESET_SYNTAX_ERR_MASK 0x00000004
    #define RESET_SYNTAX_ERR_SHIFT 2
    #define RESET_BB_MASK 0x00000008
    #define RESET_BB_SHIFT 3
    #define RESET_MCI_MASK 0x00000010
    #define RESET_MCI_SHIFT 4
    #define RESET_CTRL_MASK 0x00000020
    #define RESET_CTRL_SHIFT 5
    #define RESET_BIN_MASK 0x00000040
    #define RESET_BIN_SHIFT 6
    #define SOFT_RST_MASK 0x00008000
    #define SOFT_RST_SHIFT 15
#define  GVD_EDC_RLA_RB_BASE 0x8B18
    #define GVD_EDC_RLA_RB_BASE_ADDR_MASK 0x0FFFFFC0
    #define GVD_EDC_RLA_RB_BASE_ADDR_SHIFT 6
#define  GVD_EDC_RLA_RB_CTRL 0x8B1C
    #define GVD_EDC_RLA_RB_CTRL_SIZE_MASK 0x03FFFFC0
    #define GVD_EDC_RLA_RB_CTRL_SIZE_SHIFT 6
#define  GVD_EDC_RLA_RB_RPTR 0x8B24
    #define GVD_EDC_RLA_RB_RPTR_OFFSET_MASK 0x03FFFFFC
    #define GVD_EDC_RLA_RB_RPTR_OFFSET_SHIFT 2
#define  GVD_EDC_RLA_RB_WPTR 0x8B20
    #define GVD_EDC_RLA_RB_WPTR_OFFSET_MASK 0x03FFFFFC
    #define GVD_EDC_RLA_RB_WPTR_OFFSET_SHIFT 2
#define  GVD_EDC_SLICE_CNT 0x8B60
    #define GVD_EDC_SLICE_CNT_COUNT_MASK 0x000003FF
    #define GVD_EDC_SLICE_CNT_COUNT_SHIFT 0
#define  GVD_EDC_SLICE_HDR_RB_BASE 0x8B50
    #define GVD_EDC_SLICE_HDR_RB_BASE_ADDR_MASK 0x0FFFFFF0
    #define GVD_EDC_SLICE_HDR_RB_BASE_ADDR_SHIFT 4
#define  GVD_EDC_SLICE_HDR_RB_CTRL 0x8B54
    #define GVD_EDC_SLICE_HDR_RB_CTRL_SIZE_MASK 0x000FFFF8
    #define GVD_EDC_SLICE_HDR_RB_CTRL_SIZE_SHIFT 3
#define  GVD_EDC_SLICE_HDR_RB_RPTR 0x8B58
    #define GVD_EDC_SLICE_HDR_RB_RPTR_OFFSET_MASK 0x000FFFF8
    #define GVD_EDC_SLICE_HDR_RB_RPTR_OFFSET_SHIFT 3
#define  GVD_EDC_SLICE_HDR_RB_WPTR 0x8B5C
    #define GVD_EDC_SLICE_HDR_RB_WPTR_OFFSET_MASK 0x000FFFF8
    #define GVD_EDC_SLICE_HDR_RB_WPTR_OFFSET_SHIFT 3
#define  GVD_EDC_SLICE_INFO_RB_BASE 0x8B70
    #define GVD_EDC_SLICE_INFO_RB_BASE_ADDR_MASK 0x0FFFFFF8
    #define GVD_EDC_SLICE_INFO_RB_BASE_ADDR_SHIFT 3
#define  GVD_EDC_SLICE_INFO_RB_CTRL 0x8B74
    #define GVD_EDC_SLICE_INFO_RB_CTRL_SIZE_MASK 0x000FFFF8
    #define GVD_EDC_SLICE_INFO_RB_CTRL_SIZE_SHIFT 3
#define  GVD_EDC_SLICE_INFO_RB_RPTR 0x8B7C
    #define GVD_EDC_SLICE_INFO_RB_RPTR_OFFSET_MASK 0x000FFFFC
    #define GVD_EDC_SLICE_INFO_RB_RPTR_OFFSET_SHIFT 2
#define  GVD_EDC_SLICE_INFO_RB_WPTR 0x8B78
    #define GVD_EDC_SLICE_INFO_RB_WPTR_OFFSET_MASK 0x000FFFFC
    #define GVD_EDC_SLICE_INFO_RB_WPTR_OFFSET_SHIFT 2
#define  GVD_EDC_SPS_INFO_BASE 0x8B40
    #define GVD_EDC_SPS_INFO_BASE_ADDR_MASK 0x0FFFFFF8
    #define GVD_EDC_SPS_INFO_BASE_ADDR_SHIFT 3
#define  GVD_EDC_STATUS 0x8B84
    #define PARSE_ERR_CODE_MASK 0x00000007
    #define PARSE_ERR_CODE_SHIFT 0
    #define WAIT_FLAG_MASK 0x00000008
    #define WAIT_FLAG_SHIFT 3
    #define GVD_EDC_STATUS_END_FLAG_MASK 0x00000010
    #define GVD_EDC_STATUS_END_FLAG_SHIFT 4
    #define BB_WAIT_FLAG_MASK 0x00000020
    #define BB_WAIT_FLAG_SHIFT 5
    #define GVD_EDC_STATUS_BUSY_MASK 0x00000040
    #define GVD_EDC_STATUS_BUSY_SHIFT 6
    #define MCI_ACTIVE_MASK 0x00000080
    #define MCI_ACTIVE_SHIFT 7
    #define RLA_STALL_FLAG_MASK 0x00000100
    #define RLA_STALL_FLAG_SHIFT 8
    #define MVD_STALL_FLAG_MASK 0x00000200
    #define MVD_STALL_FLAG_SHIFT 9
    #define SLC_INFO_STALL_FLAG_MASK 0x00000400
    #define SLC_INFO_STALL_FLAG_SHIFT 10
    #define SLC_HDR_STALL_FLAG_MASK 0x00000800
    #define SLC_HDR_STALL_FLAG_SHIFT 11
    #define SYNTAX_FIFO_FULL_MASK 0x00001000
    #define SYNTAX_FIFO_FULL_SHIFT 12
    #define SYNTAX_FIFO_EMPTY_MASK 0x00002000
    #define SYNTAX_FIFO_EMPTY_SHIFT 13
    #define SC_OVERRUN_ERR_MASK 0x00004000
    #define SC_OVERRUN_ERR_SHIFT 14
    #define ID_OVERRUN_ERR_MASK 0x00008000
    #define ID_OVERRUN_ERR_SHIFT 15
    #define SYNTAX_ERR_CODE_MASK 0x000F0000
    #define SYNTAX_ERR_CODE_SHIFT 16
    #define IPCM_FLAG_MASK 0x00100000
    #define IPCM_FLAG_SHIFT 20
    #define SUB_8X8FLAG_MASK 0x00200000
    #define SUB_8X8FLAG_SHIFT 21
    #define FLD_REF1_FLAG_MASK 0x00400000
    #define FLD_REF1_FLAG_SHIFT 22
    #define FRM_REF0_FLAG_MASK 0x00800000
    #define FRM_REF0_FLAG_SHIFT 23
    #define GVD_EDC_STATUS_NAL_UNIT_TYPE_MASK 0x1F000000
    #define GVD_EDC_STATUS_NAL_UNIT_TYPE_SHIFT 24
    #define GVD_EDC_STATUS_NAL_REF_IDC_MASK 0x60000000
    #define GVD_EDC_STATUS_NAL_REF_IDC_SHIFT 29
#define  GVD_EDC_STATUS2 0x8BA0
    #define FIFO_LEVEL_MASK 0x000000FF
    #define FIFO_LEVEL_SHIFT 0
    #define SYNTAX_READY_MASK 0x00000100
    #define SYNTAX_READY_SHIFT 8
    #define CTRL_STATE_MASK 0x0000F000
    #define CTRL_STATE_SHIFT 12
    #define SYNTAX_STATE_MASK 0x00FF0000
    #define SYNTAX_STATE_SHIFT 16
#define  GVD_EDC_TOTAL_BIT_CNT 0x8BAC
    #define BB_TOTAL_BIT_CNT_MASK 0x0FFFFFFF
    #define BB_TOTAL_BIT_CNT_SHIFT 0
#define  GVD_IIP_DEBUG 0x88CC
    #define GVD_IIP_DEBUG_DEBUG_MASK 0x000FFFFF
    #define GVD_IIP_DEBUG_DEBUG_SHIFT 0
#define  GVD_IIP_WCOUNT 0x88C8
    #define GVD_IIP_WCOUNT_COUNT_MASK 0x000000FF
    #define GVD_IIP_WCOUNT_COUNT_SHIFT 0
#define  GVD_INT 0x8804
    #define GVD_INTERRUPT_MASK 0x00000001
    #define GVD_INTERRUPT_SHIFT 0
#define  GVD_INT_CTRL 0x8808
    #define GVD_INT_MIPS_EN_MASK 0x00000001
    #define GVD_INT_MIPS_EN_SHIFT 0
    #define GVD_INT_HOST_EN_MASK 0x00000002
    #define GVD_INT_HOST_EN_SHIFT 1
#define  GVD_IQT_CTRL 0x8928
    #define GVD_IQT_CTRL_ENTROPY_FLG_MASK 0x00000001
    #define GVD_IQT_CTRL_ENTROPY_FLG_SHIFT 0
    #define GVD_IQT_CTRL_WEIGHT_ENB_MASK 0x00000002
    #define GVD_IQT_CTRL_WEIGHT_ENB_SHIFT 1
    #define QP_CB_OFFSET_MASK 0x000001F0
    #define QP_CB_OFFSET_SHIFT 4
    #define QP_CR_OFFSET_MASK 0x0001F000
    #define QP_CR_OFFSET_SHIFT 12
#define  GVD_IQT_RLA_RB_BASE 0x8900
    #define GVD_IQT_RLA_RB_BASE_ADDR_MASK 0x0FFFFFE0
    #define GVD_IQT_RLA_RB_BASE_ADDR_SHIFT 5
#define  GVD_IQT_RLA_RB_CTRL 0x8904
    #define GVD_IQT_RLA_RB_CTRL_SIZE_MASK 0x03FFFFF8
    #define GVD_IQT_RLA_RB_CTRL_SIZE_SHIFT 3
#define  GVD_IQT_RLA_RB_RPTR 0x8908
    #define GVD_IQT_RLA_RB_RPTR_OFFSET_MASK 0x03FFFFFC
    #define GVD_IQT_RLA_RB_RPTR_OFFSET_SHIFT 2
#define  GVD_IQT_RLA_RB_WPTR 0x890C
    #define GVD_IQT_RLA_RB_WPTR_OFFSET_MASK 0x03FFFFFC
    #define GVD_IQT_RLA_RB_WPTR_OFFSET_SHIFT 2
#define  GVD_IQT_SLICE_INFO 0x892C
    #define NUM_RL_MASK 0x00FFFFFF
    #define NUM_RL_SHIFT 0
#define  GVD_IQT_WEIGHT_TABLE 0x8924
    #define GVD_IQT_WEIGHT_TABLE_INDEX_MASK 0x0000001F
    #define GVD_IQT_WEIGHT_TABLE_INDEX_SHIFT 0
#define  GVD_IQT_WEIGHT_TABLE_0 0x8914
    #define GVD_IQT_WEIGHT_TABLE_0_VALUE_MASK 0xFFFFFFFF
    #define GVD_IQT_WEIGHT_TABLE_0_VALUE_SHIFT 0
#define  GVD_IQT_WEIGHT_TABLE_1 0x8918
    #define GVD_IQT_WEIGHT_TABLE_1_VALUE_MASK 0xFFFFFFFF
    #define GVD_IQT_WEIGHT_TABLE_1_VALUE_SHIFT 0
#define  GVD_IQT_WEIGHT_TABLE_2 0x891C
    #define GVD_IQT_WEIGHT_TABLE_2_VALUE_MASK 0xFFFFFFFF
    #define GVD_IQT_WEIGHT_TABLE_2_VALUE_SHIFT 0
#define  GVD_IQT_WEIGHT_TABLE_3 0x8920
    #define GVD_IQT_WEIGHT_TABLE_3_VALUE_MASK 0xFFFFFFFF
    #define GVD_IQT_WEIGHT_TABLE_3_VALUE_SHIFT 0
#define  GVD_MARB_ARB0 0x8A08
    #define GVD_MARB_ARB0_CLI0_REQ_CNT_LIMIT_MASK 0x0000000F
    #define GVD_MARB_ARB0_CLI0_REQ_CNT_LIMIT_SHIFT 0
    #define GVD_MARB_ARB0_CLI1_REQ_CNT_LIMIT_MASK 0x000000F0
    #define GVD_MARB_ARB0_CLI1_REQ_CNT_LIMIT_SHIFT 4
    #define GVD_MARB_ARB0_CLI2_REQ_CNT_LIMIT_MASK 0x00000F00
    #define GVD_MARB_ARB0_CLI2_REQ_CNT_LIMIT_SHIFT 8
    #define GVD_MARB_ARB0_CLI3_REQ_CNT_LIMIT_MASK 0x0000F000
    #define GVD_MARB_ARB0_CLI3_REQ_CNT_LIMIT_SHIFT 12
    #define GVD_MARB_ARB0_CLI4_REQ_CNT_LIMIT_MASK 0x000F0000
    #define GVD_MARB_ARB0_CLI4_REQ_CNT_LIMIT_SHIFT 16
    #define GVD_MARB_ARB0_CLI5_REQ_CNT_LIMIT_MASK 0x00F00000
    #define GVD_MARB_ARB0_CLI5_REQ_CNT_LIMIT_SHIFT 20
    #define GVD_MARB_ARB0_CLI6_REQ_CNT_LIMIT_MASK 0x0F000000
    #define GVD_MARB_ARB0_CLI6_REQ_CNT_LIMIT_SHIFT 24
    #define GVD_MARB_ARB0_CLI7_REQ_CNT_LIMIT_MASK 0xF0000000
    #define GVD_MARB_ARB0_CLI7_REQ_CNT_LIMIT_SHIFT 28
#define  GVD_MARB_CTRL 0x8A00
    #define GVD_MARB_CTRL_MEM_CNT_RESET_MASK 0x00000001
    #define GVD_MARB_CTRL_MEM_CNT_RESET_SHIFT 0
    #define GVD_MARB_CTRL_MEM_CNT_EN_MASK 0x00000002
    #define GVD_MARB_CTRL_MEM_CNT_EN_SHIFT 1
    #define GVD_MARB_CTRL_MEM_CNT_SEL_MASK 0x00000004
    #define GVD_MARB_CTRL_MEM_CNT_SEL_SHIFT 2
#define  GVD_MARB_PRIORITY 0x8A04
    #define GVD_MARB_PRIORITY_ABSOLUTE_PRIORITY_MASK 0x000000FF
    #define GVD_MARB_PRIORITY_ABSOLUTE_PRIORITY_SHIFT 0
#define  GVD_MEM_CNT 0x8A0C
    #define GVD_MEM_CNT_MEM_CNT_MASK 0x00FFFFFF
    #define GVD_MEM_CNT_MEM_CNT_SHIFT 0
#define  GVD_NMB_CMD_FIFO 0x8868
    #define GVD_NMB_CMD_FIFO_MBH_INDEX_MASK 0x00001FFF
    #define GVD_NMB_CMD_FIFO_MBH_INDEX_SHIFT 0
    #define MB_COUNT_MASK 0x1FFF0000
    #define MB_COUNT_SHIFT 16
#define  GVD_NMB_CTRL 0x8864
    #define GVD_NMB_CTRL_MODE_MASK 0x00000003
    #define GVD_NMB_CTRL_MODE_SHIFT 0
    #define MV_EXP_ENABLE_MASK 0x00000010
    #define MV_EXP_ENABLE_SHIFT 4
    #define GVD_NMB_CTRL_SOFT_RESET_MASK 0x80000000
    #define GVD_NMB_CTRL_SOFT_RESET_SHIFT 31
#define  GVD_NMB_DBG 0x88B0
    #define GVD_NMB_DBG_DATA_MASK 0xFFFFFFFF
    #define GVD_NMB_DBG_DATA_SHIFT 0
#define  GVD_NMB_DBG_CTRL 0x88AC
    #define GVD_NMB_DBG_CTRL_SEL_MASK 0x0000003F
    #define GVD_NMB_DBG_CTRL_SEL_SHIFT 0
    #define GVD_NMB_DBG_CTRL_MUX_MASK 0x00001F00
    #define GVD_NMB_DBG_CTRL_MUX_SHIFT 8
#define  GVD_NMB_DMV_CO_BASE 0x889C
    #define GVD_NMB_DMV_CO_BASE_ADDR_MASK 0x0FFFFFF8
    #define GVD_NMB_DMV_CO_BASE_ADDR_SHIFT 3
#define  GVD_NMB_DMV_CO_DATA 0x88B4
    #define BYTES_MASK 0x0000FFF8
    #define BYTES_SHIFT 3
#define  GVD_NMB_MBH_BASE 0x8870
    #define GVD_NMB_MBH_BASE_ADDR_MASK 0x0FFFFFF8
    #define GVD_NMB_MBH_BASE_ADDR_SHIFT 3
#define  GVD_NMB_MBH_RPTR 0x88A8
    #define GVD_NMB_MBH_RPTR_OFFSET_MASK 0x0003FFFC
    #define GVD_NMB_MBH_RPTR_OFFSET_SHIFT 2
#define  GVD_NMB_MVD_LENGTH 0x8884
    #define GVD_NMB_MVD_LENGTH_SIZE_MASK 0x000FFFFC
    #define GVD_NMB_MVD_LENGTH_SIZE_SHIFT 2
#define  GVD_NMB_MVD_RB_BASE 0x8874
    #define GVD_NMB_MVD_RB_BASE_ADDR_MASK 0x0FFFFFF8
    #define GVD_NMB_MVD_RB_BASE_ADDR_SHIFT 3
#define  GVD_NMB_MVD_RB_CTRL 0x8878
    #define GVD_NMB_MVD_RB_CTRL_SIZE_MASK 0x007FFFFC
    #define GVD_NMB_MVD_RB_CTRL_SIZE_SHIFT 2
#define  GVD_NMB_MVD_RB_RPTR 0x887C
    #define GVD_NMB_MVD_RB_RPTR_OFFSET_MASK 0x007FFFFC
    #define GVD_NMB_MVD_RB_RPTR_OFFSET_SHIFT 2
#define  GVD_NMB_MVD_RB_WPTR 0x8880
    #define GVD_NMB_MVD_RB_WPTR_OFFSET_MASK 0x007FFFFC
    #define GVD_NMB_MVD_RB_WPTR_OFFSET_SHIFT 2
#define  GVD_NMB_MV_RB_BASE 0x888C
    #define GVD_NMB_MV_RB_BASE_ADDR_MASK 0x0FFFFFF8
    #define GVD_NMB_MV_RB_BASE_ADDR_SHIFT 3
#define  GVD_NMB_MV_RB_CTRL 0x8890
    #define GVD_NMB_MV_RB_CTRL_SIZE_MASK 0x007FFFFC
    #define GVD_NMB_MV_RB_CTRL_SIZE_SHIFT 2
#define  GVD_NMB_MV_RB_RPTR 0x8894
    #define GVD_NMB_MV_RB_RPTR_OFFSET_MASK 0x007FFFFC
    #define GVD_NMB_MV_RB_RPTR_OFFSET_SHIFT 2
#define  GVD_NMB_MV_RB_WPTR 0x8898
    #define GVD_NMB_MV_RB_WPTR_OFFSET_MASK 0x007FFFFC
    #define GVD_NMB_MV_RB_WPTR_OFFSET_SHIFT 2
#define  GVD_NMB_REFIDX_MAP 0x88A0
    #define R0_L0_MASK 0x0000001F
    #define R0_L0_SHIFT 0
    #define BOT_FLD_FIRST_L0_MASK 0x00000080
    #define BOT_FLD_FIRST_L0_SHIFT 7
    #define R0_L1_MASK 0x00001F00
    #define R0_L1_SHIFT 8
    #define BOT_FLD_FIRST_L1_MASK 0x00008000
    #define BOT_FLD_FIRST_L1_SHIFT 15
#define  GVD_NMB_START_MB 0x8860
    #define GVD_NMB_START_MB_START_MB_X_MASK 0x000000FF
    #define GVD_NMB_START_MB_START_MB_X_SHIFT 0
    #define GVD_NMB_START_MB_START_MB_Y_MASK 0x00007F00
    #define GVD_NMB_START_MB_START_MB_Y_SHIFT 8
#define  GVD_NMB_STATUS 0x886C
    #define GVD_NMB_STATUS_NMB_BUSY_MASK 0x00000001
    #define GVD_NMB_STATUS_NMB_BUSY_SHIFT 0
#define  GVD_NMB_TOP_NB_BASE 0x8888
    #define GVD_NMB_TOP_NB_BASE_ADDR_MASK 0x0FFFFFF8
    #define GVD_NMB_TOP_NB_BASE_ADDR_SHIFT 3
#define  GVD_PICT_SIZE 0x8824
    #define GVD_PICT_SIZE_PICT_MB_WIDTH_MASK 0x000000FF
    #define GVD_PICT_SIZE_PICT_MB_WIDTH_SHIFT 0
    #define GVD_PICT_SIZE_PICT_MB_HEIGHT_MASK 0x0000FF00
    #define GVD_PICT_SIZE_PICT_MB_HEIGHT_SHIFT 8
#define  GVD_REF_C_ADR 0x8838
    #define GVD_REF_C_ADR_BASE_MASK 0x0FFFFF00
    #define GVD_REF_C_ADR_BASE_SHIFT 8
#define  GVD_REF_PICT_SIZE 0x8830
    #define GVD_REF_PICT_SIZE_REF_Y_SIZE_MASK 0x00007FFF
    #define GVD_REF_PICT_SIZE_REF_Y_SIZE_SHIFT 0
    #define GVD_REF_PICT_SIZE_REF_C_SIZE_MASK 0x7FFF0000
    #define GVD_REF_PICT_SIZE_REF_C_SIZE_SHIFT 16
#define  GVD_REF_PITCH 0x882C
    #define GVD_REF_PITCH_REF_PITCH_MASK 0x00000FE0
    #define GVD_REF_PITCH_REF_PITCH_SHIFT 5
#define  GVD_REF_Y_ADR 0x8834
    #define GVD_REF_Y_ADR_BASE_MASK 0x0FFFFF00
    #define GVD_REF_Y_ADR_BASE_SHIFT 8
#define  GVD_SLICE_INFO 0x8820
    #define GVD_SLICE_INFO_SLICE_TYPE_MASK 0x00000003
    #define GVD_SLICE_INFO_SLICE_TYPE_SHIFT 0
    #define GVD_SLICE_INFO_MBAFF_FLAG_MASK 0x00000010
    #define GVD_SLICE_INFO_MBAFF_FLAG_SHIFT 4
    #define GVD_SOFT_RESET_MASK 0x80000000
    #define GVD_SOFT_RESET_SHIFT 31
#define  GVD_START_MB 0x8828
    #define GVD_START_MB_START_MB_X_MASK 0x000000FF
    #define GVD_START_MB_START_MB_X_SHIFT 0
    #define GVD_START_MB_START_MB_Y_MASK 0x00007F00
    #define GVD_START_MB_START_MB_Y_SHIFT 8
#define  GVD_STATUS 0x8800
    #define GVD_STATUS_NMB_BUSY_MASK 0x00000001
    #define GVD_STATUS_NMB_BUSY_SHIFT 0
    #define IQT_BUSY_MASK 0x00000002
    #define IQT_BUSY_SHIFT 1
    #define IIP_BUSY_MASK 0x00000004
    #define IIP_BUSY_SHIFT 2
    #define DMC_BUSY_MASK 0x00000008
    #define DMC_BUSY_SHIFT 3
    #define DDB_BUSY_MASK 0x00000010
    #define DDB_BUSY_SHIFT 4
    #define DCP_BUSY_MASK 0x00000020
    #define DCP_BUSY_SHIFT 5
    #define GVD_W_BUSY_MASK 0x00010000
    #define GVD_W_BUSY_SHIFT 16
    #define GVD_R_BUSY_MASK 0x00020000
    #define GVD_R_BUSY_SHIFT 17
    #define GVD_BUSY_MASK 0x80000000
    #define GVD_BUSY_SHIFT 31
#define  GVD_TOP_MODE_ADR 0x88C4
    #define GVD_TOP_MODE_ADR_BASE_MASK 0x0FFFFFF8
    #define GVD_TOP_MODE_ADR_BASE_SHIFT 3
#define  GVD_TOP_PIXEL_ADR 0x88C0
    #define GVD_TOP_PIXEL_ADR_BASE_MASK 0x0FFFFFF8
    #define GVD_TOP_PIXEL_ADR_BASE_SHIFT 3
#define  GVP_CMD_STATUS 0x8398
    #define MS_CMD_STATUS_MASK 0x000000FF
    #define MS_CMD_STATUS_SHIFT 0
    #define IP_CMD_STATUS_MASK 0x00007F00
    #define IP_CMD_STATUS_SHIFT 8
    #define NMB_CMD_STATUS_MASK 0x00FF0000
    #define NMB_CMD_STATUS_SHIFT 16
    #define DBK_CMD_STATUS_MASK 0xFF000000
    #define DBK_CMD_STATUS_SHIFT 24
#define  GVP_CUR_C_ADR 0x801C
    #define GVP_CUR_C_ADR_BASE_MASK 0x1FFFFF00
    #define GVP_CUR_C_ADR_BASE_SHIFT 8
#define  GVP_CUR_PICT_SIZE 0x800C
    #define CUR_Y_SIZE_MASK 0x00007FFF
    #define CUR_Y_SIZE_SHIFT 0
    #define CUR_C_SIZE_MASK 0x7FFF0000
    #define CUR_C_SIZE_SHIFT 16
#define  GVP_CUR_PITCH 0x8008
    #define CUR_PITCH_MASK 0x00000FE0
    #define CUR_PITCH_SHIFT 5
#define  GVP_CUR_Y_ADR 0x8018
    #define GVP_CUR_Y_ADR_BASE_MASK 0x1FFFFF00
    #define GVP_CUR_Y_ADR_BASE_SHIFT 8
#define  GVP_DBK_C0_OFFSET 0x8190
    #define GVP_DBK_C0_OFFSET_ALPHA_C0_OFFSET_DIV2_MASK 0x0000000F
    #define GVP_DBK_C0_OFFSET_ALPHA_C0_OFFSET_DIV2_SHIFT 0
    #define GVP_DBK_C0_OFFSET_BETA_C0_OFFSET_DIV2_MASK 0x00000F00
    #define GVP_DBK_C0_OFFSET_BETA_C0_OFFSET_DIV2_SHIFT 8
#define  GVP_DBK_CHROMA_QP_INDEX_OFFSET 0x8194
    #define GVP_DBK_CHROMA_QP_INDEX_OFFSET_CHROMA_QP_INDEX_OFFSET_MASK 0x0000001F
    #define GVP_DBK_CHROMA_QP_INDEX_OFFSET_CHROMA_QP_INDEX_OFFSET_SHIFT 0
#define  GVP_DBK_CMD_FIFO 0x818C
    #define GVP_DBK_CMD_FIFO_COMMAND_TAG_MASK 0x000000FF
    #define GVP_DBK_CMD_FIFO_COMMAND_TAG_SHIFT 0
    #define GVP_DBK_CMD_FIFO_DSQA_INDEX_MASK 0x00000F00
    #define GVP_DBK_CMD_FIFO_DSQA_INDEX_SHIFT 8
    #define INPUT_MB_INDEX_MASK 0x000F0000
    #define INPUT_MB_INDEX_SHIFT 16
#define  GVP_DBK_CTRL 0x8184
    #define GVP_DBK_CTRL_DBK_BYPASS_MASK 0x00000001
    #define GVP_DBK_CTRL_DBK_BYPASS_SHIFT 0
    #define GVP_DBK_CTRL_DBK_DISABLE_MASK 0x00000002
    #define GVP_DBK_CTRL_DBK_DISABLE_SHIFT 1
    #define GVP_DBK_CTRL_DBK_REF_INDEX_MASK 0x00001F00
    #define GVP_DBK_CTRL_DBK_REF_INDEX_SHIFT 8
    #define DBK_FLD_TILE_MASK 0x00010000
    #define DBK_FLD_TILE_SHIFT 16
    #define GVP_DBK_CTRL_SOFT_RESET_MASK 0x80000000
    #define GVP_DBK_CTRL_SOFT_RESET_SHIFT 31
#define  GVP_DBK_DBG 0x81AC
    #define GVP_DBK_DBG_DATA_MASK 0xFFFFFFFF
    #define GVP_DBK_DBG_DATA_SHIFT 0
#define  GVP_DBK_DBG_CTRL 0x81A8
    #define GVP_DBK_DBG_CTRL_SEL_MASK 0x0000003F
    #define GVP_DBK_DBG_CTRL_SEL_SHIFT 0
    #define GVP_DBK_DBG_CTRL_MUX_MASK 0x00000F00
    #define GVP_DBK_DBG_CTRL_MUX_SHIFT 8
#define  GVP_DBK_DSQA_ADR 0x81A0
    #define GVP_DBK_DSQA_ADR_BASE_MASK 0x1FFFFFE0
    #define GVP_DBK_DSQA_ADR_BASE_SHIFT 5
#define  GVP_DBK_START_MB 0x8180
    #define GVP_DBK_START_MB_START_MB_X_MASK 0x000000FF
    #define GVP_DBK_START_MB_START_MB_X_SHIFT 0
    #define GVP_DBK_START_MB_START_MB_Y_MASK 0x00007F00
    #define GVP_DBK_START_MB_START_MB_Y_SHIFT 8
#define  GVP_DBK_STATUS 0x8188
    #define GVP_DBK_STATUS_DBK_BUSY_MASK 0x00000001
    #define GVP_DBK_STATUS_DBK_BUSY_SHIFT 0
    #define GVP_DBK_STATUS_COMMAND_TAG_MASK 0x0000FF00
    #define GVP_DBK_STATUS_COMMAND_TAG_SHIFT 8
    #define GVP_DBK_STATUS_FREE_ENTRIES_MASK 0x00070000
    #define GVP_DBK_STATUS_FREE_ENTRIES_SHIFT 16
#define  GVP_DCP_FIFO_0 0x83A0
    #define GVP_DCP_FIFO_0_DATA_MASK 0xFFFFFFFF
    #define GVP_DCP_FIFO_0_DATA_SHIFT 0
#define  GVP_DCP_FIFO_1 0x83A4
    #define GVP_DCP_FIFO_1_VALUE_MASK 0x1FFFFFFF
    #define GVP_DCP_FIFO_1_VALUE_SHIFT 0
    #define GVP_CMD_MASK 0xE0000000
    #define GVP_CMD_SHIFT 29
#define  GVP_DCP_STATUS 0x83A8
    #define GVP_DCP_STATUS_FIFO_FREE_MASK 0x0000001F
    #define GVP_DCP_STATUS_FIFO_FREE_SHIFT 0
    #define GVP_DCP_BUSY_MASK 0x80000000
    #define GVP_DCP_BUSY_SHIFT 31
#define  GVP_DMV_CO_ADR 0x82C4
    #define GVP_DMV_CO_ADR_BASE_MASK 0x1FFFFFF0
    #define GVP_DMV_CO_ADR_BASE_SHIFT 4
#define  GVP_DMV_CTRL 0x82C8
    #define I_COPIC_MASK 0x00000001
    #define I_COPIC_SHIFT 0
    #define BOT_FLD_FIRST_MASK 0x00000002
    #define BOT_FLD_FIRST_SHIFT 1
#define  GVP_DMV_TOP_ADR 0x82C0
    #define GVP_DMV_TOP_ADR_BASE_MASK 0x1FFFFFF0
    #define GVP_DMV_TOP_ADR_BASE_SHIFT 4
#define  GVP_EE_BITCNT_MB_RES 0x81BC
    #define BITCNT_MB_RES_MASK 0xFFFFFFFF
    #define BITCNT_MB_RES_SHIFT 0
#define  GVP_EE_BITCNT_MB_TOTAL 0x81B8
    #define BITCNT_MB_TOTAL_MASK 0xFFFFFFFF
    #define BITCNT_MB_TOTAL_SHIFT 0
#define  GVP_EE_CMD 0x81FC
    #define INT_CLR_MASK 0x10000000
    #define INT_CLR_SHIFT 28
    #define BP_CONTINUE_MASK 0x20000000
    #define BP_CONTINUE_SHIFT 29
    #define CODE_OFFLINE_MASK 0x40000000
    #define CODE_OFFLINE_SHIFT 30
    #define CODE_SLICE_HDR_MASK 0x80000000
    #define CODE_SLICE_HDR_SHIFT 31
#define  GVP_EE_CTRL 0x81D0
    #define INT_MASK_MASK 0x00000001
    #define INT_MASK_SHIFT 0
    #define GVP_EE_CTRL_SOFT_RESET_MASK 0x00000002
    #define GVP_EE_CTRL_SOFT_RESET_SHIFT 1
    #define BAC_OP_MODE_MASK 0x00000030
    #define BAC_OP_MODE_SHIFT 4
    #define BP_RES_BLK_MASK 0x00010000
    #define BP_RES_BLK_SHIFT 16
    #define EE_DEBUG_MUX_SEL_MASK 0xFFF00000
    #define EE_DEBUG_MUX_SEL_SHIFT 20
#define  GVP_EE_CTXTBL_ADR 0x8208
    #define GVP_EE_CTXTBL_ADR_ADR_MASK 0x1FFFFFF8
    #define GVP_EE_CTXTBL_ADR_ADR_SHIFT 3
#define  GVP_EE_DEBUG 0x8258
    #define GVP_EE_DEBUG_DATA_MASK 0xFFFFFFFF
    #define GVP_EE_DEBUG_DATA_SHIFT 0
#define  GVP_EE_DUMMY_REG 0x825C
    #define GVP_EE_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define GVP_EE_DUMMY_REG_DATA_SHIFT 0
#define  GVP_EE_ERROR 0x81B4
    #define EXTRA_SLICE_TRIG_MASK 0x00000001
    #define EXTRA_SLICE_TRIG_SHIFT 0
    #define MISSING_SLICE_TRIG_MASK 0x00000002
    #define MISSING_SLICE_TRIG_SHIFT 1
    #define CMD_FIFO_OVERFLOW_MASK 0x00000004
    #define CMD_FIFO_OVERFLOW_SHIFT 2
    #define NAL_BUF_OVERFLOW_MASK 0x00000008
    #define NAL_BUF_OVERFLOW_SHIFT 3
    #define RL_OFFSET_OB_MASK 0x00000010
    #define RL_OFFSET_OB_SHIFT 4
    #define RL_ILLEGAL_NUM_PAIRS_MASK 0x00000020
    #define RL_ILLEGAL_NUM_PAIRS_SHIFT 5
    #define BP_RES_BLK_ACT_MASK 0x00010000
    #define BP_RES_BLK_ACT_SHIFT 16
#define  GVP_EE_MBBOT_HDR0 0x81E0
    #define MBBOT_MB_TYPE_MASK 0x0000000F
    #define MBBOT_MB_TYPE_SHIFT 0
    #define MBBOT_TRANS_8X8_MASK 0x00000020
    #define MBBOT_TRANS_8X8_SHIFT 5
    #define MBBOT_CBP_MASK 0x00003F00
    #define MBBOT_CBP_SHIFT 8
    #define MBBOT_ICPM_MASK 0x0000C000
    #define MBBOT_ICPM_SHIFT 14
    #define MBBOT_MB_QP_DELTA_MASK 0x003F0000
    #define MBBOT_MB_QP_DELTA_SHIFT 16
#define  GVP_EE_MBBOT_HDR1 0x81E4
    #define MBBOT_ILPM_0_MASK 0x0000000F
    #define MBBOT_ILPM_0_SHIFT 0
    #define MBBOT_ILPM_1_MASK 0x000000F0
    #define MBBOT_ILPM_1_SHIFT 4
    #define MBBOT_ILPM_2_MASK 0x00000F00
    #define MBBOT_ILPM_2_SHIFT 8
    #define MBBOT_ILPM_3_MASK 0x0000F000
    #define MBBOT_ILPM_3_SHIFT 12
    #define MBBOT_ILPM_4_MASK 0x000F0000
    #define MBBOT_ILPM_4_SHIFT 16
    #define MBBOT_ILPM_5_MASK 0x00F00000
    #define MBBOT_ILPM_5_SHIFT 20
    #define MBBOT_ILPM_6_MASK 0x0F000000
    #define MBBOT_ILPM_6_SHIFT 24
    #define MBBOT_ILPM_7_MASK 0xF0000000
    #define MBBOT_ILPM_7_SHIFT 28
#define  GVP_EE_MBBOT_HDR2 0x81E8
    #define MBBOT_ILPM_8_MASK 0x0000000F
    #define MBBOT_ILPM_8_SHIFT 0
    #define MBBOT_ILPM_9_MASK 0x000000F0
    #define MBBOT_ILPM_9_SHIFT 4
    #define MBBOT_ILPM_10_MASK 0x00000F00
    #define MBBOT_ILPM_10_SHIFT 8
    #define MBBOT_ILPM_11_MASK 0x0000F000
    #define MBBOT_ILPM_11_SHIFT 12
    #define MBBOT_ILPM_12_MASK 0x000F0000
    #define MBBOT_ILPM_12_SHIFT 16
    #define MBBOT_ILPM_13_MASK 0x00F00000
    #define MBBOT_ILPM_13_SHIFT 20
    #define MBBOT_ILPM_14_MASK 0x0F000000
    #define MBBOT_ILPM_14_SHIFT 24
    #define MBBOT_ILPM_15_MASK 0xF0000000
    #define MBBOT_ILPM_15_SHIFT 28
#define  GVP_EE_MBHDR_ADR 0x8360
    #define GVP_EE_MBHDR_ADR_BASE_MASK 0x1FFFFFF8
    #define GVP_EE_MBHDR_ADR_BASE_SHIFT 3
#define  GVP_EE_MBHDR_BUF_SIZE 0x8364
    #define GVP_EE_MBHDR_BUF_SIZE_SIZE_MASK 0x000FFFF8
    #define GVP_EE_MBHDR_BUF_SIZE_SIZE_SHIFT 3
#define  GVP_EE_MBHDR_CURR_ADR 0x8244
    #define GVP_EE_MBHDR_CURR_ADR_OFFSET_MASK 0x000FFFFC
    #define GVP_EE_MBHDR_CURR_ADR_OFFSET_SHIFT 2
#define  GVP_EE_MBHDR_OFFSET 0x81EC
    #define GVP_EE_MBHDR_OFFSET_OFFSET_MASK 0x000FFFF8
    #define GVP_EE_MBHDR_OFFSET_OFFSET_SHIFT 3
#define  GVP_EE_MBTOP_HDR0 0x81D4
    #define MBTOP_MB_TYPE_MASK 0x0000000F
    #define MBTOP_MB_TYPE_SHIFT 0
    #define MBTOP_MB_FIELD_MASK 0x00000010
    #define MBTOP_MB_FIELD_SHIFT 4
    #define MBTOP_TRANS_8X8_MASK 0x00000020
    #define MBTOP_TRANS_8X8_SHIFT 5
    #define MBTOP_CBP_MASK 0x00003F00
    #define MBTOP_CBP_SHIFT 8
    #define MBTOP_ICPM_MASK 0x0000C000
    #define MBTOP_ICPM_SHIFT 14
    #define MBTOP_MB_QP_DELTA_MASK 0x003F0000
    #define MBTOP_MB_QP_DELTA_SHIFT 16
#define  GVP_EE_MBTOP_HDR1 0x81D8
    #define MBTOP_ILPM_0_MASK 0x0000000F
    #define MBTOP_ILPM_0_SHIFT 0
    #define MBTOP_ILPM_1_MASK 0x000000F0
    #define MBTOP_ILPM_1_SHIFT 4
    #define MBTOP_ILPM_2_MASK 0x00000F00
    #define MBTOP_ILPM_2_SHIFT 8
    #define MBTOP_ILPM_3_MASK 0x0000F000
    #define MBTOP_ILPM_3_SHIFT 12
    #define MBTOP_ILPM_4_MASK 0x000F0000
    #define MBTOP_ILPM_4_SHIFT 16
    #define MBTOP_ILPM_5_MASK 0x00F00000
    #define MBTOP_ILPM_5_SHIFT 20
    #define MBTOP_ILPM_6_MASK 0x0F000000
    #define MBTOP_ILPM_6_SHIFT 24
    #define MBTOP_ILPM_7_MASK 0xF0000000
    #define MBTOP_ILPM_7_SHIFT 28
#define  GVP_EE_MBTOP_HDR2 0x81DC
    #define MBTOP_ILPM_8_MASK 0x0000000F
    #define MBTOP_ILPM_8_SHIFT 0
    #define MBTOP_ILPM_9_MASK 0x000000F0
    #define MBTOP_ILPM_9_SHIFT 4
    #define MBTOP_ILPM_10_MASK 0x00000F00
    #define MBTOP_ILPM_10_SHIFT 8
    #define MBTOP_ILPM_11_MASK 0x0000F000
    #define MBTOP_ILPM_11_SHIFT 12
    #define MBTOP_ILPM_12_MASK 0x000F0000
    #define MBTOP_ILPM_12_SHIFT 16
    #define MBTOP_ILPM_13_MASK 0x00F00000
    #define MBTOP_ILPM_13_SHIFT 20
    #define MBTOP_ILPM_14_MASK 0x0F000000
    #define MBTOP_ILPM_14_SHIFT 24
    #define MBTOP_ILPM_15_MASK 0xF0000000
    #define MBTOP_ILPM_15_SHIFT 28
#define  GVP_EE_MVD_ADR 0x8368
    #define GVP_EE_MVD_ADR_BASE_MASK 0x1FFFFFF8
    #define GVP_EE_MVD_ADR_BASE_SHIFT 3
#define  GVP_EE_MVD_BUF_SIZE 0x836C
    #define GVP_EE_MVD_BUF_SIZE_SIZE_MASK 0x007FFFF8
    #define GVP_EE_MVD_BUF_SIZE_SIZE_SHIFT 3
#define  GVP_EE_MVD_CURR_ADR 0x8248
    #define GVP_EE_MVD_CURR_ADR_OFFSET_MASK 0x007FFFFC
    #define GVP_EE_MVD_CURR_ADR_OFFSET_SHIFT 2
#define  GVP_EE_MVD_OFFSET 0x81F0
    #define GVP_EE_MVD_OFFSET_OFFSET_MASK 0x007FFFFC
    #define GVP_EE_MVD_OFFSET_OFFSET_SHIFT 2
#define  GVP_EE_NAL_ADR 0x8200
    #define GVP_EE_NAL_ADR_BASE_MASK 0x1FFFFFF8
    #define GVP_EE_NAL_ADR_BASE_SHIFT 3
#define  GVP_EE_NAL_BUF_SIZE 0x8204
    #define GVP_EE_NAL_BUF_SIZE_SIZE_MASK 0x007FFF00
    #define GVP_EE_NAL_BUF_SIZE_SIZE_SHIFT 8
#define  GVP_EE_NAL_CURR_ADR 0x8240
    #define GVP_EE_NAL_CURR_ADR_OFFSET_MASK 0x007FFFFF
    #define GVP_EE_NAL_CURR_ADR_OFFSET_SHIFT 0
#define  GVP_EE_RLAC_ADR 0x8378
    #define GVP_EE_RLAC_ADR_BASE_MASK 0x1FFFFFF8
    #define GVP_EE_RLAC_ADR_BASE_SHIFT 3
#define  GVP_EE_RLAC_BUF_SIZE 0x837C
    #define GVP_EE_RLAC_BUF_SIZE_SIZE_MASK 0x00FFFFF8
    #define GVP_EE_RLAC_BUF_SIZE_SIZE_SHIFT 3
#define  GVP_EE_RLAC_CURR_ADR 0x8250
    #define GVP_EE_RLAC_CURR_ADR_OFFSET_MASK 0x00FFFFFC
    #define GVP_EE_RLAC_CURR_ADR_OFFSET_SHIFT 2
#define  GVP_EE_RLAC_OFFSET 0x81F8
    #define GVP_EE_RLAC_OFFSET_OFFSET_MASK 0x00FFFFFC
    #define GVP_EE_RLAC_OFFSET_OFFSET_SHIFT 2
#define  GVP_EE_RLDC_ADR 0x8370
    #define GVP_EE_RLDC_ADR_BASE_MASK 0x1FFFFFF8
    #define GVP_EE_RLDC_ADR_BASE_SHIFT 3
#define  GVP_EE_RLDC_BUF_SIZE 0x8374
    #define GVP_EE_RLDC_BUF_SIZE_SIZE_MASK 0x000FFFF8
    #define GVP_EE_RLDC_BUF_SIZE_SIZE_SHIFT 3
#define  GVP_EE_RLDC_CURR_ADR 0x824C
    #define GVP_EE_RLDC_CURR_ADR_OFFSET_MASK 0x000FFFFC
    #define GVP_EE_RLDC_CURR_ADR_OFFSET_SHIFT 2
#define  GVP_EE_RLDC_OFFSET 0x81F4
    #define GVP_EE_RLDC_OFFSET_OFFSET_MASK 0x000FFFFC
    #define GVP_EE_RLDC_OFFSET_OFFSET_SHIFT 2
#define  GVP_EE_SLICE_HDR0 0x8218
    #define PIC_PARAMETER_SET_ID_MASK 0x000000FF
    #define PIC_PARAMETER_SET_ID_SHIFT 0
    #define GVP_EE_SLICE_HDR0_SLICE_TYPE_MASK 0x00000F00
    #define GVP_EE_SLICE_HDR0_SLICE_TYPE_SHIFT 8
    #define FIRST_MB_IN_SLICE_MASK 0x00FF0000
    #define FIRST_MB_IN_SLICE_SHIFT 16
#define  GVP_EE_SLICE_HDR1 0x821C
    #define FRAME_NUM_MASK 0x0000FFFF
    #define FRAME_NUM_SHIFT 0
#define  GVP_EE_SLICE_HDR2 0x8220
    #define IDR_PIC_ID_MASK 0x0000FFFF
    #define IDR_PIC_ID_SHIFT 0
    #define DELTA_PIC_ORDER_ALWAYS_ZERO_MASK 0x01000000
    #define DELTA_PIC_ORDER_ALWAYS_ZERO_SHIFT 24
    #define PIC_ORDER_PRESENT_FLAG_MASK 0x02000000
    #define PIC_ORDER_PRESENT_FLAG_SHIFT 25
    #define PIC_ORDER_CNT_TYPE_MASK 0x0C000000
    #define PIC_ORDER_CNT_TYPE_SHIFT 26
    #define FIELD_PIC_FLAG_MASK 0x40000000
    #define FIELD_PIC_FLAG_SHIFT 30
    #define FRAME_MBS_ONLY_FLAG_MASK 0x80000000
    #define FRAME_MBS_ONLY_FLAG_SHIFT 31
#define  GVP_EE_SLICE_HDR3 0x8224
    #define PIC_ORDER_CNT_LSB_MASK 0x0000FFFF
    #define PIC_ORDER_CNT_LSB_SHIFT 0
#define  GVP_EE_SLICE_HDR4 0x8228
    #define DELTA_PIC_ORDER_CNT_BOTTOM_MASK 0xFFFFFFFF
    #define DELTA_PIC_ORDER_CNT_BOTTOM_SHIFT 0
#define  GVP_EE_SLICE_HDR5 0x822C
    #define DELTA_PIC_ORDER_CNT0_MASK 0xFFFFFFFF
    #define DELTA_PIC_ORDER_CNT0_SHIFT 0
#define  GVP_EE_SLICE_HDR6 0x8230
    #define DELTA_PIC_ORDER_CNT1_MASK 0xFFFFFFFF
    #define DELTA_PIC_ORDER_CNT1_SHIFT 0
#define  GVP_EE_SLICE_HDR7 0x8234
    #define NUM_REF_IDX_L1_MINUS1_MASK 0x0000001F
    #define NUM_REF_IDX_L1_MINUS1_SHIFT 0
    #define NUM_REF_IDX_L0_MINUS1_MASK 0x00001F00
    #define NUM_REF_IDX_L0_MINUS1_SHIFT 8
    #define NUM_REF_IDX_OVERRIDE_MASK 0x01000000
    #define NUM_REF_IDX_OVERRIDE_SHIFT 24
    #define DIRECT_SPATIAL_MV_PRED_MASK 0x80000000
    #define DIRECT_SPATIAL_MV_PRED_SHIFT 31
#define  GVP_EE_SLICE_HDR8 0x8238
    #define SLICE_QP_DELTA_MASK 0x0000007F
    #define SLICE_QP_DELTA_SHIFT 0
    #define CABAC_INIT_IDC_MASK 0x00000300
    #define CABAC_INIT_IDC_SHIFT 8
    #define ADPT_REF_PIC_MARKING_MODE_MASK 0x00200000
    #define ADPT_REF_PIC_MARKING_MODE_SHIFT 21
    #define LONG_TERM_REFERENCE_FLAG_MASK 0x00400000
    #define LONG_TERM_REFERENCE_FLAG_SHIFT 22
    #define NO_OUTPUT_OF_PRIOR_PICS_FLAG_MASK 0x00800000
    #define NO_OUTPUT_OF_PRIOR_PICS_FLAG_SHIFT 23
    #define REF_PIC_LIST_REORDERING_L1_MASK 0x40000000
    #define REF_PIC_LIST_REORDERING_L1_SHIFT 30
    #define REF_PIC_LIST_REORDERING_L0_MASK 0x80000000
    #define REF_PIC_LIST_REORDERING_L0_SHIFT 31
#define  GVP_EE_SLICE_HDR9 0x823C
    #define SLICE_BETA_OFFSET_DIV2_MASK 0x0000001F
    #define SLICE_BETA_OFFSET_DIV2_SHIFT 0
    #define SLICE_ALPHA_OFFSET_MASK 0x00001F00
    #define SLICE_ALPHA_OFFSET_SHIFT 8
    #define DISABLE_DBF_IDC_MASK 0x30000000
    #define DISABLE_DBF_IDC_SHIFT 28
    #define DBF_CONTROL_PRESENT_MASK 0x80000000
    #define DBF_CONTROL_PRESENT_SHIFT 31
#define  GVP_EE_SLICE_INF0 0x820C
    #define DEF_NUM_REF_IDX_L1_MINUS1_MASK 0x0000001F
    #define DEF_NUM_REF_IDX_L1_MINUS1_SHIFT 0
    #define DEF_NUM_REF_IDX_L0_MINUS1_MASK 0x00001F00
    #define DEF_NUM_REF_IDX_L0_MINUS1_SHIFT 8
    #define GVP_EE_SLICE_INF0_START_CODE_MASK 0x00030000
    #define GVP_EE_SLICE_INF0_START_CODE_SHIFT 16
    #define SYMBOL_MODE_MASK 0x00040000
    #define SYMBOL_MODE_SHIFT 18
    #define GVP_EE_SLICE_INF0_MBAFF_FLAG_MASK 0x00080000
    #define GVP_EE_SLICE_INF0_MBAFF_FLAG_SHIFT 19
    #define TRANSFORM_8X8_MODE_FLAG_MASK 0x00200000
    #define TRANSFORM_8X8_MODE_FLAG_SHIFT 21
    #define GVP_EE_SLICE_INF0_NAL_UNIT_TYPE_MASK 0x1F000000
    #define GVP_EE_SLICE_INF0_NAL_UNIT_TYPE_SHIFT 24
    #define GVP_EE_SLICE_INF0_NAL_REF_IDC_MASK 0x60000000
    #define GVP_EE_SLICE_INF0_NAL_REF_IDC_SHIFT 29
#define  GVP_EE_SLICE_INF1 0x8210
    #define FRAME_SIZE_IN_MB_MASK 0x0000FFFF
    #define FRAME_SIZE_IN_MB_SHIFT 0
    #define GVP_EE_SLICE_INF1_PICT_MB_WIDTH_MASK 0x00FF0000
    #define GVP_EE_SLICE_INF1_PICT_MB_WIDTH_SHIFT 16
#define  GVP_EE_SLICE_INF2 0x8214
    #define MAX_FRAME_NUM_BITS_MASK 0x0000003F
    #define MAX_FRAME_NUM_BITS_SHIFT 0
    #define MAX_PIC_ORDER_CNT_LSB_BITS_MASK 0x00003F00
    #define MAX_PIC_ORDER_CNT_LSB_BITS_SHIFT 8
#define  GVP_EE_STATUS 0x81B0
    #define LAST_CPL_MB_MASK 0x0000FFFF
    #define LAST_CPL_MB_SHIFT 0
    #define GVP_EE_STATUS_FREE_ENTRIES_MASK 0x00F00000
    #define GVP_EE_STATUS_FREE_ENTRIES_SHIFT 20
    #define SLICE_IN_PROGRESS_MASK 0x01000000
    #define SLICE_IN_PROGRESS_SHIFT 24
    #define GVP_EE_STATUS_ERROR_MASK 0x02000000
    #define GVP_EE_STATUS_ERROR_SHIFT 25
    #define GVP_EE_STATUS_BUSY_MASK 0x04000000
    #define GVP_EE_STATUS_BUSY_SHIFT 26
    #define GVP_EE_STATUS_INT_MASK 0x08000000
    #define GVP_EE_STATUS_INT_SHIFT 27
#define  GVP_FREE_STATUS 0x839C
    #define MS_FREE_ENTRIES_MASK 0x0000003F
    #define MS_FREE_ENTRIES_SHIFT 0
    #define IP_FREE_ENTRIES_MASK 0x00001F00
    #define IP_FREE_ENTRIES_SHIFT 8
    #define NMB_FREE_ENTRIES_MASK 0x00070000
    #define NMB_FREE_ENTRIES_SHIFT 16
    #define DBK_FREE_ENTRIES_MASK 0x00700000
    #define DBK_FREE_ENTRIES_SHIFT 20
    #define MR_FREE_ENTRIES_MASK 0x1F000000
    #define MR_FREE_ENTRIES_SHIFT 24
#define  GVP_IPTQZ_TOPNBR_C_ADR 0x8144
    #define GVP_IPTQZ_TOPNBR_C_ADR_BASE_MASK 0x1FFFFF00
    #define GVP_IPTQZ_TOPNBR_C_ADR_BASE_SHIFT 8
#define  GVP_IPTQZ_TOPNBR_Y_ADR 0x8140
    #define GVP_IPTQZ_TOPNBR_Y_ADR_BASE_MASK 0x1FFFFF00
    #define GVP_IPTQZ_TOPNBR_Y_ADR_BASE_SHIFT 8
#define  GVP_IP_CMDFIFO_0 0x80F0
    #define MODE0_8X8L_MASK 0x00000001
    #define MODE0_8X8L_SHIFT 0
    #define MODE1_8X8L_MASK 0x00000002
    #define MODE1_8X8L_SHIFT 1
    #define MODE2_8X8L_MASK 0x00000004
    #define MODE2_8X8L_SHIFT 2
    #define MODE3_8X8L_MASK 0x00000008
    #define MODE3_8X8L_SHIFT 3
    #define MODE0_4X4_MASK 0x00000010
    #define MODE0_4X4_SHIFT 4
    #define MODE1_4X4_MASK 0x00000020
    #define MODE1_4X4_SHIFT 5
    #define MODE2_4X4_MASK 0x00000040
    #define MODE2_4X4_SHIFT 6
    #define MODE3_4X4_MASK 0x00000080
    #define MODE3_4X4_SHIFT 7
    #define MODE4_4X4_MASK 0x00000100
    #define MODE4_4X4_SHIFT 8
    #define MODE5_4X4_MASK 0x00000200
    #define MODE5_4X4_SHIFT 9
    #define MODE6_4X4_MASK 0x00000400
    #define MODE6_4X4_SHIFT 10
    #define MODE7_4X4_MASK 0x00000800
    #define MODE7_4X4_SHIFT 11
    #define MODE8_4X4_MASK 0x00001000
    #define MODE8_4X4_SHIFT 12
    #define MODE4_8X8L_MASK 0x00002000
    #define MODE4_8X8L_SHIFT 13
    #define MODE5_8X8L_MASK 0x00004000
    #define MODE5_8X8L_SHIFT 14
    #define MODE6_8X8L_MASK 0x00008000
    #define MODE6_8X8L_SHIFT 15
    #define MODE0_16X16_MASK 0x00010000
    #define MODE0_16X16_SHIFT 16
    #define MODE1_16X16_MASK 0x00020000
    #define MODE1_16X16_SHIFT 17
    #define MODE2_16X16_MASK 0x00040000
    #define MODE2_16X16_SHIFT 18
    #define MODE3_16X16_MASK 0x00080000
    #define MODE3_16X16_SHIFT 19
    #define MODE0_8X8_MASK 0x00100000
    #define MODE0_8X8_SHIFT 20
    #define MODE1_8X8_MASK 0x00200000
    #define MODE1_8X8_SHIFT 21
    #define MODE2_8X8_MASK 0x00400000
    #define MODE2_8X8_SHIFT 22
    #define MODE3_8X8_MASK 0x00800000
    #define MODE3_8X8_SHIFT 23
    #define FRAME_PRED_DIS_MASK 0x01000000
    #define FRAME_PRED_DIS_SHIFT 24
    #define FIELD_PRED_DIS_MASK 0x02000000
    #define FIELD_PRED_DIS_SHIFT 25
    #define FRAME_PRED_DIS_8X8L_MASK 0x04000000
    #define FRAME_PRED_DIS_8X8L_SHIFT 26
    #define FIELD_PRED_DIS_8X8L_MASK 0x08000000
    #define FIELD_PRED_DIS_8X8L_SHIFT 27
    #define MODE7_8X8L_MASK 0x10000000
    #define MODE7_8X8L_SHIFT 28
    #define MODE8_8X8L_MASK 0x20000000
    #define MODE8_8X8L_SHIFT 29
#define  GVP_IP_CMDFIFO_1 0x80F4
    #define CURRENT_Y_MASK 0x0000000F
    #define CURRENT_Y_SHIFT 0
    #define CURRENT_C_MASK 0x000000F0
    #define CURRENT_C_SHIFT 4
    #define TOPNBR_MASK 0x00FF0000
    #define TOPNBR_SHIFT 16
#define  GVP_IP_CMDFIFO_2 0x80FC
    #define MODE_A_TOP_MASK 0x0000000F
    #define MODE_A_TOP_SHIFT 0
    #define MODE_B_TOP_MASK 0x000000F0
    #define MODE_B_TOP_SHIFT 4
    #define MODE_C_TOP_MASK 0x00000F00
    #define MODE_C_TOP_SHIFT 8
    #define MODE_D_TOP_MASK 0x0000F000
    #define MODE_D_TOP_SHIFT 12
    #define MODE_A_BOT_MASK 0x000F0000
    #define MODE_A_BOT_SHIFT 16
    #define MODE_B_BOT_MASK 0x00F00000
    #define MODE_B_BOT_SHIFT 20
    #define MODE_C_BOT_MASK 0x0F000000
    #define MODE_C_BOT_SHIFT 24
    #define MODE_D_BOT_MASK 0xF0000000
    #define MODE_D_BOT_SHIFT 28
#define  GVP_IP_CMDFIFO_3 0x8100
    #define SATD_SAD_MASK 0x00000001
    #define SATD_SAD_SHIFT 0
    #define TOP_AVAIL_MASK 0x00000010
    #define TOP_AVAIL_SHIFT 4
    #define LEFT_AVAIL_MASK 0x00000020
    #define LEFT_AVAIL_SHIFT 5
    #define TOP_LEFT_AVAIL_MASK 0x00000040
    #define TOP_LEFT_AVAIL_SHIFT 6
    #define TOP_RIGHT_AVAIL_MASK 0x00000080
    #define TOP_RIGHT_AVAIL_SHIFT 7
    #define GVP_IP_CMDFIFO_3_LAMBDA_MASK 0x00007F00
    #define GVP_IP_CMDFIFO_3_LAMBDA_SHIFT 8
    #define GVP_IP_CMDFIFO_3_CMD_TAG_MASK 0x07F00000
    #define GVP_IP_CMDFIFO_3_CMD_TAG_SHIFT 20
#define  GVP_IP_CMDFIFO_4 0x8104
    #define PAR_INDX_MASK 0x000000FF
    #define PAR_INDX_SHIFT 0
    #define IP_ROW_INDX_MASK 0x0000FF00
    #define IP_ROW_INDX_SHIFT 8
    #define RECON_INDX_MASK 0x000F0000
    #define RECON_INDX_SHIFT 16
    #define QP_MASK 0x03F00000
    #define QP_SHIFT 20
#define  GVP_IP_TQZ_DUMMY_REG 0x8108
    #define GVP_IP_TQZ_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define GVP_IP_TQZ_DUMMY_REG_DATA_SHIFT 0
#define  GVP_IP_TQZ_STATUS 0x810C
    #define GVP_IP_TQZ_STATUS_IP_BUSY_MASK 0x00000001
    #define GVP_IP_TQZ_STATUS_IP_BUSY_SHIFT 0
    #define IP_DONE_MASK 0x00000002
    #define IP_DONE_SHIFT 1
    #define GVP_IP_TQZ_STATUS_TQZ_BUSY_MASK 0x00000010
    #define GVP_IP_TQZ_STATUS_TQZ_BUSY_SHIFT 4
    #define TQZ_FWD_BUSY_MASK 0x00000020
    #define TQZ_FWD_BUSY_SHIFT 5
    #define TQZ_INV_BUSY_MASK 0x00000040
    #define TQZ_INV_BUSY_SHIFT 6
    #define TQZ_RL_BUSY_MASK 0x00000080
    #define TQZ_RL_BUSY_SHIFT 7
    #define TQZ_RL_WBUSY_MASK 0x00000100
    #define TQZ_RL_WBUSY_SHIFT 8
    #define TQZ_RECON_WBUSY_MASK 0x00000200
    #define TQZ_RECON_WBUSY_SHIFT 9
    #define TQZ_PAR_WBUSY_MASK 0x00000400
    #define TQZ_PAR_WBUSY_SHIFT 10
    #define GVP_IP_TQZ_STATUS_CMD_STATUS_MASK 0x0007F000
    #define GVP_IP_TQZ_STATUS_CMD_STATUS_SHIFT 12
    #define GVP_IP_TQZ_STATUS_FREE_ENTRIES_MASK 0x01F00000
    #define GVP_IP_TQZ_STATUS_FREE_ENTRIES_SHIFT 20
#define  GVP_MD_BIAS_0 0x82F0
    #define BIAS_INTRA_FRM_MASK 0x0000001F
    #define BIAS_INTRA_FRM_SHIFT 0
    #define BIAS_INTRA_FLD_MASK 0x000003E0
    #define BIAS_INTRA_FLD_SHIFT 5
    #define BIAS_DIRECT_16X16_FRM_MASK 0x00007C00
    #define BIAS_DIRECT_16X16_FRM_SHIFT 10
    #define BIAS_DIRECT_16X16_FLD_MASK 0x000F8000
    #define BIAS_DIRECT_16X16_FLD_SHIFT 15
    #define BIAS_16X16_FLD_MASK 0x01F00000
    #define BIAS_16X16_FLD_SHIFT 20
#define  GVP_MD_BIAS_1 0x82F4
    #define BIAS_16X8_FRM_MASK 0x0000001F
    #define BIAS_16X8_FRM_SHIFT 0
    #define BIAS_8X16_FRM_MASK 0x000003E0
    #define BIAS_8X16_FRM_SHIFT 5
    #define BIAS_8X8_ONE_DIR_FRM_MASK 0x00007C00
    #define BIAS_8X8_ONE_DIR_FRM_SHIFT 10
    #define BIAS_8X8_BIDIR_FRM_MASK 0x000F8000
    #define BIAS_8X8_BIDIR_FRM_SHIFT 15
    #define BIAS_8X8_DIRECT_FRM_MASK 0x01F00000
    #define BIAS_8X8_DIRECT_FRM_SHIFT 20
#define  GVP_MD_BIAS_2 0x82F8
    #define BIAS_16X8_FLD_MASK 0x0000001F
    #define BIAS_16X8_FLD_SHIFT 0
    #define BIAS_8X16_FLD_MASK 0x000003E0
    #define BIAS_8X16_FLD_SHIFT 5
    #define BIAS_8X8_ONE_DIR_FLD_MASK 0x00007C00
    #define BIAS_8X8_ONE_DIR_FLD_SHIFT 10
    #define BIAS_8X8_BIDIR_FLD_MASK 0x000F8000
    #define BIAS_8X8_BIDIR_FLD_SHIFT 15
    #define BIAS_8X8_DIRECT_FLD_MASK 0x01F00000
    #define BIAS_8X8_DIRECT_FLD_SHIFT 20
#define  GVP_MR_CMD_FIFO_0 0x80B4
    #define TASK_MASK 0x00000003
    #define TASK_SHIFT 0
    #define GVP_MR_CMD_FIFO_0_DIRECTION_MASK 0x0000001C
    #define GVP_MR_CMD_FIFO_0_DIRECTION_SHIFT 2
    #define WRITE_COST_MASK 0x00000020
    #define WRITE_COST_SHIFT 5
    #define GVP_MR_CMD_FIFO_0_PARTITIONS_MASK 0xFFFFFFC0
    #define GVP_MR_CMD_FIFO_0_PARTITIONS_SHIFT 6
#define  GVP_MR_CMD_FIFO_1 0x80B8
    #define GVP_MR_CMD_FIFO_1_PARTITIONS_MASK 0x000FFFFF
    #define GVP_MR_CMD_FIFO_1_PARTITIONS_SHIFT 0
    #define GVP_MR_CMD_FIFO_1_CMD_TAG_MASK 0x07F00000
    #define GVP_MR_CMD_FIFO_1_CMD_TAG_SHIFT 20
    #define GVP_MR_CMD_FIFO_1_DONE_MASK 0x08000000
    #define GVP_MR_CMD_FIFO_1_DONE_SHIFT 27
    #define PRED_DIFF_INDEX_MASK 0xF0000000
    #define PRED_DIFF_INDEX_SHIFT 28
#define  GVP_MR_CMD_FIFO_2 0x80BC
    #define CUR_Y_INDEX_MASK 0x0000000F
    #define CUR_Y_INDEX_SHIFT 0
    #define CUR_C_INDEX_MASK 0x000000F0
    #define CUR_C_INDEX_SHIFT 4
    #define FWD_INDEX_MASK 0x00000F00
    #define FWD_INDEX_SHIFT 8
    #define BWD_INDEX_MASK 0x0000F000
    #define BWD_INDEX_SHIFT 12
    #define BLEND_INDEX_MASK 0x000F0000
    #define BLEND_INDEX_SHIFT 16
    #define FIRST_ENTRY_MASK 0x00100000
    #define FIRST_ENTRY_SHIFT 20
    #define THRESHOLD_ENABLE_MASK 0x00200000
    #define THRESHOLD_ENABLE_SHIFT 21
    #define BEST_MB_PARTITION_MASK 0x00400000
    #define BEST_MB_PARTITION_SHIFT 22
    #define LAST_ENTRY_MASK 0x00800000
    #define LAST_ENTRY_SHIFT 23
    #define DIRECT_TOP_FRM_FLD_SEL_MASK 0x03000000
    #define DIRECT_TOP_FRM_FLD_SEL_SHIFT 24
    #define DIRECT_BOT_FRM_FLD_SEL_MASK 0x0C000000
    #define DIRECT_BOT_FRM_FLD_SEL_SHIFT 26
    #define WRITE_PRED_PELS_MASK 0x30000000
    #define WRITE_PRED_PELS_SHIFT 28
    #define WRITE_DIFF_PELS_MASK 0xC0000000
    #define WRITE_DIFF_PELS_SHIFT 30
#define  GVP_MR_CMD_FIFO_3 0x80C0
    #define CUR_MB_X_MASK 0x0000007F
    #define CUR_MB_X_SHIFT 0
    #define CUR_MB_Y_MASK 0x00007F00
    #define CUR_MB_Y_SHIFT 8
    #define GVP_MR_CMD_FIFO_3_LAMBDA_MASK 0x007F0000
    #define GVP_MR_CMD_FIFO_3_LAMBDA_SHIFT 16
    #define GVP_MR_CMD_FIFO_3_MB_INCREMENT_MASK 0x00800000
    #define GVP_MR_CMD_FIFO_3_MB_INCREMENT_SHIFT 23
    #define WRITE_LUMA_MASK 0x01000000
    #define WRITE_LUMA_SHIFT 24
    #define WRITE_CHROMA_MASK 0x02000000
    #define WRITE_CHROMA_SHIFT 25
    #define BWD_REF_INDEX_MASK 0x1C000000
    #define BWD_REF_INDEX_SHIFT 26
    #define FWD_REF_INDEX_MASK 0xE0000000
    #define FWD_REF_INDEX_SHIFT 29
#define  GVP_MR_CTRL 0x80C4
    #define MOTION_COMP_MASK 0x00000001
    #define MOTION_COMP_SHIFT 0
    #define REF_SLICE_MASK 0x00000002
    #define REF_SLICE_SHIFT 1
    #define SATD_MASK 0x00000004
    #define SATD_SHIFT 2
    #define FULL_PEL_REFINE_MASK 0x00000008
    #define FULL_PEL_REFINE_SHIFT 3
    #define HALF_PEL_REFINE_MASK 0x00000010
    #define HALF_PEL_REFINE_SHIFT 4
    #define QUARTER_PEL_REFINE_MASK 0x00000020
    #define QUARTER_PEL_REFINE_SHIFT 5
    #define BILINEAR_FILTER_MASK 0x00000040
    #define BILINEAR_FILTER_SHIFT 6
    #define LOCK_STEP_MODE_MASK 0x00000100
    #define LOCK_STEP_MODE_SHIFT 8
    #define FULL_PEL_4X1_REFINE_MASK 0x00000200
    #define FULL_PEL_4X1_REFINE_SHIFT 9
    #define SELECT_FRM_OR_FLD_MASK 0x00000400
    #define SELECT_FRM_OR_FLD_SHIFT 10
    #define DMV_16X16_ONLY_MASK 0x00000800
    #define DMV_16X16_ONLY_SHIFT 11
    #define SELECT_FWD_OR_BWD_MASK 0x00001000
    #define SELECT_FWD_OR_BWD_SHIFT 12
    #define PARTITION_DISABLE_MASK 0x00002000
    #define PARTITION_DISABLE_SHIFT 13
    #define SELECT_BEST_FRM_OR_FLD_MASK 0x00004000
    #define SELECT_BEST_FRM_OR_FLD_SHIFT 14
    #define VC1_MODE_MASK 0x00010000
    #define VC1_MODE_SHIFT 16
    #define VC1_ROUNDING_CTRL_MASK 0x00020000
    #define VC1_ROUNDING_CTRL_SHIFT 17
    #define CHECK_DMV_IF_STATIONARY_MASK 0x00040000
    #define CHECK_DMV_IF_STATIONARY_SHIFT 18
    #define DISABLE_BLD_WR_MASK 0x00100000
    #define DISABLE_BLD_WR_SHIFT 20
    #define MS_LOCK_STEP_EN_MASK 0x00200000
    #define MS_LOCK_STEP_EN_SHIFT 21
    #define USE_DMV_AS_PMV_MASK 0x00400000
    #define USE_DMV_AS_PMV_SHIFT 22
    #define ALTERNATE_FWDBWD_MASK 0x00800000
    #define ALTERNATE_FWDBWD_SHIFT 23
    #define FWD_FLD_TILE_MASK 0x01000000
    #define FWD_FLD_TILE_SHIFT 24
    #define BWD_FLD_TILE_MASK 0x02000000
    #define BWD_FLD_TILE_SHIFT 25
    #define GVP_MR_CTRL_SOFT_RESET_MASK 0x80000000
    #define GVP_MR_CTRL_SOFT_RESET_SHIFT 31
#define  GVP_MR_FWD_BWD_THRESHOLD 0x80DC
    #define MR_FWD_BWD_THRESHOLD_MASK 0x0007FFFF
    #define MR_FWD_BWD_THRESHOLD_SHIFT 0
#define  GVP_MR_MV_SCALE 0x80E8
    #define MR_MV_SCL_X_MASK 0x0000FFFF
    #define MR_MV_SCL_X_SHIFT 0
    #define MR_MV_SCL_Y_MASK 0xFFFF0000
    #define MR_MV_SCL_Y_SHIFT 16
#define  GVP_MR_REFINE_THRESHOLD 0x80E0
    #define THRESHOLD_COST_MASK 0x003FFFFF
    #define THRESHOLD_COST_SHIFT 0
#define  GVP_MR_STATUS 0x80B0
    #define GVP_MR_STATUS_CMD_STATUS_MASK 0x0000007F
    #define GVP_MR_STATUS_CMD_STATUS_SHIFT 0
    #define GVP_MR_STATUS_FREE_ENTRIES_MASK 0x001F0000
    #define GVP_MR_STATUS_FREE_ENTRIES_SHIFT 16
    #define GVP_MR_STATUS_BUSY_MASK 0x80000000
    #define GVP_MR_STATUS_BUSY_SHIFT 31
#define  GVP_MSR_BIAS 0x80C8
    #define DEFAULT_PRED_BIAS_MASK 0x00000001
    #define DEFAULT_PRED_BIAS_SHIFT 0
    #define DEFAULT_FIELD_BIAS_MASK 0x00000002
    #define DEFAULT_FIELD_BIAS_SHIFT 1
    #define PRED_BIAS_MASK 0x00001FFC
    #define PRED_BIAS_SHIFT 2
    #define FIELD_REF0_BIAS_MASK 0x003FE000
    #define FIELD_REF0_BIAS_SHIFT 13
    #define FIELD_REF1_BIAS_MASK 0xFFC00000
    #define FIELD_REF1_BIAS_SHIFT 22
#define  GVP_MSR_COST_ADR 0x8038
    #define GVP_MSR_COST_ADR_BASE_MASK 0x1FFFFF00
    #define GVP_MSR_COST_ADR_BASE_SHIFT 8
#define  GVP_MSR_DUMMY_REG 0x80CC
    #define GVP_MSR_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define GVP_MSR_DUMMY_REG_DATA_SHIFT 0
#define  GVP_MSR_MV_SCALE 0x80E4
    #define GVP_MSR_MV_SCALE_MV_SCL_X_MASK 0x0000FFFF
    #define GVP_MSR_MV_SCALE_MV_SCL_X_SHIFT 0
    #define GVP_MSR_MV_SCALE_MV_SCL_Y_MASK 0xFFFF0000
    #define GVP_MSR_MV_SCALE_MV_SCL_Y_SHIFT 16
#define  GVP_MS_BIAS 0x80A4
    #define BIAS_16X8_MASK 0x0000FFFF
    #define BIAS_16X8_SHIFT 0
    #define BIAS_8X8_MASK 0xFFFF0000
    #define BIAS_8X8_SHIFT 16
#define  GVP_MS_CMD_FIFO_0 0x8074
    #define SMV_Y_MASK 0x000003FF
    #define SMV_Y_SHIFT 0
    #define SMV_X_MASK 0x0FFF0000
    #define SMV_X_SHIFT 16
    #define LAST_CMD_MASK 0x80000000
    #define LAST_CMD_SHIFT 31
#define  GVP_MS_CMD_FIFO_1 0x8078
    #define PMV_Y_MASK 0x00000FFF
    #define PMV_Y_SHIFT 0
    #define SML_SRCH_DIS_MASK 0x00001000
    #define SML_SRCH_DIS_SHIFT 12
    #define LRG_SRCH_DIS_MASK 0x00002000
    #define LRG_SRCH_DIS_SHIFT 13
    #define ET_SML_FLAG_MASK 0x00004000
    #define ET_SML_FLAG_SHIFT 14
    #define ET_LRG_FLAG_MASK 0x00008000
    #define ET_LRG_FLAG_SHIFT 15
    #define PMV_X_MASK 0x3FFF0000
    #define PMV_X_SHIFT 16
    #define ET_MED_FLAG_MASK 0x40000000
    #define ET_MED_FLAG_SHIFT 30
    #define ET_NEG_COST_MASK 0x80000000
    #define ET_NEG_COST_SHIFT 31
#define  GVP_MS_CMD_FIFO_2 0x807C
    #define GVP_MS_CMD_FIFO_2_LAMBDA_MASK 0x0000007F
    #define GVP_MS_CMD_FIFO_2_LAMBDA_SHIFT 0
    #define HOLD_PREV_COST_MASK 0x00000080
    #define HOLD_PREV_COST_SHIFT 7
    #define CUR_INDEX_MASK 0x00000F00
    #define CUR_INDEX_SHIFT 8
    #define OUT_INDEX_MASK 0x0000F000
    #define OUT_INDEX_SHIFT 12
    #define REF_INDEX_MASK 0x00070000
    #define REF_INDEX_SHIFT 16
    #define OUTPUT_MV_DIS_MASK 0x00080000
    #define OUTPUT_MV_DIS_SHIFT 19
    #define GVP_MS_CMD_FIFO_2_MB_INCREMENT_MASK 0x00100000
    #define GVP_MS_CMD_FIFO_2_MB_INCREMENT_SHIFT 20
    #define PMV_EQ_SMV_MASK 0x00200000
    #define PMV_EQ_SMV_SHIFT 21
    #define ONE_FLD_FLAG_MASK 0x00C00000
    #define ONE_FLD_FLAG_SHIFT 22
    #define GVP_MS_CMD_FIFO_2_CMD_TAG_MASK 0xFF000000
    #define GVP_MS_CMD_FIFO_2_CMD_TAG_SHIFT 24
#define  GVP_MS_CTRL 0x8094
    #define GVP_MS_CTRL_SOFT_RESET_MASK 0x00000001
    #define GVP_MS_CTRL_SOFT_RESET_SHIFT 0
    #define SCALE_PIC_MASK 0x0000000C
    #define SCALE_PIC_SHIFT 2
    #define LO_HI_DIS_MASK 0x00000010
    #define LO_HI_DIS_SHIFT 4
    #define OUTPUT_COST_MASK 0x00000100
    #define OUTPUT_COST_SHIFT 8
    #define OUTPUT_STAT_MASK 0x00000200
    #define OUTPUT_STAT_SHIFT 9
    #define OUTPUT_XTRA_HINT_MASK 0x00000400
    #define OUTPUT_XTRA_HINT_SHIFT 10
    #define PARTN_RATIO_MASK 0x00007000
    #define PARTN_RATIO_SHIFT 12
    #define FRFL_RATIO_MASK 0x00070000
    #define FRFL_RATIO_SHIFT 16
    #define ET_16X16_FRM_DIS_MASK 0x00100000
    #define ET_16X16_FRM_DIS_SHIFT 20
    #define ET_16X8_FRM_DIS_MASK 0x00200000
    #define ET_16X8_FRM_DIS_SHIFT 21
    #define ET_8X16_FRM_DIS_MASK 0x00400000
    #define ET_8X16_FRM_DIS_SHIFT 22
    #define ET_8X8_FRM_DIS_MASK 0x00800000
    #define ET_8X8_FRM_DIS_SHIFT 23
    #define ET_S8X8_FRM_DIS_MASK 0x01000000
    #define ET_S8X8_FRM_DIS_SHIFT 24
    #define ET_16X16_FLD_DIS_MASK 0x02000000
    #define ET_16X16_FLD_DIS_SHIFT 25
    #define ET_16X8_FLD_DIS_MASK 0x04000000
    #define ET_16X8_FLD_DIS_SHIFT 26
    #define ET_8X16_FLD_DIS_MASK 0x08000000
    #define ET_8X16_FLD_DIS_SHIFT 27
    #define ET_8X8_FLD_DIS_MASK 0x10000000
    #define ET_8X8_FLD_DIS_SHIFT 28
    #define STATIONARY_MASK 0x80000000
    #define STATIONARY_SHIFT 31
#define  GVP_MS_LRG_16_THRESH 0x808C
    #define GVP_MS_LRG_16_THRESH_COST_16X16_MASK 0x0001FFFF
    #define GVP_MS_LRG_16_THRESH_COST_16X16_SHIFT 0
#define  GVP_MS_LRG_8_THRESH 0x8090
    #define GVP_MS_LRG_8_THRESH_COST_16X8_MASK 0x0000FFFF
    #define GVP_MS_LRG_8_THRESH_COST_16X8_SHIFT 0
    #define GVP_MS_LRG_8_THRESH_COST_8X8_MASK 0xFFFF0000
    #define GVP_MS_LRG_8_THRESH_COST_8X8_SHIFT 16
#define  GVP_MS_MED_16_THRESH 0x809C
    #define GVP_MS_MED_16_THRESH_COST_16X16_MASK 0x0001FFFF
    #define GVP_MS_MED_16_THRESH_COST_16X16_SHIFT 0
#define  GVP_MS_MED_8_THRESH 0x80A0
    #define GVP_MS_MED_8_THRESH_COST_16X8_MASK 0x0000FFFF
    #define GVP_MS_MED_8_THRESH_COST_16X8_SHIFT 0
    #define GVP_MS_MED_8_THRESH_COST_8X8_MASK 0xFFFF0000
    #define GVP_MS_MED_8_THRESH_COST_8X8_SHIFT 16
#define  GVP_MS_SML_16_THRESH 0x8084
    #define GVP_MS_SML_16_THRESH_COST_16X16_MASK 0x0001FFFF
    #define GVP_MS_SML_16_THRESH_COST_16X16_SHIFT 0
    #define COST_STATN_MASK 0xFFF00000
    #define COST_STATN_SHIFT 20
#define  GVP_MS_SML_8_THRESH 0x8088
    #define GVP_MS_SML_8_THRESH_COST_16X8_MASK 0x0000FFFF
    #define GVP_MS_SML_8_THRESH_COST_16X8_SHIFT 0
    #define GVP_MS_SML_8_THRESH_COST_8X8_MASK 0xFFFF0000
    #define GVP_MS_SML_8_THRESH_COST_8X8_SHIFT 16
#define  GVP_MS_SRCH_RANGE 0x8080
    #define SML_SRCH_XY_MASK 0x0000003F
    #define SML_SRCH_XY_SHIFT 0
    #define LRG_SRCH_X_MASK 0x00FF0000
    #define LRG_SRCH_X_SHIFT 16
    #define LRG_SRCH_Y_MASK 0xFF000000
    #define LRG_SRCH_Y_SHIFT 24
#define  GVP_MS_START_MB 0x8098
    #define GVP_MS_START_MB_START_MB_X_MASK 0x000000FF
    #define GVP_MS_START_MB_START_MB_X_SHIFT 0
    #define GVP_MS_START_MB_START_MB_Y_MASK 0x00007F00
    #define GVP_MS_START_MB_START_MB_Y_SHIFT 8
#define  GVP_MS_STATUS 0x8070
    #define GVP_MS_STATUS_CMD_STATUS_MASK 0x000000FF
    #define GVP_MS_STATUS_CMD_STATUS_SHIFT 0
    #define GVP_MS_STATUS_FREE_ENTRIES_MASK 0x003F0000
    #define GVP_MS_STATUS_FREE_ENTRIES_SHIFT 16
    #define GVP_MS_STATUS_BUSY_MASK 0x80000000
    #define GVP_MS_STATUS_BUSY_SHIFT 31
#define  GVP_NMB_CMD_FIFO 0x8318
    #define GVP_NMB_CMD_FIFO_COMMAND_TAG_MASK 0x000000FF
    #define GVP_NMB_CMD_FIFO_COMMAND_TAG_SHIFT 0
    #define GVP_NMB_CMD_FIFO_MBH_INDEX_MASK 0x00000F00
    #define GVP_NMB_CMD_FIFO_MBH_INDEX_SHIFT 8
    #define GVP_NMB_CMD_FIFO_DSQA_INDEX_MASK 0x0000F000
    #define GVP_NMB_CMD_FIFO_DSQA_INDEX_SHIFT 12
    #define SMV_INDEX_MASK 0x000F0000
    #define SMV_INDEX_SHIFT 16
    #define MV_SIZE_MASK 0x03F00000
    #define MV_SIZE_SHIFT 20
#define  GVP_NMB_CTRL 0x8314
    #define GVP_NMB_CTRL_MODE_MASK 0x00000003
    #define GVP_NMB_CTRL_MODE_SHIFT 0
    #define GVP_NMB_CTRL_SOFT_RESET_MASK 0x80000000
    #define GVP_NMB_CTRL_SOFT_RESET_SHIFT 31
#define  GVP_NMB_DBG 0x8350
    #define GVP_NMB_DBG_DATA_MASK 0xFFFFFFFF
    #define GVP_NMB_DBG_DATA_SHIFT 0
#define  GVP_NMB_DBG_CTRL 0x834C
    #define GVP_NMB_DBG_CTRL_SEL_MASK 0x0000003F
    #define GVP_NMB_DBG_CTRL_SEL_SHIFT 0
    #define GVP_NMB_DBG_CTRL_MUX_MASK 0x00001F00
    #define GVP_NMB_DBG_CTRL_MUX_SHIFT 8
#define  GVP_NMB_MBH_BASE 0x8320
    #define GVP_NMB_MBH_BASE_ADDR_MASK 0x1FFFFFF8
    #define GVP_NMB_MBH_BASE_ADDR_SHIFT 3
#define  GVP_NMB_MVA_RB_BASE 0x8324
    #define GVP_NMB_MVA_RB_BASE_ADDR_MASK 0x1FFFFFF8
    #define GVP_NMB_MVA_RB_BASE_ADDR_SHIFT 3
#define  GVP_NMB_MVA_RB_CTRL 0x8328
    #define GVP_NMB_MVA_RB_CTRL_SIZE_MASK 0x007FFFFC
    #define GVP_NMB_MVA_RB_CTRL_SIZE_SHIFT 2
#define  GVP_NMB_MVA_RB_RPTR 0x832C
    #define GVP_NMB_MVA_RB_RPTR_OFFSET_MASK 0x007FFFFC
    #define GVP_NMB_MVA_RB_RPTR_OFFSET_SHIFT 2
#define  GVP_NMB_MVA_RB_WPTR 0x8330
    #define GVP_NMB_MVA_RB_WPTR_OFFSET_MASK 0x007FFFFC
    #define GVP_NMB_MVA_RB_WPTR_OFFSET_SHIFT 2
#define  GVP_NMB_MVD_RB_BASE 0x8338
    #define GVP_NMB_MVD_RB_BASE_ADDR_MASK 0x1FFFFFF8
    #define GVP_NMB_MVD_RB_BASE_ADDR_SHIFT 3
#define  GVP_NMB_MVD_RB_CTRL 0x833C
    #define GVP_NMB_MVD_RB_CTRL_SIZE_MASK 0x007FFFFC
    #define GVP_NMB_MVD_RB_CTRL_SIZE_SHIFT 2
#define  GVP_NMB_MVD_RB_RPTR 0x8340
    #define GVP_NMB_MVD_RB_RPTR_OFFSET_MASK 0x007FFFFC
    #define GVP_NMB_MVD_RB_RPTR_OFFSET_SHIFT 2
#define  GVP_NMB_MVD_RB_WPTR 0x8344
    #define GVP_NMB_MVD_RB_WPTR_OFFSET_MASK 0x007FFFFC
    #define GVP_NMB_MVD_RB_WPTR_OFFSET_SHIFT 2
#define  GVP_NMB_SMV_BASE 0x8348
    #define GVP_NMB_SMV_BASE_ADDR_MASK 0x1FFFFFF8
    #define GVP_NMB_SMV_BASE_ADDR_SHIFT 3
#define  GVP_NMB_START_MB 0x8310
    #define GVP_NMB_START_MB_START_MB_X_MASK 0x000000FF
    #define GVP_NMB_START_MB_START_MB_X_SHIFT 0
    #define GVP_NMB_START_MB_START_MB_Y_MASK 0x00007F00
    #define GVP_NMB_START_MB_START_MB_Y_SHIFT 8
#define  GVP_NMB_STATUS 0x831C
    #define GVP_NMB_STATUS_NMB_BUSY_MASK 0x00000001
    #define GVP_NMB_STATUS_NMB_BUSY_SHIFT 0
    #define GVP_NMB_STATUS_COMMAND_TAG_MASK 0x0000FF00
    #define GVP_NMB_STATUS_COMMAND_TAG_SHIFT 8
    #define GVP_NMB_STATUS_FREE_ENTRIES_MASK 0x00070000
    #define GVP_NMB_STATUS_FREE_ENTRIES_SHIFT 16
#define  GVP_NMB_TOP_NB_BASE 0x8334
    #define GVP_NMB_TOP_NB_BASE_ADDR_MASK 0x1FFFFFF8
    #define GVP_NMB_TOP_NB_BASE_ADDR_SHIFT 3
#define  GVP_PAR_ADDR 0x8158
    #define GVP_PAR_ADDR_BASE_MASK 0x1FFFFFF8
    #define GVP_PAR_ADDR_BASE_SHIFT 3
#define  GVP_PICT_SIZE 0x8004
    #define GVP_PICT_SIZE_PICT_MB_WIDTH_MASK 0x000000FF
    #define GVP_PICT_SIZE_PICT_MB_WIDTH_SHIFT 0
    #define GVP_PICT_SIZE_PICT_MB_HEIGHT_MASK 0x0000FF00
    #define GVP_PICT_SIZE_PICT_MB_HEIGHT_SHIFT 8
#define  GVP_PRED_C_ADR 0x8034
    #define GVP_PRED_C_ADR_BASE_MASK 0x1FFFFF00
    #define GVP_PRED_C_ADR_BASE_SHIFT 8
#define  GVP_PRED_Y_ADR 0x8030
    #define GVP_PRED_Y_ADR_BASE_MASK 0x1FFFFF00
    #define GVP_PRED_Y_ADR_BASE_SHIFT 8
#define  GVP_RECON_C_ADR 0x8044
    #define GVP_RECON_C_ADR_BASE_MASK 0x1FFFFF00
    #define GVP_RECON_C_ADR_BASE_SHIFT 8
#define  GVP_RECON_Y_ADR 0x8040
    #define GVP_RECON_Y_ADR_BASE_MASK 0x1FFFFF00
    #define GVP_RECON_Y_ADR_BASE_SHIFT 8
#define  GVP_REF_CACHE 0x8060
    #define GVP_REF_CACHE_PARTITIONS_MASK 0x00000001
    #define GVP_REF_CACHE_PARTITIONS_SHIFT 0
    #define INVALIDATE_MASK 0x00000002
    #define INVALIDATE_SHIFT 1
    #define PARTN_MODE_MASK 0x00000004
    #define PARTN_MODE_SHIFT 2
    #define LOCK_STEP_EN_MASK 0x00000008
    #define LOCK_STEP_EN_SHIFT 3
    #define LOCK_STEP_NUM_MASK 0x00000030
    #define LOCK_STEP_NUM_SHIFT 4
    #define REF_PARTN_0_MASK 0x00000700
    #define REF_PARTN_0_SHIFT 8
    #define REF_PARTN_1_MASK 0x00007000
    #define REF_PARTN_1_SHIFT 12
    #define MS_CHROMA_PREFETCH_MASK 0x00010000
    #define MS_CHROMA_PREFETCH_SHIFT 16
    #define MS_PREFETCH_CNT_MASK 0x01F00000
    #define MS_PREFETCH_CNT_SHIFT 20
    #define MS_PREFETCH_Y_OFFSET_MASK 0xF0000000
    #define MS_PREFETCH_Y_OFFSET_SHIFT 28
#define  GVP_REF_CACHE_PERF_COUNTER 0x8068
    #define COUNTER_MASK 0xFFFFFFFF
    #define COUNTER_SHIFT 0
#define  GVP_REF_CACHE_PERF_CTRL 0x8064
    #define CLEAR_MASK 0x00000001
    #define CLEAR_SHIFT 0
    #define GVP_REF_CACHE_PERF_CTRL_ENABLE_MASK 0x00000002
    #define GVP_REF_CACHE_PERF_CTRL_ENABLE_SHIFT 1
    #define SELECT_MASK 0x0000007C
    #define SELECT_SHIFT 2
    #define GVP_REF_CACHE_PERF_CTRL_SOFT_RESET_MASK 0x80000000
    #define GVP_REF_CACHE_PERF_CTRL_SOFT_RESET_SHIFT 31
#define  GVP_REF_C_ADR 0x8024
    #define GVP_REF_C_ADR_BASE_MASK 0x1FFFFF00
    #define GVP_REF_C_ADR_BASE_SHIFT 8
#define  GVP_REF_PICT_SIZE 0x8014
    #define GVP_REF_PICT_SIZE_REF_Y_SIZE_MASK 0x00007FFF
    #define GVP_REF_PICT_SIZE_REF_Y_SIZE_SHIFT 0
    #define GVP_REF_PICT_SIZE_REF_C_SIZE_MASK 0x7FFF0000
    #define GVP_REF_PICT_SIZE_REF_C_SIZE_SHIFT 16
#define  GVP_REF_PITCH 0x8010
    #define GVP_REF_PITCH_REF_PITCH_MASK 0x00000FE0
    #define GVP_REF_PITCH_REF_PITCH_SHIFT 5
#define  GVP_REF_Y_ADR 0x8020
    #define GVP_REF_Y_ADR_BASE_MASK 0x1FFFFF00
    #define GVP_REF_Y_ADR_BASE_SHIFT 8
#define  GVP_RES_C_ADR 0x802C
    #define GVP_RES_C_ADR_BASE_MASK 0x1FFFFF00
    #define GVP_RES_C_ADR_BASE_SHIFT 8
#define  GVP_RES_Y_ADR 0x8028
    #define GVP_RES_Y_ADR_BASE_MASK 0x1FFFFF00
    #define GVP_RES_Y_ADR_BASE_SHIFT 8
#define  GVP_RLAC_ADR 0x8050
    #define GVP_RLAC_ADR_BASE_MASK 0x1FFFFFF8
    #define GVP_RLAC_ADR_BASE_SHIFT 3
#define  GVP_RLAC_BUF_SIZE 0x8054
    #define GVP_RLAC_BUF_SIZE_SIZE_MASK 0x00FFFFF8
    #define GVP_RLAC_BUF_SIZE_SIZE_SHIFT 3
#define  GVP_RLDC_ADR 0x8048
    #define GVP_RLDC_ADR_BASE_MASK 0x1FFFFFF8
    #define GVP_RLDC_ADR_BASE_SHIFT 3
#define  GVP_RLDC_BUF_SIZE 0x804C
    #define GVP_RLDC_BUF_SIZE_SIZE_MASK 0x000FFFF8
    #define GVP_RLDC_BUF_SIZE_SIZE_SHIFT 3
#define  GVP_SCRATCH_00 0x83B0
    #define GVP_SCRATCH_00_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_00_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_01 0x83B4
    #define GVP_SCRATCH_01_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_01_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_02 0x83B8
    #define GVP_SCRATCH_02_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_02_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_03 0x83BC
    #define GVP_SCRATCH_03_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_03_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_04 0x83C0
    #define GVP_SCRATCH_04_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_04_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_05 0x83C4
    #define GVP_SCRATCH_05_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_05_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_06 0x83C8
    #define GVP_SCRATCH_06_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_06_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_07 0x83CC
    #define GVP_SCRATCH_07_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_07_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_08 0x83D0
    #define GVP_SCRATCH_08_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_08_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_09 0x83D4
    #define GVP_SCRATCH_09_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_09_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_10 0x83D8
    #define GVP_SCRATCH_10_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_10_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_11 0x83DC
    #define GVP_SCRATCH_11_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_11_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_12 0x83E0
    #define GVP_SCRATCH_12_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_12_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_13 0x83E4
    #define GVP_SCRATCH_13_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_13_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_14 0x83E8
    #define GVP_SCRATCH_14_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_14_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_15 0x83EC
    #define GVP_SCRATCH_15_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_15_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_16 0x83F0
    #define GVP_SCRATCH_16_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_16_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_17 0x83F4
    #define GVP_SCRATCH_17_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_17_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_18 0x83F8
    #define GVP_SCRATCH_18_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_18_SCRATCH_SHIFT 0
#define  GVP_SCRATCH_19 0x83FC
    #define GVP_SCRATCH_19_SCRATCH_MASK 0xFFFFFFFF
    #define GVP_SCRATCH_19_SCRATCH_SHIFT 0
#define  GVP_SLICE_INFO 0x8000
    #define GVP_SLICE_INFO_SLICE_TYPE_MASK 0x00000003
    #define GVP_SLICE_INFO_SLICE_TYPE_SHIFT 0
    #define SLICE_STRUCT_MASK 0x0000000C
    #define SLICE_STRUCT_SHIFT 2
    #define GVP_SLICE_INFO_MBAFF_FLAG_MASK 0x00000010
    #define GVP_SLICE_INFO_MBAFF_FLAG_SHIFT 4
#define  GVP_SMB_ARB0 0x82A8
    #define GVP_SMB_ARB0_CLI0_REQ_CNT_LIMIT_MASK 0x0000000F
    #define GVP_SMB_ARB0_CLI0_REQ_CNT_LIMIT_SHIFT 0
    #define GVP_SMB_ARB0_CLI1_REQ_CNT_LIMIT_MASK 0x000000F0
    #define GVP_SMB_ARB0_CLI1_REQ_CNT_LIMIT_SHIFT 4
    #define GVP_SMB_ARB0_CLI2_REQ_CNT_LIMIT_MASK 0x00000F00
    #define GVP_SMB_ARB0_CLI2_REQ_CNT_LIMIT_SHIFT 8
    #define GVP_SMB_ARB0_CLI3_REQ_CNT_LIMIT_MASK 0x0000F000
    #define GVP_SMB_ARB0_CLI3_REQ_CNT_LIMIT_SHIFT 12
    #define GVP_SMB_ARB0_CLI4_REQ_CNT_LIMIT_MASK 0x000F0000
    #define GVP_SMB_ARB0_CLI4_REQ_CNT_LIMIT_SHIFT 16
    #define GVP_SMB_ARB0_CLI5_REQ_CNT_LIMIT_MASK 0x00F00000
    #define GVP_SMB_ARB0_CLI5_REQ_CNT_LIMIT_SHIFT 20
    #define GVP_SMB_ARB0_CLI6_REQ_CNT_LIMIT_MASK 0x0F000000
    #define GVP_SMB_ARB0_CLI6_REQ_CNT_LIMIT_SHIFT 24
    #define GVP_SMB_ARB0_CLI7_REQ_CNT_LIMIT_MASK 0xF0000000
    #define GVP_SMB_ARB0_CLI7_REQ_CNT_LIMIT_SHIFT 28
#define  GVP_SMB_ARB1 0x82AC
    #define CLI8_REQ_CNT_LIMIT_MASK 0x0000000F
    #define CLI8_REQ_CNT_LIMIT_SHIFT 0
#define  GVP_SMB_CTRL 0x82A0
    #define HOLE_ENABLE_MASK 0x00000001
    #define HOLE_ENABLE_SHIFT 0
    #define HOLE_1K_LOCATION_MASK 0x00003F00
    #define HOLE_1K_LOCATION_SHIFT 8
    #define GVP_SETTLE_MASK 0x00070000
    #define GVP_SETTLE_SHIFT 16
    #define GVP_SMB_CTRL_MEM_CNT_RESET_MASK 0x00100000
    #define GVP_SMB_CTRL_MEM_CNT_RESET_SHIFT 20
    #define GVP_SMB_CTRL_MEM_CNT_EN_MASK 0x00200000
    #define GVP_SMB_CTRL_MEM_CNT_EN_SHIFT 21
    #define GVP_SMB_CTRL_MEM_CNT_SEL_MASK 0x00400000
    #define GVP_SMB_CTRL_MEM_CNT_SEL_SHIFT 22
    #define MCLK_SOFT_RESET_MASK 0x40000000
    #define MCLK_SOFT_RESET_SHIFT 30
    #define GVPCLK_SOFT_RESET_MASK 0x80000000
    #define GVPCLK_SOFT_RESET_SHIFT 31
#define  GVP_SMB_MEM_CNT 0x82B0
    #define GVP_SMB_MEM_CNT_MEM_CNT_MASK 0x00FFFFFF
    #define GVP_SMB_MEM_CNT_MEM_CNT_SHIFT 0
#define  GVP_SMB_PRIORITY 0x82A4
    #define GVP_SMB_PRIORITY_ABSOLUTE_PRIORITY_MASK 0x000001FF
    #define GVP_SMB_PRIORITY_ABSOLUTE_PRIORITY_SHIFT 0
#define  GVP_STATUS 0x805C
    #define SMB_W_BUSY_MASK 0x00000001
    #define SMB_W_BUSY_SHIFT 0
    #define SMB_R_BUSY_MASK 0x00000002
    #define SMB_R_BUSY_SHIFT 1
    #define VMA_A_BUSY_MASK 0x00000004
    #define VMA_A_BUSY_SHIFT 2
    #define VMA_B_BUSY_MASK 0x00000008
    #define VMA_B_BUSY_SHIFT 3
    #define VMA_C_BUSY_MASK 0x00000010
    #define VMA_C_BUSY_SHIFT 4
    #define CCH_BUSY_MASK 0x00000020
    #define CCH_BUSY_SHIFT 5
    #define MS_BUSY_MASK 0x00000040
    #define MS_BUSY_SHIFT 6
    #define MR_BUSY_MASK 0x00000080
    #define MR_BUSY_SHIFT 7
    #define GVP_STATUS_IP_BUSY_MASK 0x00000100
    #define GVP_STATUS_IP_BUSY_SHIFT 8
    #define GVP_STATUS_TQZ_BUSY_MASK 0x00000200
    #define GVP_STATUS_TQZ_BUSY_SHIFT 9
    #define GVP_STATUS_DBK_BUSY_MASK 0x00000400
    #define GVP_STATUS_DBK_BUSY_SHIFT 10
    #define EE_BUSY_MASK 0x00000800
    #define EE_BUSY_SHIFT 11
    #define GVP_STATUS_NMB_BUSY_MASK 0x00001000
    #define GVP_STATUS_NMB_BUSY_SHIFT 12
#define  GVP_TQZ_CTRL 0x814C
    #define GVP_TQZ_CTRL_ENTROPY_FLG_MASK 0x00000001
    #define GVP_TQZ_CTRL_ENTROPY_FLG_SHIFT 0
    #define RECON_ENB_MASK 0x00000002
    #define RECON_ENB_SHIFT 1
    #define COST_ENB_MASK 0x00000004
    #define COST_ENB_SHIFT 2
    #define INTRA_CHROMA_COST_ENB_MASK 0x00000008
    #define INTRA_CHROMA_COST_ENB_SHIFT 3
    #define GVP_TQZ_CTRL_WEIGHT_ENB_MASK 0x00000010
    #define GVP_TQZ_CTRL_WEIGHT_ENB_SHIFT 4
    #define INTER_DECISION_MASK 0x00000060
    #define INTER_DECISION_SHIFT 5
    #define Y_8X8_COST_MASK 0x00000F00
    #define Y_8X8_COST_SHIFT 8
    #define UV_MB_COST_MASK 0x0000F000
    #define UV_MB_COST_SHIFT 12
    #define QP_C_OFFSET_MASK 0x001F0000
    #define QP_C_OFFSET_SHIFT 16
    #define IP_SFT_RST_MASK 0x01000000
    #define IP_SFT_RST_SHIFT 24
    #define TQZ_SFT_RST_MASK 0x10000000
    #define TQZ_SFT_RST_SHIFT 28
#define  GVP_TQZ_RL_HD_AC_PTR 0x8150
    #define HEAD_AC_PTR_MASK 0x00FFFFFC
    #define HEAD_AC_PTR_SHIFT 2
#define  GVP_TQZ_RL_HD_DC_PTR 0x8164
    #define HEAD_DC_PTR_MASK 0x000FFFFC
    #define HEAD_DC_PTR_SHIFT 2
#define  GVP_TQZ_RL_TAIL_AC_PTR 0x8154
    #define TAIL_AC_PTR_MASK 0x00FFFFFC
    #define TAIL_AC_PTR_SHIFT 2
#define  GVP_TQZ_RL_TAIL_DC_PTR 0x8168
    #define TAIL_DC_PTR_MASK 0x000FFFFC
    #define TAIL_DC_PTR_SHIFT 2
#define  GVP_TQZ_SAD 0x816C
    #define VAL_MASK 0xFFFFFFFF
    #define VAL_SHIFT 0
#define  GVP_TQZ_WEIGHT_TABLE_0 0x812C
    #define GVP_TQZ_WEIGHT_TABLE_0_VALUE_MASK 0xFFFFFFFF
    #define GVP_TQZ_WEIGHT_TABLE_0_VALUE_SHIFT 0
#define  GVP_TQZ_WEIGHT_TABLE_1 0x8130
    #define GVP_TQZ_WEIGHT_TABLE_1_VALUE_MASK 0xFFFFFFFF
    #define GVP_TQZ_WEIGHT_TABLE_1_VALUE_SHIFT 0
#define  GVP_TQZ_WEIGHT_TABLE_2 0x8134
    #define GVP_TQZ_WEIGHT_TABLE_2_VALUE_MASK 0xFFFFFFFF
    #define GVP_TQZ_WEIGHT_TABLE_2_VALUE_SHIFT 0
#define  GVP_TQZ_WEIGHT_TABLE_3 0x8138
    #define GVP_TQZ_WEIGHT_TABLE_3_VALUE_MASK 0xFFFFFFFF
    #define GVP_TQZ_WEIGHT_TABLE_3_VALUE_SHIFT 0
#define  GVP_TQZ_WEIGHT_TABLE_CTRL 0x813C
    #define GVP_TQZ_WEIGHT_TABLE_CTRL_INDEX_MASK 0x0000001F
    #define GVP_TQZ_WEIGHT_TABLE_CTRL_INDEX_SHIFT 0
#define  GVP_VMA_CMD_A 0x8268
    #define GVP_VMA_CMD_A_BYTECNT_MASK 0x000FFFF8
    #define GVP_VMA_CMD_A_BYTECNT_SHIFT 3
    #define GVP_VMA_CMD_A_XFER_MODE_MASK 0x00700000
    #define GVP_VMA_CMD_A_XFER_MODE_SHIFT 20
    #define GVP_VMA_CMD_A_COMMAND_TAG_MASK 0xFF000000
    #define GVP_VMA_CMD_A_COMMAND_TAG_SHIFT 24
#define  GVP_VMA_CMD_B 0x8278
    #define GVP_VMA_CMD_B_BYTECNT_MASK 0x000FFFF8
    #define GVP_VMA_CMD_B_BYTECNT_SHIFT 3
    #define GVP_VMA_CMD_B_XFER_MODE_MASK 0x00700000
    #define GVP_VMA_CMD_B_XFER_MODE_SHIFT 20
    #define GVP_VMA_CMD_B_COMMAND_TAG_MASK 0xFF000000
    #define GVP_VMA_CMD_B_COMMAND_TAG_SHIFT 24
#define  GVP_VMA_CMD_C 0x8288
    #define GVP_VMA_CMD_C_BYTECNT_MASK 0x000FFFF8
    #define GVP_VMA_CMD_C_BYTECNT_SHIFT 3
    #define GVP_VMA_CMD_C_XFER_MODE_MASK 0x00700000
    #define GVP_VMA_CMD_C_XFER_MODE_SHIFT 20
#define  GVP_VMA_CRC 0x829C
    #define GVP_VMA_CRC_CRC_MASK 0xFFFFFFFF
    #define GVP_VMA_CRC_CRC_SHIFT 0
#define  GVP_VMA_CTRL 0x8294
    #define GVP_VMA_CTRL_PITCH_MASK 0x00000FE0
    #define GVP_VMA_CTRL_PITCH_SHIFT 5
    #define ARB_TYPE_MASK 0x00010000
    #define ARB_TYPE_SHIFT 16
    #define GVP_VMA_CTRL_SOFT_RESET_MASK 0x80000000
    #define GVP_VMA_CTRL_SOFT_RESET_SHIFT 31
#define  GVP_VMA_DST_ADR_A 0x8264
    #define GVP_VMA_DST_ADR_A_DST_ADDRESS_MASK 0x1FFFFFF8
    #define GVP_VMA_DST_ADR_A_DST_ADDRESS_SHIFT 3
#define  GVP_VMA_DST_ADR_B 0x8274
    #define GVP_VMA_DST_ADR_B_DST_ADDRESS_MASK 0x1FFFFFF8
    #define GVP_VMA_DST_ADR_B_DST_ADDRESS_SHIFT 3
#define  GVP_VMA_DST_ADR_C 0x8284
    #define GVP_VMA_DST_ADR_C_DST_ADDRESS_MASK 0x1FFFFFF8
    #define GVP_VMA_DST_ADR_C_DST_ADDRESS_SHIFT 3
#define  GVP_VMA_DUMMY_REG 0x8298
    #define GVP_VMA_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define GVP_VMA_DUMMY_REG_DATA_SHIFT 0
#define  GVP_VMA_SRC2_ADR_A 0x826C
    #define GVP_VMA_SRC2_ADR_A_SRC2_ADDRESS_MASK 0x1FFFFFF8
    #define GVP_VMA_SRC2_ADR_A_SRC2_ADDRESS_SHIFT 3
#define  GVP_VMA_SRC2_ADR_B 0x827C
    #define GVP_VMA_SRC2_ADR_B_SRC2_ADDRESS_MASK 0x1FFFFFF8
    #define GVP_VMA_SRC2_ADR_B_SRC2_ADDRESS_SHIFT 3
#define  GVP_VMA_SRC2_ADR_C 0x828C
    #define GVP_VMA_SRC2_ADR_C_SRC2_ADDRESS_MASK 0x1FFFFFF8
    #define GVP_VMA_SRC2_ADR_C_SRC2_ADDRESS_SHIFT 3
#define  GVP_VMA_SRC_ADR_A 0x8260
    #define GVP_VMA_SRC_ADR_A_SRC_ADDRESS_MASK 0xFFFFFFFF
    #define GVP_VMA_SRC_ADR_A_SRC_ADDRESS_SHIFT 0
#define  GVP_VMA_SRC_ADR_B 0x8270
    #define GVP_VMA_SRC_ADR_B_SRC_ADDRESS_MASK 0xFFFFFFFF
    #define GVP_VMA_SRC_ADR_B_SRC_ADDRESS_SHIFT 0
#define  GVP_VMA_SRC_ADR_C 0x8280
    #define GVP_VMA_SRC_ADR_C_SRC_ADDRESS_MASK 0xFFFFFFFF
    #define GVP_VMA_SRC_ADR_C_SRC_ADDRESS_SHIFT 0
#define  GVP_VMA_STATUS 0x8290
    #define COMMAND_STATUS_A_MASK 0x000000FF
    #define COMMAND_STATUS_A_SHIFT 0
    #define FIFO_FREE_A_MASK 0x00000F00
    #define FIFO_FREE_A_SHIFT 8
    #define VMA_BUSY_A_MASK 0x00001000
    #define VMA_BUSY_A_SHIFT 12
    #define COMMAND_STATUS_B_MASK 0x00FF0000
    #define COMMAND_STATUS_B_SHIFT 16
    #define FIFO_FREE_B_MASK 0x0F000000
    #define FIFO_FREE_B_SHIFT 24
    #define VMA_BUSY_B_MASK 0x10000000
    #define VMA_BUSY_B_SHIFT 28
    #define VMA_BUSY_C_MASK 0x80000000
    #define VMA_BUSY_C_SHIFT 31
#define  HBI_CTRL_REG 0x2200
    #define HBI_MC2_ACCESS_MASK 0x00000001
    #define HBI_MC2_ACCESS_SHIFT 0
    #define HBI_DMA_ACCESS_MASK 0x00000002
    #define HBI_DMA_ACCESS_SHIFT 1
#define  HBI_DUMMY_REG 0x2208
    #define HBI_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define HBI_DUMMY_REG_DATA_SHIFT 0
#define  HBI_MC_UPPER_ADDR_REG 0x2204
    #define HBI_UPPER_ADDR_MASK 0x0000000F
    #define HBI_UPPER_ADDR_SHIFT 0
#define  HOST_INTERRUPT 0x0414
    #define HOST_INTERRUPT_TSD_INT0_MASK 0x00000001
    #define HOST_INTERRUPT_TSD_INT0_SHIFT 0
    #define HOST_INTERRUPT_TSD_INT1_MASK 0x00000002
    #define HOST_INTERRUPT_TSD_INT1_SHIFT 1
    #define HOST_INTERRUPT_USBD_INT_MASK 0x00000004
    #define HOST_INTERRUPT_USBD_INT_SHIFT 2
    #define HOST_INTERRUPT_USBH_INT_MASK 0x00000008
    #define HOST_INTERRUPT_USBH_INT_SHIFT 3
    #define HOST_INTERRUPT_TSD_INT4_MASK 0x00000010
    #define HOST_INTERRUPT_TSD_INT4_SHIFT 4
    #define HOST_INTERRUPT_ETH0_INT_MASK 0x00000020
    #define HOST_INTERRUPT_ETH0_INT_SHIFT 5
    #define HOST_INTERRUPT_ETH1_INT_MASK 0x00000040
    #define HOST_INTERRUPT_ETH1_INT_SHIFT 6
    #define HOST_INTERRUPT_PPC_INT_MASK 0x00000080
    #define HOST_INTERRUPT_PPC_INT_SHIFT 7
    #define HOST_INTERRUPT_DMA_INT_MASK 0x00000100
    #define HOST_INTERRUPT_DMA_INT_SHIFT 8
    #define HOST_INTERRUPT_MIPS0_INT_MASK 0x00000200
    #define HOST_INTERRUPT_MIPS0_INT_SHIFT 9
    #define HOST_INTERRUPT_RBM_INT_MASK 0x00000400
    #define HOST_INTERRUPT_RBM_INT_SHIFT 10
    #define HOST_INTERRUPT_MPP_INT_MASK 0x00000800
    #define HOST_INTERRUPT_MPP_INT_SHIFT 11
    #define HOST_INTERRUPT_MIPS1_INT_MASK 0x00001000
    #define HOST_INTERRUPT_MIPS1_INT_SHIFT 12
    #define HOST_INTERRUPT_MIPS2_INT_MASK 0x00002000
    #define HOST_INTERRUPT_MIPS2_INT_SHIFT 13
    #define HOST_INTERRUPT_RSA_INT_MASK 0x00004000
    #define HOST_INTERRUPT_RSA_INT_SHIFT 14
    #define HOST_INTERRUPT_I2S_INT_MASK 0x00008000
    #define HOST_INTERRUPT_I2S_INT_SHIFT 15
    #define HOST_INTERRUPT_RMX_INT_MASK 0x00010000
    #define HOST_INTERRUPT_RMX_INT_SHIFT 16
    #define HOST_INTERRUPT_VHE_INT_MASK 0x00020000
    #define HOST_INTERRUPT_VHE_INT_SHIFT 17
    #define HOST_INTERRUPT_VFE_INT_MASK 0x00040000
    #define HOST_INTERRUPT_VFE_INT_SHIFT 18
    #define HOST_INTERRUPT_VNE_INT_MASK 0x00080000
    #define HOST_INTERRUPT_VNE_INT_SHIFT 19
    #define HOST_INTERRUPT_MIPS3_INT_MASK 0x00100000
    #define HOST_INTERRUPT_MIPS3_INT_SHIFT 20
    #define HOST_INTERRUPT_MIPS4_INT_MASK 0x00200000
    #define HOST_INTERRUPT_MIPS4_INT_SHIFT 21
    #define HOST_INTERRUPT_GVD_INT_MASK 0x00400000
    #define HOST_INTERRUPT_GVD_INT_SHIFT 22
    #define HOST_INTERRUPT_DVE_INT_MASK 0x00800000
    #define HOST_INTERRUPT_DVE_INT_SHIFT 23
    #define HOST_INTERRUPT_SATA_INT_MASK 0x01000000
    #define HOST_INTERRUPT_SATA_INT_SHIFT 24
    #define HOST_INTERRUPT_I2STX_INT_MASK 0x02000000
    #define HOST_INTERRUPT_I2STX_INT_SHIFT 25
    #define HOST_INTERRUPT_SPDIFRX_INT_MASK 0x04000000
    #define HOST_INTERRUPT_SPDIFRX_INT_SHIFT 26
    #define HOST_INTERRUPT_SPDIFTX_INT_MASK 0x08000000
    #define HOST_INTERRUPT_SPDIFTX_INT_SHIFT 27
    #define HOST_INTERRUPT_EDC_INT_MASK 0x10000000
    #define HOST_INTERRUPT_EDC_INT_SHIFT 28
    #define HOST_INTERRUPT_DSCL_INT_MASK 0x20000000
    #define HOST_INTERRUPT_DSCL_INT_SHIFT 29
    #define HOST_INTERRUPT_EE_INT_MASK 0x40000000
    #define HOST_INTERRUPT_EE_INT_SHIFT 30
#define  HOST_INTERRUPT_MASK 0x0418
    #define HOST_INTERRUPT_MASK_TSD_INT0_MASK 0x00000001
    #define HOST_INTERRUPT_MASK_TSD_INT0_SHIFT 0
    #define HOST_INTERRUPT_MASK_TSD_INT1_MASK 0x00000002
    #define HOST_INTERRUPT_MASK_TSD_INT1_SHIFT 1
    #define HOST_INTERRUPT_MASK_USBD_INT_MASK 0x00000004
    #define HOST_INTERRUPT_MASK_USBD_INT_SHIFT 2
    #define HOST_INTERRUPT_MASK_USBH_INT_MASK 0x00000008
    #define HOST_INTERRUPT_MASK_USBH_INT_SHIFT 3
    #define HOST_INTERRUPT_MASK_TSD_INT4_MASK 0x00000010
    #define HOST_INTERRUPT_MASK_TSD_INT4_SHIFT 4
    #define HOST_INTERRUPT_MASK_ETH0_INT_MASK 0x00000020
    #define HOST_INTERRUPT_MASK_ETH0_INT_SHIFT 5
    #define HOST_INTERRUPT_MASK_ETH1_INT_MASK 0x00000040
    #define HOST_INTERRUPT_MASK_ETH1_INT_SHIFT 6
    #define HOST_INTERRUPT_MASK_PPC_INT_MASK 0x00000080
    #define HOST_INTERRUPT_MASK_PPC_INT_SHIFT 7
    #define HOST_INTERRUPT_MASK_DMA_INT_MASK 0x00000100
    #define HOST_INTERRUPT_MASK_DMA_INT_SHIFT 8
    #define HOST_INTERRUPT_MASK_MIPS0_INT_MASK 0x00000200
    #define HOST_INTERRUPT_MASK_MIPS0_INT_SHIFT 9
    #define HOST_INTERRUPT_MASK_RBM_INT_MASK 0x00000400
    #define HOST_INTERRUPT_MASK_RBM_INT_SHIFT 10
    #define HOST_INTERRUPT_MASK_MPP_INT_MASK 0x00000800
    #define HOST_INTERRUPT_MASK_MPP_INT_SHIFT 11
    #define HOST_INTERRUPT_MASK_MIPS1_INT_MASK 0x00001000
    #define HOST_INTERRUPT_MASK_MIPS1_INT_SHIFT 12
    #define HOST_INTERRUPT_MASK_MIPS2_INT_MASK 0x00002000
    #define HOST_INTERRUPT_MASK_MIPS2_INT_SHIFT 13
    #define HOST_INTERRUPT_MASK_RSA_INT_MASK 0x00004000
    #define HOST_INTERRUPT_MASK_RSA_INT_SHIFT 14
    #define HOST_INTERRUPT_MASK_I2S_INT_MASK 0x00008000
    #define HOST_INTERRUPT_MASK_I2S_INT_SHIFT 15
    #define HOST_INTERRUPT_MASK_RMX_INT_MASK 0x00010000
    #define HOST_INTERRUPT_MASK_RMX_INT_SHIFT 16
    #define HOST_INTERRUPT_MASK_VHE_INT_MASK 0x00020000
    #define HOST_INTERRUPT_MASK_VHE_INT_SHIFT 17
    #define HOST_INTERRUPT_MASK_VFE_INT_MASK 0x00040000
    #define HOST_INTERRUPT_MASK_VFE_INT_SHIFT 18
    #define HOST_INTERRUPT_MASK_VNE_INT_MASK 0x00080000
    #define HOST_INTERRUPT_MASK_VNE_INT_SHIFT 19
    #define HOST_INTERRUPT_MASK_MIPS3_INT_MASK 0x00100000
    #define HOST_INTERRUPT_MASK_MIPS3_INT_SHIFT 20
    #define HOST_INTERRUPT_MASK_MIPS4_INT_MASK 0x00200000
    #define HOST_INTERRUPT_MASK_MIPS4_INT_SHIFT 21
    #define HOST_INTERRUPT_MASK_GVD_INT_MASK 0x00400000
    #define HOST_INTERRUPT_MASK_GVD_INT_SHIFT 22
    #define HOST_INTERRUPT_MASK_DVE_INT_MASK 0x00800000
    #define HOST_INTERRUPT_MASK_DVE_INT_SHIFT 23
    #define HOST_INTERRUPT_MASK_SATA_INT_MASK 0x01000000
    #define HOST_INTERRUPT_MASK_SATA_INT_SHIFT 24
    #define HOST_INTERRUPT_MASK_I2STX_INT_MASK 0x02000000
    #define HOST_INTERRUPT_MASK_I2STX_INT_SHIFT 25
    #define HOST_INTERRUPT_MASK_SPDIFRX_INT_MASK 0x04000000
    #define HOST_INTERRUPT_MASK_SPDIFRX_INT_SHIFT 26
    #define HOST_INTERRUPT_MASK_SPDIFTX_INT_MASK 0x08000000
    #define HOST_INTERRUPT_MASK_SPDIFTX_INT_SHIFT 27
    #define HOST_INTERRUPT_MASK_EDC_INT_MASK 0x10000000
    #define HOST_INTERRUPT_MASK_EDC_INT_SHIFT 28
    #define HOST_INTERRUPT_MASK_DSCL_INT_MASK 0x20000000
    #define HOST_INTERRUPT_MASK_DSCL_INT_SHIFT 29
    #define HOST_INTERRUPT_MASK_EE_INT_MASK 0x40000000
    #define HOST_INTERRUPT_MASK_EE_INT_SHIFT 30
#define  I2C0_COMMAND 0x100C
    #define I2C0_COMMAND_BYTE_CNT_MASK 0x0000007F
    #define I2C0_COMMAND_BYTE_CNT_SHIFT 0
    #define I2C0_COMMAND_START_EN_MASK 0x00000100
    #define I2C0_COMMAND_START_EN_SHIFT 8
    #define I2C0_COMMAND_STOP_EN_MASK 0x00000200
    #define I2C0_COMMAND_STOP_EN_SHIFT 9
    #define I2C0_COMMAND_WOP_MASK 0x00001000
    #define I2C0_COMMAND_WOP_SHIFT 12
    #define I2C0_COMMAND_SLAVE_ADR_MASK 0x03FF0000
    #define I2C0_COMMAND_SLAVE_ADR_SHIFT 16
    #define I2C0_COMMAND_MSTR_BUSY_MASK 0x10000000
    #define I2C0_COMMAND_MSTR_BUSY_SHIFT 28
    #define I2C0_COMMAND_BUS_BUSY_MASK 0x20000000
    #define I2C0_COMMAND_BUS_BUSY_SHIFT 29
    #define I2C0_COMMAND_ACTIVE_MASK 0x40000000
    #define I2C0_COMMAND_ACTIVE_SHIFT 30
    #define I2C0_COMMAND_ERROR_MASK 0x80000000
    #define I2C0_COMMAND_ERROR_SHIFT 31
#define  I2C0_CONFIG 0x1000
    #define I2C0_CONFIG_ATOMIC_PERIOD_MASK 0x000003FF
    #define I2C0_CONFIG_ATOMIC_PERIOD_SHIFT 0
    #define I2C0_CONFIG_SOLE_MASTER_MASK 0x00000400
    #define I2C0_CONFIG_SOLE_MASTER_SHIFT 10
    #define I2C0_CONFIG_ADR_MODE_MASK 0x00008000
    #define I2C0_CONFIG_ADR_MODE_SHIFT 15
    #define I2C0_CONFIG_TIMEOUT_MASK 0xFFFF0000
    #define I2C0_CONFIG_TIMEOUT_SHIFT 16
#define  I2C0_DATA_LOAD 0x1004
    #define I2C0_DATA_LOAD_PORT_MASK 0xFFFFFFFF
    #define I2C0_DATA_LOAD_PORT_SHIFT 0
#define  I2C0_DATA_READ 0x1008
    #define I2C0_DATA_READ_PORT_MASK 0xFFFFFFFF
    #define I2C0_DATA_READ_PORT_SHIFT 0
#define  I2C1_COMMAND 0x101C
    #define I2C1_COMMAND_BYTE_CNT_MASK 0x0000007F
    #define I2C1_COMMAND_BYTE_CNT_SHIFT 0
    #define I2C1_COMMAND_START_EN_MASK 0x00000100
    #define I2C1_COMMAND_START_EN_SHIFT 8
    #define I2C1_COMMAND_STOP_EN_MASK 0x00000200
    #define I2C1_COMMAND_STOP_EN_SHIFT 9
    #define I2C1_COMMAND_WOP_MASK 0x00001000
    #define I2C1_COMMAND_WOP_SHIFT 12
    #define I2C1_COMMAND_SLAVE_ADR_MASK 0x03FF0000
    #define I2C1_COMMAND_SLAVE_ADR_SHIFT 16
    #define I2C1_COMMAND_MSTR_BUSY_MASK 0x10000000
    #define I2C1_COMMAND_MSTR_BUSY_SHIFT 28
    #define I2C1_COMMAND_BUS_BUSY_MASK 0x20000000
    #define I2C1_COMMAND_BUS_BUSY_SHIFT 29
    #define I2C1_COMMAND_ACTIVE_MASK 0x40000000
    #define I2C1_COMMAND_ACTIVE_SHIFT 30
    #define I2C1_COMMAND_ERROR_MASK 0x80000000
    #define I2C1_COMMAND_ERROR_SHIFT 31
#define  I2C1_CONFIG 0x1010
    #define I2C1_CONFIG_ATOMIC_PERIOD_MASK 0x000003FF
    #define I2C1_CONFIG_ATOMIC_PERIOD_SHIFT 0
    #define I2C1_CONFIG_SOLE_MASTER_MASK 0x00000400
    #define I2C1_CONFIG_SOLE_MASTER_SHIFT 10
    #define I2C1_CONFIG_ADR_MODE_MASK 0x00008000
    #define I2C1_CONFIG_ADR_MODE_SHIFT 15
    #define I2C1_CONFIG_TIMEOUT_MASK 0xFFFF0000
    #define I2C1_CONFIG_TIMEOUT_SHIFT 16
#define  I2C1_DATA_LOAD 0x1014
    #define I2C1_DATA_LOAD_PORT_MASK 0xFFFFFFFF
    #define I2C1_DATA_LOAD_PORT_SHIFT 0
#define  I2C1_DATA_READ 0x1018
    #define I2C1_DATA_READ_PORT_MASK 0xFFFFFFFF
    #define I2C1_DATA_READ_PORT_SHIFT 0
#define  I2C_SLAVE_ADDR_OVERRIDE 0x10A8
    #define I2C_SLAVE_ADDR_OVERRIDE_MASK 0x000003FF
    #define I2C_SLAVE_ADDR_OVERRIDE_SHIFT 0
#define  I2S0_90KHZ_DEN 0x14D8
    #define I2S0_90KHZ_DEN_DEN_MASK 0xFFFFFFFF
    #define I2S0_90KHZ_DEN_DEN_SHIFT 0
#define  I2S0_90KHZ_NUM 0x14D4
    #define I2S0_90KHZ_NUM_NUM_MASK 0xFFFFFFFF
    #define I2S0_90KHZ_NUM_NUM_SHIFT 0
#define  I2S0_CONFIG 0x1430
    #define I2S0_CONFIG_CHANNEL_EN_MASK 0x00000001
    #define I2S0_CONFIG_CHANNEL_EN_SHIFT 0
    #define I2S0_CONFIG_MASTER_EN_MASK 0x00000002
    #define I2S0_CONFIG_MASTER_EN_SHIFT 1
    #define I2S0_CONFIG_WORD_WIDTH_MASK 0x0000000C
    #define I2S0_CONFIG_WORD_WIDTH_SHIFT 2
    #define I2S0_CONFIG_FRAME_SIZE_MASK 0x0000FFF0
    #define I2S0_CONFIG_FRAME_SIZE_SHIFT 4
    #define I2S0_CONFIG_INT_FREQ_MASK 0x003F0000
    #define I2S0_CONFIG_INT_FREQ_SHIFT 16
    #define I2S0_CONFIG_STAMP_FREQ_MASK 0x0FC00000
    #define I2S0_CONFIG_STAMP_FREQ_SHIFT 22
    #define I2S0_CONFIG_PACK_ORDER_MASK 0x10000000
    #define I2S0_CONFIG_PACK_ORDER_SHIFT 28
    #define I2S0_CONFIG_URGENT_LVL_MASK 0x60000000
    #define I2S0_CONFIG_URGENT_LVL_SHIFT 29
    #define I2S0_CONFIG_URGENT_EN_MASK 0x80000000
    #define I2S0_CONFIG_URGENT_EN_SHIFT 31
#define  I2S0_GENLOCK_DEN 0x144C
    #define I2S0_GENLOCK_DEN_DEN_MASK 0xFFFFFFFF
    #define I2S0_GENLOCK_DEN_DEN_SHIFT 0
#define  I2S0_GENLOCK_LOWER 0x1428
    #define I2S0_GENLOCK_LOWER_GENLOCK_L_MASK 0xFFFFFFFF
    #define I2S0_GENLOCK_LOWER_GENLOCK_L_SHIFT 0
#define  I2S0_GENLOCK_NUM 0x142C
    #define I2S0_GENLOCK_NUM_NUM_MASK 0xFFFFFFFF
    #define I2S0_GENLOCK_NUM_NUM_SHIFT 0
#define  I2S0_GENLOCK_UPPER 0x1424
    #define I2S0_GENLOCK_UPPER_GENLOCK_U_MASK 0x000003FF
    #define I2S0_GENLOCK_UPPER_GENLOCK_U_SHIFT 0
#define  I2S0_PCM_BASE 0x1434
    #define I2S0_PCM_BASE_ADR_MASK 0x07FFFE00
    #define I2S0_PCM_BASE_ADR_SHIFT 9
#define  I2S0_PCM_TOP 0x1438
    #define I2S0_PCM_TOP_ADR_MASK 0x07FFFE00
    #define I2S0_PCM_TOP_ADR_SHIFT 9
#define  I2S0_RD_ADDR 0x1524
    #define I2S0_RD_ADDR_CURR_RD_ADDR_MASK 0x0FFFFFF8
    #define I2S0_RD_ADDR_CURR_RD_ADDR_SHIFT 3
#define  I2S0_TDES0 0x1528
    #define I2S0_TDES0_NUM_FRAME_MASK 0x000000FF
    #define I2S0_TDES0_NUM_FRAME_SHIFT 0
    #define I2S0_TDES0_IOC_MASK 0x00008000
    #define I2S0_TDES0_IOC_SHIFT 15
    #define I2S0_TDES0_RDWRN_MASK 0x80000000
    #define I2S0_TDES0_RDWRN_SHIFT 31
#define  I2S0_TDES1 0x152C
    #define I2S0_TDES1_DATA_BUF_ADDR_MASK 0x0FFFFFF8
    #define I2S0_TDES1_DATA_BUF_ADDR_SHIFT 3
#define  I2S0_TIMESTAMP_BASE 0x143C
    #define I2S0_TIMESTAMP_BASE_ADR_MASK 0x07FFFE00
    #define I2S0_TIMESTAMP_BASE_ADR_SHIFT 9
#define  I2S0_TIMESTAMP_CTRL 0x1448
    #define I2S0_TIMESTAMP_CTRL_OFFSET_MASK 0xFFFFFFFF
    #define I2S0_TIMESTAMP_CTRL_OFFSET_SHIFT 0
#define  I2S0_TIMESTAMP_SEL 0x14DC
    #define I2S0_TIMESTAMP_SEL_TIMESTAMP_SEL_MASK 0x00000007
    #define I2S0_TIMESTAMP_SEL_TIMESTAMP_SEL_SHIFT 0
#define  I2S0_TIMESTAMP_TOP 0x1440
    #define I2S0_TIMESTAMP_TOP_ADR_MASK 0x07FFFE00
    #define I2S0_TIMESTAMP_TOP_ADR_SHIFT 9
#define  I2S0_TIMESTAMP_WPTR 0x14B4
    #define I2S0_TIMESTAMP_WPTR_WPTR_MASK 0x07FFFFF8
    #define I2S0_TIMESTAMP_WPTR_WPTR_SHIFT 3
#define  I2S0_TX_DESC_STATUS 0x1520
    #define I2S0_TX_DESC_STATUS_CURR_FRAME_NUM_MASK 0x000000FF
    #define I2S0_TX_DESC_STATUS_CURR_FRAME_NUM_SHIFT 0
    #define I2S0_TX_DESC_STATUS_DESC_FULL_MASK 0x40000000
    #define I2S0_TX_DESC_STATUS_DESC_FULL_SHIFT 30
    #define I2S0_TX_DESC_STATUS_DESC_EMPTY_MASK 0x80000000
    #define I2S0_TX_DESC_STATUS_DESC_EMPTY_SHIFT 31
#define  I2S1_90KHZ_DEN 0x14E4
    #define I2S1_90KHZ_DEN_DEN_MASK 0xFFFFFFFF
    #define I2S1_90KHZ_DEN_DEN_SHIFT 0
#define  I2S1_90KHZ_NUM 0x14E0
    #define I2S1_90KHZ_NUM_NUM_MASK 0xFFFFFFFF
    #define I2S1_90KHZ_NUM_NUM_SHIFT 0
#define  I2S1_CONFIG 0x1450
    #define I2S1_CONFIG_CHANNEL_EN_MASK 0x00000001
    #define I2S1_CONFIG_CHANNEL_EN_SHIFT 0
    #define I2S1_CONFIG_MASTER_EN_MASK 0x00000002
    #define I2S1_CONFIG_MASTER_EN_SHIFT 1
    #define I2S1_CONFIG_WORD_WIDTH_MASK 0x0000000C
    #define I2S1_CONFIG_WORD_WIDTH_SHIFT 2
    #define I2S1_CONFIG_FRAME_SIZE_MASK 0x0000FFF0
    #define I2S1_CONFIG_FRAME_SIZE_SHIFT 4
    #define I2S1_CONFIG_INT_FREQ_MASK 0x003F0000
    #define I2S1_CONFIG_INT_FREQ_SHIFT 16
    #define I2S1_CONFIG_STAMP_FREQ_MASK 0x0FC00000
    #define I2S1_CONFIG_STAMP_FREQ_SHIFT 22
    #define I2S1_CONFIG_PACK_ORDER_MASK 0x10000000
    #define I2S1_CONFIG_PACK_ORDER_SHIFT 28
    #define I2S1_CONFIG_URGENT_LVL_MASK 0x60000000
    #define I2S1_CONFIG_URGENT_LVL_SHIFT 29
    #define I2S1_CONFIG_URGENT_EN_MASK 0x80000000
    #define I2S1_CONFIG_URGENT_EN_SHIFT 31
#define  I2S1_GENLOCK_DEN 0x14AC
    #define I2S1_GENLOCK_DEN_DEN_MASK 0xFFFFFFFF
    #define I2S1_GENLOCK_DEN_DEN_SHIFT 0
#define  I2S1_GENLOCK_LOWER 0x148C
    #define I2S1_GENLOCK_LOWER_GENLOCK_L_MASK 0xFFFFFFFF
    #define I2S1_GENLOCK_LOWER_GENLOCK_L_SHIFT 0
#define  I2S1_GENLOCK_NUM 0x14A8
    #define I2S1_GENLOCK_NUM_NUM_MASK 0xFFFFFFFF
    #define I2S1_GENLOCK_NUM_NUM_SHIFT 0
#define  I2S1_GENLOCK_UPPER 0x1488
    #define I2S1_GENLOCK_UPPER_GENLOCK_U_MASK 0x000003FF
    #define I2S1_GENLOCK_UPPER_GENLOCK_U_SHIFT 0
#define  I2S1_PCM_BASE 0x1454
    #define I2S1_PCM_BASE_ADR_MASK 0x07FFFE00
    #define I2S1_PCM_BASE_ADR_SHIFT 9
#define  I2S1_PCM_TOP 0x1458
    #define I2S1_PCM_TOP_ADR_MASK 0x07FFFE00
    #define I2S1_PCM_TOP_ADR_SHIFT 9
#define  I2S1_RD_ADDR 0x1534
    #define I2S1_RD_ADDR_CURR_RD_ADDR_MASK 0x0FFFFFF8
    #define I2S1_RD_ADDR_CURR_RD_ADDR_SHIFT 3
#define  I2S1_TDES0 0x1538
    #define I2S1_TDES0_NUM_FRAME_MASK 0x000000FF
    #define I2S1_TDES0_NUM_FRAME_SHIFT 0
    #define I2S1_TDES0_IOC_MASK 0x00008000
    #define I2S1_TDES0_IOC_SHIFT 15
    #define I2S1_TDES0_RDWRN_MASK 0x80000000
    #define I2S1_TDES0_RDWRN_SHIFT 31
#define  I2S1_TDES1 0x153C
    #define I2S1_TDES1_DATA_BUF_ADDR_MASK 0x0FFFFFF8
    #define I2S1_TDES1_DATA_BUF_ADDR_SHIFT 3
#define  I2S1_TIMESTAMP_BASE 0x145C
    #define I2S1_TIMESTAMP_BASE_ADR_MASK 0x07FFFE00
    #define I2S1_TIMESTAMP_BASE_ADR_SHIFT 9
#define  I2S1_TIMESTAMP_CTRL 0x1464
    #define I2S1_TIMESTAMP_CTRL_OFFSET_MASK 0xFFFFFFFF
    #define I2S1_TIMESTAMP_CTRL_OFFSET_SHIFT 0
#define  I2S1_TIMESTAMP_SEL 0x14E8
    #define I2S1_TIMESTAMP_SEL_TIMESTAMP_SEL_MASK 0x00000007
    #define I2S1_TIMESTAMP_SEL_TIMESTAMP_SEL_SHIFT 0
#define  I2S1_TIMESTAMP_TOP 0x1460
    #define I2S1_TIMESTAMP_TOP_ADR_MASK 0x07FFFE00
    #define I2S1_TIMESTAMP_TOP_ADR_SHIFT 9
#define  I2S1_TIMESTAMP_WPTR 0x14B8
    #define I2S1_TIMESTAMP_WPTR_WPTR_MASK 0x07FFFFF8
    #define I2S1_TIMESTAMP_WPTR_WPTR_SHIFT 3
#define  I2S1_TX_DESC_STATUS 0x1530
    #define I2S1_TX_DESC_STATUS_CURR_FRAME_NUM_MASK 0x000000FF
    #define I2S1_TX_DESC_STATUS_CURR_FRAME_NUM_SHIFT 0
    #define I2S1_TX_DESC_STATUS_DESC_FULL_MASK 0x40000000
    #define I2S1_TX_DESC_STATUS_DESC_FULL_SHIFT 30
    #define I2S1_TX_DESC_STATUS_DESC_EMPTY_MASK 0x80000000
    #define I2S1_TX_DESC_STATUS_DESC_EMPTY_SHIFT 31
#define  I2S2_RD_ADDR 0x1544
    #define I2S2_RD_ADDR_CURR_RD_ADDR_MASK 0x0FFFFFF8
    #define I2S2_RD_ADDR_CURR_RD_ADDR_SHIFT 3
#define  I2S2_TDES0 0x1548
    #define I2S2_TDES0_NUM_FRAME_MASK 0x000000FF
    #define I2S2_TDES0_NUM_FRAME_SHIFT 0
    #define I2S2_TDES0_IOC_MASK 0x00008000
    #define I2S2_TDES0_IOC_SHIFT 15
    #define I2S2_TDES0_RDWRN_MASK 0x80000000
    #define I2S2_TDES0_RDWRN_SHIFT 31
#define  I2S2_TDES1 0x154C
    #define I2S2_TDES1_DATA_BUF_ADDR_MASK 0x0FFFFFF8
    #define I2S2_TDES1_DATA_BUF_ADDR_SHIFT 3
#define  I2S2_TX_DESC_STATUS 0x1540
    #define I2S2_TX_DESC_STATUS_CURR_FRAME_NUM_MASK 0x000000FF
    #define I2S2_TX_DESC_STATUS_CURR_FRAME_NUM_SHIFT 0
    #define I2S2_TX_DESC_STATUS_DESC_FULL_MASK 0x40000000
    #define I2S2_TX_DESC_STATUS_DESC_FULL_SHIFT 30
    #define I2S2_TX_DESC_STATUS_DESC_EMPTY_MASK 0x80000000
    #define I2S2_TX_DESC_STATUS_DESC_EMPTY_SHIFT 31
#define  I2S3_RD_ADDR 0x1554
    #define I2S3_RD_ADDR_CURR_RD_ADDR_MASK 0x0FFFFFF8
    #define I2S3_RD_ADDR_CURR_RD_ADDR_SHIFT 3
#define  I2S3_TDES0 0x1558
    #define I2S3_TDES0_NUM_FRAME_MASK 0x000000FF
    #define I2S3_TDES0_NUM_FRAME_SHIFT 0
    #define I2S3_TDES0_IOC_MASK 0x00008000
    #define I2S3_TDES0_IOC_SHIFT 15
    #define I2S3_TDES0_RDWRN_MASK 0x80000000
    #define I2S3_TDES0_RDWRN_SHIFT 31
#define  I2S3_TDES1 0x155C
    #define I2S3_TDES1_DATA_BUF_ADDR_MASK 0x0FFFFFF8
    #define I2S3_TDES1_DATA_BUF_ADDR_SHIFT 3
#define  I2S3_TX_DESC_STATUS 0x1550
    #define I2S3_TX_DESC_STATUS_CURR_FRAME_NUM_MASK 0x000000FF
    #define I2S3_TX_DESC_STATUS_CURR_FRAME_NUM_SHIFT 0
    #define I2S3_TX_DESC_STATUS_DESC_FULL_MASK 0x40000000
    #define I2S3_TX_DESC_STATUS_DESC_FULL_SHIFT 30
    #define I2S3_TX_DESC_STATUS_DESC_EMPTY_MASK 0x80000000
    #define I2S3_TX_DESC_STATUS_DESC_EMPTY_SHIFT 31
#define  I2S4_RD_ADDR 0x1564
    #define I2S4_RD_ADDR_CURR_RD_ADDR_MASK 0x0FFFFFF8
    #define I2S4_RD_ADDR_CURR_RD_ADDR_SHIFT 3
#define  I2S4_TDES0 0x1568
    #define I2S4_TDES0_NUM_FRAME_MASK 0x000000FF
    #define I2S4_TDES0_NUM_FRAME_SHIFT 0
    #define I2S4_TDES0_IOC_MASK 0x00008000
    #define I2S4_TDES0_IOC_SHIFT 15
    #define I2S4_TDES0_RDWRN_MASK 0x80000000
    #define I2S4_TDES0_RDWRN_SHIFT 31
#define  I2S4_TDES1 0x156C
    #define I2S4_TDES1_DATA_BUF_ADDR_MASK 0x0FFFFFF8
    #define I2S4_TDES1_DATA_BUF_ADDR_SHIFT 3
#define  I2S4_TX_DESC_STATUS 0x1560
    #define I2S4_TX_DESC_STATUS_CURR_FRAME_NUM_MASK 0x000000FF
    #define I2S4_TX_DESC_STATUS_CURR_FRAME_NUM_SHIFT 0
    #define I2S4_TX_DESC_STATUS_DESC_FULL_MASK 0x40000000
    #define I2S4_TX_DESC_STATUS_DESC_FULL_SHIFT 30
    #define I2S4_TX_DESC_STATUS_DESC_EMPTY_MASK 0x80000000
    #define I2S4_TX_DESC_STATUS_DESC_EMPTY_SHIFT 31
#define  I2S_DUMMY_REG 0x14FC
    #define I2S_DUMMY_REG_DUMMY_BITS_MASK 0xFFFFFFFF
    #define I2S_DUMMY_REG_DUMMY_BITS_SHIFT 0
#define  I2S_DYNAMIC_CLOCK_GATE 0x14C4
    #define CLOCK_GATE_EN_MASK 0x00000001
    #define CLOCK_GATE_EN_SHIFT 0
#define  I2S_HOST_INT_ERR_MASK 0x140C
    #define I2S_HOST_INT_ERR_MASK_INT_EN_I2S0_ERR_MASK 0x00000001
    #define I2S_HOST_INT_ERR_MASK_INT_EN_I2S0_ERR_SHIFT 0
    #define I2S_HOST_INT_ERR_MASK_INT_EN_I2S1_ERR_MASK 0x00000002
    #define I2S_HOST_INT_ERR_MASK_INT_EN_I2S1_ERR_SHIFT 1
#define  I2S_HOST_INT_ERR_STATUS 0x1414
    #define I2S_HOST_INT_ERR_STATUS_I2S0_ERR_MASK 0x00000001
    #define I2S_HOST_INT_ERR_STATUS_I2S0_ERR_SHIFT 0
    #define I2S_HOST_INT_ERR_STATUS_I2S1_ERR_MASK 0x00000002
    #define I2S_HOST_INT_ERR_STATUS_I2S1_ERR_SHIFT 1
#define  I2S_HOST_INT_MASK 0x1408
    #define I2S_HOST_INT_MASK_INT_EN_I2S0_INT_MASK 0x00000001
    #define I2S_HOST_INT_MASK_INT_EN_I2S0_INT_SHIFT 0
    #define I2S_HOST_INT_MASK_INT_EN_I2S1_INT_MASK 0x00000002
    #define I2S_HOST_INT_MASK_INT_EN_I2S1_INT_SHIFT 1
#define  I2S_HOST_INT_STATUS 0x1410
    #define I2S_HOST_INT_STATUS_I2S0_INT_MASK 0x00000001
    #define I2S_HOST_INT_STATUS_I2S0_INT_SHIFT 0
    #define I2S_HOST_INT_STATUS_I2S1_INT_MASK 0x00000002
    #define I2S_HOST_INT_STATUS_I2S1_INT_SHIFT 1
#define  I2S_MDEBUG_DATA 0x14CC
    #define I2S_MDEBUG_DATA_DEBUG_DATA_MASK 0x000FFFFF
    #define I2S_MDEBUG_DATA_DEBUG_DATA_SHIFT 0
#define  I2S_MIPS_INT_ERR_MASK 0x1404
    #define I2S_MIPS_INT_ERR_MASK_INT_EN_I2S0_ERR_MASK 0x00000001
    #define I2S_MIPS_INT_ERR_MASK_INT_EN_I2S0_ERR_SHIFT 0
    #define I2S_MIPS_INT_ERR_MASK_INT_EN_I2S1_ERR_MASK 0x00000002
    #define I2S_MIPS_INT_ERR_MASK_INT_EN_I2S1_ERR_SHIFT 1
#define  I2S_MIPS_INT_ERR_STATUS 0x141C
    #define I2S_MIPS_INT_ERR_STATUS_I2S0_ERR_MASK 0x00000001
    #define I2S_MIPS_INT_ERR_STATUS_I2S0_ERR_SHIFT 0
    #define I2S_MIPS_INT_ERR_STATUS_I2S1_ERR_MASK 0x00000002
    #define I2S_MIPS_INT_ERR_STATUS_I2S1_ERR_SHIFT 1
#define  I2S_MIPS_INT_MASK 0x1400
    #define I2S_MIPS_INT_MASK_INT_EN_I2S0_INT_MASK 0x00000001
    #define I2S_MIPS_INT_MASK_INT_EN_I2S0_INT_SHIFT 0
    #define I2S_MIPS_INT_MASK_INT_EN_I2S1_INT_MASK 0x00000002
    #define I2S_MIPS_INT_MASK_INT_EN_I2S1_INT_SHIFT 1
#define  I2S_MIPS_INT_STATUS 0x1418
    #define I2S_MIPS_INT_STATUS_I2S0_INT_MASK 0x00000001
    #define I2S_MIPS_INT_STATUS_I2S0_INT_SHIFT 0
    #define I2S_MIPS_INT_STATUS_I2S1_INT_MASK 0x00000002
    #define I2S_MIPS_INT_STATUS_I2S1_INT_SHIFT 1
#define  I2S_MSTR_CTRL 0x1420
    #define RATIO_MASK 0x000003FF
    #define RATIO_SHIFT 0
    #define INPUT_LATCH_EN_MASK 0x10000000
    #define INPUT_LATCH_EN_SHIFT 28
    #define XTAL_CLR_MASK 0x20000000
    #define XTAL_CLR_SHIFT 29
    #define XTAL_EN_MASK 0x40000000
    #define XTAL_EN_SHIFT 30
    #define XTAL_DIV_EN_MASK 0x80000000
    #define XTAL_DIV_EN_SHIFT 31
#define  I2S_ODEBUG_DATA 0x14D0
    #define I2S_ODEBUG_DATA_DEBUG_DATA_MASK 0x000FFFFF
    #define I2S_ODEBUG_DATA_DEBUG_DATA_SHIFT 0
#define  I2S_SELF_TEST 0x14C8
    #define WORD_SIZE_MASK 0x00000007
    #define WORD_SIZE_SHIFT 0
#define  I2S_SFT_RSTN 0x14B0
    #define I2S0_SFT_RSTN_MASK 0x00000001
    #define I2S0_SFT_RSTN_SHIFT 0
    #define I2S1_SFT_RSTN_MASK 0x00000002
    #define I2S1_SFT_RSTN_SHIFT 1
    #define I2S_ALL_SFT_RSTN_MASK 0x00000010
    #define I2S_ALL_SFT_RSTN_SHIFT 4
#define  I2S_TX_CONFIG 0x1500
    #define CHANNEL_SYNC_MASK 0x0000001F
    #define CHANNEL_SYNC_SHIFT 0
    #define I2S_TX_CONFIG_WORD_WIDTH_MASK 0x00000040
    #define I2S_TX_CONFIG_WORD_WIDTH_SHIFT 6
    #define I2S_TX_CONFIG_PACK_ORDER_MASK 0x00000080
    #define I2S_TX_CONFIG_PACK_ORDER_SHIFT 7
    #define I2S_TX_CONFIG_ENDIAN_MASK 0x00000100
    #define I2S_TX_CONFIG_ENDIAN_SHIFT 8
    #define I2S_TX_CONFIG_FRAME_SIZE_MASK 0x001FFE00
    #define I2S_TX_CONFIG_FRAME_SIZE_SHIFT 9
    #define I2S_TX_CONFIG_UF_CTRL_EN_MASK 0x00200000
    #define I2S_TX_CONFIG_UF_CTRL_EN_SHIFT 21
    #define WS_NEGEDGE_MASK 0x00400000
    #define WS_NEGEDGE_SHIFT 22
    #define I2S_TX_CONFIG_OPERATE_MODE_MASK 0x00800000
    #define I2S_TX_CONFIG_OPERATE_MODE_SHIFT 23
    #define I2S_TX_CONFIG_RESETN_MASK 0x80000000
    #define I2S_TX_CONFIG_RESETN_SHIFT 31
#define  I2S_TX_DEN 0x1574
    #define I2S_TX_DEN_DEN_MASK 0xFFFFFFFF
    #define I2S_TX_DEN_DEN_SHIFT 0
#define  I2S_TX_DUMMY_REG 0x1580
    #define I2S_TX_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define I2S_TX_DUMMY_REG_DATA_SHIFT 0
#define  I2S_TX_EN 0x1504
    #define I2S_TX_EN_CHANNEL_EN_MASK 0x0000001F
    #define I2S_TX_EN_CHANNEL_EN_SHIFT 0
#define  I2S_TX_GENLOCK_LOWER 0x157C
    #define I2S_TX_GENLOCK_LOWER_GENLOCK_L_MASK 0xFFFFFFFF
    #define I2S_TX_GENLOCK_LOWER_GENLOCK_L_SHIFT 0
#define  I2S_TX_GENLOCK_UPPER 0x1578
    #define I2S_TX_GENLOCK_UPPER_GENLOCK_U_MASK 0x000003FF
    #define I2S_TX_GENLOCK_UPPER_GENLOCK_U_SHIFT 0
#define  I2S_TX_HOST_INT_MASK 0x1508
    #define I2S_TX_HOST_INT_MASK_UF_INT_MASK 0x0000001F
    #define I2S_TX_HOST_INT_MASK_UF_INT_SHIFT 0
    #define I2S_TX_HOST_INT_MASK_INT_MASK 0x00001F00
    #define I2S_TX_HOST_INT_MASK_INT_SHIFT 8
#define  I2S_TX_INT_STATUS 0x1510
    #define I2S_TX_INT_STATUS_UF_INT_MASK 0x0000001F
    #define I2S_TX_INT_STATUS_UF_INT_SHIFT 0
    #define I2S_TX_INT_STATUS_INT_MASK 0x00001F00
    #define I2S_TX_INT_STATUS_INT_SHIFT 8
#define  I2S_TX_MIPS_INT_MASK 0x150C
    #define I2S_TX_MIPS_INT_MASK_UF_INT_MASK 0x0000001F
    #define I2S_TX_MIPS_INT_MASK_UF_INT_SHIFT 0
    #define I2S_TX_MIPS_INT_MASK_INT_MASK 0x00001F00
    #define I2S_TX_MIPS_INT_MASK_INT_SHIFT 8
#define  I2S_TX_NUM 0x1570
    #define I2S_TX_NUM_NUM_MASK 0xFFFFFFFF
    #define I2S_TX_NUM_NUM_SHIFT 0
#define  IBB_ADV_PTR 0x0084
    #define IBB_ADV_PTR_NODATA_MASK 0xFFFFFFFF
    #define IBB_ADV_PTR_NODATA_SHIFT 0
#define  IBB_BIT_OFFSET 0x0114
    #define IBB_BIT_OFFSET_OFFSET_MASK 0x0000001F
    #define IBB_BIT_OFFSET_OFFSET_SHIFT 0
#define  IBB_BYTE_ALIGN 0x00D0
    #define IBB_BYTE_ALIGN_DATA_MASK 0xFFFFFFFF
    #define IBB_BYTE_ALIGN_DATA_SHIFT 0
#define  IBB_CTRL 0x0100
    #define LB_LOW_WM_MASK 0x00000003
    #define LB_LOW_WM_SHIFT 0
    #define FETCH_WM_MASK 0x0000003C
    #define FETCH_WM_SHIFT 2
    #define LB_HIGH_WM_MASK 0x000003C0
    #define LB_HIGH_WM_SHIFT 6
    #define IBB_CTRL_MPEG_FRMT_MASK 0x00000C00
    #define IBB_CTRL_MPEG_FRMT_SHIFT 10
    #define INPUT_BIT_SWAP_MASK 0x00001000
    #define INPUT_BIT_SWAP_SHIFT 12
    #define ESC_MASK 0x00002000
    #define ESC_SHIFT 13
    #define IBB_CTRL_BIT_SWAP_MASK 0x00004000
    #define IBB_CTRL_BIT_SWAP_SHIFT 14
    #define DIS_OVERREAD_MASK 0x00008000
    #define DIS_OVERREAD_SHIFT 15
    #define INTRA_VLC_MASK 0x00010000
    #define INTRA_VLC_SHIFT 16
    #define INPUT_CTRL_MASK 0x00020000
    #define INPUT_CTRL_SHIFT 17
    #define IBB_STOP_MASK 0x00040000
    #define IBB_STOP_SHIFT 18
#define  IBB_GET_BITS1 0x0004
    #define IBB_GET_BITS1_DATA_MASK 0x00000001
    #define IBB_GET_BITS1_DATA_SHIFT 0
#define  IBB_GET_BITS10 0x0028
    #define IBB_GET_BITS10_DATA_MASK 0x000003FF
    #define IBB_GET_BITS10_DATA_SHIFT 0
#define  IBB_GET_BITS11 0x002C
    #define IBB_GET_BITS11_DATA_MASK 0x000007FF
    #define IBB_GET_BITS11_DATA_SHIFT 0
#define  IBB_GET_BITS12 0x0030
    #define IBB_GET_BITS12_DATA_MASK 0x00000FFF
    #define IBB_GET_BITS12_DATA_SHIFT 0
#define  IBB_GET_BITS13 0x0034
    #define IBB_GET_BITS13_DATA_MASK 0x00001FFF
    #define IBB_GET_BITS13_DATA_SHIFT 0
#define  IBB_GET_BITS14 0x0038
    #define IBB_GET_BITS14_DATA_MASK 0x00003FFF
    #define IBB_GET_BITS14_DATA_SHIFT 0
#define  IBB_GET_BITS15 0x003C
    #define IBB_GET_BITS15_DATA_MASK 0x00007FFF
    #define IBB_GET_BITS15_DATA_SHIFT 0
#define  IBB_GET_BITS16 0x0040
    #define IBB_GET_BITS16_DATA_MASK 0x0000FFFF
    #define IBB_GET_BITS16_DATA_SHIFT 0
#define  IBB_GET_BITS17 0x0044
    #define IBB_GET_BITS17_DATA_MASK 0x0001FFFF
    #define IBB_GET_BITS17_DATA_SHIFT 0
#define  IBB_GET_BITS18 0x0048
    #define IBB_GET_BITS18_DATA_MASK 0x0003FFFF
    #define IBB_GET_BITS18_DATA_SHIFT 0
#define  IBB_GET_BITS19 0x004C
    #define IBB_GET_BITS19_DATA_MASK 0x0007FFFF
    #define IBB_GET_BITS19_DATA_SHIFT 0
#define  IBB_GET_BITS2 0x0008
    #define IBB_GET_BITS2_DATA_MASK 0x00000003
    #define IBB_GET_BITS2_DATA_SHIFT 0
#define  IBB_GET_BITS20 0x0050
    #define IBB_GET_BITS20_DATA_MASK 0x000FFFFF
    #define IBB_GET_BITS20_DATA_SHIFT 0
#define  IBB_GET_BITS21 0x0054
    #define IBB_GET_BITS21_DATA_MASK 0x001FFFFF
    #define IBB_GET_BITS21_DATA_SHIFT 0
#define  IBB_GET_BITS22 0x0058
    #define IBB_GET_BITS22_DATA_MASK 0x003FFFFF
    #define IBB_GET_BITS22_DATA_SHIFT 0
#define  IBB_GET_BITS23 0x005C
    #define IBB_GET_BITS23_DATA_MASK 0x007FFFFF
    #define IBB_GET_BITS23_DATA_SHIFT 0
#define  IBB_GET_BITS24 0x0060
    #define IBB_GET_BITS24_DATA_MASK 0x00FFFFFF
    #define IBB_GET_BITS24_DATA_SHIFT 0
#define  IBB_GET_BITS25 0x0064
    #define IBB_GET_BITS25_DATA_MASK 0x01FFFFFF
    #define IBB_GET_BITS25_DATA_SHIFT 0
#define  IBB_GET_BITS26 0x0068
    #define IBB_GET_BITS26_DATA_MASK 0x03FFFFFF
    #define IBB_GET_BITS26_DATA_SHIFT 0
#define  IBB_GET_BITS27 0x006C
    #define IBB_GET_BITS27_DATA_MASK 0x07FFFFFF
    #define IBB_GET_BITS27_DATA_SHIFT 0
#define  IBB_GET_BITS28 0x0070
    #define IBB_GET_BITS28_DATA_MASK 0x0FFFFFFF
    #define IBB_GET_BITS28_DATA_SHIFT 0
#define  IBB_GET_BITS29 0x0074
    #define IBB_GET_BITS29_DATA_MASK 0x1FFFFFFF
    #define IBB_GET_BITS29_DATA_SHIFT 0
#define  IBB_GET_BITS3 0x000C
    #define IBB_GET_BITS3_DATA_MASK 0x00000007
    #define IBB_GET_BITS3_DATA_SHIFT 0
#define  IBB_GET_BITS30 0x0078
    #define IBB_GET_BITS30_DATA_MASK 0x3FFFFFFF
    #define IBB_GET_BITS30_DATA_SHIFT 0
#define  IBB_GET_BITS31 0x007C
    #define IBB_GET_BITS31_DATA_MASK 0x7FFFFFFF
    #define IBB_GET_BITS31_DATA_SHIFT 0
#define  IBB_GET_BITS32 0x0080
    #define IBB_GET_BITS32_DATA_MASK 0xFFFFFFFF
    #define IBB_GET_BITS32_DATA_SHIFT 0
#define  IBB_GET_BITS4 0x0010
    #define IBB_GET_BITS4_DATA_MASK 0x0000000F
    #define IBB_GET_BITS4_DATA_SHIFT 0
#define  IBB_GET_BITS5 0x0014
    #define IBB_GET_BITS5_DATA_MASK 0x0000001F
    #define IBB_GET_BITS5_DATA_SHIFT 0
#define  IBB_GET_BITS6 0x0018
    #define IBB_GET_BITS6_DATA_MASK 0x0000003F
    #define IBB_GET_BITS6_DATA_SHIFT 0
#define  IBB_GET_BITS7 0x001C
    #define IBB_GET_BITS7_DATA_MASK 0x0000007F
    #define IBB_GET_BITS7_DATA_SHIFT 0
#define  IBB_GET_BITS8 0x0020
    #define IBB_GET_BITS8_DATA_MASK 0x000000FF
    #define IBB_GET_BITS8_DATA_SHIFT 0
#define  IBB_GET_BITS9 0x0024
    #define IBB_GET_BITS9_DATA_MASK 0x000001FF
    #define IBB_GET_BITS9_DATA_SHIFT 0
#define  IBB_HUFFMAN_B10_GET 0x00B4
    #define IBB_HUFFMAN_B10_GET_DATA_MASK 0xFFFFFFFF
    #define IBB_HUFFMAN_B10_GET_DATA_SHIFT 0
#define  IBB_HUFFMAN_B11_GET 0x00B8
    #define IBB_HUFFMAN_B11_GET_DATA_MASK 0xFFFFFFFF
    #define IBB_HUFFMAN_B11_GET_DATA_SHIFT 0
#define  IBB_HUFFMAN_B12_GET 0x00BC
    #define IBB_HUFFMAN_B12_GET_LEVEL_MASK 0x00007FFF
    #define IBB_HUFFMAN_B12_GET_LEVEL_SHIFT 0
    #define IBB_HUFFMAN_B12_GET_LEVEL_SIGN_MASK 0x00008000
    #define IBB_HUFFMAN_B12_GET_LEVEL_SIGN_SHIFT 15
    #define IBB_HUFFMAN_B12_GET_RUN_MASK 0x007F0000
    #define IBB_HUFFMAN_B12_GET_RUN_SHIFT 16
#define  IBB_HUFFMAN_B13_GET 0x00C0
    #define IBB_HUFFMAN_B13_GET_LEVEL_MASK 0x00007FFF
    #define IBB_HUFFMAN_B13_GET_LEVEL_SHIFT 0
    #define IBB_HUFFMAN_B13_GET_LEVEL_SIGN_MASK 0x00008000
    #define IBB_HUFFMAN_B13_GET_LEVEL_SIGN_SHIFT 15
    #define IBB_HUFFMAN_B13_GET_RUN_MASK 0x007F0000
    #define IBB_HUFFMAN_B13_GET_RUN_SHIFT 16
#define  IBB_HUFFMAN_B14AC_GET 0x00C8
    #define IBB_HUFFMAN_B14AC_GET_LEVEL_MASK 0x00007FFF
    #define IBB_HUFFMAN_B14AC_GET_LEVEL_SHIFT 0
    #define IBB_HUFFMAN_B14AC_GET_LEVEL_SIGN_MASK 0x00008000
    #define IBB_HUFFMAN_B14AC_GET_LEVEL_SIGN_SHIFT 15
    #define IBB_HUFFMAN_B14AC_GET_RUN_MASK 0x007F0000
    #define IBB_HUFFMAN_B14AC_GET_RUN_SHIFT 16
#define  IBB_HUFFMAN_B14DC_GET 0x00C4
    #define IBB_HUFFMAN_B14DC_GET_LEVEL_MASK 0x00007FFF
    #define IBB_HUFFMAN_B14DC_GET_LEVEL_SHIFT 0
    #define IBB_HUFFMAN_B14DC_GET_LEVEL_SIGN_MASK 0x00008000
    #define IBB_HUFFMAN_B14DC_GET_LEVEL_SIGN_SHIFT 15
    #define IBB_HUFFMAN_B14DC_GET_RUN_MASK 0x007F0000
    #define IBB_HUFFMAN_B14DC_GET_RUN_SHIFT 16
#define  IBB_HUFFMAN_B15_GET 0x00CC
    #define IBB_HUFFMAN_B15_GET_DATA_MASK 0xFFFFFFFF
    #define IBB_HUFFMAN_B15_GET_DATA_SHIFT 0
#define  IBB_HUFFMAN_B1_GET 0x0090
    #define IBB_HUFFMAN_B1_GET_LEVEL_MASK 0x00007FFF
    #define IBB_HUFFMAN_B1_GET_LEVEL_SHIFT 0
    #define IBB_HUFFMAN_B1_GET_RUN_MASK 0x007F0000
    #define IBB_HUFFMAN_B1_GET_RUN_SHIFT 16
#define  IBB_HUFFMAN_B2_GET 0x0094
    #define IBB_HUFFMAN_B2_GET_DATA_MASK 0xFFFFFFFF
    #define IBB_HUFFMAN_B2_GET_DATA_SHIFT 0
#define  IBB_HUFFMAN_B3_GET 0x0098
    #define IBB_HUFFMAN_B3_GET_DATA_MASK 0xFFFFFFFF
    #define IBB_HUFFMAN_B3_GET_DATA_SHIFT 0
#define  IBB_HUFFMAN_B4_GET 0x009C
    #define IBB_HUFFMAN_B4_GET_DATA_MASK 0xFFFFFFFF
    #define IBB_HUFFMAN_B4_GET_DATA_SHIFT 0
#define  IBB_HUFFMAN_B5_GET 0x00A0
    #define IBB_HUFFMAN_B5_GET_DATA_MASK 0xFFFFFFFF
    #define IBB_HUFFMAN_B5_GET_DATA_SHIFT 0
#define  IBB_HUFFMAN_B6_GET 0x00A4
    #define IBB_HUFFMAN_B6_GET_DATA_MASK 0xFFFFFFFF
    #define IBB_HUFFMAN_B6_GET_DATA_SHIFT 0
#define  IBB_HUFFMAN_B7_GET 0x00A8
    #define IBB_HUFFMAN_B7_GET_DATA_MASK 0xFFFFFFFF
    #define IBB_HUFFMAN_B7_GET_DATA_SHIFT 0
#define  IBB_HUFFMAN_B8_GET 0x00AC
    #define IBB_HUFFMAN_B8_GET_DATA_MASK 0xFFFFFFFF
    #define IBB_HUFFMAN_B8_GET_DATA_SHIFT 0
#define  IBB_HUFFMAN_B9_GET 0x00B0
    #define IBB_HUFFMAN_B9_GET_DATA_MASK 0xFFFFFFFF
    #define IBB_HUFFMAN_B9_GET_DATA_SHIFT 0
#define  IBB_INT_MASK 0x0124
    #define IBB_INT_MASK_IBB_NOT_READY_MASK 0x00000001
    #define IBB_INT_MASK_IBB_NOT_READY_SHIFT 0
    #define IBB_INT_MASK_IBB_READY_MASK 0x00000002
    #define IBB_INT_MASK_IBB_READY_SHIFT 1
    #define IBB_INT_MASK_HUFFMAN_ERROR_MASK 0x00000004
    #define IBB_INT_MASK_HUFFMAN_ERROR_SHIFT 2
#define  IBB_INT_STATUS 0x0120
    #define IBB_INT_STATUS_IBB_NOT_READY_MASK 0x00000001
    #define IBB_INT_STATUS_IBB_NOT_READY_SHIFT 0
    #define IBB_INT_STATUS_IBB_READY_MASK 0x00000002
    #define IBB_INT_STATUS_IBB_READY_SHIFT 1
    #define IBB_INT_STATUS_HUFFMAN_ERROR_MASK 0x00000004
    #define IBB_INT_STATUS_HUFFMAN_ERROR_SHIFT 2
#define  IBB_MC_PENDING 0x011C
    #define NUMBER_MASK 0x000000FF
    #define NUMBER_SHIFT 0
#define  IBB_RB_ADR 0x0108
    #define IBB_RB_ADR_BASE_MASK 0x0000FFFF
    #define IBB_RB_ADR_BASE_SHIFT 0
    #define TOP_MASK 0xFFFF0000
    #define TOP_SHIFT 16
#define  IBB_RB_HEAD 0x0118
    #define IBB_RB_HEAD_BASE_MASK 0x0FFFFFF0
    #define IBB_RB_HEAD_BASE_SHIFT 4
#define  IBB_RB_TAIL_INI 0x010C
    #define IBB_RB_TAIL_INI_BASE_MASK 0x0FFFFFFC
    #define IBB_RB_TAIL_INI_BASE_SHIFT 2
#define  IBB_RB_TAIL_READ 0x0110
    #define IBB_RB_TAIL_READ_BASE_MASK 0x0FFFFFFC
    #define IBB_RB_TAIL_READ_BASE_SHIFT 2
#define  IBB_SHOW_BITS32 0x0000
    #define IBB_SHOW_BITS32_DATA_MASK 0xFFFFFFFF
    #define IBB_SHOW_BITS32_DATA_SHIFT 0
#define  IBB_STATUS 0x0104
    #define LB_CNT_MASK 0x000001FF
    #define LB_CNT_SHIFT 0
    #define IBB_MC_PENDING_MASK 0x10000000
    #define IBB_MC_PENDING_SHIFT 28
    #define HUFMAN_ERR_MASK 0x20000000
    #define HUFMAN_ERR_SHIFT 29
    #define READY_MASK 0x40000000
    #define READY_SHIFT 30
    #define NOT_READY_MASK 0x80000000
    #define NOT_READY_SHIFT 31
#define  IDCT_CTRL 0x7304
    #define IDCT_DCT_TYPE_MASK 0x00000001
    #define IDCT_DCT_TYPE_SHIFT 0
    #define IDCT_OUT_ORDER_MASK 0x00000002
    #define IDCT_OUT_ORDER_SHIFT 1
    #define IDCT_CTRL_MB_PATTERN_MASK 0x000000FC
    #define IDCT_CTRL_MB_PATTERN_SHIFT 2
    #define IDCT_CTRL_QSCALE_MASK 0x00007F00
    #define IDCT_CTRL_QSCALE_SHIFT 8
    #define IDCT_CTRL_MB_TYPE_MASK 0x40000000
    #define IDCT_CTRL_MB_TYPE_SHIFT 30
    #define RESET_DCPRED_MASK 0x80000000
    #define RESET_DCPRED_SHIFT 31
#define  IDQS_CLK_CTRL 0x74C0
    #define IDQS_ECLK_GATE_EN_MASK 0x00000001
    #define IDQS_ECLK_GATE_EN_SHIFT 0
    #define IDQS_MCLK_GATE_EN_MASK 0x00000002
    #define IDQS_MCLK_GATE_EN_SHIFT 1
    #define IDQS_CLK_CTRL_XCODE_ECLK_GATE_EN_MASK 0x00000004
    #define IDQS_CLK_CTRL_XCODE_ECLK_GATE_EN_SHIFT 2
    #define XCODE_MCLK_GATE_EN_MASK 0x00000008
    #define XCODE_MCLK_GATE_EN_SHIFT 3
#define  IDQS_DUMMY_REG 0x72D4
    #define IDQS_DUMMY_REG_DUMMY_MASK 0xFFFFFFFF
    #define IDQS_DUMMY_REG_DUMMY_SHIFT 0
#define  IDQS_SCL_SPRAM_RM 0x72E4
    #define SPRAM_RM_MASK 0x0000000F
    #define SPRAM_RM_SHIFT 0
#define  IDQS_STAT_MUX 0x7268
    #define IDQS_STAT_MUX_STAT_MUX_MASK 0x0000001F
    #define IDQS_STAT_MUX_STAT_MUX_SHIFT 0
#define  IDQS_STAT_MUX_RB 0x7264
    #define IDQS_STAT_MUX_RB_STAT_RB_MASK 0xFFFFFFFF
    #define IDQS_STAT_MUX_RB_STAT_RB_SHIFT 0
#define  INDIRECT_IO_DATA 0x0004
    #define INDIRECT_IO_DATA_DATA_MASK 0xFFFFFFFF
    #define INDIRECT_IO_DATA_DATA_SHIFT 0
#define  INDIRECT_IO_INDEX 0x0000
    #define INDIRECT_IO_INDEX_DATA_MASK 0x0000FFFF
    #define INDIRECT_IO_INDEX_DATA_SHIFT 0
#define  LP_FILTER_BYPASS 0x111C
    #define I2C0_MASTER_FILTER_BYPASS_MASK 0x00000001
    #define I2C0_MASTER_FILTER_BYPASS_SHIFT 0
    #define I2C1_MASTER_FILTER_BYPASS_MASK 0x00000002
    #define I2C1_MASTER_FILTER_BYPASS_SHIFT 1
    #define I2C_SLAVE_FILTER_BYPASS_MASK 0x00000004
    #define I2C_SLAVE_FILTER_BYPASS_SHIFT 2
#define  MBD0_CQA_ADR 0xA124
    #define MBD0_CQA_ADR_BASE_MASK 0x07FFFFFE
    #define MBD0_CQA_ADR_BASE_SHIFT 1
#define  MBD0_INFO 0xA178
    #define MBD0_INFO_MB_TYPE_MASK 0x0000000F
    #define MBD0_INFO_MB_TYPE_SHIFT 0
    #define MBD0_INFO_MO_TYPE_MASK 0x00000030
    #define MBD0_INFO_MO_TYPE_SHIFT 4
    #define MBD0_INFO_DCT_TYPE_MASK 0x00000040
    #define MBD0_INFO_DCT_TYPE_SHIFT 6
    #define MBD0_INFO_MB_PATTERN_MASK 0x00003F00
    #define MBD0_INFO_MB_PATTERN_SHIFT 8
    #define MBD0_INFO_QSCALE_MASK 0x007F0000
    #define MBD0_INFO_QSCALE_SHIFT 16
#define  MBD0_SLICE_QSCALE 0xA16C
    #define MBD0_SLICE_QSCALE_QSCALE_MASK 0x0000007F
    #define MBD0_SLICE_QSCALE_QSCALE_SHIFT 0
#define  MBD0_STATUS 0xA174
    #define MBD0_STATUS_DONE_MASK 0x00000001
    #define MBD0_STATUS_DONE_SHIFT 0
    #define MBD0_STATUS_DIP_END_MASK 0x07FFFFFC
    #define MBD0_STATUS_DIP_END_SHIFT 2
    #define MBD0_STATUS_ERROR_MASK 0xF0000000
    #define MBD0_STATUS_ERROR_SHIFT 28
#define  MBD0_TRIG 0xA170
    #define MBD0_TRIG_SKIP_MB_CNT_MASK 0x0000007F
    #define MBD0_TRIG_SKIP_MB_CNT_SHIFT 0
    #define MBD0_TRIG_MB_IDX_X_MASK 0x007F0000
    #define MBD0_TRIG_MB_IDX_X_SHIFT 16
    #define MBD0_TRIG_MB_IDX_Y_MASK 0x7F000000
    #define MBD0_TRIG_MB_IDX_Y_SHIFT 24
#define  MBD1_CQA_ADR 0xA524
    #define MBD1_CQA_ADR_BASE_MASK 0x07FFFFFE
    #define MBD1_CQA_ADR_BASE_SHIFT 1
#define  MBD1_INFO 0xA578
    #define MBD1_INFO_MB_TYPE_MASK 0x0000000F
    #define MBD1_INFO_MB_TYPE_SHIFT 0
    #define MBD1_INFO_MO_TYPE_MASK 0x00000030
    #define MBD1_INFO_MO_TYPE_SHIFT 4
    #define MBD1_INFO_DCT_TYPE_MASK 0x00000040
    #define MBD1_INFO_DCT_TYPE_SHIFT 6
    #define MBD1_INFO_MB_PATTERN_MASK 0x00003F00
    #define MBD1_INFO_MB_PATTERN_SHIFT 8
    #define MBD1_INFO_QSCALE_MASK 0x007F0000
    #define MBD1_INFO_QSCALE_SHIFT 16
#define  MBD1_SLICE_QSCALE 0xA56C
    #define MBD1_SLICE_QSCALE_QSCALE_MASK 0x0000007F
    #define MBD1_SLICE_QSCALE_QSCALE_SHIFT 0
#define  MBD1_STATUS 0xA574
    #define MBD1_STATUS_DONE_MASK 0x00000001
    #define MBD1_STATUS_DONE_SHIFT 0
    #define MBD1_STATUS_DIP_END_MASK 0x07FFFFFC
    #define MBD1_STATUS_DIP_END_SHIFT 2
    #define MBD1_STATUS_ERROR_MASK 0xF0000000
    #define MBD1_STATUS_ERROR_SHIFT 28
#define  MBD1_TRIG 0xA570
    #define MBD1_TRIG_SKIP_MB_CNT_MASK 0x0000007F
    #define MBD1_TRIG_SKIP_MB_CNT_SHIFT 0
    #define MBD1_TRIG_MB_IDX_X_MASK 0x007F0000
    #define MBD1_TRIG_MB_IDX_X_SHIFT 16
    #define MBD1_TRIG_MB_IDX_Y_MASK 0x7F000000
    #define MBD1_TRIG_MB_IDX_Y_SHIFT 24
#define  MC_ARB_CTRLA 0x0840
    #define MC_ARB_CTRLA_CL0_TIMER_MASK 0x0000000F
    #define MC_ARB_CTRLA_CL0_TIMER_SHIFT 0
    #define MC_ARB_CTRLA_CL1_TIMER_MASK 0x000000F0
    #define MC_ARB_CTRLA_CL1_TIMER_SHIFT 4
    #define MC_ARB_CTRLA_CL2_TIMER_MASK 0x00000F00
    #define MC_ARB_CTRLA_CL2_TIMER_SHIFT 8
    #define MC_ARB_CTRLA_CL3_TIMER_MASK 0x0000F000
    #define MC_ARB_CTRLA_CL3_TIMER_SHIFT 12
    #define MC_ARB_CTRLA_CL4_TIMER_MASK 0x000F0000
    #define MC_ARB_CTRLA_CL4_TIMER_SHIFT 16
    #define MC_ARB_CTRLA_CL5_TIMER_MASK 0x00F00000
    #define MC_ARB_CTRLA_CL5_TIMER_SHIFT 20
    #define MC_ARB_CTRLA_CL6_TIMER_MASK 0x0F000000
    #define MC_ARB_CTRLA_CL6_TIMER_SHIFT 24
    #define MC_ARB_CTRLA_CL7_TIMER_MASK 0xF0000000
    #define MC_ARB_CTRLA_CL7_TIMER_SHIFT 28
#define  MC_ARB_CTRLB 0x0844
    #define MC_ARB_CTRLB_CL8_TIMER_MASK 0x0000000F
    #define MC_ARB_CTRLB_CL8_TIMER_SHIFT 0
    #define MC_ARB_CTRLB_CL9_TIMER_MASK 0x000000F0
    #define MC_ARB_CTRLB_CL9_TIMER_SHIFT 4
    #define MC_ARB_CTRLB_CL10_TIMER_MASK 0x00000F00
    #define MC_ARB_CTRLB_CL10_TIMER_SHIFT 8
    #define MC_ARB_CTRLB_CL11_TIMER_MASK 0x0000F000
    #define MC_ARB_CTRLB_CL11_TIMER_SHIFT 12
#define  MC_ARB_LATENCY_TIMER_CTRLA 0x0894
    #define MC_ARB_LATENCY_TIMER_CTRLA_CL0_LATENCY_TIMER_MASK 0x000000FF
    #define MC_ARB_LATENCY_TIMER_CTRLA_CL0_LATENCY_TIMER_SHIFT 0
    #define MC_ARB_LATENCY_TIMER_CTRLA_CL1_LATENCY_TIMER_MASK 0x0000FF00
    #define MC_ARB_LATENCY_TIMER_CTRLA_CL1_LATENCY_TIMER_SHIFT 8
    #define MC_ARB_LATENCY_TIMER_CTRLA_CL2_LATENCY_TIMER_MASK 0x00FF0000
    #define MC_ARB_LATENCY_TIMER_CTRLA_CL2_LATENCY_TIMER_SHIFT 16
    #define MC_ARB_LATENCY_TIMER_CTRLA_CL3_LATENCY_TIMER_MASK 0xFF000000
    #define MC_ARB_LATENCY_TIMER_CTRLA_CL3_LATENCY_TIMER_SHIFT 24
#define  MC_ARB_LATENCY_TIMER_CTRLB 0x0898
    #define MC_ARB_LATENCY_TIMER_CTRLB_CL4_LATENCY_TIMER_MASK 0x000000FF
    #define MC_ARB_LATENCY_TIMER_CTRLB_CL4_LATENCY_TIMER_SHIFT 0
    #define MC_ARB_LATENCY_TIMER_CTRLB_CL5_LATENCY_TIMER_MASK 0x0000FF00
    #define MC_ARB_LATENCY_TIMER_CTRLB_CL5_LATENCY_TIMER_SHIFT 8
    #define MC_ARB_LATENCY_TIMER_CTRLB_CL6_LATENCY_TIMER_MASK 0x00FF0000
    #define MC_ARB_LATENCY_TIMER_CTRLB_CL6_LATENCY_TIMER_SHIFT 16
    #define MC_ARB_LATENCY_TIMER_CTRLB_CL7_LATENCY_TIMER_MASK 0xFF000000
    #define MC_ARB_LATENCY_TIMER_CTRLB_CL7_LATENCY_TIMER_SHIFT 24
#define  MC_ARB_LATENCY_TIMER_CTRLC 0x089C
    #define MC_ARB_LATENCY_TIMER_CTRLC_CL8_LATENCY_TIMER_MASK 0x000000FF
    #define MC_ARB_LATENCY_TIMER_CTRLC_CL8_LATENCY_TIMER_SHIFT 0
    #define MC_ARB_LATENCY_TIMER_CTRLC_CL9_LATENCY_TIMER_MASK 0x0000FF00
    #define MC_ARB_LATENCY_TIMER_CTRLC_CL9_LATENCY_TIMER_SHIFT 8
    #define MC_ARB_LATENCY_TIMER_CTRLC_CL10_LATENCY_TIMER_MASK 0x00FF0000
    #define MC_ARB_LATENCY_TIMER_CTRLC_CL10_LATENCY_TIMER_SHIFT 16
    #define MC_ARB_LATENCY_TIMER_CTRLC_CL11_LATENCY_TIMER_MASK 0xFF000000
    #define MC_ARB_LATENCY_TIMER_CTRLC_CL11_LATENCY_TIMER_SHIFT 24
#define  MC_ARB_MAIN_CTRL 0x0848
    #define MC_ARB_MAIN_CTRL_LVL1_PRI_DIS_MASK 0x00000010
    #define MC_ARB_MAIN_CTRL_LVL1_PRI_DIS_SHIFT 4
    #define MC_ARB_MAIN_CTRL_URG_PRI_DIS_MASK 0x00000040
    #define MC_ARB_MAIN_CTRL_URG_PRI_DIS_SHIFT 6
    #define MC_ARB_MAIN_CTRL_LAT_PRI_DIS_MASK 0x00000080
    #define MC_ARB_MAIN_CTRL_LAT_PRI_DIS_SHIFT 7
    #define MC_ARB_MAIN_CTRL_CLI_URGENT_SET_MASK 0x0FFF0000
    #define MC_ARB_MAIN_CTRL_CLI_URGENT_SET_SHIFT 16
#define  MC_ARB_PAGE_TIMER_CTRLA 0x08A0
    #define MC_ARB_PAGE_TIMER_CTRLA_CL0_PAGE_TIMER_MASK 0x0000000F
    #define MC_ARB_PAGE_TIMER_CTRLA_CL0_PAGE_TIMER_SHIFT 0
    #define MC_ARB_PAGE_TIMER_CTRLA_CL1_PAGE_TIMER_MASK 0x000000F0
    #define MC_ARB_PAGE_TIMER_CTRLA_CL1_PAGE_TIMER_SHIFT 4
    #define MC_ARB_PAGE_TIMER_CTRLA_CL2_PAGE_TIMER_MASK 0x00000F00
    #define MC_ARB_PAGE_TIMER_CTRLA_CL2_PAGE_TIMER_SHIFT 8
    #define MC_ARB_PAGE_TIMER_CTRLA_CL3_PAGE_TIMER_MASK 0x0000F000
    #define MC_ARB_PAGE_TIMER_CTRLA_CL3_PAGE_TIMER_SHIFT 12
    #define MC_ARB_PAGE_TIMER_CTRLA_CL4_PAGE_TIMER_MASK 0x000F0000
    #define MC_ARB_PAGE_TIMER_CTRLA_CL4_PAGE_TIMER_SHIFT 16
    #define MC_ARB_PAGE_TIMER_CTRLA_CL5_PAGE_TIMER_MASK 0x00F00000
    #define MC_ARB_PAGE_TIMER_CTRLA_CL5_PAGE_TIMER_SHIFT 20
    #define MC_ARB_PAGE_TIMER_CTRLA_CL6_PAGE_TIMER_MASK 0x0F000000
    #define MC_ARB_PAGE_TIMER_CTRLA_CL6_PAGE_TIMER_SHIFT 24
    #define MC_ARB_PAGE_TIMER_CTRLA_CL7_PAGE_TIMER_MASK 0xF0000000
    #define MC_ARB_PAGE_TIMER_CTRLA_CL7_PAGE_TIMER_SHIFT 28
#define  MC_ARB_PAGE_TIMER_CTRLB 0x08A4
    #define MC_ARB_PAGE_TIMER_CTRLB_CL8_PAGE_TIMER_MASK 0x0000000F
    #define MC_ARB_PAGE_TIMER_CTRLB_CL8_PAGE_TIMER_SHIFT 0
    #define MC_ARB_PAGE_TIMER_CTRLB_CL9_PAGE_TIMER_MASK 0x000000F0
    #define MC_ARB_PAGE_TIMER_CTRLB_CL9_PAGE_TIMER_SHIFT 4
    #define MC_ARB_PAGE_TIMER_CTRLB_CL10_PAGE_TIMER_MASK 0x00000F00
    #define MC_ARB_PAGE_TIMER_CTRLB_CL10_PAGE_TIMER_SHIFT 8
    #define MC_ARB_PAGE_TIMER_CTRLB_CL11_PAGE_TIMER_MASK 0x0000F000
    #define MC_ARB_PAGE_TIMER_CTRLB_CL11_PAGE_TIMER_SHIFT 12
#define  MC_ARB_PRIORITY_CTRL 0x084C
    #define MC_ARB_PRIORITY_CTRL_CL_DISABLE_LAT_PRIORITY_MASK 0x00000FFF
    #define MC_ARB_PRIORITY_CTRL_CL_DISABLE_LAT_PRIORITY_SHIFT 0
    #define MC_ARB_PRIORITY_CTRL_CL_DISABLE_URG_PRIORITY_MASK 0x0FFF0000
    #define MC_ARB_PRIORITY_CTRL_CL_DISABLE_URG_PRIORITY_SHIFT 16
#define  MC_CH0_ARB_CTRLA 0x9130
    #define MC_CH0_ARB_CTRLA_CL0_TIMER_MASK 0x0000000F
    #define MC_CH0_ARB_CTRLA_CL0_TIMER_SHIFT 0
    #define MC_CH0_ARB_CTRLA_CL1_TIMER_MASK 0x000000F0
    #define MC_CH0_ARB_CTRLA_CL1_TIMER_SHIFT 4
    #define MC_CH0_ARB_CTRLA_CL2_TIMER_MASK 0x00000F00
    #define MC_CH0_ARB_CTRLA_CL2_TIMER_SHIFT 8
    #define MC_CH0_ARB_CTRLA_CL3_TIMER_MASK 0x0000F000
    #define MC_CH0_ARB_CTRLA_CL3_TIMER_SHIFT 12
    #define MC_CH0_ARB_CTRLA_CL4_TIMER_MASK 0x000F0000
    #define MC_CH0_ARB_CTRLA_CL4_TIMER_SHIFT 16
    #define MC_CH0_ARB_CTRLA_CL5_TIMER_MASK 0x00F00000
    #define MC_CH0_ARB_CTRLA_CL5_TIMER_SHIFT 20
    #define MC_CH0_ARB_CTRLA_CL6_TIMER_MASK 0x0F000000
    #define MC_CH0_ARB_CTRLA_CL6_TIMER_SHIFT 24
    #define MC_CH0_ARB_CTRLA_CL7_TIMER_MASK 0xF0000000
    #define MC_CH0_ARB_CTRLA_CL7_TIMER_SHIFT 28
#define  MC_CH0_ARB_CTRLB 0x9134
    #define MC_CH0_ARB_CTRLB_CL8_TIMER_MASK 0x0000000F
    #define MC_CH0_ARB_CTRLB_CL8_TIMER_SHIFT 0
    #define MC_CH0_ARB_CTRLB_CL9_TIMER_MASK 0x000000F0
    #define MC_CH0_ARB_CTRLB_CL9_TIMER_SHIFT 4
    #define MC_CH0_ARB_CTRLB_CL10_TIMER_MASK 0x00000F00
    #define MC_CH0_ARB_CTRLB_CL10_TIMER_SHIFT 8
    #define MC_CH0_ARB_CTRLB_CL11_TIMER_MASK 0x0000F000
    #define MC_CH0_ARB_CTRLB_CL11_TIMER_SHIFT 12
    #define MC_CH0_ARB_CTRLB_CL12_TIMER_MASK 0x000F0000
    #define MC_CH0_ARB_CTRLB_CL12_TIMER_SHIFT 16
    #define MC_CH0_ARB_CTRLB_CL13_TIMER_MASK 0x00F00000
    #define MC_CH0_ARB_CTRLB_CL13_TIMER_SHIFT 20
    #define MC_CH0_ARB_CTRLB_CL14_TIMER_MASK 0x0F000000
    #define MC_CH0_ARB_CTRLB_CL14_TIMER_SHIFT 24
    #define MC_CH0_ARB_CTRLB_CL15_TIMER_MASK 0xF0000000
    #define MC_CH0_ARB_CTRLB_CL15_TIMER_SHIFT 28
#define  MC_CH0_ARB_CTRLC 0x9138
    #define MC_CH0_ARB_CTRLC_CL16_TIMER_MASK 0x0000000F
    #define MC_CH0_ARB_CTRLC_CL16_TIMER_SHIFT 0
    #define MC_CH0_ARB_CTRLC_CL17_TIMER_MASK 0x000000F0
    #define MC_CH0_ARB_CTRLC_CL17_TIMER_SHIFT 4
    #define MC_CH0_ARB_CTRLC_CL18_TIMER_MASK 0x00000F00
    #define MC_CH0_ARB_CTRLC_CL18_TIMER_SHIFT 8
    #define MC_CH0_ARB_CTRLC_CL19_TIMER_MASK 0x0000F000
    #define MC_CH0_ARB_CTRLC_CL19_TIMER_SHIFT 12
#define  MC_CH0_ARB_LATENCY_TIMER_CTRLA 0x9150
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLA_CL0_LATENCY_TIMER_MASK 0x000000FF
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLA_CL0_LATENCY_TIMER_SHIFT 0
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLA_CL1_LATENCY_TIMER_MASK 0x0000FF00
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLA_CL1_LATENCY_TIMER_SHIFT 8
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLA_CL2_LATENCY_TIMER_MASK 0x00FF0000
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLA_CL2_LATENCY_TIMER_SHIFT 16
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLA_CL3_LATENCY_TIMER_MASK 0xFF000000
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLA_CL3_LATENCY_TIMER_SHIFT 24
#define  MC_CH0_ARB_LATENCY_TIMER_CTRLB 0x9154
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLB_CL4_LATENCY_TIMER_MASK 0x000000FF
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLB_CL4_LATENCY_TIMER_SHIFT 0
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLB_CL5_LATENCY_TIMER_MASK 0x0000FF00
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLB_CL5_LATENCY_TIMER_SHIFT 8
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLB_CL6_LATENCY_TIMER_MASK 0x00FF0000
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLB_CL6_LATENCY_TIMER_SHIFT 16
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLB_CL7_LATENCY_TIMER_MASK 0xFF000000
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLB_CL7_LATENCY_TIMER_SHIFT 24
#define  MC_CH0_ARB_LATENCY_TIMER_CTRLC 0x9158
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLC_CL8_LATENCY_TIMER_MASK 0x000000FF
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLC_CL8_LATENCY_TIMER_SHIFT 0
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLC_CL9_LATENCY_TIMER_MASK 0x0000FF00
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLC_CL9_LATENCY_TIMER_SHIFT 8
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLC_CL10_LATENCY_TIMER_MASK 0x00FF0000
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLC_CL10_LATENCY_TIMER_SHIFT 16
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLC_CL11_LATENCY_TIMER_MASK 0xFF000000
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLC_CL11_LATENCY_TIMER_SHIFT 24
#define  MC_CH0_ARB_LATENCY_TIMER_CTRLD 0x915C
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLD_CL12_LATENCY_TIMER_MASK 0x000000FF
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLD_CL12_LATENCY_TIMER_SHIFT 0
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLD_CL13_LATENCY_TIMER_MASK 0x0000FF00
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLD_CL13_LATENCY_TIMER_SHIFT 8
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLD_CL14_LATENCY_TIMER_MASK 0x00FF0000
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLD_CL14_LATENCY_TIMER_SHIFT 16
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLD_CL15_LATENCY_TIMER_MASK 0xFF000000
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLD_CL15_LATENCY_TIMER_SHIFT 24
#define  MC_CH0_ARB_LATENCY_TIMER_CTRLE 0x9160
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLE_CL16_LATENCY_TIMER_MASK 0x000000FF
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLE_CL16_LATENCY_TIMER_SHIFT 0
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLE_CL17_LATENCY_TIMER_MASK 0x0000FF00
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLE_CL17_LATENCY_TIMER_SHIFT 8
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLE_CL18_LATENCY_TIMER_MASK 0x00FF0000
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLE_CL18_LATENCY_TIMER_SHIFT 16
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLE_CL19_LATENCY_TIMER_MASK 0xFF000000
    #define MC_CH0_ARB_LATENCY_TIMER_CTRLE_CL19_LATENCY_TIMER_SHIFT 24
#define  MC_CH0_ARB_MAIN_CTRL 0x9170
    #define MC_CH0_ARB_MAIN_CTRL_LVL1_PRI_DIS_MASK 0x00000010
    #define MC_CH0_ARB_MAIN_CTRL_LVL1_PRI_DIS_SHIFT 4
    #define MC_CH0_ARB_MAIN_CTRL_URG_PRI_DIS_MASK 0x00000040
    #define MC_CH0_ARB_MAIN_CTRL_URG_PRI_DIS_SHIFT 6
    #define MC_CH0_ARB_MAIN_CTRL_LAT_PRI_DIS_MASK 0x00000080
    #define MC_CH0_ARB_MAIN_CTRL_LAT_PRI_DIS_SHIFT 7
    #define MC_CH0_ARB_MAIN_CTRL_CLI_URGENT_SET_MASK 0xFFFFF000
    #define MC_CH0_ARB_MAIN_CTRL_CLI_URGENT_SET_SHIFT 12
#define  MC_CH0_ARB_PAGE_TIMER_CTRLA 0x9140
    #define MC_CH0_ARB_PAGE_TIMER_CTRLA_CL0_PAGE_TIMER_MASK 0x0000000F
    #define MC_CH0_ARB_PAGE_TIMER_CTRLA_CL0_PAGE_TIMER_SHIFT 0
    #define MC_CH0_ARB_PAGE_TIMER_CTRLA_CL1_PAGE_TIMER_MASK 0x000000F0
    #define MC_CH0_ARB_PAGE_TIMER_CTRLA_CL1_PAGE_TIMER_SHIFT 4
    #define MC_CH0_ARB_PAGE_TIMER_CTRLA_CL2_PAGE_TIMER_MASK 0x00000F00
    #define MC_CH0_ARB_PAGE_TIMER_CTRLA_CL2_PAGE_TIMER_SHIFT 8
    #define MC_CH0_ARB_PAGE_TIMER_CTRLA_CL3_PAGE_TIMER_MASK 0x0000F000
    #define MC_CH0_ARB_PAGE_TIMER_CTRLA_CL3_PAGE_TIMER_SHIFT 12
    #define MC_CH0_ARB_PAGE_TIMER_CTRLA_CL4_PAGE_TIMER_MASK 0x000F0000
    #define MC_CH0_ARB_PAGE_TIMER_CTRLA_CL4_PAGE_TIMER_SHIFT 16
    #define MC_CH0_ARB_PAGE_TIMER_CTRLA_CL5_PAGE_TIMER_MASK 0x00F00000
    #define MC_CH0_ARB_PAGE_TIMER_CTRLA_CL5_PAGE_TIMER_SHIFT 20
    #define MC_CH0_ARB_PAGE_TIMER_CTRLA_CL6_PAGE_TIMER_MASK 0x0F000000
    #define MC_CH0_ARB_PAGE_TIMER_CTRLA_CL6_PAGE_TIMER_SHIFT 24
    #define MC_CH0_ARB_PAGE_TIMER_CTRLA_CL7_PAGE_TIMER_MASK 0xF0000000
    #define MC_CH0_ARB_PAGE_TIMER_CTRLA_CL7_PAGE_TIMER_SHIFT 28
#define  MC_CH0_ARB_PAGE_TIMER_CTRLB 0x9144
    #define MC_CH0_ARB_PAGE_TIMER_CTRLB_CL8_PAGE_TIMER_MASK 0x0000000F
    #define MC_CH0_ARB_PAGE_TIMER_CTRLB_CL8_PAGE_TIMER_SHIFT 0
    #define MC_CH0_ARB_PAGE_TIMER_CTRLB_CL9_PAGE_TIMER_MASK 0x000000F0
    #define MC_CH0_ARB_PAGE_TIMER_CTRLB_CL9_PAGE_TIMER_SHIFT 4
    #define MC_CH0_ARB_PAGE_TIMER_CTRLB_CL10_PAGE_TIMER_MASK 0x00000F00
    #define MC_CH0_ARB_PAGE_TIMER_CTRLB_CL10_PAGE_TIMER_SHIFT 8
    #define MC_CH0_ARB_PAGE_TIMER_CTRLB_CL11_PAGE_TIMER_MASK 0x0000F000
    #define MC_CH0_ARB_PAGE_TIMER_CTRLB_CL11_PAGE_TIMER_SHIFT 12
    #define MC_CH0_ARB_PAGE_TIMER_CTRLB_CL12_PAGE_TIMER_MASK 0x000F0000
    #define MC_CH0_ARB_PAGE_TIMER_CTRLB_CL12_PAGE_TIMER_SHIFT 16
    #define MC_CH0_ARB_PAGE_TIMER_CTRLB_CL13_PAGE_TIMER_MASK 0x00F00000
    #define MC_CH0_ARB_PAGE_TIMER_CTRLB_CL13_PAGE_TIMER_SHIFT 20
    #define MC_CH0_ARB_PAGE_TIMER_CTRLB_CL14_PAGE_TIMER_MASK 0x0F000000
    #define MC_CH0_ARB_PAGE_TIMER_CTRLB_CL14_PAGE_TIMER_SHIFT 24
    #define MC_CH0_ARB_PAGE_TIMER_CTRLB_CL15_PAGE_TIMER_MASK 0xF0000000
    #define MC_CH0_ARB_PAGE_TIMER_CTRLB_CL15_PAGE_TIMER_SHIFT 28
#define  MC_CH0_ARB_PAGE_TIMER_CTRLC 0x9148
    #define MC_CH0_ARB_PAGE_TIMER_CTRLC_CL16_PAGE_TIMER_MASK 0x0000000F
    #define MC_CH0_ARB_PAGE_TIMER_CTRLC_CL16_PAGE_TIMER_SHIFT 0
    #define MC_CH0_ARB_PAGE_TIMER_CTRLC_CL17_PAGE_TIMER_MASK 0x000000F0
    #define MC_CH0_ARB_PAGE_TIMER_CTRLC_CL17_PAGE_TIMER_SHIFT 4
    #define MC_CH0_ARB_PAGE_TIMER_CTRLC_CL18_PAGE_TIMER_MASK 0x00000F00
    #define MC_CH0_ARB_PAGE_TIMER_CTRLC_CL18_PAGE_TIMER_SHIFT 8
    #define MC_CH0_ARB_PAGE_TIMER_CTRLC_CL19_PAGE_TIMER_MASK 0x0000F000
    #define MC_CH0_ARB_PAGE_TIMER_CTRLC_CL19_PAGE_TIMER_SHIFT 12
#define  MC_CH0_ARB_PRIORITY_CTRLA 0x9174
    #define MC_CH0_ARB_PRIORITY_CTRLA_CL_DISABLE_LAT_PRIORITY_MASK 0x000FFFFF
    #define MC_CH0_ARB_PRIORITY_CTRLA_CL_DISABLE_LAT_PRIORITY_SHIFT 0
#define  MC_CH0_ARB_PRIORITY_CTRLB 0x9178
    #define MC_CH0_ARB_PRIORITY_CTRLB_CL_DISABLE_URG_PRIORITY_MASK 0x000FFFFF
    #define MC_CH0_ARB_PRIORITY_CTRLB_CL_DISABLE_URG_PRIORITY_SHIFT 0
#define  MC_CH0_LOCK_EN 0x9110
    #define MC_CH0_LOCK_EN_LOCK_CL_ID_MASK 0x001FFFFF
    #define MC_CH0_LOCK_EN_LOCK_CL_ID_SHIFT 0
#define  MC_CH0_MEM_CONFIG 0x9100
    #define MC_CH0_MEM_CONFIG_BANKPINS_MASK 0x00000003
    #define MC_CH0_MEM_CONFIG_BANKPINS_SHIFT 0
    #define MC_CH0_MEM_CONFIG_ADDRPINS_MASK 0x0000007C
    #define MC_CH0_MEM_CONFIG_ADDRPINS_SHIFT 2
    #define MC_CH0_MEM_CONFIG_COLCOUNT_MASK 0x00000F80
    #define MC_CH0_MEM_CONFIG_COLCOUNT_SHIFT 7
    #define MC_CH0_MEM_CONFIG_ROWBANKCOL_MASK 0x00001000
    #define MC_CH0_MEM_CONFIG_ROWBANKCOL_SHIFT 12
    #define MC_CH0_MEM_CONFIG_BSTLENGTH_MASK 0x00070000
    #define MC_CH0_MEM_CONFIG_BSTLENGTH_SHIFT 16
#define  MC_CH0_MISC_REG 0x9104
    #define MC_CH0_MISC_REG_MRLOGIC_RSTN_MASK 0x00000001
    #define MC_CH0_MISC_REG_MRLOGIC_RSTN_SHIFT 0
    #define MC_CH0_MISC_REG_MDLOGIC_RSTN_MASK 0x00000002
    #define MC_CH0_MISC_REG_MDLOGIC_RSTN_SHIFT 1
#define  MC_CH0_RD_LOCK_STATUS 0x9118
    #define MC_CH0_RD_LOCK_STATUS_READ_ATTEMPT_CL_ID_MASK 0x001FFFFF
    #define MC_CH0_RD_LOCK_STATUS_READ_ATTEMPT_CL_ID_SHIFT 0
#define  MC_CH0_WR_LOCK_STATUS 0x9114
    #define MC_CH0_WR_LOCK_STATUS_WRITE_ATTEMPT_CL_ID_MASK 0x001FFFFF
    #define MC_CH0_WR_LOCK_STATUS_WRITE_ATTEMPT_CL_ID_SHIFT 0
#define  MC_CH1_ARB_CTRLA 0x9230
    #define MC_CH1_ARB_CTRLA_CL0_TIMER_MASK 0x0000000F
    #define MC_CH1_ARB_CTRLA_CL0_TIMER_SHIFT 0
    #define MC_CH1_ARB_CTRLA_CL1_TIMER_MASK 0x000000F0
    #define MC_CH1_ARB_CTRLA_CL1_TIMER_SHIFT 4
    #define MC_CH1_ARB_CTRLA_CL2_TIMER_MASK 0x00000F00
    #define MC_CH1_ARB_CTRLA_CL2_TIMER_SHIFT 8
    #define MC_CH1_ARB_CTRLA_CL3_TIMER_MASK 0x0000F000
    #define MC_CH1_ARB_CTRLA_CL3_TIMER_SHIFT 12
    #define MC_CH1_ARB_CTRLA_CL4_TIMER_MASK 0x000F0000
    #define MC_CH1_ARB_CTRLA_CL4_TIMER_SHIFT 16
    #define MC_CH1_ARB_CTRLA_CL5_TIMER_MASK 0x00F00000
    #define MC_CH1_ARB_CTRLA_CL5_TIMER_SHIFT 20
    #define MC_CH1_ARB_CTRLA_CL6_TIMER_MASK 0x0F000000
    #define MC_CH1_ARB_CTRLA_CL6_TIMER_SHIFT 24
    #define MC_CH1_ARB_CTRLA_CL7_TIMER_MASK 0xF0000000
    #define MC_CH1_ARB_CTRLA_CL7_TIMER_SHIFT 28
#define  MC_CH1_ARB_CTRLB 0x9234
    #define MC_CH1_ARB_CTRLB_CL8_TIMER_MASK 0x0000000F
    #define MC_CH1_ARB_CTRLB_CL8_TIMER_SHIFT 0
    #define MC_CH1_ARB_CTRLB_CL9_TIMER_MASK 0x000000F0
    #define MC_CH1_ARB_CTRLB_CL9_TIMER_SHIFT 4
    #define MC_CH1_ARB_CTRLB_CL10_TIMER_MASK 0x00000F00
    #define MC_CH1_ARB_CTRLB_CL10_TIMER_SHIFT 8
    #define MC_CH1_ARB_CTRLB_CL11_TIMER_MASK 0x0000F000
    #define MC_CH1_ARB_CTRLB_CL11_TIMER_SHIFT 12
    #define MC_CH1_ARB_CTRLB_CL12_TIMER_MASK 0x000F0000
    #define MC_CH1_ARB_CTRLB_CL12_TIMER_SHIFT 16
    #define MC_CH1_ARB_CTRLB_CL13_TIMER_MASK 0x00F00000
    #define MC_CH1_ARB_CTRLB_CL13_TIMER_SHIFT 20
    #define MC_CH1_ARB_CTRLB_CL14_TIMER_MASK 0x0F000000
    #define MC_CH1_ARB_CTRLB_CL14_TIMER_SHIFT 24
    #define MC_CH1_ARB_CTRLB_CL15_TIMER_MASK 0xF0000000
    #define MC_CH1_ARB_CTRLB_CL15_TIMER_SHIFT 28
#define  MC_CH1_ARB_CTRLC 0x9238
    #define MC_CH1_ARB_CTRLC_CL16_TIMER_MASK 0x0000000F
    #define MC_CH1_ARB_CTRLC_CL16_TIMER_SHIFT 0
    #define MC_CH1_ARB_CTRLC_CL17_TIMER_MASK 0x000000F0
    #define MC_CH1_ARB_CTRLC_CL17_TIMER_SHIFT 4
    #define MC_CH1_ARB_CTRLC_CL18_TIMER_MASK 0x00000F00
    #define MC_CH1_ARB_CTRLC_CL18_TIMER_SHIFT 8
    #define MC_CH1_ARB_CTRLC_CL19_TIMER_MASK 0x0000F000
    #define MC_CH1_ARB_CTRLC_CL19_TIMER_SHIFT 12
#define  MC_CH1_ARB_LATENCY_TIMER_CTRLA 0x9250
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLA_CL0_LATENCY_TIMER_MASK 0x000000FF
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLA_CL0_LATENCY_TIMER_SHIFT 0
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLA_CL1_LATENCY_TIMER_MASK 0x0000FF00
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLA_CL1_LATENCY_TIMER_SHIFT 8
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLA_CL2_LATENCY_TIMER_MASK 0x00FF0000
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLA_CL2_LATENCY_TIMER_SHIFT 16
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLA_CL3_LATENCY_TIMER_MASK 0xFF000000
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLA_CL3_LATENCY_TIMER_SHIFT 24
#define  MC_CH1_ARB_LATENCY_TIMER_CTRLB 0x9254
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLB_CL4_LATENCY_TIMER_MASK 0x000000FF
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLB_CL4_LATENCY_TIMER_SHIFT 0
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLB_CL5_LATENCY_TIMER_MASK 0x0000FF00
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLB_CL5_LATENCY_TIMER_SHIFT 8
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLB_CL6_LATENCY_TIMER_MASK 0x00FF0000
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLB_CL6_LATENCY_TIMER_SHIFT 16
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLB_CL7_LATENCY_TIMER_MASK 0xFF000000
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLB_CL7_LATENCY_TIMER_SHIFT 24
#define  MC_CH1_ARB_LATENCY_TIMER_CTRLC 0x9258
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLC_CL8_LATENCY_TIMER_MASK 0x000000FF
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLC_CL8_LATENCY_TIMER_SHIFT 0
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLC_CL9_LATENCY_TIMER_MASK 0x0000FF00
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLC_CL9_LATENCY_TIMER_SHIFT 8
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLC_CL10_LATENCY_TIMER_MASK 0x00FF0000
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLC_CL10_LATENCY_TIMER_SHIFT 16
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLC_CL11_LATENCY_TIMER_MASK 0xFF000000
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLC_CL11_LATENCY_TIMER_SHIFT 24
#define  MC_CH1_ARB_LATENCY_TIMER_CTRLD 0x925C
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLD_CL12_LATENCY_TIMER_MASK 0x000000FF
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLD_CL12_LATENCY_TIMER_SHIFT 0
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLD_CL13_LATENCY_TIMER_MASK 0x0000FF00
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLD_CL13_LATENCY_TIMER_SHIFT 8
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLD_CL14_LATENCY_TIMER_MASK 0x00FF0000
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLD_CL14_LATENCY_TIMER_SHIFT 16
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLD_CL15_LATENCY_TIMER_MASK 0xFF000000
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLD_CL15_LATENCY_TIMER_SHIFT 24
#define  MC_CH1_ARB_LATENCY_TIMER_CTRLE 0x9260
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLE_CL16_LATENCY_TIMER_MASK 0x000000FF
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLE_CL16_LATENCY_TIMER_SHIFT 0
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLE_CL17_LATENCY_TIMER_MASK 0x0000FF00
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLE_CL17_LATENCY_TIMER_SHIFT 8
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLE_CL18_LATENCY_TIMER_MASK 0x00FF0000
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLE_CL18_LATENCY_TIMER_SHIFT 16
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLE_CL19_LATENCY_TIMER_MASK 0xFF000000
    #define MC_CH1_ARB_LATENCY_TIMER_CTRLE_CL19_LATENCY_TIMER_SHIFT 24
#define  MC_CH1_ARB_MAIN_CTRL 0x9270
    #define MC_CH1_ARB_MAIN_CTRL_LVL1_PRI_DIS_MASK 0x00000010
    #define MC_CH1_ARB_MAIN_CTRL_LVL1_PRI_DIS_SHIFT 4
    #define MC_CH1_ARB_MAIN_CTRL_URG_PRI_DIS_MASK 0x00000040
    #define MC_CH1_ARB_MAIN_CTRL_URG_PRI_DIS_SHIFT 6
    #define MC_CH1_ARB_MAIN_CTRL_LAT_PRI_DIS_MASK 0x00000080
    #define MC_CH1_ARB_MAIN_CTRL_LAT_PRI_DIS_SHIFT 7
    #define MC_CH1_ARB_MAIN_CTRL_CLI_URGENT_SET_MASK 0xFFFFF000
    #define MC_CH1_ARB_MAIN_CTRL_CLI_URGENT_SET_SHIFT 12
#define  MC_CH1_ARB_PAGE_TIMER_CTRLA 0x9240
    #define MC_CH1_ARB_PAGE_TIMER_CTRLA_CL0_PAGE_TIMER_MASK 0x0000000F
    #define MC_CH1_ARB_PAGE_TIMER_CTRLA_CL0_PAGE_TIMER_SHIFT 0
    #define MC_CH1_ARB_PAGE_TIMER_CTRLA_CL1_PAGE_TIMER_MASK 0x000000F0
    #define MC_CH1_ARB_PAGE_TIMER_CTRLA_CL1_PAGE_TIMER_SHIFT 4
    #define MC_CH1_ARB_PAGE_TIMER_CTRLA_CL2_PAGE_TIMER_MASK 0x00000F00
    #define MC_CH1_ARB_PAGE_TIMER_CTRLA_CL2_PAGE_TIMER_SHIFT 8
    #define MC_CH1_ARB_PAGE_TIMER_CTRLA_CL3_PAGE_TIMER_MASK 0x0000F000
    #define MC_CH1_ARB_PAGE_TIMER_CTRLA_CL3_PAGE_TIMER_SHIFT 12
    #define MC_CH1_ARB_PAGE_TIMER_CTRLA_CL4_PAGE_TIMER_MASK 0x000F0000
    #define MC_CH1_ARB_PAGE_TIMER_CTRLA_CL4_PAGE_TIMER_SHIFT 16
    #define MC_CH1_ARB_PAGE_TIMER_CTRLA_CL5_PAGE_TIMER_MASK 0x00F00000
    #define MC_CH1_ARB_PAGE_TIMER_CTRLA_CL5_PAGE_TIMER_SHIFT 20
    #define MC_CH1_ARB_PAGE_TIMER_CTRLA_CL6_PAGE_TIMER_MASK 0x0F000000
    #define MC_CH1_ARB_PAGE_TIMER_CTRLA_CL6_PAGE_TIMER_SHIFT 24
    #define MC_CH1_ARB_PAGE_TIMER_CTRLA_CL7_PAGE_TIMER_MASK 0xF0000000
    #define MC_CH1_ARB_PAGE_TIMER_CTRLA_CL7_PAGE_TIMER_SHIFT 28
#define  MC_CH1_ARB_PAGE_TIMER_CTRLB 0x9244
    #define MC_CH1_ARB_PAGE_TIMER_CTRLB_CL8_PAGE_TIMER_MASK 0x0000000F
    #define MC_CH1_ARB_PAGE_TIMER_CTRLB_CL8_PAGE_TIMER_SHIFT 0
    #define MC_CH1_ARB_PAGE_TIMER_CTRLB_CL9_PAGE_TIMER_MASK 0x000000F0
    #define MC_CH1_ARB_PAGE_TIMER_CTRLB_CL9_PAGE_TIMER_SHIFT 4
    #define MC_CH1_ARB_PAGE_TIMER_CTRLB_CL10_PAGE_TIMER_MASK 0x00000F00
    #define MC_CH1_ARB_PAGE_TIMER_CTRLB_CL10_PAGE_TIMER_SHIFT 8
    #define MC_CH1_ARB_PAGE_TIMER_CTRLB_CL11_PAGE_TIMER_MASK 0x0000F000
    #define MC_CH1_ARB_PAGE_TIMER_CTRLB_CL11_PAGE_TIMER_SHIFT 12
    #define MC_CH1_ARB_PAGE_TIMER_CTRLB_CL12_PAGE_TIMER_MASK 0x000F0000
    #define MC_CH1_ARB_PAGE_TIMER_CTRLB_CL12_PAGE_TIMER_SHIFT 16
    #define MC_CH1_ARB_PAGE_TIMER_CTRLB_CL13_PAGE_TIMER_MASK 0x00F00000
    #define MC_CH1_ARB_PAGE_TIMER_CTRLB_CL13_PAGE_TIMER_SHIFT 20
    #define MC_CH1_ARB_PAGE_TIMER_CTRLB_CL14_PAGE_TIMER_MASK 0x0F000000
    #define MC_CH1_ARB_PAGE_TIMER_CTRLB_CL14_PAGE_TIMER_SHIFT 24
    #define MC_CH1_ARB_PAGE_TIMER_CTRLB_CL15_PAGE_TIMER_MASK 0xF0000000
    #define MC_CH1_ARB_PAGE_TIMER_CTRLB_CL15_PAGE_TIMER_SHIFT 28
#define  MC_CH1_ARB_PAGE_TIMER_CTRLC 0x9248
    #define MC_CH1_ARB_PAGE_TIMER_CTRLC_CL16_PAGE_TIMER_MASK 0x0000000F
    #define MC_CH1_ARB_PAGE_TIMER_CTRLC_CL16_PAGE_TIMER_SHIFT 0
    #define MC_CH1_ARB_PAGE_TIMER_CTRLC_CL17_PAGE_TIMER_MASK 0x000000F0
    #define MC_CH1_ARB_PAGE_TIMER_CTRLC_CL17_PAGE_TIMER_SHIFT 4
    #define MC_CH1_ARB_PAGE_TIMER_CTRLC_CL18_PAGE_TIMER_MASK 0x00000F00
    #define MC_CH1_ARB_PAGE_TIMER_CTRLC_CL18_PAGE_TIMER_SHIFT 8
    #define MC_CH1_ARB_PAGE_TIMER_CTRLC_CL19_PAGE_TIMER_MASK 0x0000F000
    #define MC_CH1_ARB_PAGE_TIMER_CTRLC_CL19_PAGE_TIMER_SHIFT 12
#define  MC_CH1_ARB_PRIORITY_CTRLA 0x9274
    #define MC_CH1_ARB_PRIORITY_CTRLA_CL_DISABLE_LAT_PRIORITY_MASK 0x000FFFFF
    #define MC_CH1_ARB_PRIORITY_CTRLA_CL_DISABLE_LAT_PRIORITY_SHIFT 0
#define  MC_CH1_ARB_PRIORITY_CTRLB 0x9278
    #define MC_CH1_ARB_PRIORITY_CTRLB_CL_DISABLE_URG_PRIORITY_MASK 0x000FFFFF
    #define MC_CH1_ARB_PRIORITY_CTRLB_CL_DISABLE_URG_PRIORITY_SHIFT 0
#define  MC_CH1_LOCK_EN 0x9210
    #define MC_CH1_LOCK_EN_LOCK_CL_ID_MASK 0x001FFFFF
    #define MC_CH1_LOCK_EN_LOCK_CL_ID_SHIFT 0
#define  MC_CH1_MEM_CONFIG 0x9200
    #define MC_CH1_MEM_CONFIG_BANKPINS_MASK 0x00000003
    #define MC_CH1_MEM_CONFIG_BANKPINS_SHIFT 0
    #define MC_CH1_MEM_CONFIG_ADDRPINS_MASK 0x0000007C
    #define MC_CH1_MEM_CONFIG_ADDRPINS_SHIFT 2
    #define MC_CH1_MEM_CONFIG_COLCOUNT_MASK 0x00000F80
    #define MC_CH1_MEM_CONFIG_COLCOUNT_SHIFT 7
    #define MC_CH1_MEM_CONFIG_ROWBANKCOL_MASK 0x00001000
    #define MC_CH1_MEM_CONFIG_ROWBANKCOL_SHIFT 12
    #define MC_CH1_MEM_CONFIG_BSTLENGTH_MASK 0x00070000
    #define MC_CH1_MEM_CONFIG_BSTLENGTH_SHIFT 16
#define  MC_CH1_MISC_REG 0x9204
    #define MC_CH1_MISC_REG_MRLOGIC_RSTN_MASK 0x00000001
    #define MC_CH1_MISC_REG_MRLOGIC_RSTN_SHIFT 0
    #define MC_CH1_MISC_REG_MDLOGIC_RSTN_MASK 0x00000002
    #define MC_CH1_MISC_REG_MDLOGIC_RSTN_SHIFT 1
#define  MC_CH1_RD_LOCK_STATUS 0x9218
    #define MC_CH1_RD_LOCK_STATUS_READ_ATTEMPT_CL_ID_MASK 0x001FFFFF
    #define MC_CH1_RD_LOCK_STATUS_READ_ATTEMPT_CL_ID_SHIFT 0
#define  MC_CH1_WR_LOCK_STATUS 0x9214
    #define MC_CH1_WR_LOCK_STATUS_WRITE_ATTEMPT_CL_ID_MASK 0x001FFFFF
    #define MC_CH1_WR_LOCK_STATUS_WRITE_ATTEMPT_CL_ID_SHIFT 0
#define  MC_CH2_ARB_CTRLA 0x9330
    #define MC_CH2_ARB_CTRLA_CL0_TIMER_MASK 0x0000000F
    #define MC_CH2_ARB_CTRLA_CL0_TIMER_SHIFT 0
    #define MC_CH2_ARB_CTRLA_CL1_TIMER_MASK 0x000000F0
    #define MC_CH2_ARB_CTRLA_CL1_TIMER_SHIFT 4
    #define MC_CH2_ARB_CTRLA_CL2_TIMER_MASK 0x00000F00
    #define MC_CH2_ARB_CTRLA_CL2_TIMER_SHIFT 8
    #define MC_CH2_ARB_CTRLA_CL3_TIMER_MASK 0x0000F000
    #define MC_CH2_ARB_CTRLA_CL3_TIMER_SHIFT 12
    #define MC_CH2_ARB_CTRLA_CL4_TIMER_MASK 0x000F0000
    #define MC_CH2_ARB_CTRLA_CL4_TIMER_SHIFT 16
    #define MC_CH2_ARB_CTRLA_CL5_TIMER_MASK 0x00F00000
    #define MC_CH2_ARB_CTRLA_CL5_TIMER_SHIFT 20
    #define MC_CH2_ARB_CTRLA_CL6_TIMER_MASK 0x0F000000
    #define MC_CH2_ARB_CTRLA_CL6_TIMER_SHIFT 24
    #define MC_CH2_ARB_CTRLA_CL7_TIMER_MASK 0xF0000000
    #define MC_CH2_ARB_CTRLA_CL7_TIMER_SHIFT 28
#define  MC_CH2_ARB_CTRLB 0x9334
    #define MC_CH2_ARB_CTRLB_CL8_TIMER_MASK 0x0000000F
    #define MC_CH2_ARB_CTRLB_CL8_TIMER_SHIFT 0
    #define MC_CH2_ARB_CTRLB_CL9_TIMER_MASK 0x000000F0
    #define MC_CH2_ARB_CTRLB_CL9_TIMER_SHIFT 4
    #define MC_CH2_ARB_CTRLB_CL10_TIMER_MASK 0x00000F00
    #define MC_CH2_ARB_CTRLB_CL10_TIMER_SHIFT 8
    #define MC_CH2_ARB_CTRLB_CL11_TIMER_MASK 0x0000F000
    #define MC_CH2_ARB_CTRLB_CL11_TIMER_SHIFT 12
    #define MC_CH2_ARB_CTRLB_CL12_TIMER_MASK 0x000F0000
    #define MC_CH2_ARB_CTRLB_CL12_TIMER_SHIFT 16
    #define MC_CH2_ARB_CTRLB_CL13_TIMER_MASK 0x00F00000
    #define MC_CH2_ARB_CTRLB_CL13_TIMER_SHIFT 20
    #define MC_CH2_ARB_CTRLB_CL14_TIMER_MASK 0x0F000000
    #define MC_CH2_ARB_CTRLB_CL14_TIMER_SHIFT 24
    #define MC_CH2_ARB_CTRLB_CL15_TIMER_MASK 0xF0000000
    #define MC_CH2_ARB_CTRLB_CL15_TIMER_SHIFT 28
#define  MC_CH2_ARB_CTRLC 0x9338
    #define MC_CH2_ARB_CTRLC_CL16_TIMER_MASK 0x0000000F
    #define MC_CH2_ARB_CTRLC_CL16_TIMER_SHIFT 0
    #define MC_CH2_ARB_CTRLC_CL17_TIMER_MASK 0x000000F0
    #define MC_CH2_ARB_CTRLC_CL17_TIMER_SHIFT 4
    #define MC_CH2_ARB_CTRLC_CL18_TIMER_MASK 0x00000F00
    #define MC_CH2_ARB_CTRLC_CL18_TIMER_SHIFT 8
    #define MC_CH2_ARB_CTRLC_CL19_TIMER_MASK 0x0000F000
    #define MC_CH2_ARB_CTRLC_CL19_TIMER_SHIFT 12
#define  MC_CH2_ARB_LATENCY_TIMER_CTRLA 0x9350
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLA_CL0_LATENCY_TIMER_MASK 0x000000FF
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLA_CL0_LATENCY_TIMER_SHIFT 0
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLA_CL1_LATENCY_TIMER_MASK 0x0000FF00
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLA_CL1_LATENCY_TIMER_SHIFT 8
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLA_CL2_LATENCY_TIMER_MASK 0x00FF0000
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLA_CL2_LATENCY_TIMER_SHIFT 16
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLA_CL3_LATENCY_TIMER_MASK 0xFF000000
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLA_CL3_LATENCY_TIMER_SHIFT 24
#define  MC_CH2_ARB_LATENCY_TIMER_CTRLB 0x9354
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLB_CL4_LATENCY_TIMER_MASK 0x000000FF
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLB_CL4_LATENCY_TIMER_SHIFT 0
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLB_CL5_LATENCY_TIMER_MASK 0x0000FF00
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLB_CL5_LATENCY_TIMER_SHIFT 8
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLB_CL6_LATENCY_TIMER_MASK 0x00FF0000
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLB_CL6_LATENCY_TIMER_SHIFT 16
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLB_CL7_LATENCY_TIMER_MASK 0xFF000000
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLB_CL7_LATENCY_TIMER_SHIFT 24
#define  MC_CH2_ARB_LATENCY_TIMER_CTRLC 0x9358
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLC_CL8_LATENCY_TIMER_MASK 0x000000FF
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLC_CL8_LATENCY_TIMER_SHIFT 0
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLC_CL9_LATENCY_TIMER_MASK 0x0000FF00
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLC_CL9_LATENCY_TIMER_SHIFT 8
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLC_CL10_LATENCY_TIMER_MASK 0x00FF0000
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLC_CL10_LATENCY_TIMER_SHIFT 16
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLC_CL11_LATENCY_TIMER_MASK 0xFF000000
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLC_CL11_LATENCY_TIMER_SHIFT 24
#define  MC_CH2_ARB_LATENCY_TIMER_CTRLD 0x935C
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLD_CL12_LATENCY_TIMER_MASK 0x000000FF
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLD_CL12_LATENCY_TIMER_SHIFT 0
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLD_CL13_LATENCY_TIMER_MASK 0x0000FF00
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLD_CL13_LATENCY_TIMER_SHIFT 8
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLD_CL14_LATENCY_TIMER_MASK 0x00FF0000
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLD_CL14_LATENCY_TIMER_SHIFT 16
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLD_CL15_LATENCY_TIMER_MASK 0xFF000000
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLD_CL15_LATENCY_TIMER_SHIFT 24
#define  MC_CH2_ARB_LATENCY_TIMER_CTRLE 0x9360
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLE_CL16_LATENCY_TIMER_MASK 0x000000FF
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLE_CL16_LATENCY_TIMER_SHIFT 0
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLE_CL17_LATENCY_TIMER_MASK 0x0000FF00
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLE_CL17_LATENCY_TIMER_SHIFT 8
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLE_CL18_LATENCY_TIMER_MASK 0x00FF0000
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLE_CL18_LATENCY_TIMER_SHIFT 16
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLE_CL19_LATENCY_TIMER_MASK 0xFF000000
    #define MC_CH2_ARB_LATENCY_TIMER_CTRLE_CL19_LATENCY_TIMER_SHIFT 24
#define  MC_CH2_ARB_MAIN_CTRL 0x9370
    #define MC_CH2_ARB_MAIN_CTRL_LVL1_PRI_DIS_MASK 0x00000010
    #define MC_CH2_ARB_MAIN_CTRL_LVL1_PRI_DIS_SHIFT 4
    #define MC_CH2_ARB_MAIN_CTRL_URG_PRI_DIS_MASK 0x00000040
    #define MC_CH2_ARB_MAIN_CTRL_URG_PRI_DIS_SHIFT 6
    #define MC_CH2_ARB_MAIN_CTRL_LAT_PRI_DIS_MASK 0x00000080
    #define MC_CH2_ARB_MAIN_CTRL_LAT_PRI_DIS_SHIFT 7
    #define MC_CH2_ARB_MAIN_CTRL_CLI_URGENT_SET_MASK 0xFFFFF000
    #define MC_CH2_ARB_MAIN_CTRL_CLI_URGENT_SET_SHIFT 12
#define  MC_CH2_ARB_PAGE_TIMER_CTRLA 0x9340
    #define MC_CH2_ARB_PAGE_TIMER_CTRLA_CL0_PAGE_TIMER_MASK 0x0000000F
    #define MC_CH2_ARB_PAGE_TIMER_CTRLA_CL0_PAGE_TIMER_SHIFT 0
    #define MC_CH2_ARB_PAGE_TIMER_CTRLA_CL1_PAGE_TIMER_MASK 0x000000F0
    #define MC_CH2_ARB_PAGE_TIMER_CTRLA_CL1_PAGE_TIMER_SHIFT 4
    #define MC_CH2_ARB_PAGE_TIMER_CTRLA_CL2_PAGE_TIMER_MASK 0x00000F00
    #define MC_CH2_ARB_PAGE_TIMER_CTRLA_CL2_PAGE_TIMER_SHIFT 8
    #define MC_CH2_ARB_PAGE_TIMER_CTRLA_CL3_PAGE_TIMER_MASK 0x0000F000
    #define MC_CH2_ARB_PAGE_TIMER_CTRLA_CL3_PAGE_TIMER_SHIFT 12
    #define MC_CH2_ARB_PAGE_TIMER_CTRLA_CL4_PAGE_TIMER_MASK 0x000F0000
    #define MC_CH2_ARB_PAGE_TIMER_CTRLA_CL4_PAGE_TIMER_SHIFT 16
    #define MC_CH2_ARB_PAGE_TIMER_CTRLA_CL5_PAGE_TIMER_MASK 0x00F00000
    #define MC_CH2_ARB_PAGE_TIMER_CTRLA_CL5_PAGE_TIMER_SHIFT 20
    #define MC_CH2_ARB_PAGE_TIMER_CTRLA_CL6_PAGE_TIMER_MASK 0x0F000000
    #define MC_CH2_ARB_PAGE_TIMER_CTRLA_CL6_PAGE_TIMER_SHIFT 24
    #define MC_CH2_ARB_PAGE_TIMER_CTRLA_CL7_PAGE_TIMER_MASK 0xF0000000
    #define MC_CH2_ARB_PAGE_TIMER_CTRLA_CL7_PAGE_TIMER_SHIFT 28
#define  MC_CH2_ARB_PAGE_TIMER_CTRLB 0x9344
    #define MC_CH2_ARB_PAGE_TIMER_CTRLB_CL8_PAGE_TIMER_MASK 0x0000000F
    #define MC_CH2_ARB_PAGE_TIMER_CTRLB_CL8_PAGE_TIMER_SHIFT 0
    #define MC_CH2_ARB_PAGE_TIMER_CTRLB_CL9_PAGE_TIMER_MASK 0x000000F0
    #define MC_CH2_ARB_PAGE_TIMER_CTRLB_CL9_PAGE_TIMER_SHIFT 4
    #define MC_CH2_ARB_PAGE_TIMER_CTRLB_CL10_PAGE_TIMER_MASK 0x00000F00
    #define MC_CH2_ARB_PAGE_TIMER_CTRLB_CL10_PAGE_TIMER_SHIFT 8
    #define MC_CH2_ARB_PAGE_TIMER_CTRLB_CL11_PAGE_TIMER_MASK 0x0000F000
    #define MC_CH2_ARB_PAGE_TIMER_CTRLB_CL11_PAGE_TIMER_SHIFT 12
    #define MC_CH2_ARB_PAGE_TIMER_CTRLB_CL12_PAGE_TIMER_MASK 0x000F0000
    #define MC_CH2_ARB_PAGE_TIMER_CTRLB_CL12_PAGE_TIMER_SHIFT 16
    #define MC_CH2_ARB_PAGE_TIMER_CTRLB_CL13_PAGE_TIMER_MASK 0x00F00000
    #define MC_CH2_ARB_PAGE_TIMER_CTRLB_CL13_PAGE_TIMER_SHIFT 20
    #define MC_CH2_ARB_PAGE_TIMER_CTRLB_CL14_PAGE_TIMER_MASK 0x0F000000
    #define MC_CH2_ARB_PAGE_TIMER_CTRLB_CL14_PAGE_TIMER_SHIFT 24
    #define MC_CH2_ARB_PAGE_TIMER_CTRLB_CL15_PAGE_TIMER_MASK 0xF0000000
    #define MC_CH2_ARB_PAGE_TIMER_CTRLB_CL15_PAGE_TIMER_SHIFT 28
#define  MC_CH2_ARB_PAGE_TIMER_CTRLC 0x9348
    #define MC_CH2_ARB_PAGE_TIMER_CTRLC_CL16_PAGE_TIMER_MASK 0x0000000F
    #define MC_CH2_ARB_PAGE_TIMER_CTRLC_CL16_PAGE_TIMER_SHIFT 0
    #define MC_CH2_ARB_PAGE_TIMER_CTRLC_CL17_PAGE_TIMER_MASK 0x000000F0
    #define MC_CH2_ARB_PAGE_TIMER_CTRLC_CL17_PAGE_TIMER_SHIFT 4
    #define MC_CH2_ARB_PAGE_TIMER_CTRLC_CL18_PAGE_TIMER_MASK 0x00000F00
    #define MC_CH2_ARB_PAGE_TIMER_CTRLC_CL18_PAGE_TIMER_SHIFT 8
    #define MC_CH2_ARB_PAGE_TIMER_CTRLC_CL19_PAGE_TIMER_MASK 0x0000F000
    #define MC_CH2_ARB_PAGE_TIMER_CTRLC_CL19_PAGE_TIMER_SHIFT 12
#define  MC_CH2_ARB_PRIORITY_CTRLA 0x9374
    #define MC_CH2_ARB_PRIORITY_CTRLA_CL_DISABLE_LAT_PRIORITY_MASK 0x000FFFFF
    #define MC_CH2_ARB_PRIORITY_CTRLA_CL_DISABLE_LAT_PRIORITY_SHIFT 0
#define  MC_CH2_ARB_PRIORITY_CTRLB 0x9378
    #define MC_CH2_ARB_PRIORITY_CTRLB_CL_DISABLE_URG_PRIORITY_MASK 0x000FFFFF
    #define MC_CH2_ARB_PRIORITY_CTRLB_CL_DISABLE_URG_PRIORITY_SHIFT 0
#define  MC_CH2_LOCK_EN 0x9310
    #define MC_CH2_LOCK_EN_LOCK_CL_ID_MASK 0x001FFFFF
    #define MC_CH2_LOCK_EN_LOCK_CL_ID_SHIFT 0
#define  MC_CH2_MEM_CONFIG 0x9300
    #define MC_CH2_MEM_CONFIG_BANKPINS_MASK 0x00000003
    #define MC_CH2_MEM_CONFIG_BANKPINS_SHIFT 0
    #define MC_CH2_MEM_CONFIG_ADDRPINS_MASK 0x0000007C
    #define MC_CH2_MEM_CONFIG_ADDRPINS_SHIFT 2
    #define MC_CH2_MEM_CONFIG_COLCOUNT_MASK 0x00000F80
    #define MC_CH2_MEM_CONFIG_COLCOUNT_SHIFT 7
    #define MC_CH2_MEM_CONFIG_ROWBANKCOL_MASK 0x00001000
    #define MC_CH2_MEM_CONFIG_ROWBANKCOL_SHIFT 12
    #define MC_CH2_MEM_CONFIG_BSTLENGTH_MASK 0x00070000
    #define MC_CH2_MEM_CONFIG_BSTLENGTH_SHIFT 16
#define  MC_CH2_MISC_REG 0x9304
    #define MC_CH2_MISC_REG_MRLOGIC_RSTN_MASK 0x00000001
    #define MC_CH2_MISC_REG_MRLOGIC_RSTN_SHIFT 0
    #define MC_CH2_MISC_REG_MDLOGIC_RSTN_MASK 0x00000002
    #define MC_CH2_MISC_REG_MDLOGIC_RSTN_SHIFT 1
#define  MC_CH2_RD_LOCK_STATUS 0x9318
    #define MC_CH2_RD_LOCK_STATUS_READ_ATTEMPT_CL_ID_MASK 0x001FFFFF
    #define MC_CH2_RD_LOCK_STATUS_READ_ATTEMPT_CL_ID_SHIFT 0
#define  MC_CH2_WR_LOCK_STATUS 0x9314
    #define MC_CH2_WR_LOCK_STATUS_WRITE_ATTEMPT_CL_ID_MASK 0x001FFFFF
    #define MC_CH2_WR_LOCK_STATUS_WRITE_ATTEMPT_CL_ID_SHIFT 0
#define  MC_CONFIG_REG 0x9004
    #define CHANNELBIT_MASK 0x0000001F
    #define CHANNELBIT_SHIFT 0
    #define CHANNEL3_EN_MASK 0x00000100
    #define CHANNEL3_EN_SHIFT 8
    #define MC_CONFIG_REG_COLDIS_MASK 0x00001000
    #define MC_CONFIG_REG_COLDIS_SHIFT 12
    #define MC_CONFIG_REG_EXTMEMSIZE_MASK 0x00006000
    #define MC_CONFIG_REG_EXTMEMSIZE_SHIFT 13
#define  MC_DDRIO_CTRL 0x0800
    #define DDRIO_RESET_MASK 0x0000000F
    #define DDRIO_RESET_SHIFT 0
#define  MC_DDR_ACTIVATE_CNT 0x08D8
    #define ACTIVATE_CNT_MASK 0xFFFFFFFF
    #define ACTIVATE_CNT_SHIFT 0
#define  MC_DDR_CTRL0 0x0820
    #define INITREQ_MASK 0x00000001
    #define INITREQ_SHIFT 0
    #define DDRINITDONE_MASK 0x00000002
    #define DDRINITDONE_SHIFT 1
    #define SYNCDISABLE_MASK 0x00000004
    #define SYNCDISABLE_SHIFT 2
    #define WENVALUE_MASK 0x00000010
    #define WENVALUE_SHIFT 4
    #define CASNVALUE_MASK 0x00000020
    #define CASNVALUE_SHIFT 5
    #define RASNVALUE_MASK 0x00000040
    #define RASNVALUE_SHIFT 6
    #define CKEVALUE_MASK 0x00000080
    #define CKEVALUE_SHIFT 7
    #define CSNVALUE_MASK 0x00000100
    #define CSNVALUE_SHIFT 8
    #define BANKVALUE_MASK 0x00003000
    #define BANKVALUE_SHIFT 12
#define  MC_DDR_CTRL1 0x0824
    #define ADDRVALUE_MASK 0x00001FFF
    #define ADDRVALUE_SHIFT 0
    #define COUNTVALUE_MASK 0xFFFF0000
    #define COUNTVALUE_SHIFT 16
#define  MC_DDR_DATAACTIVE_CNT 0x08E8
    #define DATAACTIVE_CNT_MASK 0xFFFFFFFF
    #define DATAACTIVE_CNT_SHIFT 0
#define  MC_DDR_MONITOR_CTRL 0x08D0
    #define CLK_COUNT_MASK 0xFFFFFFFF
    #define CLK_COUNT_SHIFT 0
#define  MC_DDR_NOREQ_CNT 0x08D4
    #define NOREQ_CNT_MASK 0xFFFFFFFF
    #define NOREQ_CNT_SHIFT 0
#define  MC_DDR_READ_CNT 0x08E0
    #define READ_CNT_MASK 0xFFFFFFFF
    #define READ_CNT_SHIFT 0
#define  MC_DDR_STATUS 0x0828
    #define MC_DDR_STATUS_INITRDY_MASK 0x00000001
    #define MC_DDR_STATUS_INITRDY_SHIFT 0
#define  MC_DDR_TIMING0 0x0814
    #define TRASMIN_MASK 0x0000000F
    #define TRASMIN_SHIFT 0
    #define TRCDWMIN_MASK 0x000000F0
    #define TRCDWMIN_SHIFT 4
    #define TRCMIN_MASK 0x0000FF00
    #define TRCMIN_SHIFT 8
    #define TREFMAX_MASK 0xFFFF0000
    #define TREFMAX_SHIFT 16
#define  MC_DDR_TIMING1 0x0818
    #define TRFCMIN_MASK 0x000000FF
    #define TRFCMIN_SHIFT 0
    #define TRPMIN_MASK 0x00000F00
    #define TRPMIN_SHIFT 8
    #define TRRDMIN_MASK 0x0000F000
    #define TRRDMIN_SHIFT 12
    #define TWRMIN_MASK 0x000F0000
    #define TWRMIN_SHIFT 16
    #define TWTRMIN_MASK 0x00F00000
    #define TWTRMIN_SHIFT 20
    #define TPDXMIN_MASK 0x0F000000
    #define TPDXMIN_SHIFT 24
    #define TRCDRMIN_MASK 0xF0000000
    #define TRCDRMIN_SHIFT 28
#define  MC_DDR_TIMING2 0x081C
    #define WRLAT_MASK 0x0000000F
    #define WRLAT_SHIFT 0
    #define RDLAT_MASK 0x000000F0
    #define RDLAT_SHIFT 4
    #define RDHALFLAT_MASK 0x00000100
    #define RDHALFLAT_SHIFT 8
#define  MC_DDR_TIMING3 0x0808
    #define TXSRDMIN_MASK 0x0000FFFF
    #define TXSRDMIN_SHIFT 0
    #define TXSNRMIN_MASK 0x00FF0000
    #define TXSNRMIN_SHIFT 16
    #define TRCRMIN_MASK 0xFF000000
    #define TRCRMIN_SHIFT 24
#define  MC_DDR_TIMING4 0x080C
    #define TXS_PWRDWN_MASK 0x0000FFFF
    #define TXS_PWRDWN_SHIFT 0
    #define TXS_RESET_MASK 0xFFFF0000
    #define TXS_RESET_SHIFT 16
#define  MC_DDR_WRITE_CNT 0x08E4
    #define WRITE_CNT_MASK 0xFFFFFFFF
    #define WRITE_CNT_SHIFT 0
#define  MC_DQSDLL0_CTRL 0x0860
    #define MC_DQSDLL0_CTRL_PWD_MASK 0x00000001
    #define MC_DQSDLL0_CTRL_PWD_SHIFT 0
    #define MC_DQSDLL0_CTRL_RSTN_MASK 0x00000002
    #define MC_DQSDLL0_CTRL_RSTN_SHIFT 1
    #define MC_DQSDLL0_CTRL_KDLYUP_MASK 0x00000004
    #define MC_DQSDLL0_CTRL_KDLYUP_SHIFT 2
    #define MC_DQSDLL0_CTRL_KDLYDN_MASK 0x00000008
    #define MC_DQSDLL0_CTRL_KDLYDN_SHIFT 3
    #define MC_DQSDLL0_CTRL_CP2X_MASK 0x00000010
    #define MC_DQSDLL0_CTRL_CP2X_SHIFT 4
    #define MC_DQSDLL0_CTRL_CPHALF_MASK 0x00000020
    #define MC_DQSDLL0_CTRL_CPHALF_SHIFT 5
    #define MC_DQSDLL0_CTRL_ENERRDET_MASK 0x00000040
    #define MC_DQSDLL0_CTRL_ENERRDET_SHIFT 6
    #define MC_DQSDLL0_CTRL_SELFBIAS_MASK 0x00000080
    #define MC_DQSDLL0_CTRL_SELFBIAS_SHIFT 7
    #define MC_DQSDLL0_CTRL_ERRDETSEL_MASK 0x00000700
    #define MC_DQSDLL0_CTRL_ERRDETSEL_SHIFT 8
    #define MC_DQSDLL0_CTRL_DLYSELECT_MASK 0x0000F000
    #define MC_DQSDLL0_CTRL_DLYSELECT_SHIFT 12
    #define MC_DQSDLL0_CTRL_CPCTL_MASK 0x001F0000
    #define MC_DQSDLL0_CTRL_CPCTL_SHIFT 16
    #define MC_DQSDLL0_CTRL_DLYADJ_MASK 0x07000000
    #define MC_DQSDLL0_CTRL_DLYADJ_SHIFT 24
    #define MC_DQSDLL0_CTRL_DLYFBADJ_MASK 0x70000000
    #define MC_DQSDLL0_CTRL_DLYFBADJ_SHIFT 28
#define  MC_DQSDLL1_CTRL 0x0864
    #define MC_DQSDLL1_CTRL_PWD_MASK 0x00000001
    #define MC_DQSDLL1_CTRL_PWD_SHIFT 0
    #define MC_DQSDLL1_CTRL_RSTN_MASK 0x00000002
    #define MC_DQSDLL1_CTRL_RSTN_SHIFT 1
    #define MC_DQSDLL1_CTRL_KDLYUP_MASK 0x00000004
    #define MC_DQSDLL1_CTRL_KDLYUP_SHIFT 2
    #define MC_DQSDLL1_CTRL_KDLYDN_MASK 0x00000008
    #define MC_DQSDLL1_CTRL_KDLYDN_SHIFT 3
    #define MC_DQSDLL1_CTRL_CP2X_MASK 0x00000010
    #define MC_DQSDLL1_CTRL_CP2X_SHIFT 4
    #define MC_DQSDLL1_CTRL_CPHALF_MASK 0x00000020
    #define MC_DQSDLL1_CTRL_CPHALF_SHIFT 5
    #define MC_DQSDLL1_CTRL_ENERRDET_MASK 0x00000040
    #define MC_DQSDLL1_CTRL_ENERRDET_SHIFT 6
    #define MC_DQSDLL1_CTRL_SELFBIAS_MASK 0x00000080
    #define MC_DQSDLL1_CTRL_SELFBIAS_SHIFT 7
    #define MC_DQSDLL1_CTRL_ERRDETSEL_MASK 0x00000700
    #define MC_DQSDLL1_CTRL_ERRDETSEL_SHIFT 8
    #define MC_DQSDLL1_CTRL_DLYSELECT_MASK 0x0000F000
    #define MC_DQSDLL1_CTRL_DLYSELECT_SHIFT 12
    #define MC_DQSDLL1_CTRL_CPCTL_MASK 0x001F0000
    #define MC_DQSDLL1_CTRL_CPCTL_SHIFT 16
    #define MC_DQSDLL1_CTRL_DLYADJ_MASK 0x07000000
    #define MC_DQSDLL1_CTRL_DLYADJ_SHIFT 24
    #define MC_DQSDLL1_CTRL_DLYFBADJ_MASK 0x70000000
    #define MC_DQSDLL1_CTRL_DLYFBADJ_SHIFT 28
#define  MC_DQSDLL_MISC_CTRL 0x085C
    #define DLL0_MISC_MASK 0x000000FF
    #define DLL0_MISC_SHIFT 0
    #define DLL1_MISC_MASK 0x0000FF00
    #define DLL1_MISC_SHIFT 8
    #define DLL0_STROBEDLYSELECT_MASK 0x000F0000
    #define DLL0_STROBEDLYSELECT_SHIFT 16
    #define DLL1_STROBEDLYSELECT_MASK 0x00F00000
    #define DLL1_STROBEDLYSELECT_SHIFT 20
#define  MC_DQSDLL_STATUS0 0x0854
    #define DQSDLL0_CMPHIGH_MASK 0x00000001
    #define DQSDLL0_CMPHIGH_SHIFT 0
    #define DQSDLL1_CMPHIGH_MASK 0x00000002
    #define DQSDLL1_CMPHIGH_SHIFT 1
    #define DQSDLL0_CMPLOW_MASK 0x00000010
    #define DQSDLL0_CMPLOW_SHIFT 4
    #define DQSDLL1_CMPLOW_MASK 0x00000020
    #define DQSDLL1_CMPLOW_SHIFT 5
    #define DQSDLL0_WINDOWED_MASK 0x00000100
    #define DQSDLL0_WINDOWED_SHIFT 8
    #define DQSDLL1_WINDOWED_MASK 0x00000200
    #define DQSDLL1_WINDOWED_SHIFT 9
#define  MC_DUMMY_REG 0x9000
    #define MC_DUMMY_REG_REG_MASK 0xFFFFFFFF
    #define MC_DUMMY_REG_REG_SHIFT 0
#define  MC_LOCK_EN 0x9014
    #define MC_LOCK_EN_LOCK_CL_ID_MASK 0x001FFFFF
    #define MC_LOCK_EN_LOCK_CL_ID_SHIFT 0
    #define STICKY_RANGE_MASK 0x40000000
    #define STICKY_RANGE_SHIFT 30
    #define MC_LOCK_EN_ENCRYPT_EN_MASK 0x80000000
    #define MC_LOCK_EN_ENCRYPT_EN_SHIFT 31
#define  MC_LOCK_RANGE_END_0 0x08B4
    #define MC_LOCK_RANGE_END_0_VALUE_MASK 0x07FFF000
    #define MC_LOCK_RANGE_END_0_VALUE_SHIFT 12
#define  MC_LOCK_RANGE_END_1 0x08BC
    #define MC_LOCK_RANGE_END_1_VALUE_MASK 0x07FFF000
    #define MC_LOCK_RANGE_END_1_VALUE_SHIFT 12
#define  MC_LOCK_RANGE_START_0 0x08B0
    #define MC_LOCK_RANGE_START_0_VALUE_MASK 0x07FFF000
    #define MC_LOCK_RANGE_START_0_VALUE_SHIFT 12
#define  MC_LOCK_RANGE_START_1 0x08B8
    #define MC_LOCK_RANGE_START_1_VALUE_MASK 0x07FFF000
    #define MC_LOCK_RANGE_START_1_VALUE_SHIFT 12
#define  MC_MCLKDLL_CTRL 0x0880
    #define MC_MCLKDLL_CTRL_RSTN_MASK 0x00000002
    #define MC_MCLKDLL_CTRL_RSTN_SHIFT 1
    #define CLKSEL_MASK 0x00000C00
    #define CLKSEL_SHIFT 10
#define  MC_MEM_CONFIG 0x0810
    #define MC_MEM_CONFIG_BANKPINS_MASK 0x00000003
    #define MC_MEM_CONFIG_BANKPINS_SHIFT 0
    #define MC_MEM_CONFIG_ADDRPINS_MASK 0x0000007C
    #define MC_MEM_CONFIG_ADDRPINS_SHIFT 2
    #define MC_MEM_CONFIG_COLCOUNT_MASK 0x00001F00
    #define MC_MEM_CONFIG_COLCOUNT_SHIFT 8
    #define MC_MEM_CONFIG_COLDIS_MASK 0x00008000
    #define MC_MEM_CONFIG_COLDIS_SHIFT 15
    #define PRECHARGEBIT_MASK 0x001F0000
    #define PRECHARGEBIT_SHIFT 16
    #define ALLOWAP_MASK 0x00200000
    #define ALLOWAP_SHIFT 21
    #define ALLOWPWRDWN_MASK 0x00400000
    #define ALLOWPWRDWN_SHIFT 22
    #define NOWRINTERRUPT_MASK 0x00800000
    #define NOWRINTERRUPT_SHIFT 23
    #define MC_MEM_CONFIG_BSTLENGTH_MASK 0x07000000
    #define MC_MEM_CONFIG_BSTLENGTH_SHIFT 24
    #define MC_MEM_CONFIG_EXTMEMSIZE_MASK 0x30000000
    #define MC_MEM_CONFIG_EXTMEMSIZE_SHIFT 28
    #define ALLOWSELFRFRSH_MASK 0x40000000
    #define ALLOWSELFRFRSH_SHIFT 30
    #define SELFRFRSH_MODE_MASK 0x80000000
    #define SELFRFRSH_MODE_SHIFT 31
#define  MC_MISC_CTRL 0x0850
    #define LOCK_RANGE_EN0_MASK 0x00000010
    #define LOCK_RANGE_EN0_SHIFT 4
    #define LOCK_RANGE_EN1_MASK 0x00000020
    #define LOCK_RANGE_EN1_SHIFT 5
#define  MC_MISC_ERR 0x900C
    #define RING_WVLD_MASK 0x00000001
    #define RING_WVLD_SHIFT 0
    #define FB_OW_CH2_MASK 0x00000002
    #define FB_OW_CH2_SHIFT 1
#define  MC_MISC_REG 0x9008
    #define MC_MISC_REG_MRLOGIC_RSTN_MASK 0x00000001
    #define MC_MISC_REG_MRLOGIC_RSTN_SHIFT 0
    #define MC_MISC_REG_MDLOGIC_RSTN_MASK 0x00000002
    #define MC_MISC_REG_MDLOGIC_RSTN_SHIFT 1
#define  MC_MISC_STATUS 0x08C0
    #define WRITE_ATTEMPT_0_MASK 0x00000010
    #define WRITE_ATTEMPT_0_SHIFT 4
    #define WRITE_ATTEMPT_1_MASK 0x00000020
    #define WRITE_ATTEMPT_1_SHIFT 5
#define  MC_PAD_CTRL 0x0890
    #define FBVALIDINPD_MASK 0x00000002
    #define FBVALIDINPD_SHIFT 1
    #define FBVALIDOUTOE_MASK 0x00000004
    #define FBVALIDOUTOE_SHIFT 2
    #define CKEOE_MASK 0x00000008
    #define CKEOE_SHIFT 3
#define  MC_REGDAT 0x9054
    #define MCREQ_DATA_MASK 0xFFFFFFFF
    #define MCREQ_DATA_SHIFT 0
#define  MC_REGDAT_IDX 0x9058
    #define DATA_IDX_MASK 0x0000000F
    #define DATA_IDX_SHIFT 0
    #define MCREQ_BE_MASK 0x00000F00
    #define MCREQ_BE_SHIFT 8
    #define DATA_WOP_MASK 0x00001000
    #define DATA_WOP_SHIFT 12
#define  MC_REGREQ_CTRL 0x9050
    #define MCREQ_SIZE_MASK 0x00000003
    #define MCREQ_SIZE_SHIFT 0
    #define MCREQ_WOP_MASK 0x00000004
    #define MCREQ_WOP_SHIFT 2
    #define MCREQ_ADR_MASK 0x0FFFFFF8
    #define MCREQ_ADR_SHIFT 3
    #define MCREQ_URGENT_MASK 0x10000000
    #define MCREQ_URGENT_SHIFT 28
    #define MCREQ_TAG_MASK 0xE0000000
    #define MCREQ_TAG_SHIFT 29
#define  MC_REGREQ_STATUS 0x905C
    #define MCREQ_IDLE_MASK 0x00000001
    #define MCREQ_IDLE_SHIFT 0
    #define MCREQ_WTAG_MISMATCH_MASK 0x00000002
    #define MCREQ_WTAG_MISMATCH_SHIFT 1
    #define MCREQ_RTAG_MISMATCH_MASK 0x00000004
    #define MCREQ_RTAG_MISMATCH_SHIFT 2
#define  MC_SSTL_DRIVER 0x08F8
    #define CLOCK_DRV_SR_MASK 0x00000001
    #define CLOCK_DRV_SR_SHIFT 0
    #define CLOCK_DRV_PP1_MASK 0x00000002
    #define CLOCK_DRV_PP1_SHIFT 1
    #define CLOCK_DRV_PN1_MASK 0x00000004
    #define CLOCK_DRV_PN1_SHIFT 2
    #define CLOCK_DRV_E1_MASK 0x00000008
    #define CLOCK_DRV_E1_SHIFT 3
    #define CLOCK_DRV_PDB_MASK 0x00000010
    #define CLOCK_DRV_PDB_SHIFT 4
    #define CTRL_DRV_SR_MASK 0x00000100
    #define CTRL_DRV_SR_SHIFT 8
    #define CTRL_DRV_PP1_MASK 0x00000200
    #define CTRL_DRV_PP1_SHIFT 9
    #define CTRL_DRV_PN1_MASK 0x00000400
    #define CTRL_DRV_PN1_SHIFT 10
    #define CTRL_DRV_E1_MASK 0x00000800
    #define CTRL_DRV_E1_SHIFT 11
    #define CTRL_DRV_PDB_MASK 0x00001000
    #define CTRL_DRV_PDB_SHIFT 12
    #define WORD0_DRV_SR_MASK 0x00010000
    #define WORD0_DRV_SR_SHIFT 16
    #define WORD0_DRV_PP1_MASK 0x00020000
    #define WORD0_DRV_PP1_SHIFT 17
    #define WORD0_DRV_PN1_MASK 0x00040000
    #define WORD0_DRV_PN1_SHIFT 18
    #define WORD0_DRV_E1_MASK 0x00080000
    #define WORD0_DRV_E1_SHIFT 19
    #define WORD0_DRV_PDB_MASK 0x00100000
    #define WORD0_DRV_PDB_SHIFT 20
    #define WORD1_DRV_SR_MASK 0x01000000
    #define WORD1_DRV_SR_SHIFT 24
    #define WORD1_DRV_PP1_MASK 0x02000000
    #define WORD1_DRV_PP1_SHIFT 25
    #define WORD1_DRV_PN1_MASK 0x04000000
    #define WORD1_DRV_PN1_SHIFT 26
    #define WORD1_DRV_E1_MASK 0x08000000
    #define WORD1_DRV_E1_SHIFT 27
    #define WORD1_DRV_PDB_MASK 0x10000000
    #define WORD1_DRV_PDB_SHIFT 28
#define  MC_STATS_BW1 0x903C
    #define CLI_ID1_BW_MASK 0xFFFFFFFF
    #define CLI_ID1_BW_SHIFT 0
#define  MC_STATS_BW2 0x9040
    #define CLI_ID2_BW_MASK 0xFFFFFFFF
    #define CLI_ID2_BW_SHIFT 0
#define  MC_STATS_BW3 0x9044
    #define CLI_ID3_BW_MASK 0xFFFFFFFF
    #define CLI_ID3_BW_SHIFT 0
#define  MC_STATS_BW4 0x9048
    #define CLI_ID4_BW_MASK 0xFFFFFFFF
    #define CLI_ID4_BW_SHIFT 0
#define  MC_STATS_LATENCY1 0x9024
    #define CLI_ID1_LAT_MASK 0x00000FFF
    #define CLI_ID1_LAT_SHIFT 0
    #define CLI_ID2_LAT_MASK 0x0FFF0000
    #define CLI_ID2_LAT_SHIFT 16
#define  MC_STATS_LATENCY2 0x9028
    #define CLI_ID3_LAT_MASK 0x00000FFF
    #define CLI_ID3_LAT_SHIFT 0
    #define CLI_ID4_LAT_MASK 0x0FFF0000
    #define CLI_ID4_LAT_SHIFT 16
#define  MC_STATS_NUM_REQ1 0x902C
    #define CLI_ID1_NREQ_MASK 0xFFFFFFFF
    #define CLI_ID1_NREQ_SHIFT 0
#define  MC_STATS_NUM_REQ2 0x9030
    #define CLI_ID2_NREQ_MASK 0xFFFFFFFF
    #define CLI_ID2_NREQ_SHIFT 0
#define  MC_STATS_NUM_REQ3 0x9034
    #define CLI_ID3_NREQ_MASK 0xFFFFFFFF
    #define CLI_ID3_NREQ_SHIFT 0
#define  MC_STATS_NUM_REQ4 0x9038
    #define CLI_ID4_NREQ_MASK 0xFFFFFFFF
    #define CLI_ID4_NREQ_SHIFT 0
#define  MC_STATS_REG 0x9020
    #define CLI_ID1_MASK 0x0000001F
    #define CLI_ID1_SHIFT 0
    #define RESET_CLI1_MASK 0x00000020
    #define RESET_CLI1_SHIFT 5
    #define CLI_ID2_MASK 0x00001F00
    #define CLI_ID2_SHIFT 8
    #define RESET_CLI2_MASK 0x00002000
    #define RESET_CLI2_SHIFT 13
    #define CLI_ID3_MASK 0x001F0000
    #define CLI_ID3_SHIFT 16
    #define RESET_CLI3_MASK 0x00200000
    #define RESET_CLI3_SHIFT 21
    #define CLI_ID4_MASK 0x1F000000
    #define CLI_ID4_SHIFT 24
    #define RESET_CLI4_MASK 0x20000000
    #define RESET_CLI4_SHIFT 29
#define  MC_STATUS 0x9010
    #define MC_STATUS_INITRDY_MASK 0x00000001
    #define MC_STATUS_INITRDY_SHIFT 0
#define  MC_TEST_CMD_BE 0x0838
    #define MC_TEST_BE_MASK 0x000000FF
    #define MC_TEST_BE_SHIFT 0
    #define MC_TEST_ADDR_MASK 0x001FFF00
    #define MC_TEST_ADDR_SHIFT 8
    #define MC_TEST_CKE_MASK 0x00200000
    #define MC_TEST_CKE_SHIFT 21
    #define MC_TEST_BA_MASK 0x00C00000
    #define MC_TEST_BA_SHIFT 22
    #define MC_TEST_WEN_MASK 0x01000000
    #define MC_TEST_WEN_SHIFT 24
    #define MC_TEST_CASN_MASK 0x02000000
    #define MC_TEST_CASN_SHIFT 25
    #define MC_TEST_RASN_MASK 0x04000000
    #define MC_TEST_RASN_SHIFT 26
    #define MC_TEST_CSN_MASK 0x08000000
    #define MC_TEST_CSN_SHIFT 27
    #define MC_TEST_RE_MASK 0x10000000
    #define MC_TEST_RE_SHIFT 28
    #define MC_TEST_ROE_MASK 0x20000000
    #define MC_TEST_ROE_SHIFT 29
    #define MC_TEST_WE_MASK 0x40000000
    #define MC_TEST_WE_SHIFT 30
    #define MC_TEST_WOE_MASK 0x80000000
    #define MC_TEST_WOE_SHIFT 31
#define  MC_TEST_CTRL 0x082C
    #define MC_TEST_MODE_MASK 0x00000001
    #define MC_TEST_MODE_SHIFT 0
    #define MC_TEST_LENGTH_MASK 0x00000700
    #define MC_TEST_LENGTH_SHIFT 8
#define  MC_TEST_FIFO_CTRL 0x083C
    #define MC_FIFO_RDY_MASK 0x00000001
    #define MC_FIFO_RDY_SHIFT 0
    #define MC_FIFO_TYPE_MASK 0x00000030
    #define MC_FIFO_TYPE_SHIFT 4
#define  MC_TEST_LDATA 0x0830
    #define MC_TEST_LDATA_MASK 0xFFFFFFFF
    #define MC_TEST_LDATA_SHIFT 0
#define  MC_TEST_UDATA 0x0834
    #define MC_TEST_UDATA_MASK 0xFFFFFFFF
    #define MC_TEST_UDATA_SHIFT 0
#define  MC_UNLOCK_RANGE 0x9018
    #define START_ADDR_MASK 0x000000FF
    #define START_ADDR_SHIFT 0
    #define END_ADDR_MASK 0x0003FC00
    #define END_ADDR_SHIFT 10
#define  MGE0_INFO 0xA168
    #define MGE0_INFO_MVA_ADR_MASK 0x07FFFFFE
    #define MGE0_INFO_MVA_ADR_SHIFT 1
#define  MGE0_MVA_ADR 0xA11C
    #define MGE0_MVA_ADR_BASE_MASK 0x07FFFFF0
    #define MGE0_MVA_ADR_BASE_SHIFT 4
#define  MGE0_STATUS 0xA160
    #define MGE0_STATUS_DONE_MASK 0x04000000
    #define MGE0_STATUS_DONE_SHIFT 26
    #define MGE0_STATUS_ERROR_MASK 0xF0000000
    #define MGE0_STATUS_ERROR_SHIFT 28
#define  MGE0_TRIG 0xA164
    #define MGE0_TRIG_MB_TYPE_MASK 0x0000000F
    #define MGE0_TRIG_MB_TYPE_SHIFT 0
    #define MGE0_TRIG_MO_TYPE_MASK 0x00000030
    #define MGE0_TRIG_MO_TYPE_SHIFT 4
    #define MGE0_TRIG_MV_CNT_MASK 0x80000000
    #define MGE0_TRIG_MV_CNT_SHIFT 31
#define  MGE1_INFO 0xA568
    #define MGE1_INFO_MVA_ADR_MASK 0x07FFFFFE
    #define MGE1_INFO_MVA_ADR_SHIFT 1
#define  MGE1_MVA_ADR 0xA51C
    #define MGE1_MVA_ADR_BASE_MASK 0x07FFFFF0
    #define MGE1_MVA_ADR_BASE_SHIFT 4
#define  MGE1_STATUS 0xA560
    #define MGE1_STATUS_DONE_MASK 0x04000000
    #define MGE1_STATUS_DONE_SHIFT 26
    #define MGE1_STATUS_ERROR_MASK 0xF0000000
    #define MGE1_STATUS_ERROR_SHIFT 28
#define  MGE1_TRIG 0xA564
    #define MGE1_TRIG_MB_TYPE_MASK 0x0000000F
    #define MGE1_TRIG_MB_TYPE_SHIFT 0
    #define MGE1_TRIG_MO_TYPE_MASK 0x00000030
    #define MGE1_TRIG_MO_TYPE_SHIFT 4
    #define MGE1_TRIG_MV_CNT_MASK 0x80000000
    #define MGE1_TRIG_MV_CNT_SHIFT 31
#define  MIPS0_INTERRUPT 0x041C
    #define MIPS0_INTERRUPT_TSD_INT0_MASK 0x00000001
    #define MIPS0_INTERRUPT_TSD_INT0_SHIFT 0
    #define MIPS0_INTERRUPT_TSD_INT1_MASK 0x00000002
    #define MIPS0_INTERRUPT_TSD_INT1_SHIFT 1
    #define MIPS0_INTERRUPT_USBD_INT_MASK 0x00000004
    #define MIPS0_INTERRUPT_USBD_INT_SHIFT 2
    #define MIPS0_INTERRUPT_USBH_INT_MASK 0x00000008
    #define MIPS0_INTERRUPT_USBH_INT_SHIFT 3
    #define MIPS0_INTERRUPT_TSD_INT4_MASK 0x00000010
    #define MIPS0_INTERRUPT_TSD_INT4_SHIFT 4
    #define MIPS0_INTERRUPT_ETH0_INT_MASK 0x00000020
    #define MIPS0_INTERRUPT_ETH0_INT_SHIFT 5
    #define MIPS0_INTERRUPT_ETH1_INT_MASK 0x00000040
    #define MIPS0_INTERRUPT_ETH1_INT_SHIFT 6
    #define MIPS0_INTERRUPT_PPC_INT_MASK 0x00000080
    #define MIPS0_INTERRUPT_PPC_INT_SHIFT 7
    #define MIPS0_INTERRUPT_DMA_INT_MASK 0x00000100
    #define MIPS0_INTERRUPT_DMA_INT_SHIFT 8
    #define MIPS0_INTERRUPT_RBM_INT_MASK 0x00000200
    #define MIPS0_INTERRUPT_RBM_INT_SHIFT 9
    #define MIPS0_INTERRUPT_MPP_INT_MASK 0x00000400
    #define MIPS0_INTERRUPT_MPP_INT_SHIFT 10
    #define MIPS0_INTERRUPT_RSA_INT_MASK 0x00000800
    #define MIPS0_INTERRUPT_RSA_INT_SHIFT 11
    #define MIPS0_INTERRUPT_I2S_INT_MASK 0x00001000
    #define MIPS0_INTERRUPT_I2S_INT_SHIFT 12
    #define MIPS0_INTERRUPT_RMX_INT_MASK 0x00002000
    #define MIPS0_INTERRUPT_RMX_INT_SHIFT 13
    #define MIPS0_INTERRUPT_VHE_INT_MASK 0x00004000
    #define MIPS0_INTERRUPT_VHE_INT_SHIFT 14
    #define MIPS0_INTERRUPT_VFE_INT_MASK 0x00008000
    #define MIPS0_INTERRUPT_VFE_INT_SHIFT 15
    #define MIPS0_INTERRUPT_VNE_INT_MASK 0x00010000
    #define MIPS0_INTERRUPT_VNE_INT_SHIFT 16
    #define MIPS0_INTERRUPT_GVD_INT_MASK 0x00020000
    #define MIPS0_INTERRUPT_GVD_INT_SHIFT 17
    #define MIPS0_INTERRUPT_DVE_INT_MASK 0x00040000
    #define MIPS0_INTERRUPT_DVE_INT_SHIFT 18
    #define MIPS0_INTERRUPT_SATA_INT_MASK 0x00080000
    #define MIPS0_INTERRUPT_SATA_INT_SHIFT 19
    #define MIPS0_INTERRUPT_I2STX_INT_MASK 0x00100000
    #define MIPS0_INTERRUPT_I2STX_INT_SHIFT 20
    #define MIPS0_INTERRUPT_SPDIFRX_INT_MASK 0x00200000
    #define MIPS0_INTERRUPT_SPDIFRX_INT_SHIFT 21
    #define MIPS0_INTERRUPT_SPDIFTX_INT_MASK 0x00400000
    #define MIPS0_INTERRUPT_SPDIFTX_INT_SHIFT 22
    #define MIPS0_INTERRUPT_EDC_INT_MASK 0x00800000
    #define MIPS0_INTERRUPT_EDC_INT_SHIFT 23
    #define MIPS0_INTERRUPT_DSCL_INT_MASK 0x01000000
    #define MIPS0_INTERRUPT_DSCL_INT_SHIFT 24
    #define MIPS0_INTERRUPT_EE_INT_MASK 0x02000000
    #define MIPS0_INTERRUPT_EE_INT_SHIFT 25
#define  MIPS0_INTERRUPT_MASK 0x0420
    #define MIPS0_INTERRUPT_MASK_TSD_INT0_MASK 0x00000001
    #define MIPS0_INTERRUPT_MASK_TSD_INT0_SHIFT 0
    #define MIPS0_INTERRUPT_MASK_TSD_INT1_MASK 0x00000002
    #define MIPS0_INTERRUPT_MASK_TSD_INT1_SHIFT 1
    #define MIPS0_INTERRUPT_MASK_USBD_INT_MASK 0x00000004
    #define MIPS0_INTERRUPT_MASK_USBD_INT_SHIFT 2
    #define MIPS0_INTERRUPT_MASK_USBH_INT_MASK 0x00000008
    #define MIPS0_INTERRUPT_MASK_USBH_INT_SHIFT 3
    #define MIPS0_INTERRUPT_MASK_TSD_INT4_MASK 0x00000010
    #define MIPS0_INTERRUPT_MASK_TSD_INT4_SHIFT 4
    #define MIPS0_INTERRUPT_MASK_ETH0_INT_MASK 0x00000020
    #define MIPS0_INTERRUPT_MASK_ETH0_INT_SHIFT 5
    #define MIPS0_INTERRUPT_MASK_ETH1_INT_MASK 0x00000040
    #define MIPS0_INTERRUPT_MASK_ETH1_INT_SHIFT 6
    #define MIPS0_INTERRUPT_MASK_PPC_INT_MASK 0x00000080
    #define MIPS0_INTERRUPT_MASK_PPC_INT_SHIFT 7
    #define MIPS0_INTERRUPT_MASK_DMA_INT_MASK 0x00000100
    #define MIPS0_INTERRUPT_MASK_DMA_INT_SHIFT 8
    #define MIPS0_INTERRUPT_MASK_RBM_INT_MASK 0x00000200
    #define MIPS0_INTERRUPT_MASK_RBM_INT_SHIFT 9
    #define MIPS0_INTERRUPT_MASK_MPP_INT_MASK 0x00000400
    #define MIPS0_INTERRUPT_MASK_MPP_INT_SHIFT 10
    #define MIPS0_INTERRUPT_MASK_RSA_INT_MASK 0x00000800
    #define MIPS0_INTERRUPT_MASK_RSA_INT_SHIFT 11
    #define MIPS0_INTERRUPT_MASK_I2S_INT_MASK 0x00001000
    #define MIPS0_INTERRUPT_MASK_I2S_INT_SHIFT 12
    #define MIPS0_INTERRUPT_MASK_RMX_INT_MASK 0x00002000
    #define MIPS0_INTERRUPT_MASK_RMX_INT_SHIFT 13
    #define MIPS0_INTERRUPT_MASK_VHE_INT_MASK 0x00004000
    #define MIPS0_INTERRUPT_MASK_VHE_INT_SHIFT 14
    #define MIPS0_INTERRUPT_MASK_VFE_INT_MASK 0x00008000
    #define MIPS0_INTERRUPT_MASK_VFE_INT_SHIFT 15
    #define MIPS0_INTERRUPT_MASK_VNE_INT_MASK 0x00010000
    #define MIPS0_INTERRUPT_MASK_VNE_INT_SHIFT 16
    #define MIPS0_INTERRUPT_MASK_GVD_INT_MASK 0x00020000
    #define MIPS0_INTERRUPT_MASK_GVD_INT_SHIFT 17
    #define MIPS0_INTERRUPT_MASK_DVE_INT_MASK 0x00040000
    #define MIPS0_INTERRUPT_MASK_DVE_INT_SHIFT 18
    #define MIPS0_INTERRUPT_MASK_SATA_INT_MASK 0x00080000
    #define MIPS0_INTERRUPT_MASK_SATA_INT_SHIFT 19
    #define MIPS0_INTERRUPT_MASK_I2STX_INT_MASK 0x00100000
    #define MIPS0_INTERRUPT_MASK_I2STX_INT_SHIFT 20
    #define MIPS0_INTERRUPT_MASK_SPDIFRX_INT_MASK 0x00200000
    #define MIPS0_INTERRUPT_MASK_SPDIFRX_INT_SHIFT 21
    #define MIPS0_INTERRUPT_MASK_SPDIFTX_INT_MASK 0x00400000
    #define MIPS0_INTERRUPT_MASK_SPDIFTX_INT_SHIFT 22
    #define MIPS0_INTERRUPT_MASK_EDC_INT_MASK 0x00800000
    #define MIPS0_INTERRUPT_MASK_EDC_INT_SHIFT 23
    #define MIPS0_INTERRUPT_MASK_DSCL_INT_MASK 0x01000000
    #define MIPS0_INTERRUPT_MASK_DSCL_INT_SHIFT 24
    #define MIPS0_INTERRUPT_MASK_EE_INT_MASK 0x02000000
    #define MIPS0_INTERRUPT_MASK_EE_INT_SHIFT 25
#define  MIPS1_INTERRUPT 0x0424
    #define MIPS1_INTERRUPT_TSD_INT0_MASK 0x00000001
    #define MIPS1_INTERRUPT_TSD_INT0_SHIFT 0
    #define MIPS1_INTERRUPT_TSD_INT1_MASK 0x00000002
    #define MIPS1_INTERRUPT_TSD_INT1_SHIFT 1
    #define MIPS1_INTERRUPT_USBD_INT_MASK 0x00000004
    #define MIPS1_INTERRUPT_USBD_INT_SHIFT 2
    #define MIPS1_INTERRUPT_USBH_INT_MASK 0x00000008
    #define MIPS1_INTERRUPT_USBH_INT_SHIFT 3
    #define MIPS1_INTERRUPT_TSD_INT4_MASK 0x00000010
    #define MIPS1_INTERRUPT_TSD_INT4_SHIFT 4
    #define MIPS1_INTERRUPT_ETH0_INT_MASK 0x00000020
    #define MIPS1_INTERRUPT_ETH0_INT_SHIFT 5
    #define MIPS1_INTERRUPT_ETH1_INT_MASK 0x00000040
    #define MIPS1_INTERRUPT_ETH1_INT_SHIFT 6
    #define MIPS1_INTERRUPT_PPC_INT_MASK 0x00000080
    #define MIPS1_INTERRUPT_PPC_INT_SHIFT 7
    #define MIPS1_INTERRUPT_DMA_INT_MASK 0x00000100
    #define MIPS1_INTERRUPT_DMA_INT_SHIFT 8
    #define MIPS1_INTERRUPT_RBM_INT_MASK 0x00000200
    #define MIPS1_INTERRUPT_RBM_INT_SHIFT 9
    #define MIPS1_INTERRUPT_MPP_INT_MASK 0x00000400
    #define MIPS1_INTERRUPT_MPP_INT_SHIFT 10
    #define MIPS1_INTERRUPT_RSA_INT_MASK 0x00000800
    #define MIPS1_INTERRUPT_RSA_INT_SHIFT 11
    #define MIPS1_INTERRUPT_I2S_INT_MASK 0x00001000
    #define MIPS1_INTERRUPT_I2S_INT_SHIFT 12
    #define MIPS1_INTERRUPT_RMX_INT_MASK 0x00002000
    #define MIPS1_INTERRUPT_RMX_INT_SHIFT 13
    #define MIPS1_INTERRUPT_VHE_INT_MASK 0x00004000
    #define MIPS1_INTERRUPT_VHE_INT_SHIFT 14
    #define MIPS1_INTERRUPT_VFE_INT_MASK 0x00008000
    #define MIPS1_INTERRUPT_VFE_INT_SHIFT 15
    #define MIPS1_INTERRUPT_VNE_INT_MASK 0x00010000
    #define MIPS1_INTERRUPT_VNE_INT_SHIFT 16
    #define MIPS1_INTERRUPT_GVD_INT_MASK 0x00020000
    #define MIPS1_INTERRUPT_GVD_INT_SHIFT 17
    #define MIPS1_INTERRUPT_DVE_INT_MASK 0x00040000
    #define MIPS1_INTERRUPT_DVE_INT_SHIFT 18
    #define MIPS1_INTERRUPT_SATA_INT_MASK 0x00080000
    #define MIPS1_INTERRUPT_SATA_INT_SHIFT 19
    #define MIPS1_INTERRUPT_I2STX_INT_MASK 0x00100000
    #define MIPS1_INTERRUPT_I2STX_INT_SHIFT 20
    #define MIPS1_INTERRUPT_SPDIFRX_INT_MASK 0x00200000
    #define MIPS1_INTERRUPT_SPDIFRX_INT_SHIFT 21
    #define MIPS1_INTERRUPT_SPDIFTX_INT_MASK 0x00400000
    #define MIPS1_INTERRUPT_SPDIFTX_INT_SHIFT 22
    #define MIPS1_INTERRUPT_EDC_INT_MASK 0x00800000
    #define MIPS1_INTERRUPT_EDC_INT_SHIFT 23
    #define MIPS1_INTERRUPT_DSCL_INT_MASK 0x01000000
    #define MIPS1_INTERRUPT_DSCL_INT_SHIFT 24
    #define MIPS1_INTERRUPT_EE_INT_MASK 0x02000000
    #define MIPS1_INTERRUPT_EE_INT_SHIFT 25
#define  MIPS1_INTERRUPT_MASK 0x0428
    #define MIPS1_INTERRUPT_MASK_TSD_INT0_MASK 0x00000001
    #define MIPS1_INTERRUPT_MASK_TSD_INT0_SHIFT 0
    #define MIPS1_INTERRUPT_MASK_TSD_INT1_MASK 0x00000002
    #define MIPS1_INTERRUPT_MASK_TSD_INT1_SHIFT 1
    #define MIPS1_INTERRUPT_MASK_USBD_INT_MASK 0x00000004
    #define MIPS1_INTERRUPT_MASK_USBD_INT_SHIFT 2
    #define MIPS1_INTERRUPT_MASK_USBH_INT_MASK 0x00000008
    #define MIPS1_INTERRUPT_MASK_USBH_INT_SHIFT 3
    #define MIPS1_INTERRUPT_MASK_TSD_INT4_MASK 0x00000010
    #define MIPS1_INTERRUPT_MASK_TSD_INT4_SHIFT 4
    #define MIPS1_INTERRUPT_MASK_ETH0_INT_MASK 0x00000020
    #define MIPS1_INTERRUPT_MASK_ETH0_INT_SHIFT 5
    #define MIPS1_INTERRUPT_MASK_ETH1_INT_MASK 0x00000040
    #define MIPS1_INTERRUPT_MASK_ETH1_INT_SHIFT 6
    #define MIPS1_INTERRUPT_MASK_PPC_INT_MASK 0x00000080
    #define MIPS1_INTERRUPT_MASK_PPC_INT_SHIFT 7
    #define MIPS1_INTERRUPT_MASK_DMA_INT_MASK 0x00000100
    #define MIPS1_INTERRUPT_MASK_DMA_INT_SHIFT 8
    #define MIPS1_INTERRUPT_MASK_RBM_INT_MASK 0x00000200
    #define MIPS1_INTERRUPT_MASK_RBM_INT_SHIFT 9
    #define MIPS1_INTERRUPT_MASK_MPP_INT_MASK 0x00000400
    #define MIPS1_INTERRUPT_MASK_MPP_INT_SHIFT 10
    #define MIPS1_INTERRUPT_MASK_RSA_INT_MASK 0x00000800
    #define MIPS1_INTERRUPT_MASK_RSA_INT_SHIFT 11
    #define MIPS1_INTERRUPT_MASK_I2S_INT_MASK 0x00001000
    #define MIPS1_INTERRUPT_MASK_I2S_INT_SHIFT 12
    #define MIPS1_INTERRUPT_MASK_RMX_INT_MASK 0x00002000
    #define MIPS1_INTERRUPT_MASK_RMX_INT_SHIFT 13
    #define MIPS1_INTERRUPT_MASK_VHE_INT_MASK 0x00004000
    #define MIPS1_INTERRUPT_MASK_VHE_INT_SHIFT 14
    #define MIPS1_INTERRUPT_MASK_VFE_INT_MASK 0x00008000
    #define MIPS1_INTERRUPT_MASK_VFE_INT_SHIFT 15
    #define MIPS1_INTERRUPT_MASK_VNE_INT_MASK 0x00010000
    #define MIPS1_INTERRUPT_MASK_VNE_INT_SHIFT 16
    #define MIPS1_INTERRUPT_MASK_GVD_INT_MASK 0x00020000
    #define MIPS1_INTERRUPT_MASK_GVD_INT_SHIFT 17
    #define MIPS1_INTERRUPT_MASK_DVE_INT_MASK 0x00040000
    #define MIPS1_INTERRUPT_MASK_DVE_INT_SHIFT 18
    #define MIPS1_INTERRUPT_MASK_SATA_INT_MASK 0x00080000
    #define MIPS1_INTERRUPT_MASK_SATA_INT_SHIFT 19
    #define MIPS1_INTERRUPT_MASK_I2STX_INT_MASK 0x00100000
    #define MIPS1_INTERRUPT_MASK_I2STX_INT_SHIFT 20
    #define MIPS1_INTERRUPT_MASK_SPDIFRX_INT_MASK 0x00200000
    #define MIPS1_INTERRUPT_MASK_SPDIFRX_INT_SHIFT 21
    #define MIPS1_INTERRUPT_MASK_SPDIFTX_INT_MASK 0x00400000
    #define MIPS1_INTERRUPT_MASK_SPDIFTX_INT_SHIFT 22
    #define MIPS1_INTERRUPT_MASK_EDC_INT_MASK 0x00800000
    #define MIPS1_INTERRUPT_MASK_EDC_INT_SHIFT 23
    #define MIPS1_INTERRUPT_MASK_DSCL_INT_MASK 0x01000000
    #define MIPS1_INTERRUPT_MASK_DSCL_INT_SHIFT 24
    #define MIPS1_INTERRUPT_MASK_EE_INT_MASK 0x02000000
    #define MIPS1_INTERRUPT_MASK_EE_INT_SHIFT 25
#define  MIPS2_DBG_INBOUND 0x3860
    #define MIPS2_DBG_INBOUND_DATA_MASK 0xFFFFFFFF
    #define MIPS2_DBG_INBOUND_DATA_SHIFT 0
#define  MIPS2_DBG_OUTBOUND 0x3864
    #define MIPS2_DBG_OUTBOUND_DATA_MASK 0xFFFFFFFF
    #define MIPS2_DBG_OUTBOUND_DATA_SHIFT 0
#define  MIPS2_DUMMY_REG 0x38FC
    #define MIPS2_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define MIPS2_DUMMY_REG_DATA_SHIFT 0
#define  MIPS2_FB_TOP 0x3800
    #define MIPS2_FB_TOP_BASE_MASK 0x07FFFC00
    #define MIPS2_FB_TOP_BASE_SHIFT 10
#define  MIPS2_HOST_INT_MASK 0x38E4
    #define MIPS2_HOST_INT_MASK_INT_EN_OUTBOUND_CALL0_MASK 0x00000001
    #define MIPS2_HOST_INT_MASK_INT_EN_OUTBOUND_CALL0_SHIFT 0
    #define MIPS2_HOST_INT_MASK_INT_EN_OUTBOUND_CALL1_MASK 0x00000002
    #define MIPS2_HOST_INT_MASK_INT_EN_OUTBOUND_CALL1_SHIFT 1
    #define MIPS2_HOST_INT_MASK_INT_EN_OUTBOUND_DBG_MASK 0x00000004
    #define MIPS2_HOST_INT_MASK_INT_EN_OUTBOUND_DBG_SHIFT 2
    #define INT_EN_MIPS2_HANG_MASK 0x80000000
    #define INT_EN_MIPS2_HANG_SHIFT 31
#define  MIPS2_HOST_INT_STATUS 0x38E0
    #define MIPS2_HOST_INT_STATUS_OUTBOUND_CALL0_MASK 0x00000001
    #define MIPS2_HOST_INT_STATUS_OUTBOUND_CALL0_SHIFT 0
    #define MIPS2_HOST_INT_STATUS_OUTBOUND_CALL1_MASK 0x00000002
    #define MIPS2_HOST_INT_STATUS_OUTBOUND_CALL1_SHIFT 1
    #define MIPS2_HOST_INT_STATUS_OUTBOUND_DBG_MASK 0x00000004
    #define MIPS2_HOST_INT_STATUS_OUTBOUND_DBG_SHIFT 2
    #define MIPS2_HANG_MASK 0x80000000
    #define MIPS2_HANG_SHIFT 31
#define  MIPS2_INBOUND_CALL_0 0x3820
    #define MIPS2_INBOUND_CALL_0_DATA_MASK 0xFFFFFFFF
    #define MIPS2_INBOUND_CALL_0_DATA_SHIFT 0
#define  MIPS2_INBOUND_CALL_1 0x3824
    #define MIPS2_INBOUND_CALL_1_DATA_MASK 0xFFFFFFFF
    #define MIPS2_INBOUND_CALL_1_DATA_SHIFT 0
#define  MIPS2_INTERRUPT 0x042C
    #define MIPS2_INTERRUPT_TSD_INT0_MASK 0x00000001
    #define MIPS2_INTERRUPT_TSD_INT0_SHIFT 0
    #define MIPS2_INTERRUPT_TSD_INT1_MASK 0x00000002
    #define MIPS2_INTERRUPT_TSD_INT1_SHIFT 1
    #define MIPS2_INTERRUPT_USBD_INT_MASK 0x00000004
    #define MIPS2_INTERRUPT_USBD_INT_SHIFT 2
    #define MIPS2_INTERRUPT_USBH_INT_MASK 0x00000008
    #define MIPS2_INTERRUPT_USBH_INT_SHIFT 3
    #define MIPS2_INTERRUPT_TSD_INT4_MASK 0x00000010
    #define MIPS2_INTERRUPT_TSD_INT4_SHIFT 4
    #define MIPS2_INTERRUPT_ETH0_INT_MASK 0x00000020
    #define MIPS2_INTERRUPT_ETH0_INT_SHIFT 5
    #define MIPS2_INTERRUPT_ETH1_INT_MASK 0x00000040
    #define MIPS2_INTERRUPT_ETH1_INT_SHIFT 6
    #define MIPS2_INTERRUPT_PPC_INT_MASK 0x00000080
    #define MIPS2_INTERRUPT_PPC_INT_SHIFT 7
    #define MIPS2_INTERRUPT_DMA_INT_MASK 0x00000100
    #define MIPS2_INTERRUPT_DMA_INT_SHIFT 8
    #define MIPS2_INTERRUPT_RBM_INT_MASK 0x00000200
    #define MIPS2_INTERRUPT_RBM_INT_SHIFT 9
    #define MIPS2_INTERRUPT_MPP_INT_MASK 0x00000400
    #define MIPS2_INTERRUPT_MPP_INT_SHIFT 10
    #define MIPS2_INTERRUPT_RSA_INT_MASK 0x00000800
    #define MIPS2_INTERRUPT_RSA_INT_SHIFT 11
    #define MIPS2_INTERRUPT_I2S_INT_MASK 0x00001000
    #define MIPS2_INTERRUPT_I2S_INT_SHIFT 12
    #define MIPS2_INTERRUPT_RMX_INT_MASK 0x00002000
    #define MIPS2_INTERRUPT_RMX_INT_SHIFT 13
    #define MIPS2_INTERRUPT_VHE_INT_MASK 0x00004000
    #define MIPS2_INTERRUPT_VHE_INT_SHIFT 14
    #define MIPS2_INTERRUPT_VFE_INT_MASK 0x00008000
    #define MIPS2_INTERRUPT_VFE_INT_SHIFT 15
    #define MIPS2_INTERRUPT_VNE_INT_MASK 0x00010000
    #define MIPS2_INTERRUPT_VNE_INT_SHIFT 16
    #define MIPS2_INTERRUPT_GVD_INT_MASK 0x00020000
    #define MIPS2_INTERRUPT_GVD_INT_SHIFT 17
    #define MIPS2_INTERRUPT_DVE_INT_MASK 0x00040000
    #define MIPS2_INTERRUPT_DVE_INT_SHIFT 18
    #define MIPS2_INTERRUPT_SATA_INT_MASK 0x00080000
    #define MIPS2_INTERRUPT_SATA_INT_SHIFT 19
    #define MIPS2_INTERRUPT_I2STX_INT_MASK 0x00100000
    #define MIPS2_INTERRUPT_I2STX_INT_SHIFT 20
    #define MIPS2_INTERRUPT_SPDIFRX_INT_MASK 0x00200000
    #define MIPS2_INTERRUPT_SPDIFRX_INT_SHIFT 21
    #define MIPS2_INTERRUPT_SPDIFTX_INT_MASK 0x00400000
    #define MIPS2_INTERRUPT_SPDIFTX_INT_SHIFT 22
    #define MIPS2_INTERRUPT_EDC_INT_MASK 0x00800000
    #define MIPS2_INTERRUPT_EDC_INT_SHIFT 23
    #define MIPS2_INTERRUPT_DSCL_INT_MASK 0x01000000
    #define MIPS2_INTERRUPT_DSCL_INT_SHIFT 24
    #define MIPS2_INTERRUPT_EE_INT_MASK 0x02000000
    #define MIPS2_INTERRUPT_EE_INT_SHIFT 25
#define  MIPS2_INTERRUPT_MASK 0x0430
    #define MIPS2_INTERRUPT_MASK_TSD_INT0_MASK 0x00000001
    #define MIPS2_INTERRUPT_MASK_TSD_INT0_SHIFT 0
    #define MIPS2_INTERRUPT_MASK_TSD_INT1_MASK 0x00000002
    #define MIPS2_INTERRUPT_MASK_TSD_INT1_SHIFT 1
    #define MIPS2_INTERRUPT_MASK_USBD_INT_MASK 0x00000004
    #define MIPS2_INTERRUPT_MASK_USBD_INT_SHIFT 2
    #define MIPS2_INTERRUPT_MASK_USBH_INT_MASK 0x00000008
    #define MIPS2_INTERRUPT_MASK_USBH_INT_SHIFT 3
    #define MIPS2_INTERRUPT_MASK_TSD_INT4_MASK 0x00000010
    #define MIPS2_INTERRUPT_MASK_TSD_INT4_SHIFT 4
    #define MIPS2_INTERRUPT_MASK_ETH0_INT_MASK 0x00000020
    #define MIPS2_INTERRUPT_MASK_ETH0_INT_SHIFT 5
    #define MIPS2_INTERRUPT_MASK_ETH1_INT_MASK 0x00000040
    #define MIPS2_INTERRUPT_MASK_ETH1_INT_SHIFT 6
    #define MIPS2_INTERRUPT_MASK_PPC_INT_MASK 0x00000080
    #define MIPS2_INTERRUPT_MASK_PPC_INT_SHIFT 7
    #define MIPS2_INTERRUPT_MASK_DMA_INT_MASK 0x00000100
    #define MIPS2_INTERRUPT_MASK_DMA_INT_SHIFT 8
    #define MIPS2_INTERRUPT_MASK_RBM_INT_MASK 0x00000200
    #define MIPS2_INTERRUPT_MASK_RBM_INT_SHIFT 9
    #define MIPS2_INTERRUPT_MASK_MPP_INT_MASK 0x00000400
    #define MIPS2_INTERRUPT_MASK_MPP_INT_SHIFT 10
    #define MIPS2_INTERRUPT_MASK_RSA_INT_MASK 0x00000800
    #define MIPS2_INTERRUPT_MASK_RSA_INT_SHIFT 11
    #define MIPS2_INTERRUPT_MASK_I2S_INT_MASK 0x00001000
    #define MIPS2_INTERRUPT_MASK_I2S_INT_SHIFT 12
    #define MIPS2_INTERRUPT_MASK_RMX_INT_MASK 0x00002000
    #define MIPS2_INTERRUPT_MASK_RMX_INT_SHIFT 13
    #define MIPS2_INTERRUPT_MASK_VHE_INT_MASK 0x00004000
    #define MIPS2_INTERRUPT_MASK_VHE_INT_SHIFT 14
    #define MIPS2_INTERRUPT_MASK_VFE_INT_MASK 0x00008000
    #define MIPS2_INTERRUPT_MASK_VFE_INT_SHIFT 15
    #define MIPS2_INTERRUPT_MASK_VNE_INT_MASK 0x00010000
    #define MIPS2_INTERRUPT_MASK_VNE_INT_SHIFT 16
    #define MIPS2_INTERRUPT_MASK_GVD_INT_MASK 0x00020000
    #define MIPS2_INTERRUPT_MASK_GVD_INT_SHIFT 17
    #define MIPS2_INTERRUPT_MASK_DVE_INT_MASK 0x00040000
    #define MIPS2_INTERRUPT_MASK_DVE_INT_SHIFT 18
    #define MIPS2_INTERRUPT_MASK_SATA_INT_MASK 0x00080000
    #define MIPS2_INTERRUPT_MASK_SATA_INT_SHIFT 19
    #define MIPS2_INTERRUPT_MASK_I2STX_INT_MASK 0x00100000
    #define MIPS2_INTERRUPT_MASK_I2STX_INT_SHIFT 20
    #define MIPS2_INTERRUPT_MASK_SPDIFRX_INT_MASK 0x00200000
    #define MIPS2_INTERRUPT_MASK_SPDIFRX_INT_SHIFT 21
    #define MIPS2_INTERRUPT_MASK_SPDIFTX_INT_MASK 0x00400000
    #define MIPS2_INTERRUPT_MASK_SPDIFTX_INT_SHIFT 22
    #define MIPS2_INTERRUPT_MASK_EDC_INT_MASK 0x00800000
    #define MIPS2_INTERRUPT_MASK_EDC_INT_SHIFT 23
    #define MIPS2_INTERRUPT_MASK_DSCL_INT_MASK 0x01000000
    #define MIPS2_INTERRUPT_MASK_DSCL_INT_SHIFT 24
    #define MIPS2_INTERRUPT_MASK_EE_INT_MASK 0x02000000
    #define MIPS2_INTERRUPT_MASK_EE_INT_SHIFT 25
#define  MIPS2_IPC_CALL 0x38F0
    #define MIPS2_IPC_CALL_DATA_MASK 0xFFFFFFFF
    #define MIPS2_IPC_CALL_DATA_SHIFT 0
#define  MIPS2_MIPS_INT_MASK 0x38EC
    #define MIPS2_MIPS_INT_MASK_INT_EN_INBOUND_CALL0_MASK 0x00000001
    #define MIPS2_MIPS_INT_MASK_INT_EN_INBOUND_CALL0_SHIFT 0
    #define MIPS2_MIPS_INT_MASK_INT_EN_INBOUND_CALL1_MASK 0x00000002
    #define MIPS2_MIPS_INT_MASK_INT_EN_INBOUND_CALL1_SHIFT 1
    #define INT_EN_INBOUND_DBG_MASK 0x00000004
    #define INT_EN_INBOUND_DBG_SHIFT 2
    #define MIPS2_MIPS_INT_MASK_INT_EN_IPC_CALL_MASK 0x00000008
    #define MIPS2_MIPS_INT_MASK_INT_EN_IPC_CALL_SHIFT 3
#define  MIPS2_MIPS_INT_STATUS 0x38E8
    #define MIPS2_MIPS_INT_STATUS_INBOUND_CALL0_MASK 0x00000001
    #define MIPS2_MIPS_INT_STATUS_INBOUND_CALL0_SHIFT 0
    #define MIPS2_MIPS_INT_STATUS_INBOUND_CALL1_MASK 0x00000002
    #define MIPS2_MIPS_INT_STATUS_INBOUND_CALL1_SHIFT 1
    #define INBOUND_DBG_MASK 0x00000004
    #define INBOUND_DBG_SHIFT 2
    #define MIPS2_MIPS_INT_STATUS_IPC_CALL_MASK 0x00000008
    #define MIPS2_MIPS_INT_STATUS_IPC_CALL_SHIFT 3
#define  MIPS2_MISC_STATUS 0x3890
    #define SI_ERL_MASK 0x00000001
    #define SI_ERL_SHIFT 0
    #define EB_BLAST_MASK 0x00000002
    #define EB_BLAST_SHIFT 1
    #define EB_INSTR_MASK 0x00000004
    #define EB_INSTR_SHIFT 2
    #define SI_SLEEP_MASK 0x00000008
    #define SI_SLEEP_SHIFT 3
    #define SI_RP_MASK 0x00000010
    #define SI_RP_SHIFT 4
    #define SI_EXL_MASK 0x00000020
    #define SI_EXL_SHIFT 5
#define  MIPS2_MMREG_APER 0x3808
    #define MIPS2_MMREG_APER_BASE_MASK 0x00001FFF
    #define MIPS2_MMREG_APER_BASE_SHIFT 0
    #define MIPS2_MMREG_APER_SIZE_MASK 0x1FFF0000
    #define MIPS2_MMREG_APER_SIZE_SHIFT 16
#define  MIPS2_MSG_DATA_0 0x3830
    #define MIPS2_MSG_DATA_0_DATA_MASK 0xFFFFFFFF
    #define MIPS2_MSG_DATA_0_DATA_SHIFT 0
#define  MIPS2_MSG_DATA_1 0x3834
    #define MIPS2_MSG_DATA_1_DATA_MASK 0xFFFFFFFF
    #define MIPS2_MSG_DATA_1_DATA_SHIFT 0
#define  MIPS2_MSG_DATA_10 0x3858
    #define MIPS2_MSG_DATA_10_DATA_MASK 0xFFFFFFFF
    #define MIPS2_MSG_DATA_10_DATA_SHIFT 0
#define  MIPS2_MSG_DATA_11 0x385C
    #define MIPS2_MSG_DATA_11_DATA_MASK 0xFFFFFFFF
    #define MIPS2_MSG_DATA_11_DATA_SHIFT 0
#define  MIPS2_MSG_DATA_2 0x3838
    #define MIPS2_MSG_DATA_2_DATA_MASK 0xFFFFFFFF
    #define MIPS2_MSG_DATA_2_DATA_SHIFT 0
#define  MIPS2_MSG_DATA_3 0x383C
    #define MIPS2_MSG_DATA_3_DATA_MASK 0xFFFFFFFF
    #define MIPS2_MSG_DATA_3_DATA_SHIFT 0
#define  MIPS2_MSG_DATA_4 0x3840
    #define MIPS2_MSG_DATA_4_DATA_MASK 0xFFFFFFFF
    #define MIPS2_MSG_DATA_4_DATA_SHIFT 0
#define  MIPS2_MSG_DATA_5 0x3844
    #define MIPS2_MSG_DATA_5_DATA_MASK 0xFFFFFFFF
    #define MIPS2_MSG_DATA_5_DATA_SHIFT 0
#define  MIPS2_MSG_DATA_6 0x3848
    #define MIPS2_MSG_DATA_6_DATA_MASK 0xFFFFFFFF
    #define MIPS2_MSG_DATA_6_DATA_SHIFT 0
#define  MIPS2_MSG_DATA_7 0x384C
    #define MIPS2_MSG_DATA_7_DATA_MASK 0xFFFFFFFF
    #define MIPS2_MSG_DATA_7_DATA_SHIFT 0
#define  MIPS2_MSG_DATA_8 0x3850
    #define MIPS2_MSG_DATA_8_DATA_MASK 0xFFFFFFFF
    #define MIPS2_MSG_DATA_8_DATA_SHIFT 0
#define  MIPS2_MSG_DATA_9 0x3854
    #define MIPS2_MSG_DATA_9_DATA_MASK 0xFFFFFFFF
    #define MIPS2_MSG_DATA_9_DATA_SHIFT 0
#define  MIPS2_NMI_TRIG 0x3870
    #define MIPS2_NMI_TRIG_NODATA_MASK 0x00000001
    #define MIPS2_NMI_TRIG_NODATA_SHIFT 0
#define  MIPS2_OUTBOUND_CALL_0 0x3828
    #define MIPS2_OUTBOUND_CALL_0_DATA_MASK 0xFFFFFFFF
    #define MIPS2_OUTBOUND_CALL_0_DATA_SHIFT 0
#define  MIPS2_OUTBOUND_CALL_1 0x382C
    #define MIPS2_OUTBOUND_CALL_1_DATA_MASK 0xFFFFFFFF
    #define MIPS2_OUTBOUND_CALL_1_DATA_SHIFT 0
#define  MIPS2_PERF_CNTA_STAT 0x3888
    #define MIPS2_PERF_CNTA_STAT_DATA_MASK 0xFFFFFFFF
    #define MIPS2_PERF_CNTA_STAT_DATA_SHIFT 0
#define  MIPS2_PERF_CNTB_STAT 0x388C
    #define MIPS2_PERF_CNTB_STAT_DATA_MASK 0xFFFFFFFF
    #define MIPS2_PERF_CNTB_STAT_DATA_SHIFT 0
#define  MIPS2_RST 0x38F8
    #define MIPS2_RST_SOFT_RSTN_MASK 0x00000001
    #define MIPS2_RST_SOFT_RSTN_SHIFT 0
    #define HARD_RSTN_MASK 0x00000002
    #define HARD_RSTN_SHIFT 1
#define  MIPS2_SHADOW_IBB_CTRL 0x38B0
    #define MIPS2_SHADOW_IBB_CTRL_SHADOW_IBB_CTRL_MASK 0xFFFFFFFF
    #define MIPS2_SHADOW_IBB_CTRL_SHADOW_IBB_CTRL_SHIFT 0
#define  MIPS2_SHADOW_IBB_RB_ADR 0x38B8
    #define MIPS2_SHADOW_IBB_RB_ADR_SHADOW_IBB_RB_ADR_MASK 0xFFFFFFFF
    #define MIPS2_SHADOW_IBB_RB_ADR_SHADOW_IBB_RB_ADR_SHIFT 0
#define  MIPS2_SHADOW_IBB_RB_HEAD 0x38C8
    #define MIPS2_SHADOW_IBB_RB_HEAD_SHADOW_IBB_RB_HEAD_MASK 0xFFFFFFFF
    #define MIPS2_SHADOW_IBB_RB_HEAD_SHADOW_IBB_RB_HEAD_SHIFT 0
#define  MIPS2_SHADOW_IBB_RB_TAIL 0x38BC
    #define MIPS2_SHADOW_IBB_RB_TAIL_SHADOW_IBB_RB_TAIL_MASK 0xFFFFFFFF
    #define MIPS2_SHADOW_IBB_RB_TAIL_SHADOW_IBB_RB_TAIL_SHIFT 0
#define  MIPS2_SHADOW_IBB_RB_TAIL_READ 0x38C0
    #define MIPS2_SHADOW_IBB_RB_TAIL_READ_SHADOW_IBB_RB_TAIL_READ_MASK 0xFFFFFFFF
    #define MIPS2_SHADOW_IBB_RB_TAIL_READ_SHADOW_IBB_RB_TAIL_READ_SHIFT 0
#define  MIPS2_SPRAM_RM 0x3814
    #define IDATA_MASK 0x0000000F
    #define IDATA_SHIFT 0
    #define ITAG_MASK 0x000000F0
    #define ITAG_SHIFT 4
    #define DDATA_MASK 0x00000F00
    #define DDATA_SHIFT 8
    #define DTAG_MASK 0x0000F000
    #define DTAG_SHIFT 12
    #define DWS_MASK 0x0F000000
    #define DWS_SHIFT 24
    #define IWS_MASK 0xF0000000
    #define IWS_SHIFT 28
#define  MIPS2_STATIC_CONFIG 0x3810
    #define MIPS2_STATIC_CONFIG_ENDIAN_MASK 0x00000001
    #define MIPS2_STATIC_CONFIG_ENDIAN_SHIFT 0
    #define MERGE_MODE_MASK 0x00000006
    #define MERGE_MODE_SHIFT 1
    #define PERF_CNTA_MUX_MASK 0x000000F0
    #define PERF_CNTA_MUX_SHIFT 4
    #define PERF_CNTA_EN_MASK 0x00000100
    #define PERF_CNTA_EN_SHIFT 8
    #define PERF_CNTB_MUX_MASK 0x00001E00
    #define PERF_CNTB_MUX_SHIFT 9
    #define PERF_CNTB_EN_MASK 0x00002000
    #define PERF_CNTB_EN_SHIFT 13
    #define SPRAM_DELAY_MASK 0x00004000
    #define SPRAM_DELAY_SHIFT 14
    #define SIMPLEBE_MASK 0x00030000
    #define SIMPLEBE_SHIFT 16
#define  MIPS2_WATCHDOG_CNT 0x3880
    #define MIPS2_WATCHDOG_CNT_DATA_MASK 0xFFFFFFFF
    #define MIPS2_WATCHDOG_CNT_DATA_SHIFT 0
#define  MIPS2_WATCHDOG_COMPARE 0x3884
    #define MIPS2_WATCHDOG_COMPARE_DATA_MASK 0xFFFFFFFF
    #define MIPS2_WATCHDOG_COMPARE_DATA_SHIFT 0
#define  MIPS3_INTERRUPT 0x04D0
    #define MIPS3_INTERRUPT_TSD_INT0_MASK 0x00000001
    #define MIPS3_INTERRUPT_TSD_INT0_SHIFT 0
    #define MIPS3_INTERRUPT_TSD_INT1_MASK 0x00000002
    #define MIPS3_INTERRUPT_TSD_INT1_SHIFT 1
    #define MIPS3_INTERRUPT_USBD_INT_MASK 0x00000004
    #define MIPS3_INTERRUPT_USBD_INT_SHIFT 2
    #define MIPS3_INTERRUPT_USBH_INT_MASK 0x00000008
    #define MIPS3_INTERRUPT_USBH_INT_SHIFT 3
    #define MIPS3_INTERRUPT_TSD_INT4_MASK 0x00000010
    #define MIPS3_INTERRUPT_TSD_INT4_SHIFT 4
    #define MIPS3_INTERRUPT_ETH0_INT_MASK 0x00000020
    #define MIPS3_INTERRUPT_ETH0_INT_SHIFT 5
    #define MIPS3_INTERRUPT_ETH1_INT_MASK 0x00000040
    #define MIPS3_INTERRUPT_ETH1_INT_SHIFT 6
    #define MIPS3_INTERRUPT_PPC_INT_MASK 0x00000080
    #define MIPS3_INTERRUPT_PPC_INT_SHIFT 7
    #define MIPS3_INTERRUPT_DMA_INT_MASK 0x00000100
    #define MIPS3_INTERRUPT_DMA_INT_SHIFT 8
    #define MIPS3_INTERRUPT_RBM_INT_MASK 0x00000200
    #define MIPS3_INTERRUPT_RBM_INT_SHIFT 9
    #define MIPS3_INTERRUPT_MPP_INT_MASK 0x00000400
    #define MIPS3_INTERRUPT_MPP_INT_SHIFT 10
    #define MIPS3_INTERRUPT_RSA_INT_MASK 0x00000800
    #define MIPS3_INTERRUPT_RSA_INT_SHIFT 11
    #define MIPS3_INTERRUPT_I2S_INT_MASK 0x00001000
    #define MIPS3_INTERRUPT_I2S_INT_SHIFT 12
    #define MIPS3_INTERRUPT_RMX_INT_MASK 0x00002000
    #define MIPS3_INTERRUPT_RMX_INT_SHIFT 13
    #define MIPS3_INTERRUPT_VHE_INT_MASK 0x00004000
    #define MIPS3_INTERRUPT_VHE_INT_SHIFT 14
    #define MIPS3_INTERRUPT_VFE_INT_MASK 0x00008000
    #define MIPS3_INTERRUPT_VFE_INT_SHIFT 15
    #define MIPS3_INTERRUPT_VNE_INT_MASK 0x00010000
    #define MIPS3_INTERRUPT_VNE_INT_SHIFT 16
    #define MIPS3_INTERRUPT_GVD_INT_MASK 0x00020000
    #define MIPS3_INTERRUPT_GVD_INT_SHIFT 17
    #define MIPS3_INTERRUPT_DVE_INT_MASK 0x00040000
    #define MIPS3_INTERRUPT_DVE_INT_SHIFT 18
    #define MIPS3_INTERRUPT_SATA_INT_MASK 0x00080000
    #define MIPS3_INTERRUPT_SATA_INT_SHIFT 19
    #define MIPS3_INTERRUPT_I2STX_INT_MASK 0x00100000
    #define MIPS3_INTERRUPT_I2STX_INT_SHIFT 20
    #define MIPS3_INTERRUPT_SPDIFRX_INT_MASK 0x00200000
    #define MIPS3_INTERRUPT_SPDIFRX_INT_SHIFT 21
    #define MIPS3_INTERRUPT_SPDIFTX_INT_MASK 0x00400000
    #define MIPS3_INTERRUPT_SPDIFTX_INT_SHIFT 22
    #define MIPS3_INTERRUPT_EDC_INT_MASK 0x00800000
    #define MIPS3_INTERRUPT_EDC_INT_SHIFT 23
    #define MIPS3_INTERRUPT_DSCL_INT_MASK 0x01000000
    #define MIPS3_INTERRUPT_DSCL_INT_SHIFT 24
    #define MIPS3_INTERRUPT_EE_INT_MASK 0x02000000
    #define MIPS3_INTERRUPT_EE_INT_SHIFT 25
#define  MIPS3_INTERRUPT_MASK 0x04D4
    #define MIPS3_INTERRUPT_MASK_TSD_INT0_MASK 0x00000001
    #define MIPS3_INTERRUPT_MASK_TSD_INT0_SHIFT 0
    #define MIPS3_INTERRUPT_MASK_TSD_INT1_MASK 0x00000002
    #define MIPS3_INTERRUPT_MASK_TSD_INT1_SHIFT 1
    #define MIPS3_INTERRUPT_MASK_USBD_INT_MASK 0x00000004
    #define MIPS3_INTERRUPT_MASK_USBD_INT_SHIFT 2
    #define MIPS3_INTERRUPT_MASK_USBH_INT_MASK 0x00000008
    #define MIPS3_INTERRUPT_MASK_USBH_INT_SHIFT 3
    #define MIPS3_INTERRUPT_MASK_TSD_INT4_MASK 0x00000010
    #define MIPS3_INTERRUPT_MASK_TSD_INT4_SHIFT 4
    #define MIPS3_INTERRUPT_MASK_ETH0_INT_MASK 0x00000020
    #define MIPS3_INTERRUPT_MASK_ETH0_INT_SHIFT 5
    #define MIPS3_INTERRUPT_MASK_ETH1_INT_MASK 0x00000040
    #define MIPS3_INTERRUPT_MASK_ETH1_INT_SHIFT 6
    #define MIPS3_INTERRUPT_MASK_PPC_INT_MASK 0x00000080
    #define MIPS3_INTERRUPT_MASK_PPC_INT_SHIFT 7
    #define MIPS3_INTERRUPT_MASK_DMA_INT_MASK 0x00000100
    #define MIPS3_INTERRUPT_MASK_DMA_INT_SHIFT 8
    #define MIPS3_INTERRUPT_MASK_RBM_INT_MASK 0x00000200
    #define MIPS3_INTERRUPT_MASK_RBM_INT_SHIFT 9
    #define MIPS3_INTERRUPT_MASK_MPP_INT_MASK 0x00000400
    #define MIPS3_INTERRUPT_MASK_MPP_INT_SHIFT 10
    #define MIPS3_INTERRUPT_MASK_RSA_INT_MASK 0x00000800
    #define MIPS3_INTERRUPT_MASK_RSA_INT_SHIFT 11
    #define MIPS3_INTERRUPT_MASK_I2S_INT_MASK 0x00001000
    #define MIPS3_INTERRUPT_MASK_I2S_INT_SHIFT 12
    #define MIPS3_INTERRUPT_MASK_RMX_INT_MASK 0x00002000
    #define MIPS3_INTERRUPT_MASK_RMX_INT_SHIFT 13
    #define MIPS3_INTERRUPT_MASK_VHE_INT_MASK 0x00004000
    #define MIPS3_INTERRUPT_MASK_VHE_INT_SHIFT 14
    #define MIPS3_INTERRUPT_MASK_VFE_INT_MASK 0x00008000
    #define MIPS3_INTERRUPT_MASK_VFE_INT_SHIFT 15
    #define MIPS3_INTERRUPT_MASK_VNE_INT_MASK 0x00010000
    #define MIPS3_INTERRUPT_MASK_VNE_INT_SHIFT 16
    #define MIPS3_INTERRUPT_MASK_GVD_INT_MASK 0x00020000
    #define MIPS3_INTERRUPT_MASK_GVD_INT_SHIFT 17
    #define MIPS3_INTERRUPT_MASK_DVE_INT_MASK 0x00040000
    #define MIPS3_INTERRUPT_MASK_DVE_INT_SHIFT 18
    #define MIPS3_INTERRUPT_MASK_SATA_INT_MASK 0x00080000
    #define MIPS3_INTERRUPT_MASK_SATA_INT_SHIFT 19
    #define MIPS3_INTERRUPT_MASK_I2STX_INT_MASK 0x00100000
    #define MIPS3_INTERRUPT_MASK_I2STX_INT_SHIFT 20
    #define MIPS3_INTERRUPT_MASK_SPDIFRX_INT_MASK 0x00200000
    #define MIPS3_INTERRUPT_MASK_SPDIFRX_INT_SHIFT 21
    #define MIPS3_INTERRUPT_MASK_SPDIFTX_INT_MASK 0x00400000
    #define MIPS3_INTERRUPT_MASK_SPDIFTX_INT_SHIFT 22
    #define MIPS3_INTERRUPT_MASK_EDC_INT_MASK 0x00800000
    #define MIPS3_INTERRUPT_MASK_EDC_INT_SHIFT 23
    #define MIPS3_INTERRUPT_MASK_DSCL_INT_MASK 0x01000000
    #define MIPS3_INTERRUPT_MASK_DSCL_INT_SHIFT 24
    #define MIPS3_INTERRUPT_MASK_EE_INT_MASK 0x02000000
    #define MIPS3_INTERRUPT_MASK_EE_INT_SHIFT 25
#define  MIPS4_INTERRUPT 0x04D8
    #define MIPS4_INTERRUPT_TSD_INT0_MASK 0x00000001
    #define MIPS4_INTERRUPT_TSD_INT0_SHIFT 0
    #define MIPS4_INTERRUPT_TSD_INT1_MASK 0x00000002
    #define MIPS4_INTERRUPT_TSD_INT1_SHIFT 1
    #define MIPS4_INTERRUPT_USBD_INT_MASK 0x00000004
    #define MIPS4_INTERRUPT_USBD_INT_SHIFT 2
    #define MIPS4_INTERRUPT_USBH_INT_MASK 0x00000008
    #define MIPS4_INTERRUPT_USBH_INT_SHIFT 3
    #define MIPS4_INTERRUPT_TSD_INT4_MASK 0x00000010
    #define MIPS4_INTERRUPT_TSD_INT4_SHIFT 4
    #define MIPS4_INTERRUPT_ETH0_INT_MASK 0x00000020
    #define MIPS4_INTERRUPT_ETH0_INT_SHIFT 5
    #define MIPS4_INTERRUPT_ETH1_INT_MASK 0x00000040
    #define MIPS4_INTERRUPT_ETH1_INT_SHIFT 6
    #define MIPS4_INTERRUPT_PPC_INT_MASK 0x00000080
    #define MIPS4_INTERRUPT_PPC_INT_SHIFT 7
    #define MIPS4_INTERRUPT_DMA_INT_MASK 0x00000100
    #define MIPS4_INTERRUPT_DMA_INT_SHIFT 8
    #define MIPS4_INTERRUPT_RBM_INT_MASK 0x00000200
    #define MIPS4_INTERRUPT_RBM_INT_SHIFT 9
    #define MIPS4_INTERRUPT_MPP_INT_MASK 0x00000400
    #define MIPS4_INTERRUPT_MPP_INT_SHIFT 10
    #define MIPS4_INTERRUPT_RSA_INT_MASK 0x00000800
    #define MIPS4_INTERRUPT_RSA_INT_SHIFT 11
    #define MIPS4_INTERRUPT_I2S_INT_MASK 0x00001000
    #define MIPS4_INTERRUPT_I2S_INT_SHIFT 12
    #define MIPS4_INTERRUPT_RMX_INT_MASK 0x00002000
    #define MIPS4_INTERRUPT_RMX_INT_SHIFT 13
    #define MIPS4_INTERRUPT_VHE_INT_MASK 0x00004000
    #define MIPS4_INTERRUPT_VHE_INT_SHIFT 14
    #define MIPS4_INTERRUPT_VFE_INT_MASK 0x00008000
    #define MIPS4_INTERRUPT_VFE_INT_SHIFT 15
    #define MIPS4_INTERRUPT_VNE_INT_MASK 0x00010000
    #define MIPS4_INTERRUPT_VNE_INT_SHIFT 16
    #define MIPS4_INTERRUPT_GVD_INT_MASK 0x00020000
    #define MIPS4_INTERRUPT_GVD_INT_SHIFT 17
    #define MIPS4_INTERRUPT_DVE_INT_MASK 0x00040000
    #define MIPS4_INTERRUPT_DVE_INT_SHIFT 18
    #define MIPS4_INTERRUPT_SATA_INT_MASK 0x00080000
    #define MIPS4_INTERRUPT_SATA_INT_SHIFT 19
    #define MIPS4_INTERRUPT_I2STX_INT_MASK 0x00100000
    #define MIPS4_INTERRUPT_I2STX_INT_SHIFT 20
    #define MIPS4_INTERRUPT_SPDIFRX_INT_MASK 0x00200000
    #define MIPS4_INTERRUPT_SPDIFRX_INT_SHIFT 21
    #define MIPS4_INTERRUPT_SPDIFTX_INT_MASK 0x00400000
    #define MIPS4_INTERRUPT_SPDIFTX_INT_SHIFT 22
    #define MIPS4_INTERRUPT_EDC_INT_MASK 0x00800000
    #define MIPS4_INTERRUPT_EDC_INT_SHIFT 23
    #define MIPS4_INTERRUPT_DSCL_INT_MASK 0x01000000
    #define MIPS4_INTERRUPT_DSCL_INT_SHIFT 24
    #define MIPS4_INTERRUPT_EE_INT_MASK 0x02000000
    #define MIPS4_INTERRUPT_EE_INT_SHIFT 25
    #define MIPS4_INTERRUPT_NFC_INT_MASK 0x04000000
	#define MIPS4_INTERRUPT_NFC_INT_SHIFT 26	
#define  MIPS4_INTERRUPT_MASK 0x04DC
    #define MIPS4_INTERRUPT_MASK_TSD_INT0_MASK 0x00000001
    #define MIPS4_INTERRUPT_MASK_TSD_INT0_SHIFT 0
    #define MIPS4_INTERRUPT_MASK_TSD_INT1_MASK 0x00000002
    #define MIPS4_INTERRUPT_MASK_TSD_INT1_SHIFT 1
    #define MIPS4_INTERRUPT_MASK_USBD_INT_MASK 0x00000004
    #define MIPS4_INTERRUPT_MASK_USBD_INT_SHIFT 2
    #define MIPS4_INTERRUPT_MASK_USBH_INT_MASK 0x00000008
    #define MIPS4_INTERRUPT_MASK_USBH_INT_SHIFT 3
    #define MIPS4_INTERRUPT_MASK_TSD_INT4_MASK 0x00000010
    #define MIPS4_INTERRUPT_MASK_TSD_INT4_SHIFT 4
    #define MIPS4_INTERRUPT_MASK_ETH0_INT_MASK 0x00000020
    #define MIPS4_INTERRUPT_MASK_ETH0_INT_SHIFT 5
    #define MIPS4_INTERRUPT_MASK_ETH1_INT_MASK 0x00000040
    #define MIPS4_INTERRUPT_MASK_ETH1_INT_SHIFT 6
    #define MIPS4_INTERRUPT_MASK_PPC_INT_MASK 0x00000080
    #define MIPS4_INTERRUPT_MASK_PPC_INT_SHIFT 7
    #define MIPS4_INTERRUPT_MASK_DMA_INT_MASK 0x00000100
    #define MIPS4_INTERRUPT_MASK_DMA_INT_SHIFT 8
    #define MIPS4_INTERRUPT_MASK_RBM_INT_MASK 0x00000200
    #define MIPS4_INTERRUPT_MASK_RBM_INT_SHIFT 9
    #define MIPS4_INTERRUPT_MASK_MPP_INT_MASK 0x00000400
    #define MIPS4_INTERRUPT_MASK_MPP_INT_SHIFT 10
    #define MIPS4_INTERRUPT_MASK_RSA_INT_MASK 0x00000800
    #define MIPS4_INTERRUPT_MASK_RSA_INT_SHIFT 11
    #define MIPS4_INTERRUPT_MASK_I2S_INT_MASK 0x00001000
    #define MIPS4_INTERRUPT_MASK_I2S_INT_SHIFT 12
    #define MIPS4_INTERRUPT_MASK_RMX_INT_MASK 0x00002000
    #define MIPS4_INTERRUPT_MASK_RMX_INT_SHIFT 13
    #define MIPS4_INTERRUPT_MASK_VHE_INT_MASK 0x00004000
    #define MIPS4_INTERRUPT_MASK_VHE_INT_SHIFT 14
    #define MIPS4_INTERRUPT_MASK_VFE_INT_MASK 0x00008000
    #define MIPS4_INTERRUPT_MASK_VFE_INT_SHIFT 15
    #define MIPS4_INTERRUPT_MASK_VNE_INT_MASK 0x00010000
    #define MIPS4_INTERRUPT_MASK_VNE_INT_SHIFT 16
    #define MIPS4_INTERRUPT_MASK_GVD_INT_MASK 0x00020000
    #define MIPS4_INTERRUPT_MASK_GVD_INT_SHIFT 17
    #define MIPS4_INTERRUPT_MASK_DVE_INT_MASK 0x00040000
    #define MIPS4_INTERRUPT_MASK_DVE_INT_SHIFT 18
    #define MIPS4_INTERRUPT_MASK_SATA_INT_MASK 0x00080000
    #define MIPS4_INTERRUPT_MASK_SATA_INT_SHIFT 19
    #define MIPS4_INTERRUPT_MASK_I2STX_INT_MASK 0x00100000
    #define MIPS4_INTERRUPT_MASK_I2STX_INT_SHIFT 20
    #define MIPS4_INTERRUPT_MASK_SPDIFRX_INT_MASK 0x00200000
    #define MIPS4_INTERRUPT_MASK_SPDIFRX_INT_SHIFT 21
    #define MIPS4_INTERRUPT_MASK_SPDIFTX_INT_MASK 0x00400000
    #define MIPS4_INTERRUPT_MASK_SPDIFTX_INT_SHIFT 22
    #define MIPS4_INTERRUPT_MASK_EDC_INT_MASK 0x00800000
    #define MIPS4_INTERRUPT_MASK_EDC_INT_SHIFT 23
    #define MIPS4_INTERRUPT_MASK_DSCL_INT_MASK 0x01000000
    #define MIPS4_INTERRUPT_MASK_DSCL_INT_SHIFT 24
    #define MIPS4_INTERRUPT_MASK_EE_INT_MASK 0x02000000
    #define MIPS4_INTERRUPT_MASK_EE_INT_SHIFT 25
    #define MIPS4_INTERRUPT_MASK_NFC_INT_MASK 0x04000000
	#define MIPS4_INTERRUPT_MASK_NFC_INT_SHIFT 26	
#define  MIPS_INTERLOCK0 0x0440
    #define MIPS_INTERLOCK0_ID_MASK 0x000000FF
    #define MIPS_INTERLOCK0_ID_SHIFT 0
    #define MIPS_INTERLOCK0_LOCK_MASK 0x80000000
    #define MIPS_INTERLOCK0_LOCK_SHIFT 31
#define  MIPS_INTERLOCK1 0x0444
    #define MIPS_INTERLOCK1_ID_MASK 0x000000FF
    #define MIPS_INTERLOCK1_ID_SHIFT 0
    #define MIPS_INTERLOCK1_LOCK_MASK 0x80000000
    #define MIPS_INTERLOCK1_LOCK_SHIFT 31
#define  MIPS_INTERLOCK10 0x04B8
    #define MIPS_INTERLOCK10_ID_MASK 0x000000FF
    #define MIPS_INTERLOCK10_ID_SHIFT 0
    #define MIPS_INTERLOCK10_LOCK_MASK 0x80000000
    #define MIPS_INTERLOCK10_LOCK_SHIFT 31
#define  MIPS_INTERLOCK11 0x04BC
    #define MIPS_INTERLOCK11_ID_MASK 0x000000FF
    #define MIPS_INTERLOCK11_ID_SHIFT 0
    #define MIPS_INTERLOCK11_LOCK_MASK 0x80000000
    #define MIPS_INTERLOCK11_LOCK_SHIFT 31
#define  MIPS_INTERLOCK12 0x04C0
    #define MIPS_INTERLOCK12_ID_MASK 0x000000FF
    #define MIPS_INTERLOCK12_ID_SHIFT 0
    #define MIPS_INTERLOCK12_LOCK_MASK 0x80000000
    #define MIPS_INTERLOCK12_LOCK_SHIFT 31
#define  MIPS_INTERLOCK13 0x04C4
    #define MIPS_INTERLOCK13_ID_MASK 0x000000FF
    #define MIPS_INTERLOCK13_ID_SHIFT 0
    #define MIPS_INTERLOCK13_LOCK_MASK 0x80000000
    #define MIPS_INTERLOCK13_LOCK_SHIFT 31
#define  MIPS_INTERLOCK14 0x04C8
    #define MIPS_INTERLOCK14_ID_MASK 0x000000FF
    #define MIPS_INTERLOCK14_ID_SHIFT 0
    #define MIPS_INTERLOCK14_LOCK_MASK 0x80000000
    #define MIPS_INTERLOCK14_LOCK_SHIFT 31
#define  MIPS_INTERLOCK15 0x04CC
    #define MIPS_INTERLOCK15_ID_MASK 0x000000FF
    #define MIPS_INTERLOCK15_ID_SHIFT 0
    #define MIPS_INTERLOCK15_LOCK_MASK 0x80000000
    #define MIPS_INTERLOCK15_LOCK_SHIFT 31
#define  MIPS_INTERLOCK2 0x0448
    #define MIPS_INTERLOCK2_ID_MASK 0x000000FF
    #define MIPS_INTERLOCK2_ID_SHIFT 0
    #define MIPS_INTERLOCK2_LOCK_MASK 0x80000000
    #define MIPS_INTERLOCK2_LOCK_SHIFT 31
#define  MIPS_INTERLOCK3 0x044C
    #define MIPS_INTERLOCK3_ID_MASK 0x000000FF
    #define MIPS_INTERLOCK3_ID_SHIFT 0
    #define MIPS_INTERLOCK3_LOCK_MASK 0x80000000
    #define MIPS_INTERLOCK3_LOCK_SHIFT 31
#define  MIPS_INTERLOCK4 0x0450
    #define MIPS_INTERLOCK4_ID_MASK 0x000000FF
    #define MIPS_INTERLOCK4_ID_SHIFT 0
    #define MIPS_INTERLOCK4_LOCK_MASK 0x80000000
    #define MIPS_INTERLOCK4_LOCK_SHIFT 31
#define  MIPS_INTERLOCK5 0x0454
    #define MIPS_INTERLOCK5_ID_MASK 0x000000FF
    #define MIPS_INTERLOCK5_ID_SHIFT 0
    #define MIPS_INTERLOCK5_LOCK_MASK 0x80000000
    #define MIPS_INTERLOCK5_LOCK_SHIFT 31
#define  MIPS_INTERLOCK6 0x0458
    #define MIPS_INTERLOCK6_ID_MASK 0x000000FF
    #define MIPS_INTERLOCK6_ID_SHIFT 0
    #define MIPS_INTERLOCK6_LOCK_MASK 0x80000000
    #define MIPS_INTERLOCK6_LOCK_SHIFT 31
#define  MIPS_INTERLOCK7 0x045C
    #define MIPS_INTERLOCK7_ID_MASK 0x000000FF
    #define MIPS_INTERLOCK7_ID_SHIFT 0
    #define MIPS_INTERLOCK7_LOCK_MASK 0x80000000
    #define MIPS_INTERLOCK7_LOCK_SHIFT 31
#define  MIPS_INTERLOCK8 0x04B0
    #define MIPS_INTERLOCK8_ID_MASK 0x000000FF
    #define MIPS_INTERLOCK8_ID_SHIFT 0
    #define MIPS_INTERLOCK8_LOCK_MASK 0x80000000
    #define MIPS_INTERLOCK8_LOCK_SHIFT 31
#define  MIPS_INTERLOCK9 0x04B4
    #define MIPS_INTERLOCK9_ID_MASK 0x000000FF
    #define MIPS_INTERLOCK9_ID_SHIFT 0
    #define MIPS_INTERLOCK9_LOCK_MASK 0x80000000
    #define MIPS_INTERLOCK9_LOCK_SHIFT 31
#define  MPP_INT_TRIG 0x72D0
    #define MPP_INT_TRIG_NODATA_MASK 0x00000001
    #define MPP_INT_TRIG_NODATA_SHIFT 0
#define  MPP_STATUS 0x7260
    #define EVENTBUF_FREECNT_MASK 0x0000001F
    #define EVENTBUF_FREECNT_SHIFT 0
    #define DZQ_REGBUSY_MASK 0x00000100
    #define DZQ_REGBUSY_SHIFT 8
    #define DZQ_BUSY_MASK 0x00000200
    #define DZQ_BUSY_SHIFT 9
    #define IDCT_REGBUSY_MASK 0x00000400
    #define IDCT_REGBUSY_SHIFT 10
    #define IDCT_BUSY_MASK 0x00000800
    #define IDCT_BUSY_SHIFT 11
    #define MSC_BUSY_MASK 0x00001000
    #define MSC_BUSY_SHIFT 12
    #define SCL_BUSY_MASK 0x00002000
    #define SCL_BUSY_SHIFT 13
    #define MRE_BUSY_MASK 0x00010000
    #define MRE_BUSY_SHIFT 16
    #define DCT_BUSY_MASK 0x00020000
    #define DCT_BUSY_SHIFT 17
    #define EIDCT_BUSY_MASK 0x00040000
    #define EIDCT_BUSY_SHIFT 18
    #define EZQ_BUSY_MASK 0x00080000
    #define EZQ_BUSY_SHIFT 19
    #define OSF_REGBUSY_MASK 0x00100000
    #define OSF_REGBUSY_SHIFT 20
    #define OSF_BUSY_MASK 0x00200000
    #define OSF_BUSY_SHIFT 21
    #define RCB_BUSY_MASK 0x00400000
    #define RCB_BUSY_SHIFT 22
    #define DEC_BUSY_MASK 0x20000000
    #define DEC_BUSY_SHIFT 29
    #define ENC_BUSY_MASK 0x40000000
    #define ENC_BUSY_SHIFT 30
    #define MPP_BUSY_MASK 0x80000000
    #define MPP_BUSY_SHIFT 31
#define  MPP_WAIT_UNTIL 0x7320
    #define DZQ_REGRDY_MASK 0x00000100
    #define DZQ_REGRDY_SHIFT 8
    #define DZQ_IDLE_MASK 0x00000200
    #define DZQ_IDLE_SHIFT 9
    #define IDCT_REGRDY_MASK 0x00000400
    #define IDCT_REGRDY_SHIFT 10
    #define IDCT_IDLE_MASK 0x00000800
    #define IDCT_IDLE_SHIFT 11
    #define MRE_IDLE_MASK 0x00001000
    #define MRE_IDLE_SHIFT 12
    #define SCL_IDLE_MASK 0x00002000
    #define SCL_IDLE_SHIFT 13
    #define MSC_IDLE_MASK 0x00010000
    #define MSC_IDLE_SHIFT 16
    #define DCT_IDLE_MASK 0x00020000
    #define DCT_IDLE_SHIFT 17
    #define EIDCT_IDLE_MASK 0x00040000
    #define EIDCT_IDLE_SHIFT 18
    #define EZQ_IDLE_MASK 0x00080000
    #define EZQ_IDLE_SHIFT 19
    #define OSF_REGRDY_MASK 0x00100000
    #define OSF_REGRDY_SHIFT 20
    #define OSF_IDLE_MASK 0x00200000
    #define OSF_IDLE_SHIFT 21
    #define DEC_IDLE_MASK 0x20000000
    #define DEC_IDLE_SHIFT 29
    #define ENC_IDLE_MASK 0x40000000
    #define ENC_IDLE_SHIFT 30
    #define MPP_IDLE_MASK 0x80000000
    #define MPP_IDLE_SHIFT 31
#define  MRE_CLK_CTRL 0x74C8
    #define MRE_ECLK_GATE_EN_MASK 0x00000001
    #define MRE_ECLK_GATE_EN_SHIFT 0
    #define MRE_MCLK_GATE_EN_MASK 0x00000002
    #define MRE_MCLK_GATE_EN_SHIFT 1
    #define PICT_ECLK_GATE_EN_MASK 0x00000004
    #define PICT_ECLK_GATE_EN_SHIFT 2
    #define PICT_MCLK_GATE_EN_MASK 0x00000008
    #define PICT_MCLK_GATE_EN_SHIFT 3
    #define REF_ECLK_GATE_EN_MASK 0x00000010
    #define REF_ECLK_GATE_EN_SHIFT 4
    #define YCACHE_MCLK_GATE_EN_MASK 0x00000020
    #define YCACHE_MCLK_GATE_EN_SHIFT 5
    #define CCACHE_MCLK_GATE_EN_MASK 0x00000040
    #define CCACHE_MCLK_GATE_EN_SHIFT 6
#define  MRE_CTRL 0x73F4
    #define MRE_CTRL_SRCH_FRM_EN_MASK 0x00000001
    #define MRE_CTRL_SRCH_FRM_EN_SHIFT 0
    #define MRE_CTRL_SRCH_FLD_EN_MASK 0x00000002
    #define MRE_CTRL_SRCH_FLD_EN_SHIFT 1
    #define SRCH_FWD_BWD_EN_MASK 0x0000000C
    #define SRCH_FWD_BWD_EN_SHIFT 2
    #define MV_SCALE_H_EN_MASK 0x00000010
    #define MV_SCALE_H_EN_SHIFT 4
    #define MV_SCALE_V_EN_MASK 0x00000020
    #define MV_SCALE_V_EN_SHIFT 5
    #define INTRA_EN_MASK 0x00000040
    #define INTRA_EN_SHIFT 6
    #define FORCE_FRM_MO_MASK 0x00000080
    #define FORCE_FRM_MO_SHIFT 7
    #define IN_MODE_MASK 0x00000300
    #define IN_MODE_SHIFT 8
    #define MRE_CTRL_MV_BIAS_SHIFT_MASK 0x0000F000
    #define MRE_CTRL_MV_BIAS_SHIFT_SHIFT 12
    #define ENC_STATIONARY_EN_MASK 0x00010000
    #define ENC_STATIONARY_EN_SHIFT 16
    #define FCODE_CLAMP_EN_MASK 0x00020000
    #define FCODE_CLAMP_EN_SHIFT 17
    #define FIRST_PASS_FLAG_MASK 0x00040000
    #define FIRST_PASS_FLAG_SHIFT 18
    #define SECOND_PASS_FLAG_MASK 0x00080000
    #define SECOND_PASS_FLAG_SHIFT 19
    #define MV_SCALE_H_OVERRIDE_EN_MASK 0x00100000
    #define MV_SCALE_H_OVERRIDE_EN_SHIFT 20
    #define MV_SCALE_V_OVERRIDE_EN_MASK 0x00200000
    #define MV_SCALE_V_OVERRIDE_EN_SHIFT 21
    #define READ_8X8_TILE_MASK 0x00400000
    #define READ_8X8_TILE_SHIFT 22
#define  MRE_DBG_C_ADR 0x7290
    #define MRE_DBG_C_ADR_BASE_MASK 0x0FFFE000
    #define MRE_DBG_C_ADR_BASE_SHIFT 13
#define  MRE_DBG_Y_ADR 0x728C
    #define MRE_DBG_Y_ADR_BASE_MASK 0x0FFFE000
    #define MRE_DBG_Y_ADR_BASE_SHIFT 13
    #define MRE_DBG_Y_ADR_DEBUG_B_EN_MASK 0x80000000
    #define MRE_DBG_Y_ADR_DEBUG_B_EN_SHIFT 31
#define  MRE_DUMMY_REG 0x72DC
    #define MRE_DUMMY_REG_DUMMY_MASK 0xFFFFFFFF
    #define MRE_DUMMY_REG_DUMMY_SHIFT 0
#define  MRE_REFINE_MODE_SEL 0x74A8
    #define INTRA_THRES_MASK 0x00FFFFFF
    #define INTRA_THRES_SHIFT 0
    #define INTRA_MULT_MASK 0xF0000000
    #define INTRA_MULT_SHIFT 28
#define  MRE_STAT_A 0x727C
    #define MRE_STAT_A_STAT_A_MASK 0xFFFFFFFF
    #define MRE_STAT_A_STAT_A_SHIFT 0
#define  MRE_STAT_B 0x7280
    #define MRE_STAT_B_STAT_B_MASK 0xFFFFFFFF
    #define MRE_STAT_B_STAT_B_SHIFT 0
#define  MRE_STAT_MUX 0x7278
    #define MRE_STAT_MUX_STAT_SEL_A_MASK 0x0000000F
    #define MRE_STAT_MUX_STAT_SEL_A_SHIFT 0
    #define MRE_STAT_MUX_STAT_SEL_B_MASK 0x00000F00
    #define MRE_STAT_MUX_STAT_SEL_B_SHIFT 8
#define  MRE_TRIG 0x7310
    #define MRE_TRIG_MB_CNT_MASK 0x00007FFF
    #define MRE_TRIG_MB_CNT_SHIFT 0
    #define MRE_TRIG_FIELD_SCALE_MASK 0x00010000
    #define MRE_TRIG_FIELD_SCALE_SHIFT 16
    #define RESET_CNT_MASK 0x08000000
    #define RESET_CNT_SHIFT 27
    #define LOCK_CNT_MASK 0x10000000
    #define LOCK_CNT_SHIFT 28
    #define USE_MVI_MASK 0x20000000
    #define USE_MVI_SHIFT 29
    #define MRE_TRIG_TRIG_TYPE_MASK 0x80000000
    #define MRE_TRIG_TRIG_TYPE_SHIFT 31
#define  MSC_BWD_SUBFRM_ADR 0x7488
    #define MSC_BWD_SUBFRM_ADR_BASE_MASK 0x0FFFE000
    #define MSC_BWD_SUBFRM_ADR_BASE_SHIFT 13
#define  MSC_CLK_CTRL 0x74C4
    #define MSC_ECLK_GATE_EN_MASK 0x00000001
    #define MSC_ECLK_GATE_EN_SHIFT 0
    #define MSC_MCLK_GATE_EN_MASK 0x00000002
    #define MSC_MCLK_GATE_EN_SHIFT 1
    #define MSC_CLK_CTRL_XCODE_ECLK_GATE_EN_MASK 0x00000004
    #define MSC_CLK_CTRL_XCODE_ECLK_GATE_EN_SHIFT 2
    #define NCODE_ECLK_GATE_EN_MASK 0x00000008
    #define NCODE_ECLK_GATE_EN_SHIFT 3
    #define PBPICT_ECLK_GATE_EN_MASK 0x00000010
    #define PBPICT_ECLK_GATE_EN_SHIFT 4
    #define PBPICT_MCLK_GATE_EN_MASK 0x00000020
    #define PBPICT_MCLK_GATE_EN_SHIFT 5
#define  MSC_CTRL 0x7460
    #define MSC_CTRL_SRCH_FRM_EN_MASK 0x00000001
    #define MSC_CTRL_SRCH_FRM_EN_SHIFT 0
    #define MSC_CTRL_SRCH_FLD_EN_MASK 0x00000002
    #define MSC_CTRL_SRCH_FLD_EN_SHIFT 1
    #define SRCH_FWD_MV_EN_MASK 0x00000004
    #define SRCH_FWD_MV_EN_SHIFT 2
    #define SRCH_BWD_MV_EN_MASK 0x00000008
    #define SRCH_BWD_MV_EN_SHIFT 3
    #define SRCH_TMPRL_MVA_EN_MASK 0x00000010
    #define SRCH_TMPRL_MVA_EN_SHIFT 4
    #define MSC_CTRL_MV_BIAS_SHIFT_MASK 0x00000F00
    #define MSC_CTRL_MV_BIAS_SHIFT_SHIFT 8
    #define SRCH_MAX_MASK 0x1FFF0000
    #define SRCH_MAX_SHIFT 16
#define  MSC_DBG_C_ADR 0x7288
    #define MSC_DBG_C_ADR_BASE_MASK 0x0FFFE000
    #define MSC_DBG_C_ADR_BASE_SHIFT 13
#define  MSC_DBG_Y_ADR 0x7284
    #define MSC_DBG_Y_ADR_BASE_MASK 0x0FFFE000
    #define MSC_DBG_Y_ADR_BASE_SHIFT 13
    #define MSC_DBG_Y_ADR_DEBUG_B_EN_MASK 0x80000000
    #define MSC_DBG_Y_ADR_DEBUG_B_EN_SHIFT 31
#define  MSC_DUMMY_REG 0x72D8
    #define MSC_DUMMY_REG_DUMMY_MASK 0xFFFFFFFF
    #define MSC_DUMMY_REG_DUMMY_SHIFT 0
#define  MSC_FWD_SUBFRM_ADR 0x7480
    #define MSC_FWD_SUBFRM_ADR_BASE_MASK 0x0FFFE000
    #define MSC_FWD_SUBFRM_ADR_BASE_SHIFT 13
#define  MSC_MVA_TMPRL_ADR 0x7498
    #define MSC_MVA_TMPRL_ADR_BASE_MASK 0x0FFFFC00
    #define MSC_MVA_TMPRL_ADR_BASE_SHIFT 10
#define  MSC_SRCH_FRM_THRES 0x7468
    #define THRES_STATION_MASK 0x00003FFF
    #define THRES_STATION_SHIFT 0
    #define THRES_CANDIDATE_MASK 0x3FFF0000
    #define THRES_CANDIDATE_SHIFT 16
#define  MSC_SRCH_FULL 0x7470
    #define FULL_SPAN_X_MASK 0x000003FE
    #define FULL_SPAN_X_SHIFT 1
    #define FULL_SPAN_Y_MASK 0x03FE0000
    #define FULL_SPAN_Y_SHIFT 17
#define  MSC_SRCH_MAX 0x747C
    #define MAX_SPAN_X_MASK 0x00000FFE
    #define MAX_SPAN_X_SHIFT 1
    #define MAX_SPAN_Y_MASK 0x0FFE0000
    #define MAX_SPAN_Y_SHIFT 17
#define  MSC_SRCH_MV_SCL 0x746C
    #define MV_SCL_FWD_MASK 0x0000FFFF
    #define MV_SCL_FWD_SHIFT 0
    #define MV_SCL_BWD_MASK 0xFFFF0000
    #define MV_SCL_BWD_SHIFT 16
#define  MSC_SRCH_PART 0x7478
    #define PART_SPAN_X_MASK 0x000003FE
    #define PART_SPAN_X_SHIFT 1
    #define PART_SPAN_Y_MASK 0x03FE0000
    #define PART_SPAN_Y_SHIFT 17
#define  MSC_SRCH_SUB_THRES 0x7464
    #define THRES_FULL_MASK 0x00003FFF
    #define THRES_FULL_SHIFT 0
    #define THRES_PART_MASK 0x3FFF0000
    #define THRES_PART_SHIFT 16
#define  MSC_STAT_A 0x7270
    #define MSC_STAT_A_STAT_A_MASK 0xFFFFFFFF
    #define MSC_STAT_A_STAT_A_SHIFT 0
#define  MSC_STAT_B 0x7274
    #define MSC_STAT_B_STAT_B_MASK 0xFFFFFFFF
    #define MSC_STAT_B_STAT_B_SHIFT 0
#define  MSC_STAT_MUX 0x726C
    #define MSC_STAT_MUX_STAT_SEL_A_MASK 0x0000000F
    #define MSC_STAT_MUX_STAT_SEL_A_SHIFT 0
    #define MSC_STAT_MUX_STAT_SEL_B_MASK 0x00000F00
    #define MSC_STAT_MUX_STAT_SEL_B_SHIFT 8
#define  MSC_TRIG 0x7308
    #define MSC_TRIG_MB_CNT_MASK 0x00003FFF
    #define MSC_TRIG_MB_CNT_SHIFT 0
    #define MSC_TRIG_TRIG_TYPE_MASK 0x80000000
    #define MSC_TRIG_TRIG_TYPE_SHIFT 31
#define  MVD0_CTRL 0xA118
    #define MVD0_CTRL_FCODE_FWD_HORI_MASK 0x0000000F
    #define MVD0_CTRL_FCODE_FWD_HORI_SHIFT 0
    #define MVD0_CTRL_FCODE_FWD_VERT_MASK 0x000000F0
    #define MVD0_CTRL_FCODE_FWD_VERT_SHIFT 4
    #define MVD0_CTRL_FCODE_BWD_HORI_MASK 0x00000F00
    #define MVD0_CTRL_FCODE_BWD_HORI_SHIFT 8
    #define MVD0_CTRL_FCODE_BWD_VERT_MASK 0x0000F000
    #define MVD0_CTRL_FCODE_BWD_VERT_SHIFT 12
    #define MVD0_CTRL_FULL_PEL_FWD_MASK 0x00010000
    #define MVD0_CTRL_FULL_PEL_FWD_SHIFT 16
    #define MVD0_CTRL_FULL_PEL_BWD_MASK 0x00020000
    #define MVD0_CTRL_FULL_PEL_BWD_SHIFT 17
#define  MVD0_MV0_BWD 0xA148
    #define MVD0_MV0_BWD_MV_HORI_MASK 0x00001FFF
    #define MVD0_MV0_BWD_MV_HORI_SHIFT 0
    #define MVD0_MV0_BWD_MV_VERT_MASK 0x1FFF0000
    #define MVD0_MV0_BWD_MV_VERT_SHIFT 16
    #define MVD0_MV0_BWD_FLD_SEL_MASK 0x80000000
    #define MVD0_MV0_BWD_FLD_SEL_SHIFT 31
#define  MVD0_MV0_FWD 0xA144
    #define MVD0_MV0_FWD_MV_HORI_MASK 0x00001FFF
    #define MVD0_MV0_FWD_MV_HORI_SHIFT 0
    #define MVD0_MV0_FWD_MV_VERT_MASK 0x1FFF0000
    #define MVD0_MV0_FWD_MV_VERT_SHIFT 16
    #define MVD0_MV0_FWD_FLD_SEL_MASK 0x80000000
    #define MVD0_MV0_FWD_FLD_SEL_SHIFT 31
#define  MVD0_MV1_BWD 0xA150
    #define MVD0_MV1_BWD_MV_HORI_MASK 0x00001FFF
    #define MVD0_MV1_BWD_MV_HORI_SHIFT 0
    #define MVD0_MV1_BWD_MV_VERT_MASK 0x1FFF0000
    #define MVD0_MV1_BWD_MV_VERT_SHIFT 16
    #define MVD0_MV1_BWD_FLD_SEL_MASK 0x80000000
    #define MVD0_MV1_BWD_FLD_SEL_SHIFT 31
#define  MVD0_MV1_FWD 0xA14C
    #define MVD0_MV1_FWD_MV_HORI_MASK 0x00001FFF
    #define MVD0_MV1_FWD_MV_HORI_SHIFT 0
    #define MVD0_MV1_FWD_MV_VERT_MASK 0x1FFF0000
    #define MVD0_MV1_FWD_MV_VERT_SHIFT 16
    #define MVD0_MV1_FWD_FLD_SEL_MASK 0x80000000
    #define MVD0_MV1_FWD_FLD_SEL_SHIFT 31
#define  MVD0_PICT_RES 0xA114
    #define MVD0_PICT_RES_MB_WIDTH_MASK 0x0000007F
    #define MVD0_PICT_RES_MB_WIDTH_SHIFT 0
    #define MVD0_PICT_RES_MB_HEIGHT_MASK 0x007F0000
    #define MVD0_PICT_RES_MB_HEIGHT_SHIFT 16
    #define MVD0_PICT_RES_NO_VERIFY_X_MASK 0x40000000
    #define MVD0_PICT_RES_NO_VERIFY_X_SHIFT 30
    #define MVD0_PICT_RES_NO_VERIFY_Y_MASK 0x80000000
    #define MVD0_PICT_RES_NO_VERIFY_Y_SHIFT 31
#define  MVD0_RESET_PRED 0xA154
    #define MVD0_RESET_PRED_DATA_MASK 0xFFFFFFFF
    #define MVD0_RESET_PRED_DATA_SHIFT 0
#define  MVD0_STATUS 0xA15C
    #define MVD0_STATUS_DONE_MASK 0x00000001
    #define MVD0_STATUS_DONE_SHIFT 0
    #define MVD0_STATUS_MV0_FWD_VALID_MASK 0x00000010
    #define MVD0_STATUS_MV0_FWD_VALID_SHIFT 4
    #define MVD0_STATUS_MV0_BWD_VALID_MASK 0x00000020
    #define MVD0_STATUS_MV0_BWD_VALID_SHIFT 5
    #define MVD0_STATUS_MV1_FWD_VALID_MASK 0x00000040
    #define MVD0_STATUS_MV1_FWD_VALID_SHIFT 6
    #define MVD0_STATUS_MV1_BWD_VALID_MASK 0x00000080
    #define MVD0_STATUS_MV1_BWD_VALID_SHIFT 7
    #define MVD0_STATUS_ERROR_MASK 0xF0000000
    #define MVD0_STATUS_ERROR_SHIFT 28
#define  MVD0_TRIG 0xA158
    #define MVD0_TRIG_MB_TYPE_MASK 0x0000000F
    #define MVD0_TRIG_MB_TYPE_SHIFT 0
    #define MVD0_TRIG_MO_TYPE_MASK 0x00000030
    #define MVD0_TRIG_MO_TYPE_SHIFT 4
    #define MVD0_TRIG_MV_CNT_MASK 0x00000100
    #define MVD0_TRIG_MV_CNT_SHIFT 8
    #define MVD0_TRIG_MB_IDX_X_MASK 0x007F0000
    #define MVD0_TRIG_MB_IDX_X_SHIFT 16
    #define MVD0_TRIG_MB_IDX_Y_MASK 0x7F000000
    #define MVD0_TRIG_MB_IDX_Y_SHIFT 24
#define  MVD1_CTRL 0xA518
    #define MVD1_CTRL_FCODE_FWD_HORI_MASK 0x0000000F
    #define MVD1_CTRL_FCODE_FWD_HORI_SHIFT 0
    #define MVD1_CTRL_FCODE_FWD_VERT_MASK 0x000000F0
    #define MVD1_CTRL_FCODE_FWD_VERT_SHIFT 4
    #define MVD1_CTRL_FCODE_BWD_HORI_MASK 0x00000F00
    #define MVD1_CTRL_FCODE_BWD_HORI_SHIFT 8
    #define MVD1_CTRL_FCODE_BWD_VERT_MASK 0x0000F000
    #define MVD1_CTRL_FCODE_BWD_VERT_SHIFT 12
    #define MVD1_CTRL_FULL_PEL_FWD_MASK 0x00010000
    #define MVD1_CTRL_FULL_PEL_FWD_SHIFT 16
    #define MVD1_CTRL_FULL_PEL_BWD_MASK 0x00020000
    #define MVD1_CTRL_FULL_PEL_BWD_SHIFT 17
#define  MVD1_MV0_BWD 0xA548
    #define MVD1_MV0_BWD_MV_HORI_MASK 0x00001FFF
    #define MVD1_MV0_BWD_MV_HORI_SHIFT 0
    #define MVD1_MV0_BWD_MV_VERT_MASK 0x1FFF0000
    #define MVD1_MV0_BWD_MV_VERT_SHIFT 16
    #define MVD1_MV0_BWD_FLD_SEL_MASK 0x80000000
    #define MVD1_MV0_BWD_FLD_SEL_SHIFT 31
#define  MVD1_MV0_FWD 0xA544
    #define MVD1_MV0_FWD_MV_HORI_MASK 0x00001FFF
    #define MVD1_MV0_FWD_MV_HORI_SHIFT 0
    #define MVD1_MV0_FWD_MV_VERT_MASK 0x1FFF0000
    #define MVD1_MV0_FWD_MV_VERT_SHIFT 16
    #define MVD1_MV0_FWD_FLD_SEL_MASK 0x80000000
    #define MVD1_MV0_FWD_FLD_SEL_SHIFT 31
#define  MVD1_MV1_BWD 0xA550
    #define MVD1_MV1_BWD_MV_HORI_MASK 0x00001FFF
    #define MVD1_MV1_BWD_MV_HORI_SHIFT 0
    #define MVD1_MV1_BWD_MV_VERT_MASK 0x1FFF0000
    #define MVD1_MV1_BWD_MV_VERT_SHIFT 16
    #define MVD1_MV1_BWD_FLD_SEL_MASK 0x80000000
    #define MVD1_MV1_BWD_FLD_SEL_SHIFT 31
#define  MVD1_MV1_FWD 0xA54C
    #define MVD1_MV1_FWD_MV_HORI_MASK 0x00001FFF
    #define MVD1_MV1_FWD_MV_HORI_SHIFT 0
    #define MVD1_MV1_FWD_MV_VERT_MASK 0x1FFF0000
    #define MVD1_MV1_FWD_MV_VERT_SHIFT 16
    #define MVD1_MV1_FWD_FLD_SEL_MASK 0x80000000
    #define MVD1_MV1_FWD_FLD_SEL_SHIFT 31
#define  MVD1_PICT_RES 0xA514
    #define MVD1_PICT_RES_MB_WIDTH_MASK 0x0000007F
    #define MVD1_PICT_RES_MB_WIDTH_SHIFT 0
    #define MVD1_PICT_RES_MB_HEIGHT_MASK 0x007F0000
    #define MVD1_PICT_RES_MB_HEIGHT_SHIFT 16
    #define MVD1_PICT_RES_NO_VERIFY_X_MASK 0x40000000
    #define MVD1_PICT_RES_NO_VERIFY_X_SHIFT 30
    #define MVD1_PICT_RES_NO_VERIFY_Y_MASK 0x80000000
    #define MVD1_PICT_RES_NO_VERIFY_Y_SHIFT 31
#define  MVD1_RESET_PRED 0xA554
    #define MVD1_RESET_PRED_DATA_MASK 0xFFFFFFFF
    #define MVD1_RESET_PRED_DATA_SHIFT 0
#define  MVD1_STATUS 0xA55C
    #define MVD1_STATUS_DONE_MASK 0x00000001
    #define MVD1_STATUS_DONE_SHIFT 0
    #define MVD1_STATUS_MV0_FWD_VALID_MASK 0x00000010
    #define MVD1_STATUS_MV0_FWD_VALID_SHIFT 4
    #define MVD1_STATUS_MV0_BWD_VALID_MASK 0x00000020
    #define MVD1_STATUS_MV0_BWD_VALID_SHIFT 5
    #define MVD1_STATUS_MV1_FWD_VALID_MASK 0x00000040
    #define MVD1_STATUS_MV1_FWD_VALID_SHIFT 6
    #define MVD1_STATUS_MV1_BWD_VALID_MASK 0x00000080
    #define MVD1_STATUS_MV1_BWD_VALID_SHIFT 7
    #define MVD1_STATUS_ERROR_MASK 0xF0000000
    #define MVD1_STATUS_ERROR_SHIFT 28
#define  MVD1_TRIG 0xA558
    #define MVD1_TRIG_MB_TYPE_MASK 0x0000000F
    #define MVD1_TRIG_MB_TYPE_SHIFT 0
    #define MVD1_TRIG_MO_TYPE_MASK 0x00000030
    #define MVD1_TRIG_MO_TYPE_SHIFT 4
    #define MVD1_TRIG_MV_CNT_MASK 0x00000100
    #define MVD1_TRIG_MV_CNT_SHIFT 8
    #define MVD1_TRIG_MB_IDX_X_MASK 0x007F0000
    #define MVD1_TRIG_MB_IDX_X_SHIFT 16
    #define MVD1_TRIG_MB_IDX_Y_MASK 0x7F000000
    #define MVD1_TRIG_MB_IDX_Y_SHIFT 24
#define  OSF_CONST_REG1 0x7314
    #define OSF_CONST_REG1_DATA_MASK 0xFFFFFFFF
    #define OSF_CONST_REG1_DATA_SHIFT 0
#define  OSF_CONST_REG2 0x7318
    #define OSF_CONST_REG2_CNT_MASK 0x0000001F
    #define OSF_CONST_REG2_CNT_SHIFT 0
    #define OSF_CONST_REG2_DATA_MASK 0xFFFFFFE0
    #define OSF_CONST_REG2_DATA_SHIFT 5
#define  OSF_CTRL 0x73F8
    #define PADDING_MASK 0x00000003
    #define PADDING_SHIFT 0
    #define MB_SKIP_EN_MASK 0x00000004
    #define MB_SKIP_EN_SHIFT 2
    #define ENC_FRMPRED_FRMDCT_MASK 0x00000008
    #define ENC_FRMPRED_FRMDCT_SHIFT 3
    #define QSCALE_INITIAL_MASK 0x000007F0
    #define QSCALE_INITIAL_SHIFT 4
    #define OSF_CTRL_PROG_FRM_MASK 0x00000800
    #define OSF_CTRL_PROG_FRM_SHIFT 11
    #define MB_ADR_BITS_MASK 0x0000F000
    #define MB_ADR_BITS_SHIFT 12
    #define FCODE_FW_H_MASK 0x000F0000
    #define FCODE_FW_H_SHIFT 16
    #define FCODE_FW_V_MASK 0x00F00000
    #define FCODE_FW_V_SHIFT 20
    #define FCODE_BW_H_MASK 0x0F000000
    #define FCODE_BW_H_SHIFT 24
    #define FCODE_BW_V_MASK 0xF0000000
    #define FCODE_BW_V_SHIFT 28
#define  OSF_DST_ADR 0x745C
    #define OSF_DST_ADR_BASE_MASK 0x0FFFFC00
    #define OSF_DST_ADR_BASE_SHIFT 10
#define  OSF_MAX_BYTES 0x74D0
    #define MAX_BYTES_VALUE_MASK 0x00FFFFF8
    #define MAX_BYTES_VALUE_SHIFT 3
#define  OSF_OBB_CNT_FREERUN 0x72B0
    #define OBB_CNT_FREERUN_MASK 0x00FFFFFF
    #define OBB_CNT_FREERUN_SHIFT 0
#define  OSF_OBB_CNT_STATIC 0x72B4
    #define OBB_CNT_STATIC_MASK 0x00FFFFFF
    #define OBB_CNT_STATIC_SHIFT 0
#define  OSF_TRIG 0x731C
    #define OSF_TRIG_NODATA_MASK 0x00000001
    #define OSF_TRIG_NODATA_SHIFT 0
#define  PCIE_ASYNC_IF_STATUS 0x1C28
    #define DBI_ACK_MASK 0x00000001
    #define DBI_ACK_SHIFT 0
    #define MSI_GRANT_MASK 0x00000002
    #define MSI_GRANT_SHIFT 1
    #define MSI_EN_MASK 0x00000004
    #define MSI_EN_SHIFT 2
    #define VMI_GRANT_MASK 0x00000008
    #define VMI_GRANT_SHIFT 3
    #define VMI_VALID_MASK 0x00000010
    #define VMI_VALID_SHIFT 4
#define  PCIE_ASYNC_IF_WDAT_HI 0x1C00
    #define PCIE_ASYNC_IF_WDAT_HI_WDAT_MASK 0xFFFFFFFF
    #define PCIE_ASYNC_IF_WDAT_HI_WDAT_SHIFT 0
#define  PCIE_ASYNC_IF_WDAT_LO 0x1C04
    #define PCIE_ASYNC_IF_WDAT_LO_WDAT_MASK 0xFFFFFFFF
    #define PCIE_ASYNC_IF_WDAT_LO_WDAT_SHIFT 0
#define  PCIE_AUTO_MSI 0x1C18
    #define AUTO_MSI_EN_MASK 0x00000001
    #define AUTO_MSI_EN_SHIFT 0
    #define AUTO_MSI_ASSERT_MASK 0x0000003E
    #define AUTO_MSI_ASSERT_SHIFT 1
    #define AUTO_MSI_DEASSERT_MASK 0x000007C0
    #define AUTO_MSI_DEASSERT_SHIFT 6
#define  PCIE_DBI_ADDR 0x1C08
    #define DBI_ADDR_MASK 0xFFFFFFFF
    #define DBI_ADDR_SHIFT 0
#define  PCIE_DBI_CTRL 0x1C0C
    #define DBI_CS_MASK 0x00000001
    #define DBI_CS_SHIFT 0
    #define DBI_CS2_MASK 0x00000002
    #define DBI_CS2_SHIFT 1
    #define DBI_WR_MASK 0x000000F0
    #define DBI_WR_SHIFT 4
#define  PCIE_DBI_DOUT 0x1C10
    #define DBI_RDAT_MASK 0xFFFFFFFF
    #define DBI_RDAT_SHIFT 0
#define  PCIE_DEBUG 0x1C40
    #define PCIE_DEBUG_DEBUG_DATA_MASK 0x000FFFFF
    #define PCIE_DEBUG_DEBUG_DATA_SHIFT 0
#define  PCIE_DIAGNOSTIC 0x1C3C
    #define DIAGNOSTIC_TD_MASK 0x00000001
    #define DIAGNOSTIC_TD_SHIFT 0
    #define DIAGNOSTIC_EP_MASK 0x00000002
    #define DIAGNOSTIC_EP_SHIFT 1
    #define DIAGNOSTIC_INT_MASK 0x00000004
    #define DIAGNOSTIC_INT_SHIFT 2
    #define DIAGNOSTIC_DMAR_MASK 0x00000008
    #define DIAGNOSTIC_DMAR_SHIFT 3
    #define DIAGNOSTIC_DMAW_MASK 0x00000010
    #define DIAGNOSTIC_DMAW_SHIFT 4
    #define DIAGNOSTIC_LTSSM_EN_MASK 0x00000020
    #define DIAGNOSTIC_LTSSM_EN_SHIFT 5
    #define DIAGNOSTIC_CFG_RETRY_MASK 0x00000040
    #define DIAGNOSTIC_CFG_RETRY_SHIFT 6
    #define DIAG_CTRL_BUS_MASK 0x00000300
    #define DIAG_CTRL_BUS_SHIFT 8
    #define REFCLK_RAMP_TIME_MASK 0xFF000000
    #define REFCLK_RAMP_TIME_SHIFT 24
#define  PCIE_DMA_READ_CFG0 0x1C34
    #define MAX_REQ_DW_SZ_MASK 0x000007FF
    #define MAX_REQ_DW_SZ_SHIFT 0
    #define MAX_REQ_DW_SZ_OVERRIDE_MASK 0x00001000
    #define MAX_REQ_DW_SZ_OVERRIDE_SHIFT 12
    #define TLP_TID_LB_MASK 0x001F0000
    #define TLP_TID_LB_SHIFT 16
    #define TLP_TID_UB_MASK 0x1F000000
    #define TLP_TID_UB_SHIFT 24
#define  PCIE_DMA_READ_CFG1 0x1C38
    #define MTU0_DISABLE_MASK 0x00000001
    #define MTU0_DISABLE_SHIFT 0
    #define MTU1_DISABLE_MASK 0x00000002
    #define MTU1_DISABLE_SHIFT 1
    #define MTU2_DISABLE_MASK 0x00000004
    #define MTU2_DISABLE_SHIFT 2
    #define MTU3_DISABLE_MASK 0x00000008
    #define MTU3_DISABLE_SHIFT 3
    #define RETRY_WAIT_CYC_MASK 0x00FF0000
    #define RETRY_WAIT_CYC_SHIFT 16
#define  PCIE_DUMMY_REG 0x1C48
    #define PCIE_DUMMY_REG_DUMMY_BITS_MASK 0xFFFFFFFF
    #define PCIE_DUMMY_REG_DUMMY_BITS_SHIFT 0
#define  PCIE_MSI_CTRL 0x1C14
    #define MSI_FUN_NUM_MASK 0x00000007
    #define MSI_FUN_NUM_SHIFT 0
    #define MSI_TC_MASK 0x00000070
    #define MSI_TC_SHIFT 4
    #define MSI_VECTOR_MASK 0x00001F00
    #define MSI_VECTOR_SHIFT 8
#define  PCIE_PHY_COMMON_CTRL 0x1C54
    #define PCIE_PHY_CTRL_RTUNE_DO_TUNE_MASK 0x00000001
    #define PCIE_PHY_CTRL_RTUNE_DO_TUNE_SHIFT 0
    #define PCIE_PHY_CTRL_TX_LVL_MASK 0x0000003E
    #define PCIE_PHY_CTRL_TX_LVL_SHIFT 1
    #define PCIE_PHY_CTRL_LOS_LVL_MASK 0x000007C0
    #define PCIE_PHY_CTRL_LOS_LVL_SHIFT 6
    #define PCIE_PHY_CTRL_ACJT_LVL_MASK 0x0000F800
    #define PCIE_PHY_CTRL_ACJT_LVL_SHIFT 11
    #define PCIE_PHY_CTRL_RESET_N_MASK 0x00010000
    #define PCIE_PHY_CTRL_RESET_N_SHIFT 16
    #define PCIE_PHY_CTRL_OVERRIDE_CTRL_MASK 0x00020000
    #define PCIE_PHY_CTRL_OVERRIDE_CTRL_SHIFT 17
#define  PCIE_PHY_CR_IN 0x1C5C
    #define PCIE_PHY_CR_IN_DATA_MASK 0x0000FFFF
    #define PCIE_PHY_CR_IN_DATA_SHIFT 0
    #define PCIE_PHY_CR_IN_ACK_MASK 0x00010000
    #define PCIE_PHY_CR_IN_ACK_SHIFT 16
#define  PCIE_PHY_CR_OUT 0x1C58
    #define PCIE_PHY_CR_OUT_DATA_MASK 0x0000FFFF
    #define PCIE_PHY_CR_OUT_DATA_SHIFT 0
    #define PCIE_PHY_CR_OUT_CAP_ADDR_MASK 0x00010000
    #define PCIE_PHY_CR_OUT_CAP_ADDR_SHIFT 16
    #define PCIE_PHY_CR_OUT_CAP_DATA_MASK 0x00020000
    #define PCIE_PHY_CR_OUT_CAP_DATA_SHIFT 17
    #define PCIE_PHY_CR_OUT_WRITE_MASK 0x00040000
    #define PCIE_PHY_CR_OUT_WRITE_SHIFT 18
    #define PCIE_PHY_CR_OUT_READ_MASK 0x00080000
    #define PCIE_PHY_CR_OUT_READ_SHIFT 19
#define  PCIE_PHY_MPLL_CTRL 0x1C50
    #define PCIE_PHY_CTRL_MPLL_CK_OFF_MASK 0x00000001
    #define PCIE_PHY_CTRL_MPLL_CK_OFF_SHIFT 0
    #define PCIE_PHY_CTRL_MPLL_PWRON_MASK 0x00000002
    #define PCIE_PHY_CTRL_MPLL_PWRON_SHIFT 1
    #define PCIE_PHY_CTRL_MPLL_PRESCALE_MASK 0x00000018
    #define PCIE_PHY_CTRL_MPLL_PRESCALE_SHIFT 3
    #define PCIE_PHY_CTRL_MPLL_SS_EN_MASK 0x00000020
    #define PCIE_PHY_CTRL_MPLL_SS_EN_SHIFT 5
    #define PCIE_PHY_CTRL_MPLL_NCY_MASK 0x00000F80
    #define PCIE_PHY_CTRL_MPLL_NCY_SHIFT 7
    #define PCIE_PHY_CTRL_MPLL_NCY5_MASK 0x00003000
    #define PCIE_PHY_CTRL_MPLL_NCY5_SHIFT 12
    #define PCIE_PHY_CTRL_MPLL_INT_CTL_MASK 0x00038000
    #define PCIE_PHY_CTRL_MPLL_INT_CTL_SHIFT 15
    #define PCIE_PHY_CTRL_MPLL_PROP_CTL_MASK 0x00380000
    #define PCIE_PHY_CTRL_MPLL_PROP_CTL_SHIFT 19
    #define PCIE_PHY_CTRL_CKO_WORD_CON_MASK 0x03800000
    #define PCIE_PHY_CTRL_CKO_WORD_CON_SHIFT 23
    #define PCIE_PHY_CTRL_CKO_ALIVE_CON_MASK 0x18000000
    #define PCIE_PHY_CTRL_CKO_ALIVE_CON_SHIFT 27
#define  PCIE_PHY_TXRX_CTRL 0x1C4C
    #define PCIE_PHY_CTRL_TX_EN_MASK 0x00000007
    #define PCIE_PHY_CTRL_TX_EN_SHIFT 0
    #define PCIE_PHY_CTRL_TX_BOOST_MASK 0x000000F0
    #define PCIE_PHY_CTRL_TX_BOOST_SHIFT 4
    #define PCIE_PHY_CTRL_TX_ATTEN_MASK 0x00000700
    #define PCIE_PHY_CTRL_TX_ATTEN_SHIFT 8
    #define PCIE_PHY_CTRL_TX_CLK_ALIGN_MASK 0x00000800
    #define PCIE_PHY_CTRL_TX_CLK_ALIGN_SHIFT 11
    #define PCIE_PHY_CTRL_TX_CKO_EN_MASK 0x00001000
    #define PCIE_PHY_CTRL_TX_CKO_EN_SHIFT 12
    #define PCIE_PHY_CTRL_TX_EDGERATE_MASK 0x00006000
    #define PCIE_PHY_CTRL_TX_EDGERATE_SHIFT 13
    #define PCIE_PHY_CTRL_RX_EN_MASK 0x00008000
    #define PCIE_PHY_CTRL_RX_EN_SHIFT 15
    #define PCIE_PHY_CTRL_RX_PLL_PWRON_MASK 0x00010000
    #define PCIE_PHY_CTRL_RX_PLL_PWRON_SHIFT 16
    #define PCIE_PHY_CTRL_RX_ALIGN_EN_MASK 0x00020000
    #define PCIE_PHY_CTRL_RX_ALIGN_EN_SHIFT 17
    #define PCIE_PHY_CTRL_RX_TERM_EN_MASK 0x00040000
    #define PCIE_PHY_CTRL_RX_TERM_EN_SHIFT 18
    #define PCIE_PHY_CTRL_RX_EQ_VAL_MASK 0x00700000
    #define PCIE_PHY_CTRL_RX_EQ_VAL_SHIFT 20
    #define PCIE_PHY_CTRL_RX_DPLL_MODE_MASK 0x07000000
    #define PCIE_PHY_CTRL_RX_DPLL_MODE_SHIFT 24
    #define PCIE_PHY_CTRL_DPLL_RESET_MASK 0x10000000
    #define PCIE_PHY_CTRL_DPLL_RESET_SHIFT 28
    #define PCIE_PHY_CTRL_RX_LOS_CTL_MASK 0x60000000
    #define PCIE_PHY_CTRL_RX_LOS_CTL_SHIFT 29
    #define PCIE_PHY_CTRL_TX_CALC_MASK 0x80000000
    #define PCIE_PHY_CTRL_TX_CALC_SHIFT 31
#define  PCIE_POWER_MGMT 0x1C60
    #define CLKREQ_N_MASK 0x00000001
    #define CLKREQ_N_SHIFT 0
    #define CLKREQ_SEL_MASK 0x00000002
    #define CLKREQ_SEL_SHIFT 1
#define  PCIE_SFT_RSTN 0x1C44
    #define PCIE_SFT_RSTN_SFT_RSTN_MASK 0x00000001
    #define PCIE_SFT_RSTN_SFT_RSTN_SHIFT 0
#define  PCIE_SII_IDX 0x1C2C
    #define SII_IDX_MASK 0x00000003
    #define SII_IDX_SHIFT 0
    #define DIAG_STATUS_BUS_MUX_MASK 0x000001E0
    #define DIAG_STATUS_BUS_MUX_SHIFT 5
#define  PCIE_SII_RDAT 0x1C30
    #define SII_RDAT_MASK 0xFFFFFFFF
    #define SII_RDAT_SHIFT 0
#define  PCIE_VMI_CTRL 0x1C20
    #define VMI_FUN_NUM_MASK 0x00000007
    #define VMI_FUN_NUM_SHIFT 0
    #define VMI_TAG_MASK 0x00000FF0
    #define VMI_TAG_SHIFT 4
    #define VMI_CODE_MASK 0x000FF000
    #define VMI_CODE_SHIFT 12
#define  PCIE_VMI_DOUT 0x1C24
    #define VMI_RDAT_MASK 0xFFFFFFFF
    #define VMI_RDAT_SHIFT 0
#define  PCIE_VMI_PARAM 0x1C1C
    #define VMI_FMT_MASK 0x00000003
    #define VMI_FMT_SHIFT 0
    #define VMI_TYPE_MASK 0x000001F0
    #define VMI_TYPE_SHIFT 4
    #define VMI_TC_MASK 0x00007000
    #define VMI_TC_SHIFT 12
    #define VMI_TD_MASK 0x00010000
    #define VMI_TD_SHIFT 16
    #define VMI_EP_MASK 0x00020000
    #define VMI_EP_SHIFT 17
    #define VMI_ATTR_MASK 0x000C0000
    #define VMI_ATTR_SHIFT 18
    #define VMI_LEN_MASK 0x3FF00000
    #define VMI_LEN_SHIFT 20
#define  PID_TABLE_ADR 0x6040
    #define PID_TABLE_ADR_BASE_MASK 0x0000003F
    #define PID_TABLE_ADR_BASE_SHIFT 0
#define  PID_TABLE_LWDAT 0x6044
    #define PID_MASK 0x00001FFF
    #define PID_SHIFT 0
    #define SID_MASK 0x0000E000
    #define SID_SHIFT 13
    #define PID_RMAP_MASK 0x1FFF0000
    #define PID_RMAP_SHIFT 16
    #define RMAP_EN_MASK 0x20000000
    #define RMAP_EN_SHIFT 29
    #define TSOUT_EN_MASK 0x40000000
    #define TSOUT_EN_SHIFT 30
    #define PTVALID_MASK 0x80000000
    #define PTVALID_SHIFT 31
#define  PID_TABLE_UWDAT 0x6048
    #define RID_MASK 0x0000000F
    #define RID_SHIFT 0
    #define PID_TABLE_UWDAT_MODE_MASK 0x00000300
    #define PID_TABLE_UWDAT_MODE_SHIFT 8
#define  POD_CTRL 0x6050
    #define INSERT_HDR_MASK 0x00000001
    #define INSERT_HDR_SHIFT 0
    #define POD_MDI_NEG_DETECT_MASK 0x00000002
    #define POD_MDI_NEG_DETECT_SHIFT 1
    #define POD_MOCLK_INV_MASK 0x00000004
    #define POD_MOCLK_INV_SHIFT 2
    #define POD_VAL_ACTIVE_HIGH_MASK 0x00000008
    #define POD_VAL_ACTIVE_HIGH_SHIFT 3
    #define POD_IGNORE_VAL_MASK 0x00000010
    #define POD_IGNORE_VAL_SHIFT 4
#define  POD_GPIO_CTRL 0x60B0
    #define GPIO_OUT_EN_MASK 0x00000001
    #define GPIO_OUT_EN_SHIFT 0
    #define GPIO_IN_EN_MASK 0x00000002
    #define GPIO_IN_EN_SHIFT 1
#define  POD_GPIO_IN_0_9 0x60B8
    #define GPIO_IN0_MASK 0x00000001
    #define GPIO_IN0_SHIFT 0
    #define GPIO_IN1_MASK 0x00000002
    #define GPIO_IN1_SHIFT 1
    #define GPIO_IN2_MASK 0x00000004
    #define GPIO_IN2_SHIFT 2
    #define GPIO_IN3_MASK 0x00000008
    #define GPIO_IN3_SHIFT 3
    #define GPIO_IN4_MASK 0x00000010
    #define GPIO_IN4_SHIFT 4
    #define GPIO_IN5_MASK 0x00000020
    #define GPIO_IN5_SHIFT 5
    #define GPIO_IN6_MASK 0x00000040
    #define GPIO_IN6_SHIFT 6
    #define GPIO_IN7_MASK 0x00000080
    #define GPIO_IN7_SHIFT 7
    #define GPIO_IN8_MASK 0x00000100
    #define GPIO_IN8_SHIFT 8
    #define GPIO_IN9_MASK 0x00000200
    #define GPIO_IN9_SHIFT 9
#define  POD_GPIO_OUT_0_9 0x60B4
    #define GPIO_OUT0_MASK 0x00000001
    #define GPIO_OUT0_SHIFT 0
    #define GPIO_OUT1_MASK 0x00000002
    #define GPIO_OUT1_SHIFT 1
    #define GPIO_OUT2_MASK 0x00000004
    #define GPIO_OUT2_SHIFT 2
    #define GPIO_OUT3_MASK 0x00000008
    #define GPIO_OUT3_SHIFT 3
    #define GPIO_OUT4_MASK 0x00000010
    #define GPIO_OUT4_SHIFT 4
    #define GPIO_OUT5_MASK 0x00000020
    #define GPIO_OUT5_SHIFT 5
    #define GPIO_OUT6_MASK 0x00000040
    #define GPIO_OUT6_SHIFT 6
    #define GPIO_OUT7_MASK 0x00000080
    #define GPIO_OUT7_SHIFT 7
    #define GPIO_OUT8_MASK 0x00000100
    #define GPIO_OUT8_SHIFT 8
    #define GPIO_OUT9_MASK 0x00000200
    #define GPIO_OUT9_SHIFT 9
#define  POD_HDR0_0 0x6054
    #define POD_HDR0_0_HDR_MASK 0xFFFFFFFF
    #define POD_HDR0_0_HDR_SHIFT 0
#define  POD_HDR0_1 0x6058
    #define POD_HDR0_1_HDR_MASK 0xFFFFFFFF
    #define POD_HDR0_1_HDR_SHIFT 0
#define  POD_HDR0_2 0x605C
    #define POD_HDR0_2_HDR_MASK 0xFFFFFFFF
    #define POD_HDR0_2_HDR_SHIFT 0
#define  POD_HDR1_0 0x6064
    #define POD_HDR1_0_HDR_MASK 0xFFFFFFFF
    #define POD_HDR1_0_HDR_SHIFT 0
#define  POD_HDR1_1 0x6068
    #define POD_HDR1_1_HDR_MASK 0xFFFFFFFF
    #define POD_HDR1_1_HDR_SHIFT 0
#define  POD_HDR1_2 0x606C
    #define POD_HDR1_2_HDR_MASK 0xFFFFFFFF
    #define POD_HDR1_2_HDR_SHIFT 0
#define  POD_HDR2_0 0x6074
    #define POD_HDR2_0_HDR_MASK 0xFFFFFFFF
    #define POD_HDR2_0_HDR_SHIFT 0
#define  POD_HDR2_1 0x6078
    #define POD_HDR2_1_HDR_MASK 0xFFFFFFFF
    #define POD_HDR2_1_HDR_SHIFT 0
#define  POD_HDR2_2 0x607C
    #define POD_HDR2_2_HDR_MASK 0xFFFFFFFF
    #define POD_HDR2_2_HDR_SHIFT 0
#define  POD_IN0_HDR 0x6020
    #define POD_IN0_HDR_CC_RES_MASK 0x0000FFFF
    #define POD_IN0_HDR_CC_RES_SHIFT 0
    #define POD_IN0_HDR_CRC_MASK 0x00FF0000
    #define POD_IN0_HDR_CRC_SHIFT 16
#define  POD_IN1_HDR 0x6024
    #define POD_IN1_HDR_CC_RES_MASK 0x0000FFFF
    #define POD_IN1_HDR_CC_RES_SHIFT 0
    #define POD_IN1_HDR_CRC_MASK 0x00FF0000
    #define POD_IN1_HDR_CRC_SHIFT 16
#define  POD_IN2_HDR 0x6028
    #define POD_IN2_HDR_CC_RES_MASK 0x0000FFFF
    #define POD_IN2_HDR_CC_RES_SHIFT 0
    #define POD_IN2_HDR_CRC_MASK 0x00FF0000
    #define POD_IN2_HDR_CRC_SHIFT 16
#define  POD_IN_STATUS 0x602C
    #define SYNC_ERR_MASK 0x00000001
    #define SYNC_ERR_SHIFT 0
#define  PPC_BOOTSTRAP 0x10C4
    #define BOOT_CTRL_EN_MASK 0x00000001
    #define BOOT_CTRL_EN_SHIFT 0
    #define SPI_RATE_SEL_MASK 0x0000000C
    #define SPI_RATE_SEL_SHIFT 2
    #define I2C_SLAVE_ADDR_SEL_MASK 0x00000010
    #define I2C_SLAVE_ADDR_SEL_SHIFT 4
#define  PPC_CLOCK_CTRL 0x10A0
    #define SCC0_CLOCK_GATE_EN_MASK 0x00000004
    #define SCC0_CLOCK_GATE_EN_SHIFT 2
    #define SCC1_CLOCK_GATE_EN_MASK 0x00000008
    #define SCC1_CLOCK_GATE_EN_SHIFT 3
    #define SCC2_CLOCK_GATE_EN_MASK 0x00000010
    #define SCC2_CLOCK_GATE_EN_SHIFT 4
    #define SCC3_CLOCK_GATE_EN_MASK 0x00000020
    #define SCC3_CLOCK_GATE_EN_SHIFT 5
    #define I2C0_SLAVE_DIS_MASK 0x00000080
    #define I2C0_SLAVE_DIS_SHIFT 7
    #define I2C0_SLAVE_SAMPLE_RATE_MASK 0x00000F00
    #define I2C0_SLAVE_SAMPLE_RATE_SHIFT 8
#define  PPC_DEBUG_DATA 0x10F4
    #define PPC_DEBUG_DATA_DEBUG_DATA_MASK 0x000FFFFF
    #define PPC_DEBUG_DATA_DEBUG_DATA_SHIFT 0
#define  PPC_DUMMY_REG 0x10FC
    #define PPC_DUMMY_REG_DUMMY_REG_MASK 0xFFFFFFFF
    #define PPC_DUMMY_REG_DUMMY_REG_SHIFT 0
#define  PPC_HOST_INT_MASK 0x1098
    #define PPC_HOST_INT_MASK_INT_EN_GPIO_0_INT_MASK 0x00000001
    #define PPC_HOST_INT_MASK_INT_EN_GPIO_0_INT_SHIFT 0
    #define PPC_HOST_INT_MASK_INT_EN_GPIO_1_INT_MASK 0x00000002
    #define PPC_HOST_INT_MASK_INT_EN_GPIO_1_INT_SHIFT 1
    #define PPC_HOST_INT_MASK_INT_EN_GPIO_2_INT_MASK 0x00000004
    #define PPC_HOST_INT_MASK_INT_EN_GPIO_2_INT_SHIFT 2
    #define PPC_HOST_INT_MASK_INT_EN_GPIO_3_INT_MASK 0x00000008
    #define PPC_HOST_INT_MASK_INT_EN_GPIO_3_INT_SHIFT 3
    #define PPC_HOST_INT_MASK_INT_EN_GPIO_4_INT_MASK 0x00000010
    #define PPC_HOST_INT_MASK_INT_EN_GPIO_4_INT_SHIFT 4
    #define PPC_HOST_INT_MASK_INT_EN_I2C0_XFERDONE_MASK 0x00000040
    #define PPC_HOST_INT_MASK_INT_EN_I2C0_XFERDONE_SHIFT 6
    #define PPC_HOST_INT_MASK_INT_EN_I2C1_XFERDONE_MASK 0x00000080
    #define PPC_HOST_INT_MASK_INT_EN_I2C1_XFERDONE_SHIFT 7
    #define PPC_HOST_INT_MASK_INT_EN_SCC0_TXDONE_MASK 0x00000100
    #define PPC_HOST_INT_MASK_INT_EN_SCC0_TXDONE_SHIFT 8
    #define PPC_HOST_INT_MASK_INT_EN_SCC0_PARITY_DET_MASK 0x00000200
    #define PPC_HOST_INT_MASK_INT_EN_SCC0_PARITY_DET_SHIFT 9
    #define PPC_HOST_INT_MASK_INT_EN_SCC0_ERROR_MASK 0x00000400
    #define PPC_HOST_INT_MASK_INT_EN_SCC0_ERROR_SHIFT 10
    #define PPC_HOST_INT_MASK_INT_EN_SCC1_TXDONE_MASK 0x00000800
    #define PPC_HOST_INT_MASK_INT_EN_SCC1_TXDONE_SHIFT 11
    #define PPC_HOST_INT_MASK_INT_EN_SCC1_PARITY_DET_MASK 0x00001000
    #define PPC_HOST_INT_MASK_INT_EN_SCC1_PARITY_DET_SHIFT 12
    #define PPC_HOST_INT_MASK_INT_EN_SCC1_ERROR_MASK 0x00002000
    #define PPC_HOST_INT_MASK_INT_EN_SCC1_ERROR_SHIFT 13
    #define PPC_HOST_INT_MASK_INT_EN_SCC2_TXDONE_MASK 0x00004000
    #define PPC_HOST_INT_MASK_INT_EN_SCC2_TXDONE_SHIFT 14
    #define PPC_HOST_INT_MASK_INT_EN_SCC2_PARITY_DET_MASK 0x00008000
    #define PPC_HOST_INT_MASK_INT_EN_SCC2_PARITY_DET_SHIFT 15
    #define PPC_HOST_INT_MASK_INT_EN_SCC2_ERROR_MASK 0x00010000
    #define PPC_HOST_INT_MASK_INT_EN_SCC2_ERROR_SHIFT 16
    #define PPC_HOST_INT_MASK_INT_EN_SCC3_TXDONE_MASK 0x00020000
    #define PPC_HOST_INT_MASK_INT_EN_SCC3_TXDONE_SHIFT 17
    #define PPC_HOST_INT_MASK_INT_EN_SCC3_PARITY_DET_MASK 0x00040000
    #define PPC_HOST_INT_MASK_INT_EN_SCC3_PARITY_DET_SHIFT 18
    #define PPC_HOST_INT_MASK_INT_EN_SCC3_ERROR_MASK 0x00080000
    #define PPC_HOST_INT_MASK_INT_EN_SCC3_ERROR_SHIFT 19
    #define PPC_HOST_INT_MASK_INT_EN_I2C0_ARB_FAIL_MASK 0x00100000
    #define PPC_HOST_INT_MASK_INT_EN_I2C0_ARB_FAIL_SHIFT 20
    #define PPC_HOST_INT_MASK_INT_EN_I2C0_BUSY_ERROR_MASK 0x00200000
    #define PPC_HOST_INT_MASK_INT_EN_I2C0_BUSY_ERROR_SHIFT 21
    #define PPC_HOST_INT_MASK_INT_EN_CCSPI_RX_PACKET_DONE_MASK 0x00400000
    #define PPC_HOST_INT_MASK_INT_EN_CCSPI_RX_PACKET_DONE_SHIFT 22
    #define PPC_HOST_INT_MASK_INT_EN_CCSPI_TX_PACKET_DONE_MASK 0x00800000
    #define PPC_HOST_INT_MASK_INT_EN_CCSPI_TX_PACKET_DONE_SHIFT 23
    #define PPC_HOST_INT_MASK_INT_EN_SPI_DONE_MASK 0x01000000
    #define PPC_HOST_INT_MASK_INT_EN_SPI_DONE_SHIFT 24
    #define PPC_HOST_INT_MASK_INT_EN_I2C1_ARB_FAIL_MASK 0x02000000
    #define PPC_HOST_INT_MASK_INT_EN_I2C1_ARB_FAIL_SHIFT 25
    #define PPC_HOST_INT_MASK_INT_EN_I2C1_BUSY_ERROR_MASK 0x04000000
    #define PPC_HOST_INT_MASK_INT_EN_I2C1_BUSY_ERROR_SHIFT 26
#define  PPC_INT_STATUS 0x1094
    #define GPIO_0_INT_MASK 0x00000001
    #define GPIO_0_INT_SHIFT 0
    #define GPIO_1_INT_MASK 0x00000002
    #define GPIO_1_INT_SHIFT 1
    #define GPIO_2_INT_MASK 0x00000004
    #define GPIO_2_INT_SHIFT 2
    #define GPIO_3_INT_MASK 0x00000008
    #define GPIO_3_INT_SHIFT 3
    #define GPIO_4_INT_MASK 0x00000010
    #define GPIO_4_INT_SHIFT 4
    #define I2C0_XFERDONE_MASK 0x00000040
    #define I2C0_XFERDONE_SHIFT 6
    #define I2C1_XFERDONE_MASK 0x00000080
    #define I2C1_XFERDONE_SHIFT 7
    #define SCC0_TXDONE_MASK 0x00000100
    #define SCC0_TXDONE_SHIFT 8
    #define SCC0_PARITY_DET_MASK 0x00000200
    #define SCC0_PARITY_DET_SHIFT 9
    #define SCC0_ERROR_MASK 0x00000400
    #define SCC0_ERROR_SHIFT 10
    #define SCC1_TXDONE_MASK 0x00000800
    #define SCC1_TXDONE_SHIFT 11
    #define SCC1_PARITY_DET_MASK 0x00001000
    #define SCC1_PARITY_DET_SHIFT 12
    #define SCC1_ERROR_MASK 0x00002000
    #define SCC1_ERROR_SHIFT 13
    #define SCC2_TXDONE_MASK 0x00004000
    #define SCC2_TXDONE_SHIFT 14
    #define SCC2_PARITY_DET_MASK 0x00008000
    #define SCC2_PARITY_DET_SHIFT 15
    #define SCC2_ERROR_MASK 0x00010000
    #define SCC2_ERROR_SHIFT 16
    #define SCC3_TXDONE_MASK 0x00020000
    #define SCC3_TXDONE_SHIFT 17
    #define SCC3_PARITY_DET_MASK 0x00040000
    #define SCC3_PARITY_DET_SHIFT 18
    #define SCC3_ERROR_MASK 0x00080000
    #define SCC3_ERROR_SHIFT 19
    #define I2C0_ARB_FAIL_MASK 0x00100000
    #define I2C0_ARB_FAIL_SHIFT 20
    #define I2C0_BUSY_ERROR_MASK 0x00200000
    #define I2C0_BUSY_ERROR_SHIFT 21
    #define CCSPI_RX_PACKET_DONE_MASK 0x00400000
    #define CCSPI_RX_PACKET_DONE_SHIFT 22
    #define CCSPI_TX_PACKET_DONE_MASK 0x00800000
    #define CCSPI_TX_PACKET_DONE_SHIFT 23
    #define SPI_DONE_MASK 0x01000000
    #define SPI_DONE_SHIFT 24
    #define I2C1_ARB_FAIL_MASK 0x02000000
    #define I2C1_ARB_FAIL_SHIFT 25
    #define I2C1_BUSY_ERROR_MASK 0x04000000
    #define I2C1_BUSY_ERROR_SHIFT 26
#define  PPC_MIPS_INT_MASK 0x109C
    #define PPC_MIPS_INT_MASK_INT_EN_GPIO_0_INT_MASK 0x00000001
    #define PPC_MIPS_INT_MASK_INT_EN_GPIO_0_INT_SHIFT 0
    #define PPC_MIPS_INT_MASK_INT_EN_GPIO_1_INT_MASK 0x00000002
    #define PPC_MIPS_INT_MASK_INT_EN_GPIO_1_INT_SHIFT 1
    #define PPC_MIPS_INT_MASK_INT_EN_GPIO_2_INT_MASK 0x00000004
    #define PPC_MIPS_INT_MASK_INT_EN_GPIO_2_INT_SHIFT 2
    #define PPC_MIPS_INT_MASK_INT_EN_GPIO_3_INT_MASK 0x00000008
    #define PPC_MIPS_INT_MASK_INT_EN_GPIO_3_INT_SHIFT 3
    #define PPC_MIPS_INT_MASK_INT_EN_GPIO_4_INT_MASK 0x00000010
    #define PPC_MIPS_INT_MASK_INT_EN_GPIO_4_INT_SHIFT 4
    #define PPC_MIPS_INT_MASK_INT_EN_I2C0_XFERDONE_MASK 0x00000040
    #define PPC_MIPS_INT_MASK_INT_EN_I2C0_XFERDONE_SHIFT 6
    #define PPC_MIPS_INT_MASK_INT_EN_I2C1_XFERDONE_MASK 0x00000080
    #define PPC_MIPS_INT_MASK_INT_EN_I2C1_XFERDONE_SHIFT 7
    #define PPC_MIPS_INT_MASK_INT_EN_SCC0_TXDONE_MASK 0x00000100
    #define PPC_MIPS_INT_MASK_INT_EN_SCC0_TXDONE_SHIFT 8
    #define PPC_MIPS_INT_MASK_INT_EN_SCC0_PARITY_DET_MASK 0x00000200
    #define PPC_MIPS_INT_MASK_INT_EN_SCC0_PARITY_DET_SHIFT 9
    #define PPC_MIPS_INT_MASK_INT_EN_SCC0_ERROR_MASK 0x00000400
    #define PPC_MIPS_INT_MASK_INT_EN_SCC0_ERROR_SHIFT 10
    #define PPC_MIPS_INT_MASK_INT_EN_SCC1_TXDONE_MASK 0x00000800
    #define PPC_MIPS_INT_MASK_INT_EN_SCC1_TXDONE_SHIFT 11
    #define PPC_MIPS_INT_MASK_INT_EN_SCC1_PARITY_DET_MASK 0x00001000
    #define PPC_MIPS_INT_MASK_INT_EN_SCC1_PARITY_DET_SHIFT 12
    #define PPC_MIPS_INT_MASK_INT_EN_SCC1_ERROR_MASK 0x00002000
    #define PPC_MIPS_INT_MASK_INT_EN_SCC1_ERROR_SHIFT 13
    #define PPC_MIPS_INT_MASK_INT_EN_SCC2_TXDONE_MASK 0x00004000
    #define PPC_MIPS_INT_MASK_INT_EN_SCC2_TXDONE_SHIFT 14
    #define PPC_MIPS_INT_MASK_INT_EN_SCC2_PARITY_DET_MASK 0x00008000
    #define PPC_MIPS_INT_MASK_INT_EN_SCC2_PARITY_DET_SHIFT 15
    #define PPC_MIPS_INT_MASK_INT_EN_SCC2_ERROR_MASK 0x00010000
    #define PPC_MIPS_INT_MASK_INT_EN_SCC2_ERROR_SHIFT 16
    #define PPC_MIPS_INT_MASK_INT_EN_SCC3_TXDONE_MASK 0x00020000
    #define PPC_MIPS_INT_MASK_INT_EN_SCC3_TXDONE_SHIFT 17
    #define PPC_MIPS_INT_MASK_INT_EN_SCC3_PARITY_DET_MASK 0x00040000
    #define PPC_MIPS_INT_MASK_INT_EN_SCC3_PARITY_DET_SHIFT 18
    #define PPC_MIPS_INT_MASK_INT_EN_SCC3_ERROR_MASK 0x00080000
    #define PPC_MIPS_INT_MASK_INT_EN_SCC3_ERROR_SHIFT 19
    #define PPC_MIPS_INT_MASK_INT_EN_I2C0_ARB_FAIL_MASK 0x00100000
    #define PPC_MIPS_INT_MASK_INT_EN_I2C0_ARB_FAIL_SHIFT 20
    #define PPC_MIPS_INT_MASK_INT_EN_I2C0_BUSY_ERROR_MASK 0x00200000
    #define PPC_MIPS_INT_MASK_INT_EN_I2C0_BUSY_ERROR_SHIFT 21
    #define PPC_MIPS_INT_MASK_INT_EN_CCSPI_RX_PACKET_DONE_MASK 0x00400000
    #define PPC_MIPS_INT_MASK_INT_EN_CCSPI_RX_PACKET_DONE_SHIFT 22
    #define PPC_MIPS_INT_MASK_INT_EN_CCSPI_TX_PACKET_DONE_MASK 0x00800000
    #define PPC_MIPS_INT_MASK_INT_EN_CCSPI_TX_PACKET_DONE_SHIFT 23
    #define PPC_MIPS_INT_MASK_INT_EN_SPI_DONE_MASK 0x01000000
    #define PPC_MIPS_INT_MASK_INT_EN_SPI_DONE_SHIFT 24
    #define PPC_MIPS_INT_MASK_INT_EN_I2C1_ARB_FAIL_MASK 0x02000000
    #define PPC_MIPS_INT_MASK_INT_EN_I2C1_ARB_FAIL_SHIFT 25
    #define PPC_MIPS_INT_MASK_INT_EN_I2C1_BUSY_ERROR_MASK 0x04000000
    #define PPC_MIPS_INT_MASK_INT_EN_I2C1_BUSY_ERROR_SHIFT 26
#define  PPC_SFT_RSTN 0x10A4
    #define PPC_SFT_RSTN_MASK 0x00000001
    #define PPC_SFT_RSTN_SHIFT 0
    #define CCSPI_SFT_RSTN_MASK 0x00000002
    #define CCSPI_SFT_RSTN_SHIFT 1
#define  PROC1_DBG_INBOUND0 0xA460
    #define PROC1_DBG_INBOUND0_DATA_MASK 0xFFFFFFFF
    #define PROC1_DBG_INBOUND0_DATA_SHIFT 0
#define  PROC1_DBG_INBOUND1 0xA4A0
    #define PROC1_DBG_INBOUND1_DATA_MASK 0xFFFFFFFF
    #define PROC1_DBG_INBOUND1_DATA_SHIFT 0
#define  PROC1_DBG_INBOUND2 0xA4A4
    #define PROC1_DBG_INBOUND2_DATA_MASK 0xFFFFFFFF
    #define PROC1_DBG_INBOUND2_DATA_SHIFT 0
#define  PROC1_DBG_INBOUND3 0xA4A8
    #define PROC1_DBG_INBOUND3_DATA_MASK 0xFFFFFFFF
    #define PROC1_DBG_INBOUND3_DATA_SHIFT 0
#define  PROC1_DBG_INBOUND4 0xA4AC
    #define PROC1_DBG_INBOUND4_DATA_MASK 0xFFFFFFFF
    #define PROC1_DBG_INBOUND4_DATA_SHIFT 0
#define  PROC1_DBG_OUTBOUND 0xA464
    #define PROC1_DBG_OUTBOUND_DATA_MASK 0xFFFFFFFF
    #define PROC1_DBG_OUTBOUND_DATA_SHIFT 0
#define  PROC1_DEBUG_REG1 0xA470
    #define PROC1_DEBUG_REG1_DATA_MASK 0xFFFFFFFF
    #define PROC1_DEBUG_REG1_DATA_SHIFT 0
#define  PROC1_DEBUG_REG2 0xA474
    #define PROC1_DEBUG_REG2_DATA_MASK 0xFFFFFFFF
    #define PROC1_DEBUG_REG2_DATA_SHIFT 0
#define  PROC1_DEBUG_REG3 0xA478
    #define PROC1_DEBUG_REG3_DATA_MASK 0xFFFFFFFF
    #define PROC1_DEBUG_REG3_DATA_SHIFT 0
#define  PROC1_DEBUG_REG4 0xA47C
    #define PROC1_DEBUG_REG4_DATA_MASK 0xFFFFFFFF
    #define PROC1_DEBUG_REG4_DATA_SHIFT 0
#define  PROC1_DEBUG_REG5 0xA488
    #define PROC1_DEBUG_REG5_DATA_MASK 0xFFFFFFFF
    #define PROC1_DEBUG_REG5_DATA_SHIFT 0
#define  PROC1_DEBUG_REG6 0xA48C
    #define PROC1_DEBUG_REG6_DATA_MASK 0xFFFFFFFF
    #define PROC1_DEBUG_REG6_DATA_SHIFT 0
#define  PROC1_DUMMY_REG 0xA4FC
    #define PROC1_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define PROC1_DUMMY_REG_DATA_SHIFT 0
#define  PROC1_FB_TOP 0xA404
    #define PROC1_FB_TOP_BASE_MASK 0x1FFFFC00
    #define PROC1_FB_TOP_BASE_SHIFT 10
#define  PROC1_HOST_INT_MASK 0xA4E4
    #define PROC1_HOST_INT_MASK_INT_EN_OUTBOUND_CALL0_MASK 0x00000001
    #define PROC1_HOST_INT_MASK_INT_EN_OUTBOUND_CALL0_SHIFT 0
    #define PROC1_HOST_INT_MASK_INT_EN_OUTBOUND_CALL1_MASK 0x00000002
    #define PROC1_HOST_INT_MASK_INT_EN_OUTBOUND_CALL1_SHIFT 1
    #define PROC1_HOST_INT_MASK_INT_EN_OUTBOUND_DBG_MASK 0x00000004
    #define PROC1_HOST_INT_MASK_INT_EN_OUTBOUND_DBG_SHIFT 2
    #define PROC1_HOST_INT_MASK_INT_EN_PROC_HANG_MASK 0x80000000
    #define PROC1_HOST_INT_MASK_INT_EN_PROC_HANG_SHIFT 31
#define  PROC1_HOST_INT_STATUS 0xA4E0
    #define PROC1_HOST_INT_STATUS_OUTBOUND_CALL0_MASK 0x00000001
    #define PROC1_HOST_INT_STATUS_OUTBOUND_CALL0_SHIFT 0
    #define PROC1_HOST_INT_STATUS_OUTBOUND_CALL1_MASK 0x00000002
    #define PROC1_HOST_INT_STATUS_OUTBOUND_CALL1_SHIFT 1
    #define PROC1_HOST_INT_STATUS_OUTBOUND_DBG_MASK 0x00000004
    #define PROC1_HOST_INT_STATUS_OUTBOUND_DBG_SHIFT 2
    #define PROC1_HOST_INT_STATUS_PROC_HANG_MASK 0x80000000
    #define PROC1_HOST_INT_STATUS_PROC_HANG_SHIFT 31
#define  PROC1_INBOUND_CALL_0 0xA420
    #define PROC1_INBOUND_CALL_0_DATA_MASK 0xFFFFFFFF
    #define PROC1_INBOUND_CALL_0_DATA_SHIFT 0
#define  PROC1_INBOUND_CALL_1 0xA424
    #define PROC1_INBOUND_CALL_1_DATA_MASK 0xFFFFFFFF
    #define PROC1_INBOUND_CALL_1_DATA_SHIFT 0
#define  PROC1_IPC_CALL 0xA4F0
    #define PROC1_IPC_CALL_DATA_MASK 0xFFFFFFFF
    #define PROC1_IPC_CALL_DATA_SHIFT 0
#define  PROC1_MBD_EMPTY 0xA4F4
    #define PROC1_MBD_EMPTY_EMPTY_MASK 0x00000001
    #define PROC1_MBD_EMPTY_EMPTY_SHIFT 0
#define  PROC1_MC_ARB 0xA418
    #define PROC1_MC_ARB_ARC_REQ_CNT_LIMIT_MASK 0x0000000F
    #define PROC1_MC_ARB_ARC_REQ_CNT_LIMIT_SHIFT 0
    #define PROC1_MC_ARB_IBB_REQ_CNT_LIMIT_MASK 0x000000F0
    #define PROC1_MC_ARB_IBB_REQ_CNT_LIMIT_SHIFT 4
    #define PROC1_MC_ARB_MBD_REQ_CNT_LIMIT_MASK 0x00000F00
    #define PROC1_MC_ARB_MBD_REQ_CNT_LIMIT_SHIFT 8
#define  PROC1_MERGED_WRITE_CTL 0xA410
    #define PROC1_MERGED_WRITE_CTL_TIMER_MASK 0x000003FF
    #define PROC1_MERGED_WRITE_CTL_TIMER_SHIFT 0
#define  PROC1_MMREG_APER 0xA408
    #define PROC1_MMREG_APER_BASE_MASK 0x00001FFF
    #define PROC1_MMREG_APER_BASE_SHIFT 0
    #define PROC1_MMREG_APER_SIZE_MASK 0x1FFF0000
    #define PROC1_MMREG_APER_SIZE_SHIFT 16
#define  PROC1_MSG_DATA_0 0xA430
    #define PROC1_MSG_DATA_0_DATA_MASK 0xFFFFFFFF
    #define PROC1_MSG_DATA_0_DATA_SHIFT 0
#define  PROC1_MSG_DATA_1 0xA434
    #define PROC1_MSG_DATA_1_DATA_MASK 0xFFFFFFFF
    #define PROC1_MSG_DATA_1_DATA_SHIFT 0
#define  PROC1_MSG_DATA_10 0xA458
    #define PROC1_MSG_DATA_10_DATA_MASK 0xFFFFFFFF
    #define PROC1_MSG_DATA_10_DATA_SHIFT 0
#define  PROC1_MSG_DATA_11 0xA45C
    #define PROC1_MSG_DATA_11_DATA_MASK 0xFFFFFFFF
    #define PROC1_MSG_DATA_11_DATA_SHIFT 0
#define  PROC1_MSG_DATA_2 0xA438
    #define PROC1_MSG_DATA_2_DATA_MASK 0xFFFFFFFF
    #define PROC1_MSG_DATA_2_DATA_SHIFT 0
#define  PROC1_MSG_DATA_3 0xA43C
    #define PROC1_MSG_DATA_3_DATA_MASK 0xFFFFFFFF
    #define PROC1_MSG_DATA_3_DATA_SHIFT 0
#define  PROC1_MSG_DATA_4 0xA440
    #define PROC1_MSG_DATA_4_DATA_MASK 0xFFFFFFFF
    #define PROC1_MSG_DATA_4_DATA_SHIFT 0
#define  PROC1_MSG_DATA_5 0xA444
    #define PROC1_MSG_DATA_5_DATA_MASK 0xFFFFFFFF
    #define PROC1_MSG_DATA_5_DATA_SHIFT 0
#define  PROC1_MSG_DATA_6 0xA448
    #define PROC1_MSG_DATA_6_DATA_MASK 0xFFFFFFFF
    #define PROC1_MSG_DATA_6_DATA_SHIFT 0
#define  PROC1_MSG_DATA_7 0xA44C
    #define PROC1_MSG_DATA_7_DATA_MASK 0xFFFFFFFF
    #define PROC1_MSG_DATA_7_DATA_SHIFT 0
#define  PROC1_MSG_DATA_8 0xA450
    #define PROC1_MSG_DATA_8_DATA_MASK 0xFFFFFFFF
    #define PROC1_MSG_DATA_8_DATA_SHIFT 0
#define  PROC1_MSG_DATA_9 0xA454
    #define PROC1_MSG_DATA_9_DATA_MASK 0xFFFFFFFF
    #define PROC1_MSG_DATA_9_DATA_SHIFT 0
#define  PROC1_OUTBOUND_CALL_0 0xA428
    #define PROC1_OUTBOUND_CALL_0_DATA_MASK 0xFFFFFFFF
    #define PROC1_OUTBOUND_CALL_0_DATA_SHIFT 0
#define  PROC1_OUTBOUND_CALL_1 0xA42C
    #define PROC1_OUTBOUND_CALL_1_DATA_MASK 0xFFFFFFFF
    #define PROC1_OUTBOUND_CALL_1_DATA_SHIFT 0
#define  PROC1_PROC_INT_MASK 0xA4EC
    #define PROC1_PROC_INT_MASK_INT_EN_INBOUND_CALL0_MASK 0x00000001
    #define PROC1_PROC_INT_MASK_INT_EN_INBOUND_CALL0_SHIFT 0
    #define PROC1_PROC_INT_MASK_INT_EN_INBOUND_CALL1_MASK 0x00000002
    #define PROC1_PROC_INT_MASK_INT_EN_INBOUND_CALL1_SHIFT 1
    #define PROC1_PROC_INT_MASK_INT_EN_IPC_CALL_MASK 0x00000008
    #define PROC1_PROC_INT_MASK_INT_EN_IPC_CALL_SHIFT 3
    #define PROC1_PROC_INT_MASK_INT_EN_DBG_INBOUND0_MASK 0x00000020
    #define PROC1_PROC_INT_MASK_INT_EN_DBG_INBOUND0_SHIFT 5
    #define PROC1_PROC_INT_MASK_INT_EN_DBG_INBOUND1_MASK 0x00000040
    #define PROC1_PROC_INT_MASK_INT_EN_DBG_INBOUND1_SHIFT 6
    #define PROC1_PROC_INT_MASK_INT_EN_DBG_INBOUND2_MASK 0x00000080
    #define PROC1_PROC_INT_MASK_INT_EN_DBG_INBOUND2_SHIFT 7
    #define PROC1_PROC_INT_MASK_INT_EN_DBG_INBOUND3_MASK 0x00000100
    #define PROC1_PROC_INT_MASK_INT_EN_DBG_INBOUND3_SHIFT 8
    #define PROC1_PROC_INT_MASK_INT_EN_DBG_INBOUND4_MASK 0x00000200
    #define PROC1_PROC_INT_MASK_INT_EN_DBG_INBOUND4_SHIFT 9
#define  PROC1_PROC_INT_STATUS 0xA4E8
    #define PROC1_PROC_INT_STATUS_INBOUND_CALL0_MASK 0x00000001
    #define PROC1_PROC_INT_STATUS_INBOUND_CALL0_SHIFT 0
    #define PROC1_PROC_INT_STATUS_INBOUND_CALL1_MASK 0x00000002
    #define PROC1_PROC_INT_STATUS_INBOUND_CALL1_SHIFT 1
    #define PROC1_PROC_INT_STATUS_IPC_CALL_MASK 0x00000008
    #define PROC1_PROC_INT_STATUS_IPC_CALL_SHIFT 3
    #define PROC1_PROC_INT_STATUS_DBG_INBOUND0_MASK 0x00000020
    #define PROC1_PROC_INT_STATUS_DBG_INBOUND0_SHIFT 5
    #define PROC1_PROC_INT_STATUS_DBG_INBOUND1_MASK 0x00000040
    #define PROC1_PROC_INT_STATUS_DBG_INBOUND1_SHIFT 6
    #define PROC1_PROC_INT_STATUS_DBG_INBOUND2_MASK 0x00000080
    #define PROC1_PROC_INT_STATUS_DBG_INBOUND2_SHIFT 7
    #define PROC1_PROC_INT_STATUS_DBG_INBOUND3_MASK 0x00000100
    #define PROC1_PROC_INT_STATUS_DBG_INBOUND3_SHIFT 8
    #define PROC1_PROC_INT_STATUS_DBG_INBOUND4_MASK 0x00000200
    #define PROC1_PROC_INT_STATUS_DBG_INBOUND4_SHIFT 9
#define  PROC1_RST 0xA414
    #define PROC1_RST_SOFT_RSTN_MASK 0x00000001
    #define PROC1_RST_SOFT_RSTN_SHIFT 0
    #define PROC1_RST_MBD_RSTN_MASK 0x00000004
    #define PROC1_RST_MBD_RSTN_SHIFT 2
    #define PROC1_RST_MBD_FLUSH_MASK 0x80000000
    #define PROC1_RST_MBD_FLUSH_SHIFT 31
#define  PROC1_SHADOW_IBB_CTRL 0xA4B0
    #define PROC1_SHADOW_IBB_CTRL_SHADOW_IBB_CTRL_MASK 0xFFFFFFFF
    #define PROC1_SHADOW_IBB_CTRL_SHADOW_IBB_CTRL_SHIFT 0
#define  PROC1_SHADOW_IBB_RB_ADR 0xA4B8
    #define PROC1_SHADOW_IBB_RB_ADR_SHADOW_IBB_RB_ADR_MASK 0xFFFFFFFF
    #define PROC1_SHADOW_IBB_RB_ADR_SHADOW_IBB_RB_ADR_SHIFT 0
#define  PROC1_SHADOW_IBB_RB_HEAD 0xA4C8
    #define PROC1_SHADOW_IBB_RB_HEAD_SHADOW_IBB_RB_HEAD_MASK 0xFFFFFFFF
    #define PROC1_SHADOW_IBB_RB_HEAD_SHADOW_IBB_RB_HEAD_SHIFT 0
#define  PROC1_SHADOW_IBB_RB_TAIL 0xA4BC
    #define PROC1_SHADOW_IBB_RB_TAIL_SHADOW_IBB_RB_TAIL_MASK 0xFFFFFFFF
    #define PROC1_SHADOW_IBB_RB_TAIL_SHADOW_IBB_RB_TAIL_SHIFT 0
#define  PROC1_SHADOW_IBB_RB_TAIL_READ 0xA4C0
    #define PROC1_SHADOW_IBB_RB_TAIL_READ_SHADOW_IBB_RB_TAIL_READ_MASK 0xFFFFFFFF
    #define PROC1_SHADOW_IBB_RB_TAIL_READ_SHADOW_IBB_RB_TAIL_READ_SHIFT 0
#define  PROC1_SHADOW_IBB_STATUS 0xA4B4
    #define PROC1_SHADOW_IBB_STATUS_SHADOW_IBB_STATUS_MASK 0xFFFFFFFF
    #define PROC1_SHADOW_IBB_STATUS_SHADOW_IBB_STATUS_SHIFT 0
#define  PROC1_WATCHDOG_CNT 0xA480
    #define PROC1_WATCHDOG_CNT_DATA_MASK 0xFFFFFFFF
    #define PROC1_WATCHDOG_CNT_DATA_SHIFT 0
#define  PROC1_WATCHDOG_COMPARE 0xA484
    #define PROC1_WATCHDOG_COMPARE_DATA_MASK 0xFFFFFFFF
    #define PROC1_WATCHDOG_COMPARE_DATA_SHIFT 0
#define  PROC2_DBG_INBOUND0 0xA860
    #define PROC2_DBG_INBOUND0_DATA_MASK 0xFFFFFFFF
    #define PROC2_DBG_INBOUND0_DATA_SHIFT 0
#define  PROC2_DBG_INBOUND1 0xA8A0
    #define PROC2_DBG_INBOUND1_DATA_MASK 0xFFFFFFFF
    #define PROC2_DBG_INBOUND1_DATA_SHIFT 0
#define  PROC2_DBG_INBOUND2 0xA8A4
    #define PROC2_DBG_INBOUND2_DATA_MASK 0xFFFFFFFF
    #define PROC2_DBG_INBOUND2_DATA_SHIFT 0
#define  PROC2_DBG_INBOUND3 0xA8A8
    #define PROC2_DBG_INBOUND3_DATA_MASK 0xFFFFFFFF
    #define PROC2_DBG_INBOUND3_DATA_SHIFT 0
#define  PROC2_DBG_INBOUND4 0xA8AC
    #define PROC2_DBG_INBOUND4_DATA_MASK 0xFFFFFFFF
    #define PROC2_DBG_INBOUND4_DATA_SHIFT 0
#define  PROC2_DBG_OUTBOUND 0xA864
    #define PROC2_DBG_OUTBOUND_DATA_MASK 0xFFFFFFFF
    #define PROC2_DBG_OUTBOUND_DATA_SHIFT 0
#define  PROC2_DMA_CONFIG 0xA898
    #define PROC2_DMA_CONFIG_LENGTH_MASK 0x000007FF
    #define PROC2_DMA_CONFIG_LENGTH_SHIFT 0
    #define PROC2_DMA_CONFIG_DIRECTION_MASK 0x00010000
    #define PROC2_DMA_CONFIG_DIRECTION_SHIFT 16
    #define PROC2_DMA_CONFIG_QUEUE_WR_EN_MASK 0x01000000
    #define PROC2_DMA_CONFIG_QUEUE_WR_EN_SHIFT 24
    #define PROC2_DMA_CONFIG_DMA_EN_MASK 0x02000000
    #define PROC2_DMA_CONFIG_DMA_EN_SHIFT 25
#define  PROC2_DMA_DCCM 0xA890
    #define PROC2_DMA_DCCM_START_ADR_MASK 0xFFFFFFFC
    #define PROC2_DMA_DCCM_START_ADR_SHIFT 2
#define  PROC2_DMA_FB 0xA894
    #define PROC2_DMA_FB_START_ADR_MASK 0x1FFFFFFC
    #define PROC2_DMA_FB_START_ADR_SHIFT 2
#define  PROC2_DMA_STATUS 0xA89C
    #define PROC2_DMA_STATUS_PENDING_NUM_MASK 0x0000000F
    #define PROC2_DMA_STATUS_PENDING_NUM_SHIFT 0
    #define PROC2_DMA_STATUS_QUEUE_FULL_MASK 0x00000010
    #define PROC2_DMA_STATUS_QUEUE_FULL_SHIFT 4
    #define PROC2_DMA_STATUS_QUEUE_EMPTY_MASK 0x00000020
    #define PROC2_DMA_STATUS_QUEUE_EMPTY_SHIFT 5
#define  PROC2_FB_TOP 0xA804
    #define PROC2_FB_TOP_BASE_MASK 0x1FFFFC00
    #define PROC2_FB_TOP_BASE_SHIFT 10
#define  PROC2_HOST_INT_MASK 0xA8E4
    #define PROC2_HOST_INT_MASK_INT_EN_OUTBOUND_CALL0_MASK 0x00000001
    #define PROC2_HOST_INT_MASK_INT_EN_OUTBOUND_CALL0_SHIFT 0
    #define PROC2_HOST_INT_MASK_INT_EN_OUTBOUND_CALL1_MASK 0x00000002
    #define PROC2_HOST_INT_MASK_INT_EN_OUTBOUND_CALL1_SHIFT 1
    #define PROC2_HOST_INT_MASK_INT_EN_OUTBOUND_DBG_MASK 0x00000004
    #define PROC2_HOST_INT_MASK_INT_EN_OUTBOUND_DBG_SHIFT 2
    #define INT_EN_PROC2_HANG_MASK 0x80000000
    #define INT_EN_PROC2_HANG_SHIFT 31
#define  PROC2_HOST_INT_STATUS 0xA8E0
    #define PROC2_HOST_INT_STATUS_OUTBOUND_CALL0_MASK 0x00000001
    #define PROC2_HOST_INT_STATUS_OUTBOUND_CALL0_SHIFT 0
    #define PROC2_HOST_INT_STATUS_OUTBOUND_CALL1_MASK 0x00000002
    #define PROC2_HOST_INT_STATUS_OUTBOUND_CALL1_SHIFT 1
    #define PROC2_HOST_INT_STATUS_OUTBOUND_DBG_MASK 0x00000004
    #define PROC2_HOST_INT_STATUS_OUTBOUND_DBG_SHIFT 2
    #define PROC2_HANG_MASK 0x80000000
    #define PROC2_HANG_SHIFT 31
#define  PROC2_INBOUND_CALL_0 0xA820
    #define PROC2_INBOUND_CALL_0_DATA_MASK 0xFFFFFFFF
    #define PROC2_INBOUND_CALL_0_DATA_SHIFT 0
#define  PROC2_INBOUND_CALL_1 0xA824
    #define PROC2_INBOUND_CALL_1_DATA_MASK 0xFFFFFFFF
    #define PROC2_INBOUND_CALL_1_DATA_SHIFT 0
#define  PROC2_IPC_CALL 0xA8F0
    #define PROC2_IPC_CALL_DATA_MASK 0xFFFFFFFF
    #define PROC2_IPC_CALL_DATA_SHIFT 0
#define  PROC2_MC_ARB 0xA818
    #define PROC2_MC_ARB_ARC_REQ_CNT_LIMIT_MASK 0x0000000F
    #define PROC2_MC_ARB_ARC_REQ_CNT_LIMIT_SHIFT 0
    #define PROC2_MC_ARB_DMA_REQ_CNT_LIMIT_MASK 0x000000F0
    #define PROC2_MC_ARB_DMA_REQ_CNT_LIMIT_SHIFT 4
#define  PROC2_MERGED_WRITE_CTL 0xA810
    #define PROC2_MERGED_WRITE_CTL_TIMER_MASK 0x000003FF
    #define PROC2_MERGED_WRITE_CTL_TIMER_SHIFT 0
#define  PROC2_MMREG_APER 0xA808
    #define PROC2_MMREG_APER_BASE_MASK 0x00001FFF
    #define PROC2_MMREG_APER_BASE_SHIFT 0
    #define PROC2_MMREG_APER_SIZE_MASK 0x1FFF0000
    #define PROC2_MMREG_APER_SIZE_SHIFT 16
#define  PROC2_MSG_DATA_0 0xA830
    #define PROC2_MSG_DATA_0_DATA_MASK 0xFFFFFFFF
    #define PROC2_MSG_DATA_0_DATA_SHIFT 0
#define  PROC2_MSG_DATA_1 0xA834
    #define PROC2_MSG_DATA_1_DATA_MASK 0xFFFFFFFF
    #define PROC2_MSG_DATA_1_DATA_SHIFT 0
#define  PROC2_MSG_DATA_10 0xA858
    #define PROC2_MSG_DATA_10_DATA_MASK 0xFFFFFFFF
    #define PROC2_MSG_DATA_10_DATA_SHIFT 0
#define  PROC2_MSG_DATA_11 0xA85C
    #define PROC2_MSG_DATA_11_DATA_MASK 0xFFFFFFFF
    #define PROC2_MSG_DATA_11_DATA_SHIFT 0
#define  PROC2_MSG_DATA_2 0xA838
    #define PROC2_MSG_DATA_2_DATA_MASK 0xFFFFFFFF
    #define PROC2_MSG_DATA_2_DATA_SHIFT 0
#define  PROC2_MSG_DATA_3 0xA83C
    #define PROC2_MSG_DATA_3_DATA_MASK 0xFFFFFFFF
    #define PROC2_MSG_DATA_3_DATA_SHIFT 0
#define  PROC2_MSG_DATA_4 0xA840
    #define PROC2_MSG_DATA_4_DATA_MASK 0xFFFFFFFF
    #define PROC2_MSG_DATA_4_DATA_SHIFT 0
#define  PROC2_MSG_DATA_5 0xA844
    #define PROC2_MSG_DATA_5_DATA_MASK 0xFFFFFFFF
    #define PROC2_MSG_DATA_5_DATA_SHIFT 0
#define  PROC2_MSG_DATA_6 0xA848
    #define PROC2_MSG_DATA_6_DATA_MASK 0xFFFFFFFF
    #define PROC2_MSG_DATA_6_DATA_SHIFT 0
#define  PROC2_MSG_DATA_7 0xA84C
    #define PROC2_MSG_DATA_7_DATA_MASK 0xFFFFFFFF
    #define PROC2_MSG_DATA_7_DATA_SHIFT 0
#define  PROC2_MSG_DATA_8 0xA850
    #define PROC2_MSG_DATA_8_DATA_MASK 0xFFFFFFFF
    #define PROC2_MSG_DATA_8_DATA_SHIFT 0
#define  PROC2_MSG_DATA_9 0xA854
    #define PROC2_MSG_DATA_9_DATA_MASK 0xFFFFFFFF
    #define PROC2_MSG_DATA_9_DATA_SHIFT 0
#define  PROC2_OUTBOUND_CALL_0 0xA828
    #define PROC2_OUTBOUND_CALL_0_DATA_MASK 0xFFFFFFFF
    #define PROC2_OUTBOUND_CALL_0_DATA_SHIFT 0
#define  PROC2_OUTBOUND_CALL_1 0xA82C
    #define PROC2_OUTBOUND_CALL_1_DATA_MASK 0xFFFFFFFF
    #define PROC2_OUTBOUND_CALL_1_DATA_SHIFT 0
#define  PROC2_PROC2_INT_MASK 0xA8EC
    #define PROC2_PROC2_INT_MASK_INT_EN_INBOUND_CALL0_MASK 0x00000001
    #define PROC2_PROC2_INT_MASK_INT_EN_INBOUND_CALL0_SHIFT 0
    #define PROC2_PROC2_INT_MASK_INT_EN_INBOUND_CALL1_MASK 0x00000002
    #define PROC2_PROC2_INT_MASK_INT_EN_INBOUND_CALL1_SHIFT 1
    #define PROC2_PROC2_INT_MASK_INT_EN_IPC_CALL_MASK 0x00000008
    #define PROC2_PROC2_INT_MASK_INT_EN_IPC_CALL_SHIFT 3
    #define PROC2_PROC2_INT_MASK_INT_EN_DMA_COMPLETE_MASK 0x00000010
    #define PROC2_PROC2_INT_MASK_INT_EN_DMA_COMPLETE_SHIFT 4
    #define PROC2_PROC2_INT_MASK_INT_EN_DBG_INBOUND0_MASK 0x00000020
    #define PROC2_PROC2_INT_MASK_INT_EN_DBG_INBOUND0_SHIFT 5
    #define PROC2_PROC2_INT_MASK_INT_EN_DBG_INBOUND1_MASK 0x00000040
    #define PROC2_PROC2_INT_MASK_INT_EN_DBG_INBOUND1_SHIFT 6
    #define PROC2_PROC2_INT_MASK_INT_EN_DBG_INBOUND2_MASK 0x00000080
    #define PROC2_PROC2_INT_MASK_INT_EN_DBG_INBOUND2_SHIFT 7
    #define PROC2_PROC2_INT_MASK_INT_EN_DBG_INBOUND3_MASK 0x00000100
    #define PROC2_PROC2_INT_MASK_INT_EN_DBG_INBOUND3_SHIFT 8
    #define PROC2_PROC2_INT_MASK_INT_EN_DBG_INBOUND4_MASK 0x00000200
    #define PROC2_PROC2_INT_MASK_INT_EN_DBG_INBOUND4_SHIFT 9
#define  PROC2_PROC2_INT_STATUS 0xA8E8
    #define PROC2_PROC2_INT_STATUS_INBOUND_CALL0_MASK 0x00000001
    #define PROC2_PROC2_INT_STATUS_INBOUND_CALL0_SHIFT 0
    #define PROC2_PROC2_INT_STATUS_INBOUND_CALL1_MASK 0x00000002
    #define PROC2_PROC2_INT_STATUS_INBOUND_CALL1_SHIFT 1
    #define PROC2_PROC2_INT_STATUS_IPC_CALL_MASK 0x00000008
    #define PROC2_PROC2_INT_STATUS_IPC_CALL_SHIFT 3
    #define PROC2_PROC2_INT_STATUS_DMA_COMPLETE_MASK 0x00000010
    #define PROC2_PROC2_INT_STATUS_DMA_COMPLETE_SHIFT 4
    #define PROC2_PROC2_INT_STATUS_DBG_INBOUND0_MASK 0x00000020
    #define PROC2_PROC2_INT_STATUS_DBG_INBOUND0_SHIFT 5
    #define PROC2_PROC2_INT_STATUS_DBG_INBOUND1_MASK 0x00000040
    #define PROC2_PROC2_INT_STATUS_DBG_INBOUND1_SHIFT 6
    #define PROC2_PROC2_INT_STATUS_DBG_INBOUND2_MASK 0x00000080
    #define PROC2_PROC2_INT_STATUS_DBG_INBOUND2_SHIFT 7
    #define PROC2_PROC2_INT_STATUS_DBG_INBOUND3_MASK 0x00000100
    #define PROC2_PROC2_INT_STATUS_DBG_INBOUND3_SHIFT 8
    #define PROC2_PROC2_INT_STATUS_DBG_INBOUND4_MASK 0x00000200
    #define PROC2_PROC2_INT_STATUS_DBG_INBOUND4_SHIFT 9
#define  PROC2_RST 0xA814
    #define PROC2_RST_SOFT_RSTN_MASK 0x00000001
    #define PROC2_RST_SOFT_RSTN_SHIFT 0
#define  PROC2_WATCHDOG_CNT 0xA880
    #define PROC2_WATCHDOG_CNT_DATA_MASK 0xFFFFFFFF
    #define PROC2_WATCHDOG_CNT_DATA_SHIFT 0
#define  PROC2_WATCHDOG_COMPARE 0xA884
    #define PROC2_WATCHDOG_COMPARE_DATA_MASK 0xFFFFFFFF
    #define PROC2_WATCHDOG_COMPARE_DATA_SHIFT 0
#define  PROC3_DBG_INBOUND0 0xAC60
    #define PROC3_DBG_INBOUND0_DATA_MASK 0xFFFFFFFF
    #define PROC3_DBG_INBOUND0_DATA_SHIFT 0
#define  PROC3_DBG_INBOUND1 0xACA0
    #define PROC3_DBG_INBOUND1_DATA_MASK 0xFFFFFFFF
    #define PROC3_DBG_INBOUND1_DATA_SHIFT 0
#define  PROC3_DBG_INBOUND2 0xACA4
    #define PROC3_DBG_INBOUND2_DATA_MASK 0xFFFFFFFF
    #define PROC3_DBG_INBOUND2_DATA_SHIFT 0
#define  PROC3_DBG_INBOUND3 0xACA8
    #define PROC3_DBG_INBOUND3_DATA_MASK 0xFFFFFFFF
    #define PROC3_DBG_INBOUND3_DATA_SHIFT 0
#define  PROC3_DBG_INBOUND4 0xACAC
    #define PROC3_DBG_INBOUND4_DATA_MASK 0xFFFFFFFF
    #define PROC3_DBG_INBOUND4_DATA_SHIFT 0
#define  PROC3_DBG_OUTBOUND 0xAC64
    #define PROC3_DBG_OUTBOUND_DATA_MASK 0xFFFFFFFF
    #define PROC3_DBG_OUTBOUND_DATA_SHIFT 0
#define  PROC3_DMA_CONFIG 0xAC98
    #define PROC3_DMA_CONFIG_LENGTH_MASK 0x000003FF
    #define PROC3_DMA_CONFIG_LENGTH_SHIFT 0
    #define PROC3_DMA_CONFIG_DIRECTION_MASK 0x00010000
    #define PROC3_DMA_CONFIG_DIRECTION_SHIFT 16
    #define PROC3_DMA_CONFIG_QUEUE_WR_EN_MASK 0x01000000
    #define PROC3_DMA_CONFIG_QUEUE_WR_EN_SHIFT 24
    #define PROC3_DMA_CONFIG_DMA_EN_MASK 0x02000000
    #define PROC3_DMA_CONFIG_DMA_EN_SHIFT 25
#define  PROC3_DMA_DCCM 0xAC90
    #define PROC3_DMA_DCCM_START_ADR_MASK 0xFFFFFFF8
    #define PROC3_DMA_DCCM_START_ADR_SHIFT 3
#define  PROC3_DMA_FB 0xAC94
    #define PROC3_DMA_FB_START_ADR_MASK 0x1FFFFFF8
    #define PROC3_DMA_FB_START_ADR_SHIFT 3
#define  PROC3_DMA_STATUS 0xAC9C
    #define PROC3_DMA_STATUS_PENDING_NUM_MASK 0x0000000F
    #define PROC3_DMA_STATUS_PENDING_NUM_SHIFT 0
    #define PROC3_DMA_STATUS_QUEUE_FULL_MASK 0x00000010
    #define PROC3_DMA_STATUS_QUEUE_FULL_SHIFT 4
    #define PROC3_DMA_STATUS_QUEUE_EMPTY_MASK 0x00000020
    #define PROC3_DMA_STATUS_QUEUE_EMPTY_SHIFT 5
#define  PROC3_FB_TOP 0xAC04
    #define PROC3_FB_TOP_BASE_MASK 0x1FFFFC00
    #define PROC3_FB_TOP_BASE_SHIFT 10
#define  PROC3_HOST_INT_MASK 0xACE4
    #define PROC3_HOST_INT_MASK_INT_EN_OUTBOUND_CALL0_MASK 0x00000001
    #define PROC3_HOST_INT_MASK_INT_EN_OUTBOUND_CALL0_SHIFT 0
    #define PROC3_HOST_INT_MASK_INT_EN_OUTBOUND_CALL1_MASK 0x00000002
    #define PROC3_HOST_INT_MASK_INT_EN_OUTBOUND_CALL1_SHIFT 1
    #define PROC3_HOST_INT_MASK_INT_EN_OUTBOUND_DBG_MASK 0x00000004
    #define PROC3_HOST_INT_MASK_INT_EN_OUTBOUND_DBG_SHIFT 2
    #define INT_EN_PROC3_HANG_MASK 0x80000000
    #define INT_EN_PROC3_HANG_SHIFT 31
#define  PROC3_HOST_INT_STATUS 0xACE0
    #define PROC3_HOST_INT_STATUS_OUTBOUND_CALL0_MASK 0x00000001
    #define PROC3_HOST_INT_STATUS_OUTBOUND_CALL0_SHIFT 0
    #define PROC3_HOST_INT_STATUS_OUTBOUND_CALL1_MASK 0x00000002
    #define PROC3_HOST_INT_STATUS_OUTBOUND_CALL1_SHIFT 1
    #define PROC3_HOST_INT_STATUS_OUTBOUND_DBG_MASK 0x00000004
    #define PROC3_HOST_INT_STATUS_OUTBOUND_DBG_SHIFT 2
    #define PROC3_HANG_MASK 0x80000000
    #define PROC3_HANG_SHIFT 31
#define  PROC3_INBOUND_CALL_0 0xAC20
    #define PROC3_INBOUND_CALL_0_DATA_MASK 0xFFFFFFFF
    #define PROC3_INBOUND_CALL_0_DATA_SHIFT 0
#define  PROC3_INBOUND_CALL_1 0xAC24
    #define PROC3_INBOUND_CALL_1_DATA_MASK 0xFFFFFFFF
    #define PROC3_INBOUND_CALL_1_DATA_SHIFT 0
#define  PROC3_IPC_CALL 0xACF0
    #define PROC3_IPC_CALL_DATA_MASK 0xFFFFFFFF
    #define PROC3_IPC_CALL_DATA_SHIFT 0
#define  PROC3_MC_ARB 0xAC18
    #define PROC3_MC_ARB_ARC_REQ_CNT_LIMIT_MASK 0x0000000F
    #define PROC3_MC_ARB_ARC_REQ_CNT_LIMIT_SHIFT 0
    #define PROC3_MC_ARB_DMA_REQ_CNT_LIMIT_MASK 0x000000F0
    #define PROC3_MC_ARB_DMA_REQ_CNT_LIMIT_SHIFT 4
#define  PROC3_MERGED_WRITE_CTL 0xAC10
    #define PROC3_MERGED_WRITE_CTL_TIMER_MASK 0x000003FF
    #define PROC3_MERGED_WRITE_CTL_TIMER_SHIFT 0
#define  PROC3_MMREG_APER 0xAC08
    #define PROC3_MMREG_APER_BASE_MASK 0x00001FFF
    #define PROC3_MMREG_APER_BASE_SHIFT 0
    #define PROC3_MMREG_APER_SIZE_MASK 0x1FFF0000
    #define PROC3_MMREG_APER_SIZE_SHIFT 16
#define  PROC3_MSG_DATA_0 0xAC30
    #define PROC3_MSG_DATA_0_DATA_MASK 0xFFFFFFFF
    #define PROC3_MSG_DATA_0_DATA_SHIFT 0
#define  PROC3_MSG_DATA_1 0xAC34
    #define PROC3_MSG_DATA_1_DATA_MASK 0xFFFFFFFF
    #define PROC3_MSG_DATA_1_DATA_SHIFT 0
#define  PROC3_MSG_DATA_10 0xAC58
    #define PROC3_MSG_DATA_10_DATA_MASK 0xFFFFFFFF
    #define PROC3_MSG_DATA_10_DATA_SHIFT 0
#define  PROC3_MSG_DATA_11 0xAC5C
    #define PROC3_MSG_DATA_11_DATA_MASK 0xFFFFFFFF
    #define PROC3_MSG_DATA_11_DATA_SHIFT 0
#define  PROC3_MSG_DATA_2 0xAC38
    #define PROC3_MSG_DATA_2_DATA_MASK 0xFFFFFFFF
    #define PROC3_MSG_DATA_2_DATA_SHIFT 0
#define  PROC3_MSG_DATA_3 0xAC3C
    #define PROC3_MSG_DATA_3_DATA_MASK 0xFFFFFFFF
    #define PROC3_MSG_DATA_3_DATA_SHIFT 0
#define  PROC3_MSG_DATA_4 0xAC40
    #define PROC3_MSG_DATA_4_DATA_MASK 0xFFFFFFFF
    #define PROC3_MSG_DATA_4_DATA_SHIFT 0
#define  PROC3_MSG_DATA_5 0xAC44
    #define PROC3_MSG_DATA_5_DATA_MASK 0xFFFFFFFF
    #define PROC3_MSG_DATA_5_DATA_SHIFT 0
#define  PROC3_MSG_DATA_6 0xAC48
    #define PROC3_MSG_DATA_6_DATA_MASK 0xFFFFFFFF
    #define PROC3_MSG_DATA_6_DATA_SHIFT 0
#define  PROC3_MSG_DATA_7 0xAC4C
    #define PROC3_MSG_DATA_7_DATA_MASK 0xFFFFFFFF
    #define PROC3_MSG_DATA_7_DATA_SHIFT 0
#define  PROC3_MSG_DATA_8 0xAC50
    #define PROC3_MSG_DATA_8_DATA_MASK 0xFFFFFFFF
    #define PROC3_MSG_DATA_8_DATA_SHIFT 0
#define  PROC3_MSG_DATA_9 0xAC54
    #define PROC3_MSG_DATA_9_DATA_MASK 0xFFFFFFFF
    #define PROC3_MSG_DATA_9_DATA_SHIFT 0
#define  PROC3_OUTBOUND_CALL_0 0xAC28
    #define PROC3_OUTBOUND_CALL_0_DATA_MASK 0xFFFFFFFF
    #define PROC3_OUTBOUND_CALL_0_DATA_SHIFT 0
#define  PROC3_OUTBOUND_CALL_1 0xAC2C
    #define PROC3_OUTBOUND_CALL_1_DATA_MASK 0xFFFFFFFF
    #define PROC3_OUTBOUND_CALL_1_DATA_SHIFT 0
#define  PROC3_PROC3_INT_MASK 0xACEC
    #define PROC3_PROC3_INT_MASK_INT_EN_INBOUND_CALL0_MASK 0x00000001
    #define PROC3_PROC3_INT_MASK_INT_EN_INBOUND_CALL0_SHIFT 0
    #define PROC3_PROC3_INT_MASK_INT_EN_INBOUND_CALL1_MASK 0x00000002
    #define PROC3_PROC3_INT_MASK_INT_EN_INBOUND_CALL1_SHIFT 1
    #define PROC3_PROC3_INT_MASK_INT_EN_IPC_CALL_MASK 0x00000008
    #define PROC3_PROC3_INT_MASK_INT_EN_IPC_CALL_SHIFT 3
    #define PROC3_PROC3_INT_MASK_INT_EN_DMA_COMPLETE_MASK 0x00000010
    #define PROC3_PROC3_INT_MASK_INT_EN_DMA_COMPLETE_SHIFT 4
    #define PROC3_PROC3_INT_MASK_INT_EN_DBG_INBOUND0_MASK 0x00000020
    #define PROC3_PROC3_INT_MASK_INT_EN_DBG_INBOUND0_SHIFT 5
    #define PROC3_PROC3_INT_MASK_INT_EN_DBG_INBOUND1_MASK 0x00000040
    #define PROC3_PROC3_INT_MASK_INT_EN_DBG_INBOUND1_SHIFT 6
    #define PROC3_PROC3_INT_MASK_INT_EN_DBG_INBOUND2_MASK 0x00000080
    #define PROC3_PROC3_INT_MASK_INT_EN_DBG_INBOUND2_SHIFT 7
    #define PROC3_PROC3_INT_MASK_INT_EN_DBG_INBOUND3_MASK 0x00000100
    #define PROC3_PROC3_INT_MASK_INT_EN_DBG_INBOUND3_SHIFT 8
    #define PROC3_PROC3_INT_MASK_INT_EN_DBG_INBOUND4_MASK 0x00000200
    #define PROC3_PROC3_INT_MASK_INT_EN_DBG_INBOUND4_SHIFT 9
#define  PROC3_PROC3_INT_STATUS 0xACE8
    #define PROC3_PROC3_INT_STATUS_INBOUND_CALL0_MASK 0x00000001
    #define PROC3_PROC3_INT_STATUS_INBOUND_CALL0_SHIFT 0
    #define PROC3_PROC3_INT_STATUS_INBOUND_CALL1_MASK 0x00000002
    #define PROC3_PROC3_INT_STATUS_INBOUND_CALL1_SHIFT 1
    #define PROC3_PROC3_INT_STATUS_IPC_CALL_MASK 0x00000008
    #define PROC3_PROC3_INT_STATUS_IPC_CALL_SHIFT 3
    #define PROC3_PROC3_INT_STATUS_DMA_COMPLETE_MASK 0x00000010
    #define PROC3_PROC3_INT_STATUS_DMA_COMPLETE_SHIFT 4
    #define PROC3_PROC3_INT_STATUS_DBG_INBOUND0_MASK 0x00000020
    #define PROC3_PROC3_INT_STATUS_DBG_INBOUND0_SHIFT 5
    #define PROC3_PROC3_INT_STATUS_DBG_INBOUND1_MASK 0x00000040
    #define PROC3_PROC3_INT_STATUS_DBG_INBOUND1_SHIFT 6
    #define PROC3_PROC3_INT_STATUS_DBG_INBOUND2_MASK 0x00000080
    #define PROC3_PROC3_INT_STATUS_DBG_INBOUND2_SHIFT 7
    #define PROC3_PROC3_INT_STATUS_DBG_INBOUND3_MASK 0x00000100
    #define PROC3_PROC3_INT_STATUS_DBG_INBOUND3_SHIFT 8
    #define PROC3_PROC3_INT_STATUS_DBG_INBOUND4_MASK 0x00000200
    #define PROC3_PROC3_INT_STATUS_DBG_INBOUND4_SHIFT 9
#define  PROC3_RST 0xAC14
    #define PROC3_RST_SOFT_RSTN_MASK 0x00000001
    #define PROC3_RST_SOFT_RSTN_SHIFT 0
#define  PROC3_WATCHDOG_CNT 0xAC80
    #define PROC3_WATCHDOG_CNT_DATA_MASK 0xFFFFFFFF
    #define PROC3_WATCHDOG_CNT_DATA_SHIFT 0
#define  PROC3_WATCHDOG_COMPARE 0xAC84
    #define PROC3_WATCHDOG_COMPARE_DATA_MASK 0xFFFFFFFF
    #define PROC3_WATCHDOG_COMPARE_DATA_SHIFT 0
#define  PROC4_DBG_INBOUND0 0xB060
    #define PROC4_DBG_INBOUND0_DATA_MASK 0xFFFFFFFF
    #define PROC4_DBG_INBOUND0_DATA_SHIFT 0
#define  PROC4_DBG_INBOUND1 0xB0A0
    #define PROC4_DBG_INBOUND1_DATA_MASK 0xFFFFFFFF
    #define PROC4_DBG_INBOUND1_DATA_SHIFT 0
#define  PROC4_DBG_INBOUND2 0xB0A4
    #define PROC4_DBG_INBOUND2_DATA_MASK 0xFFFFFFFF
    #define PROC4_DBG_INBOUND2_DATA_SHIFT 0
#define  PROC4_DBG_INBOUND3 0xB0A8
    #define PROC4_DBG_INBOUND3_DATA_MASK 0xFFFFFFFF
    #define PROC4_DBG_INBOUND3_DATA_SHIFT 0
#define  PROC4_DBG_INBOUND4 0xB0AC
    #define PROC4_DBG_INBOUND4_DATA_MASK 0xFFFFFFFF
    #define PROC4_DBG_INBOUND4_DATA_SHIFT 0
#define  PROC4_DBG_OUTBOUND 0xB064
    #define PROC4_DBG_OUTBOUND_DATA_MASK 0xFFFFFFFF
    #define PROC4_DBG_OUTBOUND_DATA_SHIFT 0
#define  PROC4_FB_TOP 0xB004
    #define PROC4_FB_TOP_BASE_MASK 0x1FFFFC00
    #define PROC4_FB_TOP_BASE_SHIFT 10
#define  PROC4_HOST_INT_MASK 0xB0E4
    #define PROC4_HOST_INT_MASK_INT_EN_OUTBOUND_CALL0_MASK 0x00000001
    #define PROC4_HOST_INT_MASK_INT_EN_OUTBOUND_CALL0_SHIFT 0
    #define PROC4_HOST_INT_MASK_INT_EN_OUTBOUND_CALL1_MASK 0x00000002
    #define PROC4_HOST_INT_MASK_INT_EN_OUTBOUND_CALL1_SHIFT 1
    #define PROC4_HOST_INT_MASK_INT_EN_OUTBOUND_DBG_MASK 0x00000004
    #define PROC4_HOST_INT_MASK_INT_EN_OUTBOUND_DBG_SHIFT 2
    #define INT_EN_PROC4_HANG_MASK 0x80000000
    #define INT_EN_PROC4_HANG_SHIFT 31
#define  PROC4_HOST_INT_STATUS 0xB0E0
    #define PROC4_HOST_INT_STATUS_OUTBOUND_CALL0_MASK 0x00000001
    #define PROC4_HOST_INT_STATUS_OUTBOUND_CALL0_SHIFT 0
    #define PROC4_HOST_INT_STATUS_OUTBOUND_CALL1_MASK 0x00000002
    #define PROC4_HOST_INT_STATUS_OUTBOUND_CALL1_SHIFT 1
    #define PROC4_HOST_INT_STATUS_OUTBOUND_DBG_MASK 0x00000004
    #define PROC4_HOST_INT_STATUS_OUTBOUND_DBG_SHIFT 2
    #define PROC4_HANG_MASK 0x80000000
    #define PROC4_HANG_SHIFT 31
#define  PROC4_INBOUND_CALL_0 0xB020
    #define PROC4_INBOUND_CALL_0_DATA_MASK 0xFFFFFFFF
    #define PROC4_INBOUND_CALL_0_DATA_SHIFT 0
#define  PROC4_INBOUND_CALL_1 0xB024
    #define PROC4_INBOUND_CALL_1_DATA_MASK 0xFFFFFFFF
    #define PROC4_INBOUND_CALL_1_DATA_SHIFT 0
#define  PROC4_IPC_CALL 0xB0F0
    #define PROC4_IPC_CALL_DATA_MASK 0xFFFFFFFF
    #define PROC4_IPC_CALL_DATA_SHIFT 0
#define  PROC4_MERGED_WRITE_CTL 0xB010
    #define PROC4_MERGED_WRITE_CTL_TIMER_MASK 0x000003FF
    #define PROC4_MERGED_WRITE_CTL_TIMER_SHIFT 0
#define  PROC4_MMREG_APER 0xB008
    #define PROC4_MMREG_APER_BASE_MASK 0x00001FFF
    #define PROC4_MMREG_APER_BASE_SHIFT 0
    #define PROC4_MMREG_APER_SIZE_MASK 0x1FFF0000
    #define PROC4_MMREG_APER_SIZE_SHIFT 16
#define  PROC4_MSG_DATA_0 0xB030
    #define PROC4_MSG_DATA_0_DATA_MASK 0xFFFFFFFF
    #define PROC4_MSG_DATA_0_DATA_SHIFT 0
#define  PROC4_MSG_DATA_1 0xB034
    #define PROC4_MSG_DATA_1_DATA_MASK 0xFFFFFFFF
    #define PROC4_MSG_DATA_1_DATA_SHIFT 0
#define  PROC4_MSG_DATA_10 0xB058
    #define PROC4_MSG_DATA_10_DATA_MASK 0xFFFFFFFF
    #define PROC4_MSG_DATA_10_DATA_SHIFT 0
#define  PROC4_MSG_DATA_11 0xB05C
    #define PROC4_MSG_DATA_11_DATA_MASK 0xFFFFFFFF
    #define PROC4_MSG_DATA_11_DATA_SHIFT 0
#define  PROC4_MSG_DATA_2 0xB038
    #define PROC4_MSG_DATA_2_DATA_MASK 0xFFFFFFFF
    #define PROC4_MSG_DATA_2_DATA_SHIFT 0
#define  PROC4_MSG_DATA_3 0xB03C
    #define PROC4_MSG_DATA_3_DATA_MASK 0xFFFFFFFF
    #define PROC4_MSG_DATA_3_DATA_SHIFT 0
#define  PROC4_MSG_DATA_4 0xB040
    #define PROC4_MSG_DATA_4_DATA_MASK 0xFFFFFFFF
    #define PROC4_MSG_DATA_4_DATA_SHIFT 0
#define  PROC4_MSG_DATA_5 0xB044
    #define PROC4_MSG_DATA_5_DATA_MASK 0xFFFFFFFF
    #define PROC4_MSG_DATA_5_DATA_SHIFT 0
#define  PROC4_MSG_DATA_6 0xB048
    #define PROC4_MSG_DATA_6_DATA_MASK 0xFFFFFFFF
    #define PROC4_MSG_DATA_6_DATA_SHIFT 0
#define  PROC4_MSG_DATA_7 0xB04C
    #define PROC4_MSG_DATA_7_DATA_MASK 0xFFFFFFFF
    #define PROC4_MSG_DATA_7_DATA_SHIFT 0
#define  PROC4_MSG_DATA_8 0xB050
    #define PROC4_MSG_DATA_8_DATA_MASK 0xFFFFFFFF
    #define PROC4_MSG_DATA_8_DATA_SHIFT 0
#define  PROC4_MSG_DATA_9 0xB054
    #define PROC4_MSG_DATA_9_DATA_MASK 0xFFFFFFFF
    #define PROC4_MSG_DATA_9_DATA_SHIFT 0
#define  PROC4_OUTBOUND_CALL_0 0xB028
    #define PROC4_OUTBOUND_CALL_0_DATA_MASK 0xFFFFFFFF
    #define PROC4_OUTBOUND_CALL_0_DATA_SHIFT 0
#define  PROC4_OUTBOUND_CALL_1 0xB02C
    #define PROC4_OUTBOUND_CALL_1_DATA_MASK 0xFFFFFFFF
    #define PROC4_OUTBOUND_CALL_1_DATA_SHIFT 0
#define  PROC4_PROC4_INT_MASK 0xB0EC
    #define PROC4_PROC4_INT_MASK_INT_EN_INBOUND_CALL0_MASK 0x00000001
    #define PROC4_PROC4_INT_MASK_INT_EN_INBOUND_CALL0_SHIFT 0
    #define PROC4_PROC4_INT_MASK_INT_EN_INBOUND_CALL1_MASK 0x00000002
    #define PROC4_PROC4_INT_MASK_INT_EN_INBOUND_CALL1_SHIFT 1
    #define PROC4_PROC4_INT_MASK_INT_EN_IPC_CALL_MASK 0x00000008
    #define PROC4_PROC4_INT_MASK_INT_EN_IPC_CALL_SHIFT 3
    #define PROC4_PROC4_INT_MASK_INT_EN_DBG_INBOUND0_MASK 0x00000020
    #define PROC4_PROC4_INT_MASK_INT_EN_DBG_INBOUND0_SHIFT 5
    #define PROC4_PROC4_INT_MASK_INT_EN_DBG_INBOUND1_MASK 0x00000040
    #define PROC4_PROC4_INT_MASK_INT_EN_DBG_INBOUND1_SHIFT 6
    #define PROC4_PROC4_INT_MASK_INT_EN_DBG_INBOUND2_MASK 0x00000080
    #define PROC4_PROC4_INT_MASK_INT_EN_DBG_INBOUND2_SHIFT 7
    #define PROC4_PROC4_INT_MASK_INT_EN_DBG_INBOUND3_MASK 0x00000100
    #define PROC4_PROC4_INT_MASK_INT_EN_DBG_INBOUND3_SHIFT 8
    #define PROC4_PROC4_INT_MASK_INT_EN_DBG_INBOUND4_MASK 0x00000200
    #define PROC4_PROC4_INT_MASK_INT_EN_DBG_INBOUND4_SHIFT 9
#define  PROC4_PROC4_INT_STATUS 0xB0E8
    #define PROC4_PROC4_INT_STATUS_INBOUND_CALL0_MASK 0x00000001
    #define PROC4_PROC4_INT_STATUS_INBOUND_CALL0_SHIFT 0
    #define PROC4_PROC4_INT_STATUS_INBOUND_CALL1_MASK 0x00000002
    #define PROC4_PROC4_INT_STATUS_INBOUND_CALL1_SHIFT 1
    #define PROC4_PROC4_INT_STATUS_IPC_CALL_MASK 0x00000008
    #define PROC4_PROC4_INT_STATUS_IPC_CALL_SHIFT 3
    #define PROC4_PROC4_INT_STATUS_DBG_INBOUND0_MASK 0x00000020
    #define PROC4_PROC4_INT_STATUS_DBG_INBOUND0_SHIFT 5
    #define PROC4_PROC4_INT_STATUS_DBG_INBOUND1_MASK 0x00000040
    #define PROC4_PROC4_INT_STATUS_DBG_INBOUND1_SHIFT 6
    #define PROC4_PROC4_INT_STATUS_DBG_INBOUND2_MASK 0x00000080
    #define PROC4_PROC4_INT_STATUS_DBG_INBOUND2_SHIFT 7
    #define PROC4_PROC4_INT_STATUS_DBG_INBOUND3_MASK 0x00000100
    #define PROC4_PROC4_INT_STATUS_DBG_INBOUND3_SHIFT 8
    #define PROC4_PROC4_INT_STATUS_DBG_INBOUND4_MASK 0x00000200
    #define PROC4_PROC4_INT_STATUS_DBG_INBOUND4_SHIFT 9
#define  PROC4_RST 0xB014
    #define PROC4_RST_SOFT_RSTN_MASK 0x00000001
    #define PROC4_RST_SOFT_RSTN_SHIFT 0
#define  PROC4_WATCHDOG_CNT 0xB080
    #define PROC4_WATCHDOG_CNT_DATA_MASK 0xFFFFFFFF
    #define PROC4_WATCHDOG_CNT_DATA_SHIFT 0
#define  PROC4_WATCHDOG_COMPARE 0xB084
    #define PROC4_WATCHDOG_COMPARE_DATA_MASK 0xFFFFFFFF
    #define PROC4_WATCHDOG_COMPARE_DATA_SHIFT 0
#define  PROC_DBG_INBOUND0 0xA060
    #define PROC_DBG_INBOUND0_DATA_MASK 0xFFFFFFFF
    #define PROC_DBG_INBOUND0_DATA_SHIFT 0
#define  PROC_DBG_INBOUND1 0xA0A0
    #define PROC_DBG_INBOUND1_DATA_MASK 0xFFFFFFFF
    #define PROC_DBG_INBOUND1_DATA_SHIFT 0
#define  PROC_DBG_INBOUND2 0xA0A4
    #define PROC_DBG_INBOUND2_DATA_MASK 0xFFFFFFFF
    #define PROC_DBG_INBOUND2_DATA_SHIFT 0
#define  PROC_DBG_INBOUND3 0xA0A8
    #define PROC_DBG_INBOUND3_DATA_MASK 0xFFFFFFFF
    #define PROC_DBG_INBOUND3_DATA_SHIFT 0
#define  PROC_DBG_INBOUND4 0xA0AC
    #define PROC_DBG_INBOUND4_DATA_MASK 0xFFFFFFFF
    #define PROC_DBG_INBOUND4_DATA_SHIFT 0
#define  PROC_DBG_OUTBOUND 0xA064
    #define PROC_DBG_OUTBOUND_DATA_MASK 0xFFFFFFFF
    #define PROC_DBG_OUTBOUND_DATA_SHIFT 0
#define  PROC_DEBUG_REG1 0xA070
    #define PROC_DEBUG_REG1_DATA_MASK 0xFFFFFFFF
    #define PROC_DEBUG_REG1_DATA_SHIFT 0
#define  PROC_DEBUG_REG2 0xA074
    #define PROC_DEBUG_REG2_DATA_MASK 0xFFFFFFFF
    #define PROC_DEBUG_REG2_DATA_SHIFT 0
#define  PROC_DEBUG_REG3 0xA078
    #define PROC_DEBUG_REG3_DATA_MASK 0xFFFFFFFF
    #define PROC_DEBUG_REG3_DATA_SHIFT 0
#define  PROC_DEBUG_REG4 0xA07C
    #define PROC_DEBUG_REG4_DATA_MASK 0xFFFFFFFF
    #define PROC_DEBUG_REG4_DATA_SHIFT 0
#define  PROC_DEBUG_REG5 0xA088
    #define PROC_DEBUG_REG5_DATA_MASK 0xFFFFFFFF
    #define PROC_DEBUG_REG5_DATA_SHIFT 0
#define  PROC_DEBUG_REG6 0xA08C
    #define PROC_DEBUG_REG6_DATA_MASK 0xFFFFFFFF
    #define PROC_DEBUG_REG6_DATA_SHIFT 0
#define  PROC_DUMMY_REG 0xA0FC
    #define PROC_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define PROC_DUMMY_REG_DATA_SHIFT 0
#define  PROC_FB_TOP 0xA004
    #define PROC_FB_TOP_BASE_MASK 0x1FFFFC00
    #define PROC_FB_TOP_BASE_SHIFT 10
#define  PROC_HOST_INT_MASK 0xA0E4
    #define PROC_HOST_INT_MASK_INT_EN_OUTBOUND_CALL0_MASK 0x00000001
    #define PROC_HOST_INT_MASK_INT_EN_OUTBOUND_CALL0_SHIFT 0
    #define PROC_HOST_INT_MASK_INT_EN_OUTBOUND_CALL1_MASK 0x00000002
    #define PROC_HOST_INT_MASK_INT_EN_OUTBOUND_CALL1_SHIFT 1
    #define PROC_HOST_INT_MASK_INT_EN_OUTBOUND_DBG_MASK 0x00000004
    #define PROC_HOST_INT_MASK_INT_EN_OUTBOUND_DBG_SHIFT 2
    #define PROC_HOST_INT_MASK_INT_EN_PROC_HANG_MASK 0x80000000
    #define PROC_HOST_INT_MASK_INT_EN_PROC_HANG_SHIFT 31
#define  PROC_HOST_INT_STATUS 0xA0E0
    #define PROC_HOST_INT_STATUS_OUTBOUND_CALL0_MASK 0x00000001
    #define PROC_HOST_INT_STATUS_OUTBOUND_CALL0_SHIFT 0
    #define PROC_HOST_INT_STATUS_OUTBOUND_CALL1_MASK 0x00000002
    #define PROC_HOST_INT_STATUS_OUTBOUND_CALL1_SHIFT 1
    #define PROC_HOST_INT_STATUS_OUTBOUND_DBG_MASK 0x00000004
    #define PROC_HOST_INT_STATUS_OUTBOUND_DBG_SHIFT 2
    #define PROC_HOST_INT_STATUS_PROC_HANG_MASK 0x80000000
    #define PROC_HOST_INT_STATUS_PROC_HANG_SHIFT 31
#define  PROC_INBOUND_CALL_0 0xA020
    #define PROC_INBOUND_CALL_0_DATA_MASK 0xFFFFFFFF
    #define PROC_INBOUND_CALL_0_DATA_SHIFT 0
#define  PROC_INBOUND_CALL_1 0xA024
    #define PROC_INBOUND_CALL_1_DATA_MASK 0xFFFFFFFF
    #define PROC_INBOUND_CALL_1_DATA_SHIFT 0
#define  PROC_IPC_CALL 0xA0F0
    #define PROC_IPC_CALL_DATA_MASK 0xFFFFFFFF
    #define PROC_IPC_CALL_DATA_SHIFT 0
#define  PROC_MBD_EMPTY 0xA0F4
    #define PROC_MBD_EMPTY_EMPTY_MASK 0x00000001
    #define PROC_MBD_EMPTY_EMPTY_SHIFT 0
#define  PROC_MC_ARB 0xA018
    #define PROC_MC_ARB_ARC_REQ_CNT_LIMIT_MASK 0x0000000F
    #define PROC_MC_ARB_ARC_REQ_CNT_LIMIT_SHIFT 0
    #define PROC_MC_ARB_IBB_REQ_CNT_LIMIT_MASK 0x000000F0
    #define PROC_MC_ARB_IBB_REQ_CNT_LIMIT_SHIFT 4
    #define PROC_MC_ARB_MBD_REQ_CNT_LIMIT_MASK 0x00000F00
    #define PROC_MC_ARB_MBD_REQ_CNT_LIMIT_SHIFT 8
#define  PROC_MERGED_WRITE_CTL 0xA010
    #define PROC_MERGED_WRITE_CTL_TIMER_MASK 0x000003FF
    #define PROC_MERGED_WRITE_CTL_TIMER_SHIFT 0
#define  PROC_MMREG_APER 0xA008
    #define PROC_MMREG_APER_BASE_MASK 0x00001FFF
    #define PROC_MMREG_APER_BASE_SHIFT 0
    #define PROC_MMREG_APER_SIZE_MASK 0x1FFF0000
    #define PROC_MMREG_APER_SIZE_SHIFT 16
#define  PROC_MSG_DATA_0 0xA030
    #define PROC_MSG_DATA_0_DATA_MASK 0xFFFFFFFF
    #define PROC_MSG_DATA_0_DATA_SHIFT 0
#define  PROC_MSG_DATA_1 0xA034
    #define PROC_MSG_DATA_1_DATA_MASK 0xFFFFFFFF
    #define PROC_MSG_DATA_1_DATA_SHIFT 0
#define  PROC_MSG_DATA_10 0xA058
    #define PROC_MSG_DATA_10_DATA_MASK 0xFFFFFFFF
    #define PROC_MSG_DATA_10_DATA_SHIFT 0
#define  PROC_MSG_DATA_11 0xA05C
    #define PROC_MSG_DATA_11_DATA_MASK 0xFFFFFFFF
    #define PROC_MSG_DATA_11_DATA_SHIFT 0
#define  PROC_MSG_DATA_2 0xA038
    #define PROC_MSG_DATA_2_DATA_MASK 0xFFFFFFFF
    #define PROC_MSG_DATA_2_DATA_SHIFT 0
#define  PROC_MSG_DATA_3 0xA03C
    #define PROC_MSG_DATA_3_DATA_MASK 0xFFFFFFFF
    #define PROC_MSG_DATA_3_DATA_SHIFT 0
#define  PROC_MSG_DATA_4 0xA040
    #define PROC_MSG_DATA_4_DATA_MASK 0xFFFFFFFF
    #define PROC_MSG_DATA_4_DATA_SHIFT 0
#define  PROC_MSG_DATA_5 0xA044
    #define PROC_MSG_DATA_5_DATA_MASK 0xFFFFFFFF
    #define PROC_MSG_DATA_5_DATA_SHIFT 0
#define  PROC_MSG_DATA_6 0xA048
    #define PROC_MSG_DATA_6_DATA_MASK 0xFFFFFFFF
    #define PROC_MSG_DATA_6_DATA_SHIFT 0
#define  PROC_MSG_DATA_7 0xA04C
    #define PROC_MSG_DATA_7_DATA_MASK 0xFFFFFFFF
    #define PROC_MSG_DATA_7_DATA_SHIFT 0
#define  PROC_MSG_DATA_8 0xA050
    #define PROC_MSG_DATA_8_DATA_MASK 0xFFFFFFFF
    #define PROC_MSG_DATA_8_DATA_SHIFT 0
#define  PROC_MSG_DATA_9 0xA054
    #define PROC_MSG_DATA_9_DATA_MASK 0xFFFFFFFF
    #define PROC_MSG_DATA_9_DATA_SHIFT 0
#define  PROC_OUTBOUND_CALL_0 0xA028
    #define PROC_OUTBOUND_CALL_0_DATA_MASK 0xFFFFFFFF
    #define PROC_OUTBOUND_CALL_0_DATA_SHIFT 0
#define  PROC_OUTBOUND_CALL_1 0xA02C
    #define PROC_OUTBOUND_CALL_1_DATA_MASK 0xFFFFFFFF
    #define PROC_OUTBOUND_CALL_1_DATA_SHIFT 0
#define  PROC_PROC_INT_MASK 0xA0EC
    #define PROC_PROC_INT_MASK_INT_EN_INBOUND_CALL0_MASK 0x00000001
    #define PROC_PROC_INT_MASK_INT_EN_INBOUND_CALL0_SHIFT 0
    #define PROC_PROC_INT_MASK_INT_EN_INBOUND_CALL1_MASK 0x00000002
    #define PROC_PROC_INT_MASK_INT_EN_INBOUND_CALL1_SHIFT 1
    #define PROC_PROC_INT_MASK_INT_EN_IPC_CALL_MASK 0x00000008
    #define PROC_PROC_INT_MASK_INT_EN_IPC_CALL_SHIFT 3
    #define PROC_PROC_INT_MASK_INT_EN_DBG_INBOUND0_MASK 0x00000020
    #define PROC_PROC_INT_MASK_INT_EN_DBG_INBOUND0_SHIFT 5
    #define PROC_PROC_INT_MASK_INT_EN_DBG_INBOUND1_MASK 0x00000040
    #define PROC_PROC_INT_MASK_INT_EN_DBG_INBOUND1_SHIFT 6
    #define PROC_PROC_INT_MASK_INT_EN_DBG_INBOUND2_MASK 0x00000080
    #define PROC_PROC_INT_MASK_INT_EN_DBG_INBOUND2_SHIFT 7
    #define PROC_PROC_INT_MASK_INT_EN_DBG_INBOUND3_MASK 0x00000100
    #define PROC_PROC_INT_MASK_INT_EN_DBG_INBOUND3_SHIFT 8
    #define PROC_PROC_INT_MASK_INT_EN_DBG_INBOUND4_MASK 0x00000200
    #define PROC_PROC_INT_MASK_INT_EN_DBG_INBOUND4_SHIFT 9
#define  PROC_PROC_INT_STATUS 0xA0E8
    #define PROC_PROC_INT_STATUS_INBOUND_CALL0_MASK 0x00000001
    #define PROC_PROC_INT_STATUS_INBOUND_CALL0_SHIFT 0
    #define PROC_PROC_INT_STATUS_INBOUND_CALL1_MASK 0x00000002
    #define PROC_PROC_INT_STATUS_INBOUND_CALL1_SHIFT 1
    #define PROC_PROC_INT_STATUS_IPC_CALL_MASK 0x00000008
    #define PROC_PROC_INT_STATUS_IPC_CALL_SHIFT 3
    #define PROC_PROC_INT_STATUS_DBG_INBOUND0_MASK 0x00000020
    #define PROC_PROC_INT_STATUS_DBG_INBOUND0_SHIFT 5
    #define PROC_PROC_INT_STATUS_DBG_INBOUND1_MASK 0x00000040
    #define PROC_PROC_INT_STATUS_DBG_INBOUND1_SHIFT 6
    #define PROC_PROC_INT_STATUS_DBG_INBOUND2_MASK 0x00000080
    #define PROC_PROC_INT_STATUS_DBG_INBOUND2_SHIFT 7
    #define PROC_PROC_INT_STATUS_DBG_INBOUND3_MASK 0x00000100
    #define PROC_PROC_INT_STATUS_DBG_INBOUND3_SHIFT 8
    #define PROC_PROC_INT_STATUS_DBG_INBOUND4_MASK 0x00000200
    #define PROC_PROC_INT_STATUS_DBG_INBOUND4_SHIFT 9
#define  PROC_RST 0xA014
    #define PROC_RST_SOFT_RSTN_MASK 0x00000001
    #define PROC_RST_SOFT_RSTN_SHIFT 0
    #define PROC_RST_MBD_RSTN_MASK 0x00000004
    #define PROC_RST_MBD_RSTN_SHIFT 2
    #define PROC_RST_MBD_FLUSH_MASK 0x80000000
    #define PROC_RST_MBD_FLUSH_SHIFT 31
#define  PROC_SHADOW_IBB_CTRL 0xA0B0
    #define PROC_SHADOW_IBB_CTRL_SHADOW_IBB_CTRL_MASK 0xFFFFFFFF
    #define PROC_SHADOW_IBB_CTRL_SHADOW_IBB_CTRL_SHIFT 0
#define  PROC_SHADOW_IBB_RB_ADR 0xA0B8
    #define PROC_SHADOW_IBB_RB_ADR_SHADOW_IBB_RB_ADR_MASK 0xFFFFFFFF
    #define PROC_SHADOW_IBB_RB_ADR_SHADOW_IBB_RB_ADR_SHIFT 0
#define  PROC_SHADOW_IBB_RB_HEAD 0xA0C8
    #define PROC_SHADOW_IBB_RB_HEAD_SHADOW_IBB_RB_HEAD_MASK 0xFFFFFFFF
    #define PROC_SHADOW_IBB_RB_HEAD_SHADOW_IBB_RB_HEAD_SHIFT 0
#define  PROC_SHADOW_IBB_RB_TAIL 0xA0BC
    #define PROC_SHADOW_IBB_RB_TAIL_SHADOW_IBB_RB_TAIL_MASK 0xFFFFFFFF
    #define PROC_SHADOW_IBB_RB_TAIL_SHADOW_IBB_RB_TAIL_SHIFT 0
#define  PROC_SHADOW_IBB_RB_TAIL_READ 0xA0C0
    #define PROC_SHADOW_IBB_RB_TAIL_READ_SHADOW_IBB_RB_TAIL_READ_MASK 0xFFFFFFFF
    #define PROC_SHADOW_IBB_RB_TAIL_READ_SHADOW_IBB_RB_TAIL_READ_SHIFT 0
#define  PROC_SHADOW_IBB_STATUS 0xA0B4
    #define PROC_SHADOW_IBB_STATUS_SHADOW_IBB_STATUS_MASK 0xFFFFFFFF
    #define PROC_SHADOW_IBB_STATUS_SHADOW_IBB_STATUS_SHIFT 0
#define  PROC_WATCHDOG_CNT 0xA080
    #define PROC_WATCHDOG_CNT_DATA_MASK 0xFFFFFFFF
    #define PROC_WATCHDOG_CNT_DATA_SHIFT 0
#define  PROC_WATCHDOG_COMPARE 0xA084
    #define PROC_WATCHDOG_COMPARE_DATA_MASK 0xFFFFFFFF
    #define PROC_WATCHDOG_COMPARE_DATA_SHIFT 0
#define  RBM_BOARD_ID 0x0478
    #define BOARD_ID_MASK 0x000000FF
    #define BOARD_ID_SHIFT 0
    #define TECH_ID_MASK 0x0000FF00
    #define TECH_ID_SHIFT 8
    #define REV_ID_MASK 0x00FF0000
    #define REV_ID_SHIFT 16
    #define PACKAGE_MASK 0x01000000
    #define PACKAGE_SHIFT 24
    #define NVBOOT_MASK 0x02000000
    #define NVBOOT_SHIFT 25
    #define BOOTROM_MASK 0x04000000
    #define BOOTROM_SHIFT 26
    #define HOSTSEL_MASK 0x18000000
    #define HOSTSEL_SHIFT 27
#define  RBM_DUMMY_REG 0x047C
    #define RBM_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define RBM_DUMMY_REG_DATA_SHIFT 0
#define  RBM_FE_FILTER_HI 0x0490
    #define RBM_FE_FILTER_HI_FILTER_MASK 0xFFFFFFFF
    #define RBM_FE_FILTER_HI_FILTER_SHIFT 0
#define  RBM_FE_FILTER_LO 0x048C
    #define RBM_FE_FILTER_LO_FILTER_MASK 0xFFFFFFFF
    #define RBM_FE_FILTER_LO_FILTER_SHIFT 0
#define  RBM_FILTER_STICKY 0x04A0
    #define FILTER_STICKY_MASK 0x000001FF
    #define FILTER_STICKY_SHIFT 0
#define  RBM_HOST_INT_MASK 0x0408
    #define RBM_HOST_INT_MASK_CLI_TIMEOUT_MASK 0x000001FF
    #define RBM_HOST_INT_MASK_CLI_TIMEOUT_SHIFT 0
#define  RBM_INT_STATUS 0x0404
    #define RBM_INT_STATUS_CLI_TIMEOUT_MASK 0x000001FF
    #define RBM_INT_STATUS_CLI_TIMEOUT_SHIFT 0
#define  RBM_MIPS_INT_MASK 0x0410
    #define RBM_MIPS_INT_MASK_CLI_TIMEOUT_MASK 0x000001FF
    #define RBM_MIPS_INT_MASK_CLI_TIMEOUT_SHIFT 0
#define  RBM_PADU_CTRL 0x04A8
    #define RBM_PADU_CTRL_MASK 0x0000FFFF
    #define RBM_PADU_CTRL_SHIFT 0
#define  RBM_PCI_CFG 0x0484
    #define PCI_CFG_MASK 0xFFFFFFFF
    #define PCI_CFG_SHIFT 0
#define  RBM_PCI_DEV_ID 0x0474
    #define PCI_DEV_ID_MASK 0x000000FF
    #define PCI_DEV_ID_SHIFT 0
#define  RBM_PCI_SUB_CFG 0x0480
    #define PCI_SUB_CFG_MASK 0xFFFFFFFF
    #define PCI_SUB_CFG_SHIFT 0
#define  RBM_STICKY_BITS 0x0488
    #define STICKY_BIT_MASK 0x000000FF
    #define STICKY_BIT_SHIFT 0
#define  RBM_SWAP 0x043C
    #define BYTE_SWAP_MASK 0x00000007
    #define BYTE_SWAP_SHIFT 0
    #define RBM_SWAP_BIT_SWAP_MASK 0x0000FF00
    #define RBM_SWAP_BIT_SWAP_SHIFT 8
    #define REQ_HELD_LOW_MASK 0x00010000
    #define REQ_HELD_LOW_SHIFT 16
    #define MC_INIT_MASK 0x00020000
    #define MC_INIT_SHIFT 17
#define  RBM_TIMEOUT_CTRL 0x04A4
    #define SETTLE_TIME_MASK 0x0000003F
    #define SETTLE_TIME_SHIFT 0
    #define TIMEOUT_TIME_MASK 0x0003FF00
    #define TIMEOUT_TIME_SHIFT 8
    #define TIMEOUT_DISABLE_MASK 0x80000000
    #define TIMEOUT_DISABLE_SHIFT 31
#define  RCB_ACT_TOTAL 0x70B0
    #define ACT_TOTAL_MASK 0x000FFFFF
    #define ACT_TOTAL_SHIFT 0
#define  RCB_ADR 0x70BC
    #define RCB_ADR_BASE_MASK 0x0FFFFFC0
    #define RCB_ADR_BASE_SHIFT 6
#define  RCB_BITCOUNT_ADR 0x70C0
    #define RCB_BITCOUNT_ADR_BASE_MASK 0x0FFFFFC0
    #define RCB_BITCOUNT_ADR_BASE_SHIFT 6
#define  RCB_CTRL 0x70A0
    #define QUANT_SRC_MASK 0x00000003
    #define QUANT_SRC_SHIFT 0
    #define QUANT_TYPE_MASK 0x00000004
    #define QUANT_TYPE_SHIFT 2
    #define ZERO_ERR_MASK 0x00000008
    #define ZERO_ERR_SHIFT 3
    #define DELAY_MASK 0x00000070
    #define DELAY_SHIFT 4
    #define USE_FRM_DCT_MASK 0x00000080
    #define USE_FRM_DCT_SHIFT 7
    #define QUANT_VALUE_MASK 0x00007F00
    #define QUANT_VALUE_SHIFT 8
    #define FORCE_QUANT_MASK 0x00008000
    #define FORCE_QUANT_SHIFT 15
    #define RCB_CTRL_MB_CNT_MASK 0x3FFF0000
    #define RCB_CTRL_MB_CNT_SHIFT 16
    #define BITCNT_EN_MASK 0x80000000
    #define BITCNT_EN_SHIFT 31
#define  RCB_QPARAM 0x70A4
    #define QIPB_MASK 0x0000003F
    #define QIPB_SHIFT 0
    #define QMAX_MASK 0x00007F00
    #define QMAX_SHIFT 8
    #define QMIN_MASK 0x007F0000
    #define QMIN_SHIFT 16
#define  RCB_QSUM 0x70B4
    #define QSUM_MASK 0x00FFFFFF
    #define QSUM_SHIFT 0
#define  RCB_REACT 0x70A8
    #define REACT_MASK 0x000FFFFF
    #define REACT_SHIFT 0
#define  RCB_TIPB 0x70AC
    #define TIPB_MASK 0x00FFFFFF
    #define TIPB_SHIFT 0
#define  RCB_XSUM 0x70B8
    #define XSUM_MASK 0x7FFFFFFF
    #define XSUM_SHIFT 0
#define  RMX0_LIST_A 0x6190
    #define RMX0_LIST_A_ADDR_MASK 0x07FFFFF0
    #define RMX0_LIST_A_ADDR_SHIFT 4
#define  RMX0_LIST_B 0x6194
    #define RMX0_LIST_B_ADDR_MASK 0x07FFFFF0
    #define RMX0_LIST_B_ADDR_SHIFT 4
#define  RMX0_STATUS 0x6250
    #define SYNC0_ERR_MASK 0x00000001
    #define SYNC0_ERR_SHIFT 0
    #define LENGTH0_ERR_MASK 0x00000002
    #define LENGTH0_ERR_SHIFT 1
    #define PESID0_ERR_MASK 0x00000004
    #define PESID0_ERR_SHIFT 2
    #define PTSFLAG0_ERR_MASK 0x00000008
    #define PTSFLAG0_ERR_SHIFT 3
    #define CC0_MASK 0x000000F0
    #define CC0_SHIFT 4
    #define SYNC1_ERR_MASK 0x00000100
    #define SYNC1_ERR_SHIFT 8
    #define LENGTH1_ERR_MASK 0x00000200
    #define LENGTH1_ERR_SHIFT 9
    #define PESID1_ERR_MASK 0x00000400
    #define PESID1_ERR_SHIFT 10
    #define PTSFLAG1_ERR_MASK 0x00000800
    #define PTSFLAG1_ERR_SHIFT 11
    #define CC1_MASK 0x0000F000
    #define CC1_SHIFT 12
    #define SYNC2_ERR_MASK 0x00010000
    #define SYNC2_ERR_SHIFT 16
    #define LENGTH2_ERR_MASK 0x00020000
    #define LENGTH2_ERR_SHIFT 17
    #define PESID2_ERR_MASK 0x00040000
    #define PESID2_ERR_SHIFT 18
    #define PTSFLAG2_ERR_MASK 0x00080000
    #define PTSFLAG2_ERR_SHIFT 19
    #define CC2_MASK 0x00F00000
    #define CC2_SHIFT 20
    #define SYNC3_ERR_MASK 0x01000000
    #define SYNC3_ERR_SHIFT 24
    #define LENGTH3_ERR_MASK 0x02000000
    #define LENGTH3_ERR_SHIFT 25
    #define PESID3_ERR_MASK 0x04000000
    #define PESID3_ERR_SHIFT 26
    #define PTSFLAG3_ERR_MASK 0x08000000
    #define PTSFLAG3_ERR_SHIFT 27
    #define CC3_MASK 0xF0000000
    #define CC3_SHIFT 28
#define  RMX0_VBV 0x6210
    #define RMX0_VBV_OFFSET_MASK 0xFFFFFFFF
    #define RMX0_VBV_OFFSET_SHIFT 0
#define  RMX1_LIST_A 0x6198
    #define RMX1_LIST_A_ADDR_MASK 0x07FFFFF0
    #define RMX1_LIST_A_ADDR_SHIFT 4
#define  RMX1_LIST_B 0x619C
    #define RMX1_LIST_B_ADDR_MASK 0x07FFFFF0
    #define RMX1_LIST_B_ADDR_SHIFT 4
#define  RMX1_VBV 0x6214
    #define RMX1_VBV_OFFSET_MASK 0xFFFFFFFF
    #define RMX1_VBV_OFFSET_SHIFT 0
#define  RMX2_LIST_A 0x61A0
    #define RMX2_LIST_A_ADDR_MASK 0x07FFFFF0
    #define RMX2_LIST_A_ADDR_SHIFT 4
#define  RMX2_LIST_B 0x61A4
    #define RMX2_LIST_B_ADDR_MASK 0x07FFFFF0
    #define RMX2_LIST_B_ADDR_SHIFT 4
#define  RMX2_VBV 0x6218
    #define RMX2_VBV_OFFSET_MASK 0xFFFFFFFF
    #define RMX2_VBV_OFFSET_SHIFT 0
#define  RMX3_LIST_A 0x61A8
    #define RMX3_LIST_A_ADDR_MASK 0x07FFFFF0
    #define RMX3_LIST_A_ADDR_SHIFT 4
#define  RMX3_LIST_B 0x61AC
    #define RMX3_LIST_B_ADDR_MASK 0x07FFFFF0
    #define RMX3_LIST_B_ADDR_SHIFT 4
#define  RMX3_VBV 0x621C
    #define RMX3_VBV_OFFSET_MASK 0xFFFFFFFF
    #define RMX3_VBV_OFFSET_SHIFT 0
#define  RMX4_LIST_A 0x61B0
    #define RMX4_LIST_A_ADDR_MASK 0x07FFFFF0
    #define RMX4_LIST_A_ADDR_SHIFT 4
#define  RMX4_LIST_B 0x61B4
    #define RMX4_LIST_B_ADDR_MASK 0x07FFFFF0
    #define RMX4_LIST_B_ADDR_SHIFT 4
#define  RMX4_STATUS 0x6254
    #define SYNC4_ERR_MASK 0x00000001
    #define SYNC4_ERR_SHIFT 0
    #define LENGTH4_ERR_MASK 0x00000002
    #define LENGTH4_ERR_SHIFT 1
    #define PESID4_ERR_MASK 0x00000004
    #define PESID4_ERR_SHIFT 2
    #define PTSFLAG4_ERR_MASK 0x00000008
    #define PTSFLAG4_ERR_SHIFT 3
    #define CC4_MASK 0x000000F0
    #define CC4_SHIFT 4
    #define SYNC5_ERR_MASK 0x00000100
    #define SYNC5_ERR_SHIFT 8
    #define LENGTH5_ERR_MASK 0x00000200
    #define LENGTH5_ERR_SHIFT 9
    #define PESID5_ERR_MASK 0x00000400
    #define PESID5_ERR_SHIFT 10
    #define PTSFLAG5_ERR_MASK 0x00000800
    #define PTSFLAG5_ERR_SHIFT 11
    #define CC5_MASK 0x0000F000
    #define CC5_SHIFT 12
    #define SYNC6_ERR_MASK 0x00010000
    #define SYNC6_ERR_SHIFT 16
    #define LENGTH6_ERR_MASK 0x00020000
    #define LENGTH6_ERR_SHIFT 17
    #define PESID6_ERR_MASK 0x00040000
    #define PESID6_ERR_SHIFT 18
    #define PTSFLAG6_ERR_MASK 0x00080000
    #define PTSFLAG6_ERR_SHIFT 19
    #define CC6_MASK 0x00F00000
    #define CC6_SHIFT 20
    #define SYNC7_ERR_MASK 0x01000000
    #define SYNC7_ERR_SHIFT 24
    #define LENGTH7_ERR_MASK 0x02000000
    #define LENGTH7_ERR_SHIFT 25
    #define PESID7_ERR_MASK 0x04000000
    #define PESID7_ERR_SHIFT 26
    #define PTSFLAG7_ERR_MASK 0x08000000
    #define PTSFLAG7_ERR_SHIFT 27
    #define CC7_MASK 0xF0000000
    #define CC7_SHIFT 28
#define  RMX4_VBV 0x6220
    #define RMX4_VBV_OFFSET_MASK 0xFFFFFFFF
    #define RMX4_VBV_OFFSET_SHIFT 0
#define  RMX5_LIST_A 0x61B8
    #define RMX5_LIST_A_ADDR_MASK 0x07FFFFF0
    #define RMX5_LIST_A_ADDR_SHIFT 4
#define  RMX5_LIST_B 0x61BC
    #define RMX5_LIST_B_ADDR_MASK 0x07FFFFF0
    #define RMX5_LIST_B_ADDR_SHIFT 4
#define  RMX5_VBV 0x6224
    #define RMX5_VBV_OFFSET_MASK 0xFFFFFFFF
    #define RMX5_VBV_OFFSET_SHIFT 0
#define  RMX6_LIST_A 0x61C0
    #define RMX6_LIST_A_ADDR_MASK 0x07FFFFF0
    #define RMX6_LIST_A_ADDR_SHIFT 4
#define  RMX6_LIST_B 0x61C4
    #define RMX6_LIST_B_ADDR_MASK 0x07FFFFF0
    #define RMX6_LIST_B_ADDR_SHIFT 4
#define  RMX6_VBV 0x6228
    #define RMX6_VBV_OFFSET_MASK 0xFFFFFFFF
    #define RMX6_VBV_OFFSET_SHIFT 0
#define  RMX7_LIST_A 0x61C8
    #define RMX7_LIST_A_ADDR_MASK 0x07FFFFF0
    #define RMX7_LIST_A_ADDR_SHIFT 4
#define  RMX7_LIST_B 0x61CC
    #define RMX7_LIST_B_ADDR_MASK 0x07FFFFF0
    #define RMX7_LIST_B_ADDR_SHIFT 4
#define  RMX7_VBV 0x622C
    #define RMX7_VBV_OFFSET_MASK 0xFFFFFFFF
    #define RMX7_VBV_OFFSET_SHIFT 0
#define  RMX_CTRL 0x6180
    #define SRC_0_MASK 0x00000001
    #define SRC_0_SHIFT 0
    #define SRC_1_MASK 0x00000002
    #define SRC_1_SHIFT 1
    #define SRC_2_MASK 0x00000004
    #define SRC_2_SHIFT 2
    #define SRC_3_MASK 0x00000008
    #define SRC_3_SHIFT 3
    #define SRC_4_MASK 0x00000010
    #define SRC_4_SHIFT 4
    #define SRC_5_MASK 0x00000020
    #define SRC_5_SHIFT 5
    #define SRC_6_MASK 0x00000040
    #define SRC_6_SHIFT 6
    #define SRC_7_MASK 0x00000080
    #define SRC_7_SHIFT 7
    #define OP_RATE_EN_MASK 0x00100000
    #define OP_RATE_EN_SHIFT 20
    #define OP_RATE_MASK 0xFF000000
    #define OP_RATE_SHIFT 24
#define  RMX_HOST_INT_MASK 0x6174
    #define RMX_HOST_INT_MASK_INT_EN_LIST0_DONE_MASK 0x00000001
    #define RMX_HOST_INT_MASK_INT_EN_LIST0_DONE_SHIFT 0
    #define RMX_HOST_INT_MASK_INT_EN_LIST1_DONE_MASK 0x00000002
    #define RMX_HOST_INT_MASK_INT_EN_LIST1_DONE_SHIFT 1
    #define RMX_HOST_INT_MASK_INT_EN_LIST2_DONE_MASK 0x00000004
    #define RMX_HOST_INT_MASK_INT_EN_LIST2_DONE_SHIFT 2
    #define RMX_HOST_INT_MASK_INT_EN_LIST3_DONE_MASK 0x00000008
    #define RMX_HOST_INT_MASK_INT_EN_LIST3_DONE_SHIFT 3
    #define RMX_HOST_INT_MASK_INT_EN_LIST4_DONE_MASK 0x00000010
    #define RMX_HOST_INT_MASK_INT_EN_LIST4_DONE_SHIFT 4
    #define RMX_HOST_INT_MASK_INT_EN_LIST5_DONE_MASK 0x00000020
    #define RMX_HOST_INT_MASK_INT_EN_LIST5_DONE_SHIFT 5
    #define RMX_HOST_INT_MASK_INT_EN_LIST6_DONE_MASK 0x00000040
    #define RMX_HOST_INT_MASK_INT_EN_LIST6_DONE_SHIFT 6
    #define RMX_HOST_INT_MASK_INT_EN_LIST7_DONE_MASK 0x00000080
    #define RMX_HOST_INT_MASK_INT_EN_LIST7_DONE_SHIFT 7
    #define RMX_HOST_INT_MASK_INT_EN_FRM_CNT_ZERO_MASK 0x00010000
    #define RMX_HOST_INT_MASK_INT_EN_FRM_CNT_ZERO_SHIFT 16
#define  RMX_INT_STATUS 0x6170
    #define LIST0_DONE_MASK 0x00000001
    #define LIST0_DONE_SHIFT 0
    #define LIST1_DONE_MASK 0x00000002
    #define LIST1_DONE_SHIFT 1
    #define LIST2_DONE_MASK 0x00000004
    #define LIST2_DONE_SHIFT 2
    #define LIST3_DONE_MASK 0x00000008
    #define LIST3_DONE_SHIFT 3
    #define LIST4_DONE_MASK 0x00000010
    #define LIST4_DONE_SHIFT 4
    #define LIST5_DONE_MASK 0x00000020
    #define LIST5_DONE_SHIFT 5
    #define LIST6_DONE_MASK 0x00000040
    #define LIST6_DONE_SHIFT 6
    #define LIST7_DONE_MASK 0x00000080
    #define LIST7_DONE_SHIFT 7
    #define FRM_CNT_ZERO_INT_MASK 0x00010000
    #define FRM_CNT_ZERO_INT_SHIFT 16
#define  RMX_MIPS_INT_MASK 0x6178
    #define RMX_MIPS_INT_MASK_INT_EN_LIST0_DONE_MASK 0x00000001
    #define RMX_MIPS_INT_MASK_INT_EN_LIST0_DONE_SHIFT 0
    #define RMX_MIPS_INT_MASK_INT_EN_LIST1_DONE_MASK 0x00000002
    #define RMX_MIPS_INT_MASK_INT_EN_LIST1_DONE_SHIFT 1
    #define RMX_MIPS_INT_MASK_INT_EN_LIST2_DONE_MASK 0x00000004
    #define RMX_MIPS_INT_MASK_INT_EN_LIST2_DONE_SHIFT 2
    #define RMX_MIPS_INT_MASK_INT_EN_LIST3_DONE_MASK 0x00000008
    #define RMX_MIPS_INT_MASK_INT_EN_LIST3_DONE_SHIFT 3
    #define RMX_MIPS_INT_MASK_INT_EN_LIST4_DONE_MASK 0x00000010
    #define RMX_MIPS_INT_MASK_INT_EN_LIST4_DONE_SHIFT 4
    #define RMX_MIPS_INT_MASK_INT_EN_LIST5_DONE_MASK 0x00000020
    #define RMX_MIPS_INT_MASK_INT_EN_LIST5_DONE_SHIFT 5
    #define RMX_MIPS_INT_MASK_INT_EN_LIST6_DONE_MASK 0x00000040
    #define RMX_MIPS_INT_MASK_INT_EN_LIST6_DONE_SHIFT 6
    #define RMX_MIPS_INT_MASK_INT_EN_LIST7_DONE_MASK 0x00000080
    #define RMX_MIPS_INT_MASK_INT_EN_LIST7_DONE_SHIFT 7
    #define RMX_MIPS_INT_MASK_INT_EN_FRM_CNT_ZERO_MASK 0x00010000
    #define RMX_MIPS_INT_MASK_INT_EN_FRM_CNT_ZERO_SHIFT 16
#define  RMX_STATE_L 0x6264
    #define STATE_L_MASK 0xFFFFFFFF
    #define STATE_L_SHIFT 0
#define  RMX_STATE_U 0x6260
    #define STATE_U_MASK 0xFFFFFFFF
    #define STATE_U_SHIFT 0
#define  ROUTING_INFO_ADR 0x6080
    #define ROUTING_INFO_BASE_MASK 0x0000000F
    #define ROUTING_INFO_BASE_SHIFT 0
#define  ROUTING_INFO_WDAT 0x6084
    #define DECRYPT_MODE_MASK 0x00000007
    #define DECRYPT_MODE_SHIFT 0
    #define DES_CTRL_S0_MASK 0x00000008
    #define DES_CTRL_S0_SHIFT 3
    #define DES_CTRL_S1_MASK 0x00000010
    #define DES_CTRL_S1_SHIFT 4
    #define DES_CTRL_S2_MASK 0x00000020
    #define DES_CTRL_S2_SHIFT 5
    #define DES_MODE_MASK 0x00000040
    #define DES_MODE_SHIFT 6
    #define DES_OC_MASK 0x00000080
    #define DES_OC_SHIFT 7
    #define VECTOR_IDX_MASK 0x00000700
    #define VECTOR_IDX_SHIFT 8
    #define CW_IDX01_MASK 0x0007C000
    #define CW_IDX01_SHIFT 14
    #define CW_IDX10_MASK 0x01F00000
    #define CW_IDX10_SHIFT 20
    #define CW_IDX11_MASK 0x7C000000
    #define CW_IDX11_SHIFT 26
#define  RSA_ARRAY_CTRL 0x182C
    #define ARRAY_DIR_WADR_MASK 0x0000007F
    #define ARRAY_DIR_WADR_SHIFT 0
    #define RSA_ARRAY_CTRL_IDLE_MASK 0x00000080
    #define RSA_ARRAY_CTRL_IDLE_SHIFT 7
#define  RSA_ARRAY_WDAT_H 0x1828
    #define RSA_ARRAY_WDAT_H_WDAT_MASK 0xFFFFFFFF
    #define RSA_ARRAY_WDAT_H_WDAT_SHIFT 0
#define  RSA_ARRAY_WDAT_L 0x1824
    #define RSA_ARRAY_WDAT_L_WDAT_MASK 0xFFFFFFFF
    #define RSA_ARRAY_WDAT_L_WDAT_SHIFT 0
#define  RSA_CLIENT_CTRL 0x1800
    #define MOD_WEN_MASK 0x00000001
    #define MOD_WEN_SHIFT 0
    #define EXP_WEN_MASK 0x00000002
    #define EXP_WEN_SHIFT 1
    #define DAT_WEN_MASK 0x00000004
    #define DAT_WEN_SHIFT 2
    #define REG_IDX_MASK 0x000003F0
    #define REG_IDX_SHIFT 4
#define  RSA_CLIENT_DIRTY0 0x180C
    #define RSA_CLIENT_DIRTY0_DIRTY_MASK 0xFFFFFFFF
    #define RSA_CLIENT_DIRTY0_DIRTY_SHIFT 0
#define  RSA_CLIENT_DIRTY1 0x1810
    #define RSA_CLIENT_DIRTY1_DIRTY_MASK 0xFFFFFFFF
    #define RSA_CLIENT_DIRTY1_DIRTY_SHIFT 0
#define  RSA_CLIENT_READ 0x1808
    #define RSA_CLIENT_READ_DATA_MASK 0xFFFFFFFF
    #define RSA_CLIENT_READ_DATA_SHIFT 0
#define  RSA_CLIENT_WRITE 0x1804
    #define RSA_CLIENT_WRITE_DATA_MASK 0xFFFFFFFF
    #define RSA_CLIENT_WRITE_DATA_SHIFT 0
#define  RSA_COPY_CTRL 0x1820
    #define COPY_START_ADR_MASK 0x0000007F
    #define COPY_START_ADR_SHIFT 0
    #define COPY_NUM_MASK 0x00000F80
    #define COPY_NUM_SHIFT 7
    #define RSA_COPY_CTRL_IDLE_MASK 0x00001000
    #define RSA_COPY_CTRL_IDLE_SHIFT 12
#define  RSA_DUMMY_REG 0x1868
    #define RSA_DUMMY_REG_DUMMY_BITS_MASK 0xFFFFFFFF
    #define RSA_DUMMY_REG_DUMMY_BITS_SHIFT 0
#define  RSA_ENGINE_CTRL 0x1814
    #define DST_MASK 0x00000001
    #define DST_SHIFT 0
    #define RSA_ENGINE_CTRL_SRC_MASK 0x00000002
    #define RSA_ENGINE_CTRL_SRC_SHIFT 1
    #define ITERATE_MASK 0x00000004
    #define ITERATE_SHIFT 2
    #define RSA_ENGINE_CTRL_BUSY_MASK 0x00000008
    #define RSA_ENGINE_CTRL_BUSY_SHIFT 3
    #define ARRAY_WADR_MASK 0x000007F0
    #define ARRAY_WADR_SHIFT 4
    #define NUM_WRITES_MASK 0x0001F000
    #define NUM_WRITES_SHIFT 12
    #define MOD_SIZE_MASK 0x7FF00000
    #define MOD_SIZE_SHIFT 20
#define  RSA_INT_MASK 0x1818
    #define RSA_INT_MASK_HOST_INT_MASK_MASK 0x00000001
    #define RSA_INT_MASK_HOST_INT_MASK_SHIFT 0
    #define RSA_INT_MASK_MIPS_INT_MASK_MASK 0x00000002
    #define RSA_INT_MASK_MIPS_INT_MASK_SHIFT 1
#define  RSA_INT_STATUS 0x181C
    #define RSA_INT_STATUS_ERROR_MASK 0x00000002
    #define RSA_INT_STATUS_ERROR_SHIFT 1
    #define RSA_INT_STATUS_DONE_MASK 0x00000004
    #define RSA_INT_STATUS_DONE_SHIFT 2
#define  RSA_NVM_CONFIG0 0x1840
    #define TPP_MASK 0x0000FFFF
    #define TPP_SHIFT 0
    #define TPR_MASK 0x00FF0000
    #define TPR_SHIFT 16
    #define TPCP_MASK 0x0F000000
    #define TPCP_SHIFT 24
#define  RSA_NVM_CONFIG1 0x1844
    #define TVPPS_MASK 0x0000FFFF
    #define TVPPS_SHIFT 0
    #define TPUR_MASK 0x00FF0000
    #define TPUR_SHIFT 16
#define  RSA_NVM_CONFIG2 0x1848
    #define TVPPH_MASK 0xFFFFFFFF
    #define TVPPH_SHIFT 0
#define  RSA_NVM_CONFIG3 0x184C
    #define TRCYC_MASK 0x0000000F
    #define TRCYC_SHIFT 0
    #define TRR_MASK 0x000000F0
    #define TRR_SHIFT 4
    #define TWCYC_MASK 0x00000F00
    #define TWCYC_SHIFT 8
    #define TWR_MASK 0x0000F000
    #define TWR_SHIFT 12
#define  RSA_NVM_CONFIG4 0x1850
    #define MAX_PGM_NUM_MASK 0x000000FF
    #define MAX_PGM_NUM_SHIFT 0
    #define PWR_DOWN_MASK 0x00000100
    #define PWR_DOWN_SHIFT 8
#define  RSA_NVM_CONFIG5 0x1854
    #define TUCYC_MASK 0x00000FFF
    #define TUCYC_SHIFT 0
    #define TUSTR_MASK 0x007FF000
    #define TUSTR_SHIFT 12
    #define TUEND_MASK 0xFF800000
    #define TUEND_SHIFT 23
#define  RSA_NVM_CTRL 0x1834
    #define NVM_DATA_MASK 0x000000FF
    #define NVM_DATA_SHIFT 0
    #define NVM_ADDR_MASK 0x000FFF00
    #define NVM_ADDR_SHIFT 8
    #define NVM_RD_MASK 0x10000000
    #define NVM_RD_SHIFT 28
    #define NVM_WR_MASK 0x20000000
    #define NVM_WR_SHIFT 29
    #define NVM_STRT_PUMP_MASK 0x40000000
    #define NVM_STRT_PUMP_SHIFT 30
    #define NVM_STOP_PUMP_MASK 0x80000000
    #define NVM_STOP_PUMP_SHIFT 31
#define  RSA_NVM_SKU 0x1860
    #define NVM_SKU_MASK 0x01FFFFFF
    #define NVM_SKU_SHIFT 0
    #define I2C_ADDR_MASK 0xFE000000
    #define I2C_ADDR_SHIFT 25
#define  RSA_NVM_STATUS 0x1838
    #define NVM_BOOTED_MASK 0x00000001
    #define NVM_BOOTED_SHIFT 0
    #define NVM_RDY_MASK 0x00000002
    #define NVM_RDY_SHIFT 1
    #define NVM_PASS_MASK 0x00000004
    #define NVM_PASS_SHIFT 2
    #define NVM_LOCKED_MASK 0x00000008
    #define NVM_LOCKED_SHIFT 3
#define  RSA_NVM_TEST 0x183C
    #define NVM_TEST_DATA_MASK 0x0000FFFF
    #define NVM_TEST_DATA_SHIFT 0
    #define NVM_MR_WR_MASK 0x00010000
    #define NVM_MR_WR_SHIFT 16
    #define NVM_MRA_WR_MASK 0x00020000
    #define NVM_MRA_WR_SHIFT 17
    #define NVM_MRB_WR_MASK 0x00040000
    #define NVM_MRB_WR_SHIFT 18
    #define NVM_MR_RST_MASK 0x00080000
    #define NVM_MR_RST_SHIFT 19
#define  RSA_SFT_RSTN 0x1830
    #define RSA_SFT_RSTN_SFT_RSTN_MASK 0x00000001
    #define RSA_SFT_RSTN_SFT_RSTN_SHIFT 0
    #define NVM_RSTN_MASK 0x00000002
    #define NVM_RSTN_SHIFT 1
#define  RSA_UNIQUE_ID 0x1864
    #define UNIQUE_ID_MASK 0xFFFFFFFF
    #define UNIQUE_ID_SHIFT 0
#define  SATA0_HOST_CTRL 0xD010
    #define SATA0_HOST_CTRL_AHB_BUS_SIZE_MASK 0x00000003
    #define SATA0_HOST_CTRL_AHB_BUS_SIZE_SHIFT 0
    #define SATA0_HOST_CTRL_DMA_DIRECTION_MASK 0x00000004
    #define SATA0_HOST_CTRL_DMA_DIRECTION_SHIFT 2
    #define SATA0_HOST_CTRL_DMA_LL_ON_MASK 0x00000008
    #define SATA0_HOST_CTRL_DMA_LL_ON_SHIFT 3
    #define SATA0_HOST_CTRL_DMA_INIT_MASK 0x00000010
    #define SATA0_HOST_CTRL_DMA_INIT_SHIFT 4
#define  SATA0_PHY_CR_IN 0xD03C
    #define SATA0_PHY_CR_IN_DATA_MASK 0x0000FFFF
    #define SATA0_PHY_CR_IN_DATA_SHIFT 0
    #define SATA0_PHY_CR_IN_ACK_MASK 0x00010000
    #define SATA0_PHY_CR_IN_ACK_SHIFT 16
#define  SATA0_PHY_CR_OUT 0xD038
    #define SATA0_PHY_CR_OUT_DATA_MASK 0x0000FFFF
    #define SATA0_PHY_CR_OUT_DATA_SHIFT 0
    #define SATA0_PHY_CR_OUT_CAP_ADDR_MASK 0x00010000
    #define SATA0_PHY_CR_OUT_CAP_ADDR_SHIFT 16
    #define SATA0_PHY_CR_OUT_CAP_DATA_MASK 0x00020000
    #define SATA0_PHY_CR_OUT_CAP_DATA_SHIFT 17
    #define SATA0_PHY_CR_OUT_WRITE_MASK 0x00040000
    #define SATA0_PHY_CR_OUT_WRITE_SHIFT 18
    #define SATA0_PHY_CR_OUT_READ_MASK 0x00080000
    #define SATA0_PHY_CR_OUT_READ_SHIFT 19
#define  SATA1_HOST_CTRL 0xD014
    #define SATA1_HOST_CTRL_AHB_BUS_SIZE_MASK 0x00000003
    #define SATA1_HOST_CTRL_AHB_BUS_SIZE_SHIFT 0
    #define SATA1_HOST_CTRL_DMA_DIRECTION_MASK 0x00000004
    #define SATA1_HOST_CTRL_DMA_DIRECTION_SHIFT 2
    #define SATA1_HOST_CTRL_DMA_LL_ON_MASK 0x00000008
    #define SATA1_HOST_CTRL_DMA_LL_ON_SHIFT 3
    #define SATA1_HOST_CTRL_DMA_INIT_MASK 0x00000010
    #define SATA1_HOST_CTRL_DMA_INIT_SHIFT 4
#define  SATA1_PHY_CR_IN 0xD044
    #define SATA1_PHY_CR_IN_DATA_MASK 0x0000FFFF
    #define SATA1_PHY_CR_IN_DATA_SHIFT 0
    #define SATA1_PHY_CR_IN_ACK_MASK 0x00010000
    #define SATA1_PHY_CR_IN_ACK_SHIFT 16
#define  SATA1_PHY_CR_OUT 0xD040
    #define SATA1_PHY_CR_OUT_DATA_MASK 0x0000FFFF
    #define SATA1_PHY_CR_OUT_DATA_SHIFT 0
    #define SATA1_PHY_CR_OUT_CAP_ADDR_MASK 0x00010000
    #define SATA1_PHY_CR_OUT_CAP_ADDR_SHIFT 16
    #define SATA1_PHY_CR_OUT_CAP_DATA_MASK 0x00020000
    #define SATA1_PHY_CR_OUT_CAP_DATA_SHIFT 17
    #define SATA1_PHY_CR_OUT_WRITE_MASK 0x00040000
    #define SATA1_PHY_CR_OUT_WRITE_SHIFT 18
    #define SATA1_PHY_CR_OUT_READ_MASK 0x00080000
    #define SATA1_PHY_CR_OUT_READ_SHIFT 19
#define  SATA_DEBUG 0xD048
    #define SATA_DEBUG_DEBUG_DATA_MASK 0x000FFFFF
    #define SATA_DEBUG_DEBUG_DATA_SHIFT 0
#define  SATA_HOST_INT_MASK 0xD024
    #define SATA_HOST_INT_MASK_SATA0_INT_MASK_MASK 0x00000001
    #define SATA_HOST_INT_MASK_SATA0_INT_MASK_SHIFT 0
    #define SATA_HOST_INT_MASK_SATA1_INT_MASK_MASK 0x00000002
    #define SATA_HOST_INT_MASK_SATA1_INT_MASK_SHIFT 1
    #define SATA_HOST_INT_MASK_DMAC_INT_MASK_MASK 0x00000004
    #define SATA_HOST_INT_MASK_DMAC_INT_MASK_SHIFT 2
    #define SATA_HOST_INT_MASK_MCIF_INT_MASK_MASK 0x00000008
    #define SATA_HOST_INT_MASK_MCIF_INT_MASK_SHIFT 3
#define  SATA_INT_STATUS 0xD01C
    #define SATA0_INT_MASK 0x00000001
    #define SATA0_INT_SHIFT 0
    #define SATA1_INT_MASK 0x00000002
    #define SATA1_INT_SHIFT 1
    #define DMAC_INT_MASK 0x00000004
    #define DMAC_INT_SHIFT 2
    #define MCIF_INT_MASK 0x00000008
    #define MCIF_INT_SHIFT 3
#define  SATA_MIPS_INT_MASK 0xD020
    #define SATA_MIPS_INT_MASK_SATA0_INT_MASK_MASK 0x00000001
    #define SATA_MIPS_INT_MASK_SATA0_INT_MASK_SHIFT 0
    #define SATA_MIPS_INT_MASK_SATA1_INT_MASK_MASK 0x00000002
    #define SATA_MIPS_INT_MASK_SATA1_INT_MASK_SHIFT 1
    #define SATA_MIPS_INT_MASK_DMAC_INT_MASK_MASK 0x00000004
    #define SATA_MIPS_INT_MASK_DMAC_INT_MASK_SHIFT 2
    #define SATA_MIPS_INT_MASK_MCIF_INT_MASK_MASK 0x00000008
    #define SATA_MIPS_INT_MASK_MCIF_INT_MASK_SHIFT 3
#define  SATA_PHY_ANALOG_CTRL 0xD034
    #define SATA0_PHY_CTRL_TX_LVL_MASK 0x0000001F
    #define SATA0_PHY_CTRL_TX_LVL_SHIFT 0
    #define SATA0_PHY_CTRL_LOS_LVL_MASK 0x000003E0
    #define SATA0_PHY_CTRL_LOS_LVL_SHIFT 5
    #define SATA0_PHY_CTRL_ACJT_LVL_MASK 0x00007C00
    #define SATA0_PHY_CTRL_ACJT_LVL_SHIFT 10
    #define SATA1_PHY_CTRL_TX_LVL_MASK 0x001F0000
    #define SATA1_PHY_CTRL_TX_LVL_SHIFT 16
    #define SATA1_PHY_CTRL_LOS_LVL_MASK 0x03E00000
    #define SATA1_PHY_CTRL_LOS_LVL_SHIFT 21
    #define SATA1_PHY_CTRL_ACJT_LVL_MASK 0x7C000000
    #define SATA1_PHY_CTRL_ACJT_LVL_SHIFT 26
#define  SATA_PHY_COMMON_STATUS 0xD028
    #define SATA0_PHY_TXDONE_MASK 0x00000001
    #define SATA0_PHY_TXDONE_SHIFT 0
    #define SATA0_PHY_RX_PLL_STATE_MASK 0x00000002
    #define SATA0_PHY_RX_PLL_STATE_SHIFT 1
    #define SATA0_PHY_RX_VALID_MASK 0x00000004
    #define SATA0_PHY_RX_VALID_SHIFT 2
    #define SATA0_PHY_OP_DONE_MASK 0x00000008
    #define SATA0_PHY_OP_DONE_SHIFT 3
    #define SATA0_PHY_POWER_GOOD_MASK 0x00000010
    #define SATA0_PHY_POWER_GOOD_SHIFT 4
    #define SATA0_PHY_DTB_OUT_MASK 0x00000060
    #define SATA0_PHY_DTB_OUT_SHIFT 5
    #define SATA1_PHY_TXDONE_MASK 0x00010000
    #define SATA1_PHY_TXDONE_SHIFT 16
    #define SATA1_PHY_RX_PLL_STATE_MASK 0x00020000
    #define SATA1_PHY_RX_PLL_STATE_SHIFT 17
    #define SATA1_PHY_RX_VALID_MASK 0x00040000
    #define SATA1_PHY_RX_VALID_SHIFT 18
    #define SATA1_PHY_OP_DONE_MASK 0x00080000
    #define SATA1_PHY_OP_DONE_SHIFT 19
    #define SATA1_PHY_POWER_GOOD_MASK 0x00100000
    #define SATA1_PHY_POWER_GOOD_SHIFT 20
    #define SATA1_PHY_DTB_OUT_MASK 0x00600000
    #define SATA1_PHY_DTB_OUT_SHIFT 21
#define  SATA_PHY_MPLL_CTRL 0xD030
    #define SATA0_PHY_CTRL_MPLL_PWRON_MASK 0x00000001
    #define SATA0_PHY_CTRL_MPLL_PWRON_SHIFT 0
    #define SATA0_PHY_CTRL_MPLL_PRESCALE_MASK 0x00000006
    #define SATA0_PHY_CTRL_MPLL_PRESCALE_SHIFT 1
    #define SATA0_PHY_CTRL_MPLL_SS_EN_MASK 0x00000008
    #define SATA0_PHY_CTRL_MPLL_SS_EN_SHIFT 3
    #define SATA0_PHY_CTRL_MPLL_NCY_MASK 0x000001F0
    #define SATA0_PHY_CTRL_MPLL_NCY_SHIFT 4
    #define SATA0_PHY_CTRL_MPLL_NCY5_MASK 0x00000600
    #define SATA0_PHY_CTRL_MPLL_NCY5_SHIFT 9
    #define SATA1_PHY_CTRL_MPLL_PWRON_MASK 0x00010000
    #define SATA1_PHY_CTRL_MPLL_PWRON_SHIFT 16
    #define SATA1_PHY_CTRL_MPLL_PRESCALE_MASK 0x00060000
    #define SATA1_PHY_CTRL_MPLL_PRESCALE_SHIFT 17
    #define SATA1_PHY_CTRL_MPLL_SS_EN_MASK 0x00080000
    #define SATA1_PHY_CTRL_MPLL_SS_EN_SHIFT 19
    #define SATA1_PHY_CTRL_MPLL_NCY_MASK 0x01F00000
    #define SATA1_PHY_CTRL_MPLL_NCY_SHIFT 20
    #define SATA1_PHY_CTRL_MPLL_NCY5_MASK 0x06000000
    #define SATA1_PHY_CTRL_MPLL_NCY5_SHIFT 25
#define  SATA_PHY_TXRX_CTRL 0xD02C
    #define SATA0_PHY_CTRL_TX_BOOST_MASK 0x0000000F
    #define SATA0_PHY_CTRL_TX_BOOST_SHIFT 0
    #define SATA0_PHY_CTRL_TX_ATTEN_MASK 0x00000070
    #define SATA0_PHY_CTRL_TX_ATTEN_SHIFT 4
    #define SATA0_PHY_CTRL_TX_EDGERATE_MASK 0x00000180
    #define SATA0_PHY_CTRL_TX_EDGERATE_SHIFT 7
    #define SATA0_PHY_CTRL_RX_EQ_VAL_MASK 0x00000E00
    #define SATA0_PHY_CTRL_RX_EQ_VAL_SHIFT 9
    #define SATA0_PHY_CTRL_RX_DPLL_MODE_MASK 0x00007000
    #define SATA0_PHY_CTRL_RX_DPLL_MODE_SHIFT 12
    #define SATA0_PHY_CTRL_RXPLL_PWRON_MASK 0x00008000
    #define SATA0_PHY_CTRL_RXPLL_PWRON_SHIFT 15
    #define SATA1_PHY_CTRL_TX_BOOST_MASK 0x000F0000
    #define SATA1_PHY_CTRL_TX_BOOST_SHIFT 16
    #define SATA1_PHY_CTRL_TX_ATTEN_MASK 0x00700000
    #define SATA1_PHY_CTRL_TX_ATTEN_SHIFT 20
    #define SATA1_PHY_CTRL_TX_EDGERATE_MASK 0x01800000
    #define SATA1_PHY_CTRL_TX_EDGERATE_SHIFT 23
    #define SATA1_PHY_CTRL_RX_EQ_VAL_MASK 0x0E000000
    #define SATA1_PHY_CTRL_RX_EQ_VAL_SHIFT 25
    #define SATA1_PHY_CTRL_RX_DPLL_MODE_MASK 0x70000000
    #define SATA1_PHY_CTRL_RX_DPLL_MODE_SHIFT 28
    #define SATA1_PHY_CTRL_RXPLL_PWRON_MASK 0x80000000
    #define SATA1_PHY_CTRL_RXPLL_PWRON_SHIFT 31
#define  SATA_SFT_RESETS 0xD018
    #define PHY0_SFT_RSTN_MASK 0x00000001
    #define PHY0_SFT_RSTN_SHIFT 0
    #define PHY1_SFT_RSTN_MASK 0x00000002
    #define PHY1_SFT_RSTN_SHIFT 1
    #define SATA0_SFT_RSTN_MASK 0x00000004
    #define SATA0_SFT_RSTN_SHIFT 2
    #define SATA1_SFT_RSTN_MASK 0x00000008
    #define SATA1_SFT_RSTN_SHIFT 3
    #define MCIF_SFT_RSTN_MASK 0x00000010
    #define MCIF_SFT_RSTN_SHIFT 4
    #define REG_SFT_RSTN_MASK 0x00000020
    #define REG_SFT_RSTN_SHIFT 5
    #define AHB_SFT_RSTN_MASK 0x00000040
    #define AHB_SFT_RSTN_SHIFT 6
#define  SCC0_COMMAND 0x1030
    #define SCC0_COMMAND_COMMAND_MASK 0x00000003
    #define SCC0_COMMAND_COMMAND_SHIFT 0
    #define SCC0_COMMAND_READ_BYTECNT_MASK 0x00007F00
    #define SCC0_COMMAND_READ_BYTECNT_SHIFT 8
    #define SCC0_COMMAND_INT_EN_RDDONE_MASK 0x00008000
    #define SCC0_COMMAND_INT_EN_RDDONE_SHIFT 15
    #define SCC0_COMMAND_BYTECNT_MASK 0x007F0000
    #define SCC0_COMMAND_BYTECNT_SHIFT 16
    #define SCC0_COMMAND_INT_EN_WRDONE_MASK 0x00800000
    #define SCC0_COMMAND_INT_EN_WRDONE_SHIFT 23
#define  SCC0_CONFIG0 0x1020
    #define SCC0_CONFIG0_ETU_VALUE_MASK 0x0000FFFF
    #define SCC0_CONFIG0_ETU_VALUE_SHIFT 0
    #define SCC0_CONFIG0_TPRH_MASK 0xFFFF0000
    #define SCC0_CONFIG0_TPRH_SHIFT 16
#define  SCC0_CONFIG1 0x1024
    #define SCC0_CONFIG1_RX_RETRYCNT_MASK 0x00000003
    #define SCC0_CONFIG1_RX_RETRYCNT_SHIFT 0
    #define SCC0_CONFIG1_TX_RETRYCNT_MASK 0x0000000C
    #define SCC0_CONFIG1_TX_RETRYCNT_SHIFT 2
    #define SCC0_CONFIG1_RX_RETRYEN_MASK 0x00000010
    #define SCC0_CONFIG1_RX_RETRYEN_SHIFT 4
    #define SCC0_CONFIG1_TX_RETRYEN_MASK 0x00000020
    #define SCC0_CONFIG1_TX_RETRYEN_SHIFT 5
    #define SCC0_CONFIG1_TS_MASK 0x00000040
    #define SCC0_CONFIG1_TS_SHIFT 6
    #define SCC0_CONFIG1_PARITY_EN_MASK 0x00000080
    #define SCC0_CONFIG1_PARITY_EN_SHIFT 7
    #define SCC0_CONFIG1_TGUARD_MASK 0x0000FF00
    #define SCC0_CONFIG1_TGUARD_SHIFT 8
    #define CARD_READER_MODE_MASK 0x00010000
    #define CARD_READER_MODE_SHIFT 16
#define  SCC0_DATA_LOAD 0x1028
    #define SCC0_DATA_LOAD_DATA_LOAD_MASK 0x000000FF
    #define SCC0_DATA_LOAD_DATA_LOAD_SHIFT 0
#define  SCC0_DATA_READ 0x102C
    #define SCC0_DATA_READ_DATA_READ_MASK 0x000000FF
    #define SCC0_DATA_READ_DATA_READ_SHIFT 0
#define  SCC0_STATUS 0x1034
    #define SCC0_STATUS_BYTEXFERED_MASK 0x0000007F
    #define SCC0_STATUS_BYTEXFERED_SHIFT 0
    #define SCC0_STATUS_CARD_PRESENT_MASK 0x00000100
    #define SCC0_STATUS_CARD_PRESENT_SHIFT 8
    #define SCC0_STATUS_ACTIVE_MASK 0x00000200
    #define SCC0_STATUS_ACTIVE_SHIFT 9
#define  SCC1_COMMAND 0x1048
    #define SCC1_COMMAND_COMMAND_MASK 0x00000003
    #define SCC1_COMMAND_COMMAND_SHIFT 0
    #define SCC1_COMMAND_READ_BYTECNT_MASK 0x00007F00
    #define SCC1_COMMAND_READ_BYTECNT_SHIFT 8
    #define SCC1_COMMAND_INT_EN_RDDONE_MASK 0x00008000
    #define SCC1_COMMAND_INT_EN_RDDONE_SHIFT 15
    #define SCC1_COMMAND_BYTECNT_MASK 0x007F0000
    #define SCC1_COMMAND_BYTECNT_SHIFT 16
    #define SCC1_COMMAND_INT_EN_WRDONE_MASK 0x00800000
    #define SCC1_COMMAND_INT_EN_WRDONE_SHIFT 23
#define  SCC1_CONFIG0 0x1038
    #define SCC1_CONFIG0_ETU_VALUE_MASK 0x0000FFFF
    #define SCC1_CONFIG0_ETU_VALUE_SHIFT 0
    #define SCC1_CONFIG0_TPRH_MASK 0xFFFF0000
    #define SCC1_CONFIG0_TPRH_SHIFT 16
#define  SCC1_CONFIG1 0x103C
    #define SCC1_CONFIG1_RX_RETRYCNT_MASK 0x00000003
    #define SCC1_CONFIG1_RX_RETRYCNT_SHIFT 0
    #define SCC1_CONFIG1_TX_RETRYCNT_MASK 0x0000000C
    #define SCC1_CONFIG1_TX_RETRYCNT_SHIFT 2
    #define SCC1_CONFIG1_RX_RETRYEN_MASK 0x00000010
    #define SCC1_CONFIG1_RX_RETRYEN_SHIFT 4
    #define SCC1_CONFIG1_TX_RETRYEN_MASK 0x00000020
    #define SCC1_CONFIG1_TX_RETRYEN_SHIFT 5
    #define SCC1_CONFIG1_TS_MASK 0x00000040
    #define SCC1_CONFIG1_TS_SHIFT 6
    #define SCC1_CONFIG1_PARITY_EN_MASK 0x00000080
    #define SCC1_CONFIG1_PARITY_EN_SHIFT 7
    #define SCC1_CONFIG1_TGUARD_MASK 0x0000FF00
    #define SCC1_CONFIG1_TGUARD_SHIFT 8
#define  SCC1_DATA_LOAD 0x1040
    #define SCC1_DATA_LOAD_DATA_LOAD_MASK 0x000000FF
    #define SCC1_DATA_LOAD_DATA_LOAD_SHIFT 0
#define  SCC1_DATA_READ 0x1044
    #define SCC1_DATA_READ_DATA_READ_MASK 0x000000FF
    #define SCC1_DATA_READ_DATA_READ_SHIFT 0
#define  SCC1_STATUS 0x104C
    #define SCC1_STATUS_BYTEXFERED_MASK 0x0000007F
    #define SCC1_STATUS_BYTEXFERED_SHIFT 0
    #define SCC1_STATUS_CARD_PRESENT_MASK 0x00000100
    #define SCC1_STATUS_CARD_PRESENT_SHIFT 8
    #define SCC1_STATUS_ACTIVE_MASK 0x00000200
    #define SCC1_STATUS_ACTIVE_SHIFT 9
#define  SCC2_COMMAND 0x1060
    #define SCC2_COMMAND_COMMAND_MASK 0x00000003
    #define SCC2_COMMAND_COMMAND_SHIFT 0
    #define SCC2_COMMAND_READ_BYTECNT_MASK 0x00007F00
    #define SCC2_COMMAND_READ_BYTECNT_SHIFT 8
    #define SCC2_COMMAND_INT_EN_RDDONE_MASK 0x00008000
    #define SCC2_COMMAND_INT_EN_RDDONE_SHIFT 15
    #define SCC2_COMMAND_BYTECNT_MASK 0x007F0000
    #define SCC2_COMMAND_BYTECNT_SHIFT 16
    #define SCC2_COMMAND_INT_EN_WRDONE_MASK 0x00800000
    #define SCC2_COMMAND_INT_EN_WRDONE_SHIFT 23
#define  SCC2_CONFIG0 0x1050
    #define SCC2_CONFIG0_ETU_VALUE_MASK 0x0000FFFF
    #define SCC2_CONFIG0_ETU_VALUE_SHIFT 0
    #define SCC2_CONFIG0_TPRH_MASK 0xFFFF0000
    #define SCC2_CONFIG0_TPRH_SHIFT 16
#define  SCC2_CONFIG1 0x1054
    #define SCC2_CONFIG1_RX_RETRYCNT_MASK 0x00000003
    #define SCC2_CONFIG1_RX_RETRYCNT_SHIFT 0
    #define SCC2_CONFIG1_TX_RETRYCNT_MASK 0x0000000C
    #define SCC2_CONFIG1_TX_RETRYCNT_SHIFT 2
    #define SCC2_CONFIG1_RX_RETRYEN_MASK 0x00000010
    #define SCC2_CONFIG1_RX_RETRYEN_SHIFT 4
    #define SCC2_CONFIG1_TX_RETRYEN_MASK 0x00000020
    #define SCC2_CONFIG1_TX_RETRYEN_SHIFT 5
    #define SCC2_CONFIG1_TS_MASK 0x00000040
    #define SCC2_CONFIG1_TS_SHIFT 6
    #define SCC2_CONFIG1_PARITY_EN_MASK 0x00000080
    #define SCC2_CONFIG1_PARITY_EN_SHIFT 7
    #define SCC2_CONFIG1_TGUARD_MASK 0x0000FF00
    #define SCC2_CONFIG1_TGUARD_SHIFT 8
#define  SCC2_DATA_LOAD 0x1058
    #define SCC2_DATA_LOAD_DATA_LOAD_MASK 0x000000FF
    #define SCC2_DATA_LOAD_DATA_LOAD_SHIFT 0
#define  SCC2_DATA_READ 0x105C
    #define SCC2_DATA_READ_DATA_READ_MASK 0x000000FF
    #define SCC2_DATA_READ_DATA_READ_SHIFT 0
#define  SCC2_STATUS 0x1064
    #define SCC2_STATUS_BYTEXFERED_MASK 0x0000007F
    #define SCC2_STATUS_BYTEXFERED_SHIFT 0
    #define SCC2_STATUS_CARD_PRESENT_MASK 0x00000100
    #define SCC2_STATUS_CARD_PRESENT_SHIFT 8
    #define SCC2_STATUS_ACTIVE_MASK 0x00000200
    #define SCC2_STATUS_ACTIVE_SHIFT 9
#define  SCC3_COMMAND 0x1078
    #define SCC3_COMMAND_COMMAND_MASK 0x00000003
    #define SCC3_COMMAND_COMMAND_SHIFT 0
    #define SCC3_COMMAND_READ_BYTECNT_MASK 0x00007F00
    #define SCC3_COMMAND_READ_BYTECNT_SHIFT 8
    #define SCC3_COMMAND_INT_EN_RDDONE_MASK 0x00008000
    #define SCC3_COMMAND_INT_EN_RDDONE_SHIFT 15
    #define SCC3_COMMAND_BYTECNT_MASK 0x007F0000
    #define SCC3_COMMAND_BYTECNT_SHIFT 16
    #define SCC3_COMMAND_INT_EN_WRDONE_MASK 0x00800000
    #define SCC3_COMMAND_INT_EN_WRDONE_SHIFT 23
#define  SCC3_CONFIG0 0x1068
    #define SCC3_CONFIG0_ETU_VALUE_MASK 0x0000FFFF
    #define SCC3_CONFIG0_ETU_VALUE_SHIFT 0
    #define SCC3_CONFIG0_TPRH_MASK 0xFFFF0000
    #define SCC3_CONFIG0_TPRH_SHIFT 16
#define  SCC3_CONFIG1 0x106C
    #define SCC3_CONFIG1_RX_RETRYCNT_MASK 0x00000003
    #define SCC3_CONFIG1_RX_RETRYCNT_SHIFT 0
    #define SCC3_CONFIG1_TX_RETRYCNT_MASK 0x0000000C
    #define SCC3_CONFIG1_TX_RETRYCNT_SHIFT 2
    #define SCC3_CONFIG1_RX_RETRYEN_MASK 0x00000010
    #define SCC3_CONFIG1_RX_RETRYEN_SHIFT 4
    #define SCC3_CONFIG1_TX_RETRYEN_MASK 0x00000020
    #define SCC3_CONFIG1_TX_RETRYEN_SHIFT 5
    #define SCC3_CONFIG1_TS_MASK 0x00000040
    #define SCC3_CONFIG1_TS_SHIFT 6
    #define SCC3_CONFIG1_PARITY_EN_MASK 0x00000080
    #define SCC3_CONFIG1_PARITY_EN_SHIFT 7
    #define SCC3_CONFIG1_TGUARD_MASK 0x0000FF00
    #define SCC3_CONFIG1_TGUARD_SHIFT 8
#define  SCC3_DATA_LOAD 0x1070
    #define SCC3_DATA_LOAD_DATA_LOAD_MASK 0x000000FF
    #define SCC3_DATA_LOAD_DATA_LOAD_SHIFT 0
#define  SCC3_DATA_READ 0x1074
    #define SCC3_DATA_READ_DATA_READ_MASK 0x000000FF
    #define SCC3_DATA_READ_DATA_READ_SHIFT 0
#define  SCC3_STATUS 0x107C
    #define SCC3_STATUS_BYTEXFERED_MASK 0x0000007F
    #define SCC3_STATUS_BYTEXFERED_SHIFT 0
    #define SCC3_STATUS_CARD_PRESENT_MASK 0x00000100
    #define SCC3_STATUS_CARD_PRESENT_SHIFT 8
    #define SCC3_STATUS_ACTIVE_MASK 0x00000200
    #define SCC3_STATUS_ACTIVE_SHIFT 9
#define  SCC_CLOCK_CTRL 0x1080
    #define HIGH_DUR_MASK 0x000000FF
    #define HIGH_DUR_SHIFT 0
    #define LOW_DUR_MASK 0x00FF0000
    #define LOW_DUR_SHIFT 16
    #define STOP_MASK 0x80000000
    #define STOP_SHIFT 31
#define  SCL_BOT_CR_WR_ADR 0x73A8
    #define SCL_BOT_CR_WR_ADR_BASE_MASK 0x0FFFE000
    #define SCL_BOT_CR_WR_ADR_BASE_SHIFT 13
#define  SCL_BOT_C_WR_ADR 0x73A4
    #define SCL_BOT_C_WR_ADR_BASE_MASK 0x0FFFE000
    #define SCL_BOT_C_WR_ADR_BASE_SHIFT 13
#define  SCL_BOT_Y_WR_ADR 0x73A0
    #define SCL_BOT_Y_WR_ADR_BASE_MASK 0x0FFFE000
    #define SCL_BOT_Y_WR_ADR_BASE_SHIFT 13
#define  SCL_CR_RD_ADR 0x739C
    #define SCL_CR_RD_ADR_BASE_MASK 0x0FFFE000
    #define SCL_CR_RD_ADR_BASE_SHIFT 13
#define  SCL_CR_WR_ADR 0x7398
    #define SCL_CR_WR_ADR_BASE_MASK 0x0FFFE000
    #define SCL_CR_WR_ADR_BASE_SHIFT 13
#define  SCL_C_RD_ADR 0x7394
    #define SCL_C_RD_ADR_BASE_MASK 0x0FFFE000
    #define SCL_C_RD_ADR_BASE_SHIFT 13
#define  SCL_C_WR_ADR 0x738C
    #define SCL_C_WR_ADR_BASE_MASK 0x0FFFE000
    #define SCL_C_WR_ADR_BASE_SHIFT 13
#define  SCL_HORI_CTRL 0x736C
    #define SCL_HORI_CTRL_SCALE_EN_MASK 0x00000001
    #define SCL_HORI_CTRL_SCALE_EN_SHIFT 0
    #define SCL_HORI_CTRL_UCODE_VCNT_MASK 0x0000007E
    #define SCL_HORI_CTRL_UCODE_VCNT_SHIFT 1
    #define SCL_HORI_CTRL_INV_DIV_MASK 0xFFFF0000
    #define SCL_HORI_CTRL_INV_DIV_SHIFT 16
#define  SCL_HORI_UCODE 0x7204
    #define SCL_HORI_UCODE_HORI0_UCODE_MASK 0x000000FF
    #define SCL_HORI_UCODE_HORI0_UCODE_SHIFT 0
    #define SCL_HORI_UCODE_HORI1_UCODE_MASK 0x0000FF00
    #define SCL_HORI_UCODE_HORI1_UCODE_SHIFT 8
    #define SCL_HORI_UCODE_HORI2_UCODE_MASK 0x00FF0000
    #define SCL_HORI_UCODE_HORI2_UCODE_SHIFT 16
    #define SCL_HORI_UCODE_HORI3_UCODE_MASK 0xFF000000
    #define SCL_HORI_UCODE_HORI3_UCODE_SHIFT 24
#define  SCL_PICT_RD_SIZE 0x7360
    #define SCL_PICT_RD_SIZE_SLICE_RD_SIZE_MASK 0x0000007F
    #define SCL_PICT_RD_SIZE_SLICE_RD_SIZE_SHIFT 0
    #define SCL_PICT_RD_SIZE_SLICE_RD_CNT_MASK 0x00007F00
    #define SCL_PICT_RD_SIZE_SLICE_RD_CNT_SHIFT 8
#define  SCL_PICT_WR_SIZE 0x7364
    #define SCL_PICT_WR_SIZE_SLICE_WR_SIZE_MASK 0x0000007F
    #define SCL_PICT_WR_SIZE_SLICE_WR_SIZE_SHIFT 0
    #define SCL_PICT_WR_SIZE_SLICE_WR_CNT_MASK 0x00007F00
    #define SCL_PICT_WR_SIZE_SLICE_WR_CNT_SHIFT 8
#define  SCL_SURF_RD_SIZE 0x73DC
    #define SCL_RD_PITCH_MASK 0x00000FC0
    #define SCL_RD_PITCH_SHIFT 6
#define  SCL_SURF_WR_SIZE 0x7368
    #define SCL_WR_PITCH_MASK 0x00000FC0
    #define SCL_WR_PITCH_SHIFT 6
#define  SCL_TRIG 0x730C
    #define SCL_TRIG_COLBITS_OVERRIDE_MASK 0x00000001
    #define SCL_TRIG_COLBITS_OVERRIDE_SHIFT 0
    #define SCL_TRIG_COLBITS_RD_VALUE_MASK 0x000000F0
    #define SCL_TRIG_COLBITS_RD_VALUE_SHIFT 4
    #define SCL_TRIG_COLBITS_WR_VALUE_MASK 0x00000F00
    #define SCL_TRIG_COLBITS_WR_VALUE_SHIFT 8
    #define SCL_TRIG_FORCE_RD_ONLY_MASK 0x00010000
    #define SCL_TRIG_FORCE_RD_ONLY_SHIFT 16
    #define SCL_TRIG_FIELD_SCALE_MASK 0x00100000
    #define SCL_TRIG_FIELD_SCALE_SHIFT 20
    #define SCL_TRIG_RD_8X8_MASK 0x00800000
    #define SCL_TRIG_RD_8X8_SHIFT 23
    #define SCL_TRIG_RD_LINEAR_MASK 0x01000000
    #define SCL_TRIG_RD_LINEAR_SHIFT 24
    #define SCL_TRIG_WR_LINEAR_MASK 0x02000000
    #define SCL_TRIG_WR_LINEAR_SHIFT 25
    #define SCL_RD_EN_MASK 0x08000000
    #define SCL_RD_EN_SHIFT 27
    #define SCL_TRIG_SCL_EN_MASK 0x10000000
    #define SCL_TRIG_SCL_EN_SHIFT 28
    #define OUT_MODE_MASK 0x20000000
    #define OUT_MODE_SHIFT 29
    #define SCL_TRIG_SKIP_FLD_EN_MASK 0x40000000
    #define SCL_TRIG_SKIP_FLD_EN_SHIFT 30
    #define SCL_TRIG_FLD_SEL_MASK 0x80000000
    #define SCL_TRIG_FLD_SEL_SHIFT 31
#define  SCL_UCODE_IDX 0x7200
    #define SCL_UCODE_IDX_HORI_IDX_MASK 0x0000000F
    #define SCL_UCODE_IDX_HORI_IDX_SHIFT 0
    #define SCL_UCODE_IDX_VERT_IDX_MASK 0x000F0000
    #define SCL_UCODE_IDX_VERT_IDX_SHIFT 16
    #define SCL_UCODE_IDX_VERT_BOT_IDX_MASK 0x00F00000
    #define SCL_UCODE_IDX_VERT_BOT_IDX_SHIFT 20
#define  SCL_VAR_ADR 0x7214
    #define SCL_VAR_ADR_BASE_MASK 0x0FFFFFC0
    #define SCL_VAR_ADR_BASE_SHIFT 6
#define  SCL_VAR_CTRL 0x7210
    #define SCL_VAR_EN_MASK 0x00000001
    #define SCL_VAR_EN_SHIFT 0
    #define SCL_VAR_FLD_DIS_MASK 0x00000002
    #define SCL_VAR_FLD_DIS_SHIFT 1
#define  SCL_VERT_BOT_CTRL 0x73AC
    #define SCL_VERT_BOT_CTRL_SCALE_EN_MASK 0x00000001
    #define SCL_VERT_BOT_CTRL_SCALE_EN_SHIFT 0
    #define SCL_VERT_BOT_CTRL_UCODE_VCNT_MASK 0x0000007E
    #define SCL_VERT_BOT_CTRL_UCODE_VCNT_SHIFT 1
    #define SCL_VERT_BOT_CTRL_INV_DIV_MASK 0xFFFF0000
    #define SCL_VERT_BOT_CTRL_INV_DIV_SHIFT 16
#define  SCL_VERT_BOT_UCODE 0x720C
    #define SCL_VERT_BOT_UCODE_VERT0_BOT_UCODE_MASK 0x000000FF
    #define SCL_VERT_BOT_UCODE_VERT0_BOT_UCODE_SHIFT 0
    #define SCL_VERT_BOT_UCODE_VERT1_BOT_UCODE_MASK 0x0000FF00
    #define SCL_VERT_BOT_UCODE_VERT1_BOT_UCODE_SHIFT 8
    #define SCL_VERT_BOT_UCODE_VERT2_BOT_UCODE_MASK 0x00FF0000
    #define SCL_VERT_BOT_UCODE_VERT2_BOT_UCODE_SHIFT 16
    #define SCL_VERT_BOT_UCODE_VERT3_BOT_UCODE_MASK 0xFF000000
    #define SCL_VERT_BOT_UCODE_VERT3_BOT_UCODE_SHIFT 24
#define  SCL_VERT_CTRL 0x7370
    #define SCL_VERT_CTRL_SCALE_EN_MASK 0x00000001
    #define SCL_VERT_CTRL_SCALE_EN_SHIFT 0
    #define SCL_VERT_CTRL_UCODE_VCNT_MASK 0x0000007E
    #define SCL_VERT_CTRL_UCODE_VCNT_SHIFT 1
    #define SCL_VERT_CTRL_INV_DIV_MASK 0xFFFF0000
    #define SCL_VERT_CTRL_INV_DIV_SHIFT 16
#define  SCL_VERT_UCODE 0x7208
    #define SCL_VERT_UCODE_VERT0_UCODE_MASK 0x000000FF
    #define SCL_VERT_UCODE_VERT0_UCODE_SHIFT 0
    #define SCL_VERT_UCODE_VERT1_UCODE_MASK 0x0000FF00
    #define SCL_VERT_UCODE_VERT1_UCODE_SHIFT 8
    #define SCL_VERT_UCODE_VERT2_UCODE_MASK 0x00FF0000
    #define SCL_VERT_UCODE_VERT2_UCODE_SHIFT 16
    #define SCL_VERT_UCODE_VERT3_UCODE_MASK 0xFF000000
    #define SCL_VERT_UCODE_VERT3_UCODE_SHIFT 24
#define  SCL_Y_RD_ADR 0x7390
    #define SCL_Y_RD_ADR_BASE_MASK 0x0FFFE000
    #define SCL_Y_RD_ADR_BASE_SHIFT 13
#define  SCL_Y_WR_ADR 0x7388
    #define SCL_Y_WR_ADR_BASE_MASK 0x0FFFE000
    #define SCL_Y_WR_ADR_BASE_SHIFT 13
#define  SCS0_FIND_START_CODE 0xA100
    #define SCS0_FIND_START_CODE_DONE_MASK 0x00000001
    #define SCS0_FIND_START_CODE_DONE_SHIFT 0
    #define SCS0_FIND_START_CODE_ERROR_MASK 0x00000002
    #define SCS0_FIND_START_CODE_ERROR_SHIFT 1
#define  SCS1_FIND_START_CODE 0xA500
    #define SCS1_FIND_START_CODE_DONE_MASK 0x00000001
    #define SCS1_FIND_START_CODE_DONE_SHIFT 0
    #define SCS1_FIND_START_CODE_ERROR_MASK 0x00000002
    #define SCS1_FIND_START_CODE_ERROR_SHIFT 1
#define  SEQ_CH0_DUMMY_REG 0xC000
    #define SEQ_CH0_DUMMY_REG_REG_MASK 0xFFFFFFFF
    #define SEQ_CH0_DUMMY_REG_REG_SHIFT 0
#define  SEQ_CH0_ITM_CTRL 0xC02C
    #define SEQ_CH0_ITM_CTRL_MSDLL0_RSTN_MASK 0x00000001
    #define SEQ_CH0_ITM_CTRL_MSDLL0_RSTN_SHIFT 0
    #define SEQ_CH0_ITM_CTRL_MSDLL1_RSTN_MASK 0x00000002
    #define SEQ_CH0_ITM_CTRL_MSDLL1_RSTN_SHIFT 1
    #define SEQ_CH0_ITM_CTRL_MDLL_RSTN_MASK 0x00000004
    #define SEQ_CH0_ITM_CTRL_MDLL_RSTN_SHIFT 2
    #define SEQ_CH0_ITM_CTRL_DTP_OUT_MASK 0x00000030
    #define SEQ_CH0_ITM_CTRL_DTP_OUT_SHIFT 4
#define  SEQ_CH0_MISC_REG 0xC024
    #define SEQ_CH0_MISC_REG_CFG_RSTN_MASK 0x00000001
    #define SEQ_CH0_MISC_REG_CFG_RSTN_SHIFT 0
    #define SEQ_CH0_MISC_REG_MSDSEQ_RSTN_MASK 0x00000002
    #define SEQ_CH0_MISC_REG_MSDSEQ_RSTN_SHIFT 1
    #define SEQ_CH0_MISC_REG_M2XLOGIC_RSTN_MASK 0x00000004
    #define SEQ_CH0_MISC_REG_M2XLOGIC_RSTN_SHIFT 2
    #define SEQ_CH0_MISC_REG_MDLOGIC_RSTN_MASK 0x00000008
    #define SEQ_CH0_MISC_REG_MDLOGIC_RSTN_SHIFT 3
    #define SEQ_CH0_MISC_REG_REQFIFO_RSTN_MASK 0x00000010
    #define SEQ_CH0_MISC_REG_REQFIFO_RSTN_SHIFT 4
    #define SEQ_CH0_MISC_REG_TEST_MODE_MASK 0x00000300
    #define SEQ_CH0_MISC_REG_TEST_MODE_SHIFT 8
    #define SEQ_CH0_MISC_REG_DLL_BYPASS_MASK 0x00000400
    #define SEQ_CH0_MISC_REG_DLL_BYPASS_SHIFT 10
    #define SEQ_CH0_MISC_REG_INIT_BYPASS_MASK 0x00000800
    #define SEQ_CH0_MISC_REG_INIT_BYPASS_SHIFT 11
#define  SEQ_CH0_REG_CTRL 0xC020
    #define SEQ_CH0_REG_CTRL_CFGREG_ADDR_MASK 0x0000003F
    #define SEQ_CH0_REG_CTRL_CFGREG_ADDR_SHIFT 0
    #define SEQ_CH0_REG_CTRL_CFGREG_WOP_MASK 0x00000100
    #define SEQ_CH0_REG_CTRL_CFGREG_WOP_SHIFT 8
#define  SEQ_CH0_REG_RDAT 0xC018
    #define SEQ_CH0_REG_RDAT_CFGREG_RDAT_MASK 0xFFFFFFFF
    #define SEQ_CH0_REG_RDAT_CFGREG_RDAT_SHIFT 0
#define  SEQ_CH0_REG_STATUS 0xC01C
    #define SEQ_CH0_REG_STATUS_CFGREG_BUSY_MASK 0x00000001
    #define SEQ_CH0_REG_STATUS_CFGREG_BUSY_SHIFT 0
#define  SEQ_CH0_REG_WDAT 0xC014
    #define SEQ_CH0_REG_WDAT_CFGREG_WDAT_MASK 0xFFFFFFFF
    #define SEQ_CH0_REG_WDAT_CFGREG_WDAT_SHIFT 0
#define  SEQ_CH0_STATUS 0xC028
    #define SEQ_CH0_STATUS_INIT_BUSY_MASK 0x00000001
    #define SEQ_CH0_STATUS_INIT_BUSY_SHIFT 0
    #define SEQ_CH0_STATUS_SEQ_ERROR_MASK 0x00000010
    #define SEQ_CH0_STATUS_SEQ_ERROR_SHIFT 4
#define  SEQ_CH1_DUMMY_REG 0xC400
    #define SEQ_CH1_DUMMY_REG_REG_MASK 0xFFFFFFFF
    #define SEQ_CH1_DUMMY_REG_REG_SHIFT 0
#define  SEQ_CH1_ITM_CTRL 0xC42C
    #define SEQ_CH1_ITM_CTRL_MSDLL0_RSTN_MASK 0x00000001
    #define SEQ_CH1_ITM_CTRL_MSDLL0_RSTN_SHIFT 0
    #define SEQ_CH1_ITM_CTRL_MSDLL1_RSTN_MASK 0x00000002
    #define SEQ_CH1_ITM_CTRL_MSDLL1_RSTN_SHIFT 1
    #define SEQ_CH1_ITM_CTRL_MDLL_RSTN_MASK 0x00000004
    #define SEQ_CH1_ITM_CTRL_MDLL_RSTN_SHIFT 2
    #define SEQ_CH1_ITM_CTRL_DTP_OUT_MASK 0x00000030
    #define SEQ_CH1_ITM_CTRL_DTP_OUT_SHIFT 4
#define  SEQ_CH1_MISC_REG 0xC424
    #define SEQ_CH1_MISC_REG_CFG_RSTN_MASK 0x00000001
    #define SEQ_CH1_MISC_REG_CFG_RSTN_SHIFT 0
    #define SEQ_CH1_MISC_REG_MSDSEQ_RSTN_MASK 0x00000002
    #define SEQ_CH1_MISC_REG_MSDSEQ_RSTN_SHIFT 1
    #define SEQ_CH1_MISC_REG_M2XLOGIC_RSTN_MASK 0x00000004
    #define SEQ_CH1_MISC_REG_M2XLOGIC_RSTN_SHIFT 2
    #define SEQ_CH1_MISC_REG_MDLOGIC_RSTN_MASK 0x00000008
    #define SEQ_CH1_MISC_REG_MDLOGIC_RSTN_SHIFT 3
    #define SEQ_CH1_MISC_REG_REQFIFO_RSTN_MASK 0x00000010
    #define SEQ_CH1_MISC_REG_REQFIFO_RSTN_SHIFT 4
    #define SEQ_CH1_MISC_REG_TEST_MODE_MASK 0x00000300
    #define SEQ_CH1_MISC_REG_TEST_MODE_SHIFT 8
    #define SEQ_CH1_MISC_REG_DLL_BYPASS_MASK 0x00000400
    #define SEQ_CH1_MISC_REG_DLL_BYPASS_SHIFT 10
    #define SEQ_CH1_MISC_REG_INIT_BYPASS_MASK 0x00000800
    #define SEQ_CH1_MISC_REG_INIT_BYPASS_SHIFT 11
#define  SEQ_CH1_REG_CTRL 0xC420
    #define SEQ_CH1_REG_CTRL_CFGREG_ADDR_MASK 0x0000003F
    #define SEQ_CH1_REG_CTRL_CFGREG_ADDR_SHIFT 0
    #define SEQ_CH1_REG_CTRL_CFGREG_WOP_MASK 0x00000100
    #define SEQ_CH1_REG_CTRL_CFGREG_WOP_SHIFT 8
#define  SEQ_CH1_REG_RDAT 0xC418
    #define SEQ_CH1_REG_RDAT_CFGREG_RDAT_MASK 0xFFFFFFFF
    #define SEQ_CH1_REG_RDAT_CFGREG_RDAT_SHIFT 0
#define  SEQ_CH1_REG_STATUS 0xC41C
    #define SEQ_CH1_REG_STATUS_CFGREG_BUSY_MASK 0x00000001
    #define SEQ_CH1_REG_STATUS_CFGREG_BUSY_SHIFT 0
#define  SEQ_CH1_REG_WDAT 0xC414
    #define SEQ_CH1_REG_WDAT_CFGREG_WDAT_MASK 0xFFFFFFFF
    #define SEQ_CH1_REG_WDAT_CFGREG_WDAT_SHIFT 0
#define  SEQ_CH1_STATUS 0xC428
    #define SEQ_CH1_STATUS_INIT_BUSY_MASK 0x00000001
    #define SEQ_CH1_STATUS_INIT_BUSY_SHIFT 0
    #define SEQ_CH1_STATUS_SEQ_ERROR_MASK 0x00000010
    #define SEQ_CH1_STATUS_SEQ_ERROR_SHIFT 4
#define  SEQ_CH2_DUMMY_REG 0xC800
    #define SEQ_CH2_DUMMY_REG_REG_MASK 0xFFFFFFFF
    #define SEQ_CH2_DUMMY_REG_REG_SHIFT 0
#define  SEQ_CH2_ITM_CTRL 0xC82C
    #define SEQ_CH2_ITM_CTRL_MSDLL0_RSTN_MASK 0x00000001
    #define SEQ_CH2_ITM_CTRL_MSDLL0_RSTN_SHIFT 0
    #define SEQ_CH2_ITM_CTRL_MSDLL1_RSTN_MASK 0x00000002
    #define SEQ_CH2_ITM_CTRL_MSDLL1_RSTN_SHIFT 1
    #define SEQ_CH2_ITM_CTRL_MDLL_RSTN_MASK 0x00000004
    #define SEQ_CH2_ITM_CTRL_MDLL_RSTN_SHIFT 2
    #define SEQ_CH2_ITM_CTRL_DTP_OUT_MASK 0x00000030
    #define SEQ_CH2_ITM_CTRL_DTP_OUT_SHIFT 4
#define  SEQ_CH2_MISC_REG 0xC824
    #define SEQ_CH2_MISC_REG_CFG_RSTN_MASK 0x00000001
    #define SEQ_CH2_MISC_REG_CFG_RSTN_SHIFT 0
    #define SEQ_CH2_MISC_REG_MSDSEQ_RSTN_MASK 0x00000002
    #define SEQ_CH2_MISC_REG_MSDSEQ_RSTN_SHIFT 1
    #define SEQ_CH2_MISC_REG_M2XLOGIC_RSTN_MASK 0x00000004
    #define SEQ_CH2_MISC_REG_M2XLOGIC_RSTN_SHIFT 2
    #define SEQ_CH2_MISC_REG_MDLOGIC_RSTN_MASK 0x00000008
    #define SEQ_CH2_MISC_REG_MDLOGIC_RSTN_SHIFT 3
    #define SEQ_CH2_MISC_REG_REQFIFO_RSTN_MASK 0x00000010
    #define SEQ_CH2_MISC_REG_REQFIFO_RSTN_SHIFT 4
    #define SEQ_CH2_MISC_REG_TEST_MODE_MASK 0x00000300
    #define SEQ_CH2_MISC_REG_TEST_MODE_SHIFT 8
    #define SEQ_CH2_MISC_REG_DLL_BYPASS_MASK 0x00000400
    #define SEQ_CH2_MISC_REG_DLL_BYPASS_SHIFT 10
    #define SEQ_CH2_MISC_REG_INIT_BYPASS_MASK 0x00000800
    #define SEQ_CH2_MISC_REG_INIT_BYPASS_SHIFT 11
#define  SEQ_CH2_REG_CTRL 0xC820
    #define SEQ_CH2_REG_CTRL_CFGREG_ADDR_MASK 0x0000003F
    #define SEQ_CH2_REG_CTRL_CFGREG_ADDR_SHIFT 0
    #define SEQ_CH2_REG_CTRL_CFGREG_WOP_MASK 0x00000100
    #define SEQ_CH2_REG_CTRL_CFGREG_WOP_SHIFT 8
#define  SEQ_CH2_REG_RDAT 0xC818
    #define SEQ_CH2_REG_RDAT_CFGREG_RDAT_MASK 0xFFFFFFFF
    #define SEQ_CH2_REG_RDAT_CFGREG_RDAT_SHIFT 0
#define  SEQ_CH2_REG_STATUS 0xC81C
    #define SEQ_CH2_REG_STATUS_CFGREG_BUSY_MASK 0x00000001
    #define SEQ_CH2_REG_STATUS_CFGREG_BUSY_SHIFT 0
#define  SEQ_CH2_REG_WDAT 0xC814
    #define SEQ_CH2_REG_WDAT_CFGREG_WDAT_MASK 0xFFFFFFFF
    #define SEQ_CH2_REG_WDAT_CFGREG_WDAT_SHIFT 0
#define  SEQ_CH2_STATUS 0xC828
    #define SEQ_CH2_STATUS_INIT_BUSY_MASK 0x00000001
    #define SEQ_CH2_STATUS_INIT_BUSY_SHIFT 0
    #define SEQ_CH2_STATUS_SEQ_ERROR_MASK 0x00000010
    #define SEQ_CH2_STATUS_SEQ_ERROR_SHIFT 4
#define  SF_BUF_CTRL 0x65E0
    #define SF_OUTBUF_ENDIAN_MASK 0x00000800
    #define SF_OUTBUF_ENDIAN_SHIFT 11
    #define SF_MEM_URGENT_MASK 0x00010000
    #define SF_MEM_URGENT_SHIFT 16
    #define SF_MEM_URGENT_WATERMARK_MASK 0x03F00000
    #define SF_MEM_URGENT_WATERMARK_SHIFT 20
#define  SF_RING0_HEAD 0x6420
    #define SF_RING0_HEAD_HEAD_PTR_MASK 0x0FFFFFFF
    #define SF_RING0_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING10_HEAD 0x64A8
    #define SF_RING10_HEAD_HEAD_PTR_MASK 0x0FFFFFFF
    #define SF_RING10_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING11_HEAD 0x64B8
    #define SF_RING11_HEAD_HEAD_PTR_MASK 0x0FFFFFFF
    #define SF_RING11_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING12_HEAD 0x64C8
    #define SF_RING12_HEAD_HEAD_PTR_MASK 0x0FFFFFFF
    #define SF_RING12_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING13_HEAD 0x64D8
    #define SF_RING13_HEAD_HEAD_PTR_MASK 0x0FFFFFFF
    #define SF_RING13_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING14_HEAD 0x64E8
    #define SF_RING14_HEAD_HEAD_PTR_MASK 0x0FFFFFFF
    #define SF_RING14_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING15_HEAD 0x64F8
    #define SF_RING15_HEAD_HEAD_PTR_MASK 0x0FFFFFFF
    #define SF_RING15_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING1_HEAD 0x6424
    #define SF_RING1_HEAD_HEAD_PTR_MASK 0x0FFFFFFF
    #define SF_RING1_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING2_HEAD 0x6428
    #define SF_RING2_HEAD_HEAD_PTR_MASK 0x0FFFFFFF
    #define SF_RING2_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING3_HEAD 0x642C
    #define SF_RING3_HEAD_HEAD_PTR_MASK 0x0FFFFFFF
    #define SF_RING3_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING4_HEAD 0x6448
    #define SF_RING4_HEAD_HEAD_PTR_MASK 0x0FFFFFFF
    #define SF_RING4_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING5_HEAD 0x6458
    #define SF_RING5_HEAD_HEAD_PTR_MASK 0x0FFFFFFF
    #define SF_RING5_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING6_HEAD 0x6468
    #define SF_RING6_HEAD_HEAD_PTR_MASK 0x0FFFFFFF
    #define SF_RING6_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING7_HEAD 0x6478
    #define SF_RING7_HEAD_HEAD_PTR_MASK 0x0FFFFFFF
    #define SF_RING7_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING8_HEAD 0x6488
    #define SF_RING8_HEAD_HEAD_PTR_MASK 0x0FFFFFFF
    #define SF_RING8_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING9_HEAD 0x6498
    #define SF_RING9_HEAD_HEAD_PTR_MASK 0x0FFFFFFF
    #define SF_RING9_HEAD_HEAD_PTR_SHIFT 0
#define  SF_RING_BASE_TOP_TAIL_ADR 0x6400
    #define SF_RING_BASE_TOP_TAIL_ADR_SF_RING_MASK 0x0000001F
    #define SF_RING_BASE_TOP_TAIL_ADR_SF_RING_SHIFT 0
    #define SF_BASE_TOP_MASK 0x00010000
    #define SF_BASE_TOP_SHIFT 16
#define  SF_RING_BASE_TOP_TAIL_DATA 0x6404
    #define SF_RING_BASE_TOP_TAIL_DATA_MASK 0xFFFFFFFF
    #define SF_RING_BASE_TOP_TAIL_DATA_SHIFT 0
#define  SF_RING_CTRL_0_1 0x6580
    #define RING_0_WHOLE_PACKET_MASK 0x00000002
    #define RING_0_WHOLE_PACKET_SHIFT 1
    #define RING_0_TEI_FILTER_MASK 0x00000004
    #define RING_0_TEI_FILTER_SHIFT 2
    #define RING_0_INT_CTRL_MASK 0x000000F0
    #define RING_0_INT_CTRL_SHIFT 4
    #define RING_0_PES2ES_MASK 0x00000100
    #define RING_0_PES2ES_SHIFT 8
    #define RING_0_CC_FILTER_MASK 0x00000200
    #define RING_0_CC_FILTER_SHIFT 9
    #define RING_1_WHOLE_PACKET_MASK 0x00020000
    #define RING_1_WHOLE_PACKET_SHIFT 17
    #define RING_1_TEI_FILTER_MASK 0x00040000
    #define RING_1_TEI_FILTER_SHIFT 18
    #define RING_1_INT_CTRL_MASK 0x00F00000
    #define RING_1_INT_CTRL_SHIFT 20
    #define RING_1_PES2ES_MASK 0x01000000
    #define RING_1_PES2ES_SHIFT 24
    #define RING_1_CC_FILTER_MASK 0x02000000
    #define RING_1_CC_FILTER_SHIFT 25
#define  SF_RING_CTRL_10_11 0x6594
    #define RING_10_WHOLE_PACKET_MASK 0x00000002
    #define RING_10_WHOLE_PACKET_SHIFT 1
    #define RING_10_TEI_FILTER_MASK 0x00000004
    #define RING_10_TEI_FILTER_SHIFT 2
    #define RING_10_INT_CTRL_MASK 0x000000F0
    #define RING_10_INT_CTRL_SHIFT 4
    #define RING_10_PES2ES_MASK 0x00000100
    #define RING_10_PES2ES_SHIFT 8
    #define RING_10_CC_FILTER_MASK 0x00000200
    #define RING_10_CC_FILTER_SHIFT 9
    #define RING_11_WHOLE_PACKET_MASK 0x00020000
    #define RING_11_WHOLE_PACKET_SHIFT 17
    #define RING_11_TEI_FILTER_MASK 0x00040000
    #define RING_11_TEI_FILTER_SHIFT 18
    #define RING_11_INT_CTRL_MASK 0x00F00000
    #define RING_11_INT_CTRL_SHIFT 20
    #define RING_11_PES2ES_MASK 0x01000000
    #define RING_11_PES2ES_SHIFT 24
    #define RING_11_CC_FILTER_MASK 0x02000000
    #define RING_11_CC_FILTER_SHIFT 25
#define  SF_RING_CTRL_12_13 0x6598
    #define RING_12_WHOLE_PACKET_MASK 0x00000002
    #define RING_12_WHOLE_PACKET_SHIFT 1
    #define RING_12_TEI_FILTER_MASK 0x00000004
    #define RING_12_TEI_FILTER_SHIFT 2
    #define RING_12_INT_CTRL_MASK 0x000000F0
    #define RING_12_INT_CTRL_SHIFT 4
    #define RING_12_PES2ES_MASK 0x00000100
    #define RING_12_PES2ES_SHIFT 8
    #define RING_12_CC_FILTER_MASK 0x00000200
    #define RING_12_CC_FILTER_SHIFT 9
    #define RING_13_WHOLE_PACKET_MASK 0x00020000
    #define RING_13_WHOLE_PACKET_SHIFT 17
    #define RING_13_TEI_FILTER_MASK 0x00040000
    #define RING_13_TEI_FILTER_SHIFT 18
    #define RING_13_INT_CTRL_MASK 0x00F00000
    #define RING_13_INT_CTRL_SHIFT 20
    #define RING_13_PES2ES_MASK 0x01000000
    #define RING_13_PES2ES_SHIFT 24
    #define RING_13_CC_FILTER_MASK 0x02000000
    #define RING_13_CC_FILTER_SHIFT 25
#define  SF_RING_CTRL_14_15 0x659C
    #define RING_14_WHOLE_PACKET_MASK 0x00000002
    #define RING_14_WHOLE_PACKET_SHIFT 1
    #define RING_14_TEI_FILTER_MASK 0x00000004
    #define RING_14_TEI_FILTER_SHIFT 2
    #define RING_14_INT_CTRL_MASK 0x000000F0
    #define RING_14_INT_CTRL_SHIFT 4
    #define RING_14_PES2ES_MASK 0x00000100
    #define RING_14_PES2ES_SHIFT 8
    #define RING_14_CC_FILTER_MASK 0x00000200
    #define RING_14_CC_FILTER_SHIFT 9
    #define RING_15_WHOLE_PACKET_MASK 0x00020000
    #define RING_15_WHOLE_PACKET_SHIFT 17
    #define RING_15_TEI_FILTER_MASK 0x00040000
    #define RING_15_TEI_FILTER_SHIFT 18
    #define RING_15_INT_CTRL_MASK 0x00F00000
    #define RING_15_INT_CTRL_SHIFT 20
    #define RING_15_PES2ES_MASK 0x01000000
    #define RING_15_PES2ES_SHIFT 24
    #define RING_15_CC_FILTER_MASK 0x02000000
    #define RING_15_CC_FILTER_SHIFT 25
#define  SF_RING_CTRL_2_3 0x6584
    #define RING_2_WHOLE_PACKET_MASK 0x00000002
    #define RING_2_WHOLE_PACKET_SHIFT 1
    #define RING_2_TEI_FILTER_MASK 0x00000004
    #define RING_2_TEI_FILTER_SHIFT 2
    #define RING_2_INT_CTRL_MASK 0x000000F0
    #define RING_2_INT_CTRL_SHIFT 4
    #define RING_2_PES2ES_MASK 0x00000100
    #define RING_2_PES2ES_SHIFT 8
    #define RING_2_CC_FILTER_MASK 0x00000200
    #define RING_2_CC_FILTER_SHIFT 9
    #define RING_3_WHOLE_PACKET_MASK 0x00020000
    #define RING_3_WHOLE_PACKET_SHIFT 17
    #define RING_3_TEI_FILTER_MASK 0x00040000
    #define RING_3_TEI_FILTER_SHIFT 18
    #define RING_3_INT_CTRL_MASK 0x00F00000
    #define RING_3_INT_CTRL_SHIFT 20
    #define RING_3_PES2ES_MASK 0x01000000
    #define RING_3_PES2ES_SHIFT 24
    #define RING_3_CC_FILTER_MASK 0x02000000
    #define RING_3_CC_FILTER_SHIFT 25
#define  SF_RING_CTRL_4_5 0x6588
    #define RING_4_WHOLE_PACKET_MASK 0x00000002
    #define RING_4_WHOLE_PACKET_SHIFT 1
    #define RING_4_TEI_FILTER_MASK 0x00000004
    #define RING_4_TEI_FILTER_SHIFT 2
    #define RING_4_INT_CTRL_MASK 0x000000F0
    #define RING_4_INT_CTRL_SHIFT 4
    #define RING_4_PES2ES_MASK 0x00000100
    #define RING_4_PES2ES_SHIFT 8
    #define RING_4_CC_FILTER_MASK 0x00000200
    #define RING_4_CC_FILTER_SHIFT 9
    #define RING_5_WHOLE_PACKET_MASK 0x00020000
    #define RING_5_WHOLE_PACKET_SHIFT 17
    #define RING_5_TEI_FILTER_MASK 0x00040000
    #define RING_5_TEI_FILTER_SHIFT 18
    #define RING_5_INT_CTRL_MASK 0x00F00000
    #define RING_5_INT_CTRL_SHIFT 20
    #define RING_5_PES2ES_MASK 0x01000000
    #define RING_5_PES2ES_SHIFT 24
    #define RING_5_CC_FILTER_MASK 0x02000000
    #define RING_5_CC_FILTER_SHIFT 25
#define  SF_RING_CTRL_6_7 0x658C
    #define RING_6_WHOLE_PACKET_MASK 0x00000002
    #define RING_6_WHOLE_PACKET_SHIFT 1
    #define RING_6_TEI_FILTER_MASK 0x00000004
    #define RING_6_TEI_FILTER_SHIFT 2
    #define RING_6_INT_CTRL_MASK 0x000000F0
    #define RING_6_INT_CTRL_SHIFT 4
    #define RING_6_PES2ES_MASK 0x00000100
    #define RING_6_PES2ES_SHIFT 8
    #define RING_6_CC_FILTER_MASK 0x00000200
    #define RING_6_CC_FILTER_SHIFT 9
    #define RING_7_WHOLE_PACKET_MASK 0x00020000
    #define RING_7_WHOLE_PACKET_SHIFT 17
    #define RING_7_TEI_FILTER_MASK 0x00040000
    #define RING_7_TEI_FILTER_SHIFT 18
    #define RING_7_INT_CTRL_MASK 0x00F00000
    #define RING_7_INT_CTRL_SHIFT 20
    #define RING_7_PES2ES_MASK 0x01000000
    #define RING_7_PES2ES_SHIFT 24
    #define RING_7_CC_FILTER_MASK 0x02000000
    #define RING_7_CC_FILTER_SHIFT 25
#define  SF_RING_CTRL_8_9 0x6590
    #define RING_8_WHOLE_PACKET_MASK 0x00000002
    #define RING_8_WHOLE_PACKET_SHIFT 1
    #define RING_8_TEI_FILTER_MASK 0x00000004
    #define RING_8_TEI_FILTER_SHIFT 2
    #define RING_8_INT_CTRL_MASK 0x000000F0
    #define RING_8_INT_CTRL_SHIFT 4
    #define RING_8_PES2ES_MASK 0x00000100
    #define RING_8_PES2ES_SHIFT 8
    #define RING_8_CC_FILTER_MASK 0x00000200
    #define RING_8_CC_FILTER_SHIFT 9
    #define RING_9_WHOLE_PACKET_MASK 0x00020000
    #define RING_9_WHOLE_PACKET_SHIFT 17
    #define RING_9_TEI_FILTER_MASK 0x00040000
    #define RING_9_TEI_FILTER_SHIFT 18
    #define RING_9_INT_CTRL_MASK 0x00F00000
    #define RING_9_INT_CTRL_SHIFT 20
    #define RING_9_PES2ES_MASK 0x01000000
    #define RING_9_PES2ES_SHIFT 24
    #define RING_9_CC_FILTER_MASK 0x02000000
    #define RING_9_CC_FILTER_SHIFT 25
#define  SF_RING_ES_START_PTR_ADR 0x6700
    #define SF_RING_ES_START_PTR_ADR_SF_RING_MASK 0x0000001F
    #define SF_RING_ES_START_PTR_ADR_SF_RING_SHIFT 0
#define  SF_RING_ES_START_PTR_DATA 0x6704
    #define SF_RING_ES_START_PTR_MASK 0x0FFFFFFF
    #define SF_RING_ES_START_PTR_SHIFT 0
    #define SF_RING_ES_START_PTR_RD_VALID_MASK 0x80000000
    #define SF_RING_ES_START_PTR_RD_VALID_SHIFT 31
#define  SF_RING_PTS_DTS_ADR 0x6600
    #define SF_RING_PTS_DTS_ADR_SF_RING_MASK 0x0000001F
    #define SF_RING_PTS_DTS_ADR_SF_RING_SHIFT 0
    #define SF_DTS_MASK 0x00010000
    #define SF_DTS_SHIFT 16
#define  SF_RING_PTS_DTS_DATA_L 0x6604
    #define SF_RING_PTS_DTS_DATA_L_MASK 0xFFFFFFFF
    #define SF_RING_PTS_DTS_DATA_L_SHIFT 0
#define  SF_RING_PTS_DTS_DATA_U 0x6608
    #define SF_RING_PTS_DTS_DATA_U_MASK 0x00000001
    #define SF_RING_PTS_DTS_DATA_U_SHIFT 0
    #define SF_RING_PTS_DTS_VALID_MASK 0x00010000
    #define SF_RING_PTS_DTS_VALID_SHIFT 16
    #define SF_RING_PTS_DTS_RD_VALID_MASK 0x80000000
    #define SF_RING_PTS_DTS_RD_VALID_SHIFT 31
#define  SF_STATUS_ADR 0x65E8
    #define SF_STATUS_ADR_MASK 0x0000001F
    #define SF_STATUS_ADR_SHIFT 0
#define  SF_STATUS_DATA 0x65EC
    #define TEI_SEEN_MASK 0x00010000
    #define TEI_SEEN_SHIFT 16
    #define CC_ERR_SEEN_MASK 0x00020000
    #define CC_ERR_SEEN_SHIFT 17
    #define OVERFLOW_MASK 0x00040000
    #define OVERFLOW_SHIFT 18
    #define PTS_SEEN_MASK 0x00080000
    #define PTS_SEEN_SHIFT 19
    #define DTS_SEEN_MASK 0x00100000
    #define DTS_SEEN_SHIFT 20
    #define DATA_VALID_MASK 0x80000000
    #define DATA_VALID_SHIFT 31
#define  SLD0_CTRL 0xA128
    #define SLD0_CTRL_PICT_STRUCT_MASK 0x00000003
    #define SLD0_CTRL_PICT_STRUCT_SHIFT 0
    #define SLD0_CTRL_PICT_TYPE_MASK 0x0000000C
    #define SLD0_CTRL_PICT_TYPE_SHIFT 2
    #define SLD0_CTRL_DEC_MPEG_FRMT_MASK 0x00000030
    #define SLD0_CTRL_DEC_MPEG_FRMT_SHIFT 4
    #define SLD0_CTRL_ENC_MPEG_FRMT_MASK 0x000000C0
    #define SLD0_CTRL_ENC_MPEG_FRMT_SHIFT 6
    #define SLD0_CTRL_QSCALE_TYPE_MASK 0x00000100
    #define SLD0_CTRL_QSCALE_TYPE_SHIFT 8
    #define SLD0_CTRL_FRM_PRED_DCT_MASK 0x00000200
    #define SLD0_CTRL_FRM_PRED_DCT_SHIFT 9
    #define SLD0_CTRL_CV_MASK 0x00000400
    #define SLD0_CTRL_CV_SHIFT 10
    #define SLD0_CTRL_MB_TOTAL_MASK 0x3FFF0000
    #define SLD0_CTRL_MB_TOTAL_SHIFT 16
#define  SLD0_HOST_INT_MASK 0xA10C
    #define SLD0_HOST_INT_MASK_DONE_HOST_INT_MASK 0x00000001
    #define SLD0_HOST_INT_MASK_DONE_HOST_INT_SHIFT 0
    #define SLD0_HOST_INT_MASK_ERROR_HOST_INT_MASK 0x00000002
    #define SLD0_HOST_INT_MASK_ERROR_HOST_INT_SHIFT 1
#define  SLD0_IBB_BIT_OFFSET 0xA138
    #define SLD0_IBB_BIT_OFFSET_OFFSET_MASK 0x0000001F
    #define SLD0_IBB_BIT_OFFSET_OFFSET_SHIFT 0
#define  SLD0_IBB_TAIL_ADR 0xA134
    #define SLD0_IBB_TAIL_ADR_BASE_MASK 0x07FFFFFC
    #define SLD0_IBB_TAIL_ADR_BASE_SHIFT 2
#define  SLD0_INFO 0xA17C
    #define SLD0_INFO_MB_ADR_MASK 0x00003FFF
    #define SLD0_INFO_MB_ADR_SHIFT 0
    #define SLD0_INFO_QSCALE_MASK 0x007F0000
    #define SLD0_INFO_QSCALE_SHIFT 16
#define  SLD0_INT_CTRL 0xA104
    #define SLD0_INT_CTRL_DONE_EN_MASK 0x00000001
    #define SLD0_INT_CTRL_DONE_EN_SHIFT 0
    #define SLD0_INT_CTRL_ERROR_EN_MASK 0x00000002
    #define SLD0_INT_CTRL_ERROR_EN_SHIFT 1
#define  SLD0_INT_STATUS 0xA108
    #define SLD0_INT_STATUS_DONE_INT_MASK 0x00000001
    #define SLD0_INT_STATUS_DONE_INT_SHIFT 0
    #define SLD0_INT_STATUS_ERROR_INT_MASK 0x00000002
    #define SLD0_INT_STATUS_ERROR_INT_SHIFT 1
#define  SLD0_MVA_STATUS 0xA180
    #define SLD0_MVA_STATUS_DATA_MASK 0xFFFFFFFF
    #define SLD0_MVA_STATUS_DATA_SHIFT 0
#define  SLD0_PROC_INT_MASK 0xA110
    #define SLD0_PROC_INT_MASK_DONE_PROC_INT_MASK_MASK 0x00000001
    #define SLD0_PROC_INT_MASK_DONE_PROC_INT_MASK_SHIFT 0
    #define SLD0_PROC_INT_MASK_ERROR_PROC_INT_MASK_MASK 0x00000002
    #define SLD0_PROC_INT_MASK_ERROR_PROC_INT_MASK_SHIFT 1
#define  SLD0_STATUS 0xA130
    #define SLD0_STATUS_DONE_MASK 0x00000001
    #define SLD0_STATUS_DONE_SHIFT 0
    #define SLD0_STATUS_DIP_END_MASK 0x07FFFFFC
    #define SLD0_STATUS_DIP_END_SHIFT 2
    #define SLD0_STATUS_ERROR_MASK 0xF0000000
    #define SLD0_STATUS_ERROR_SHIFT 28
#define  SLD0_TRIG 0xA12C
    #define SLD0_TRIG_START_CODE_MASK 0x000000FF
    #define SLD0_TRIG_START_CODE_SHIFT 0
    #define SLD0_TRIG_DEC_MB_CNT_MASK 0x3FFF0000
    #define SLD0_TRIG_DEC_MB_CNT_SHIFT 16
#define  SLD1_CTRL 0xA528
    #define SLD1_CTRL_PICT_STRUCT_MASK 0x00000003
    #define SLD1_CTRL_PICT_STRUCT_SHIFT 0
    #define SLD1_CTRL_PICT_TYPE_MASK 0x0000000C
    #define SLD1_CTRL_PICT_TYPE_SHIFT 2
    #define SLD1_CTRL_DEC_MPEG_FRMT_MASK 0x00000030
    #define SLD1_CTRL_DEC_MPEG_FRMT_SHIFT 4
    #define SLD1_CTRL_ENC_MPEG_FRMT_MASK 0x000000C0
    #define SLD1_CTRL_ENC_MPEG_FRMT_SHIFT 6
    #define SLD1_CTRL_QSCALE_TYPE_MASK 0x00000100
    #define SLD1_CTRL_QSCALE_TYPE_SHIFT 8
    #define SLD1_CTRL_FRM_PRED_DCT_MASK 0x00000200
    #define SLD1_CTRL_FRM_PRED_DCT_SHIFT 9
    #define SLD1_CTRL_CV_MASK 0x00000400
    #define SLD1_CTRL_CV_SHIFT 10
    #define SLD1_CTRL_MB_TOTAL_MASK 0x3FFF0000
    #define SLD1_CTRL_MB_TOTAL_SHIFT 16
#define  SLD1_HOST_INT_MASK 0xA50C
    #define SLD1_HOST_INT_MASK_DONE_HOST_INT_MASK 0x00000001
    #define SLD1_HOST_INT_MASK_DONE_HOST_INT_SHIFT 0
    #define SLD1_HOST_INT_MASK_ERROR_HOST_INT_MASK 0x00000002
    #define SLD1_HOST_INT_MASK_ERROR_HOST_INT_SHIFT 1
#define  SLD1_IBB_BIT_OFFSET 0xA538
    #define SLD1_IBB_BIT_OFFSET_OFFSET_MASK 0x0000001F
    #define SLD1_IBB_BIT_OFFSET_OFFSET_SHIFT 0
#define  SLD1_IBB_TAIL_ADR 0xA534
    #define SLD1_IBB_TAIL_ADR_BASE_MASK 0x07FFFFFC
    #define SLD1_IBB_TAIL_ADR_BASE_SHIFT 2
#define  SLD1_INFO 0xA57C
    #define SLD1_INFO_MB_ADR_MASK 0x00003FFF
    #define SLD1_INFO_MB_ADR_SHIFT 0
    #define SLD1_INFO_QSCALE_MASK 0x007F0000
    #define SLD1_INFO_QSCALE_SHIFT 16
#define  SLD1_INT_CTRL 0xA504
    #define SLD1_INT_CTRL_DONE_EN_MASK 0x00000001
    #define SLD1_INT_CTRL_DONE_EN_SHIFT 0
    #define SLD1_INT_CTRL_ERROR_EN_MASK 0x00000002
    #define SLD1_INT_CTRL_ERROR_EN_SHIFT 1
#define  SLD1_INT_STATUS 0xA508
    #define SLD1_INT_STATUS_DONE_INT_MASK 0x00000001
    #define SLD1_INT_STATUS_DONE_INT_SHIFT 0
    #define SLD1_INT_STATUS_ERROR_INT_MASK 0x00000002
    #define SLD1_INT_STATUS_ERROR_INT_SHIFT 1
#define  SLD1_MVA_STATUS 0xA580
    #define SLD1_MVA_STATUS_DATA_MASK 0xFFFFFFFF
    #define SLD1_MVA_STATUS_DATA_SHIFT 0
#define  SLD1_PROC_INT_MASK 0xA510
    #define SLD1_PROC_INT_MASK_DONE_PROC_INT_MASK_MASK 0x00000001
    #define SLD1_PROC_INT_MASK_DONE_PROC_INT_MASK_SHIFT 0
    #define SLD1_PROC_INT_MASK_ERROR_PROC_INT_MASK_MASK 0x00000002
    #define SLD1_PROC_INT_MASK_ERROR_PROC_INT_MASK_SHIFT 1
#define  SLD1_STATUS 0xA530
    #define SLD1_STATUS_DONE_MASK 0x00000001
    #define SLD1_STATUS_DONE_SHIFT 0
    #define SLD1_STATUS_DIP_END_MASK 0x07FFFFFC
    #define SLD1_STATUS_DIP_END_SHIFT 2
    #define SLD1_STATUS_ERROR_MASK 0xF0000000
    #define SLD1_STATUS_ERROR_SHIFT 28
#define  SLD1_TRIG 0xA52C
    #define SLD1_TRIG_START_CODE_MASK 0x000000FF
    #define SLD1_TRIG_START_CODE_SHIFT 0
    #define SLD1_TRIG_DEC_MB_CNT_MASK 0x3FFF0000
    #define SLD1_TRIG_DEC_MB_CNT_SHIFT 16
#define  SPDIF_CODE_RD_ADDR 0x1624
    #define SPDIF_CODE_RD_ADDR_CURR_RD_ADDR_MASK 0x0FFFFFF8
    #define SPDIF_CODE_RD_ADDR_CURR_RD_ADDR_SHIFT 3
#define  SPDIF_DATA_RD_ADDR 0x1614
    #define SPDIF_DATA_RD_ADDR_CURR_RD_ADDR_MASK 0x0FFFFFF8
    #define SPDIF_DATA_RD_ADDR_CURR_RD_ADDR_SHIFT 3
#define  SPDIF_DATA_WR_ADDR 0x1714
    #define SPDIF_DATA_WR_ADDR_CURR_WR_ADDR_MASK 0x0FFFFFF8
    #define SPDIF_DATA_WR_ADDR_CURR_WR_ADDR_SHIFT 3
#define  SPDIF_RDES0 0x1718
    #define SPDIF_RDES0_NUM_FRAME_MASK 0x000000FF
    #define SPDIF_RDES0_NUM_FRAME_SHIFT 0
    #define SPDIF_RDES0_IOC_MASK 0x00008000
    #define SPDIF_RDES0_IOC_SHIFT 15
    #define SPDIF_RDES0_RDWRN_MASK 0x80000000
    #define SPDIF_RDES0_RDWRN_SHIFT 31
#define  SPDIF_RDES1 0x171C
    #define SPDIF_RDES1_DATA_BUF_ADDR_MASK 0x0FFFFFF8
    #define SPDIF_RDES1_DATA_BUF_ADDR_SHIFT 3
#define  SPDIF_RDES2 0x1720
    #define TIMESTAMP_BUF_ADDR_MASK 0x0FFFFFF8
    #define TIMESTAMP_BUF_ADDR_SHIFT 3
#define  SPDIF_RX_90KHZ_DEN 0x1754
    #define SPDIF_RX_90KHZ_DEN_DEN_MASK 0xFFFFFFFF
    #define SPDIF_RX_90KHZ_DEN_DEN_SHIFT 0
#define  SPDIF_RX_90KHZ_NUM 0x1750
    #define SPDIF_RX_90KHZ_NUM_NUM_MASK 0xFFFFFFFF
    #define SPDIF_RX_90KHZ_NUM_NUM_SHIFT 0
#define  SPDIF_RX_CH1_STATUS_LOWER 0x1774
    #define CH1_STATUS_L_MASK 0xFFFFFFFF
    #define CH1_STATUS_L_SHIFT 0
#define  SPDIF_RX_CH1_STATUS_UPPER 0x1770
    #define CH1_STATUS_U_MASK 0x000003FF
    #define CH1_STATUS_U_SHIFT 0
#define  SPDIF_RX_CH2_STATUS_LOWER 0x177C
    #define CH2_STATUS_L_MASK 0xFFFFFFFF
    #define CH2_STATUS_L_SHIFT 0
#define  SPDIF_RX_CH2_STATUS_UPPER 0x1778
    #define CH2_STATUS_U_MASK 0x000003FF
    #define CH2_STATUS_U_SHIFT 0
#define  SPDIF_RX_CONFIG 0x1700
    #define SPDIF_RX_CONFIG_CHANNEL_EN_MASK 0x00000001
    #define SPDIF_RX_CONFIG_CHANNEL_EN_SHIFT 0
    #define SPDIF_RX_CONFIG_OPERATE_MODE_MASK 0x00000030
    #define SPDIF_RX_CONFIG_OPERATE_MODE_SHIFT 4
    #define CAPTURE_MODE_MASK 0x00000040
    #define CAPTURE_MODE_SHIFT 6
    #define SPDIF_RX_CONFIG_ENDIAN_MASK 0x00000100
    #define SPDIF_RX_CONFIG_ENDIAN_SHIFT 8
    #define LPF_DEPTH_MASK 0x0000F000
    #define LPF_DEPTH_SHIFT 12
    #define SPDIF_RX_CONFIG_RESETN_MASK 0x80000000
    #define SPDIF_RX_CONFIG_RESETN_SHIFT 31
#define  SPDIF_RX_DEN 0x1764
    #define SPDIF_RX_DEN_DEN_MASK 0xFFFFFFFF
    #define SPDIF_RX_DEN_DEN_SHIFT 0
#define  SPDIF_RX_DESC_STATUS 0x1710
    #define SPDIF_RX_DESC_STATUS_CURR_FRAME_NUM_MASK 0x000000FF
    #define SPDIF_RX_DESC_STATUS_CURR_FRAME_NUM_SHIFT 0
    #define SPDIF_RX_DESC_STATUS_DESC_FULL_MASK 0x40000000
    #define SPDIF_RX_DESC_STATUS_DESC_FULL_SHIFT 30
    #define SPDIF_RX_DESC_STATUS_DESC_EMPTY_MASK 0x80000000
    #define SPDIF_RX_DESC_STATUS_DESC_EMPTY_SHIFT 31
#define  SPDIF_RX_DUMMY_REG 0x17FC
    #define SPDIF_RX_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define SPDIF_RX_DUMMY_REG_DATA_SHIFT 0
#define  SPDIF_RX_FOUR_PULSE 0x1744
    #define SPDIF_RX_FOUR_PULSE_WIDTH_MASK 0x000001FF
    #define SPDIF_RX_FOUR_PULSE_WIDTH_SHIFT 0
#define  SPDIF_RX_GENLOCK_LOWER 0x176C
    #define SPDIF_RX_GENLOCK_LOWER_GENLOCK_L_MASK 0xFFFFFFFF
    #define SPDIF_RX_GENLOCK_LOWER_GENLOCK_L_SHIFT 0
#define  SPDIF_RX_GENLOCK_UPPER 0x1768
    #define SPDIF_RX_GENLOCK_UPPER_GENLOCK_U_MASK 0x000003FF
    #define SPDIF_RX_GENLOCK_UPPER_GENLOCK_U_SHIFT 0
#define  SPDIF_RX_HOST_INT_MASK 0x1704
    #define SPDIF_RX_HOST_INT_MASK_OF_INT_MASK 0x00000001
    #define SPDIF_RX_HOST_INT_MASK_OF_INT_SHIFT 0
    #define SPDIF_RX_HOST_INT_MASK_INT_MASK 0x00000100
    #define SPDIF_RX_HOST_INT_MASK_INT_SHIFT 8
    #define SPDIF_RX_HOST_INT_MASK_SHORT_PULSE_INT_MASK 0x00010000
    #define SPDIF_RX_HOST_INT_MASK_SHORT_PULSE_INT_SHIFT 16
    #define SPDIF_RX_HOST_INT_MASK_SHORT_FRAME_INT_MASK 0x00020000
    #define SPDIF_RX_HOST_INT_MASK_SHORT_FRAME_INT_SHIFT 17
    #define SPDIF_RX_HOST_INT_MASK_LOCKED_INT_MASK 0x00040000
    #define SPDIF_RX_HOST_INT_MASK_LOCKED_INT_SHIFT 18
    #define SPDIF_RX_HOST_INT_MASK_LOST_LOCKED_INT_MASK 0x00080000
    #define SPDIF_RX_HOST_INT_MASK_LOST_LOCKED_INT_SHIFT 19
#define  SPDIF_RX_INT_STATUS 0x170C
    #define SPDIF_RX_INT_STATUS_OF_INT_MASK 0x00000001
    #define SPDIF_RX_INT_STATUS_OF_INT_SHIFT 0
    #define SPDIF_RX_INT_STATUS_INT_MASK 0x00000100
    #define SPDIF_RX_INT_STATUS_INT_SHIFT 8
    #define SPDIF_RX_INT_STATUS_SHORT_PULSE_INT_MASK 0x00010000
    #define SPDIF_RX_INT_STATUS_SHORT_PULSE_INT_SHIFT 16
    #define SPDIF_RX_INT_STATUS_SHORT_FRAME_INT_MASK 0x00020000
    #define SPDIF_RX_INT_STATUS_SHORT_FRAME_INT_SHIFT 17
    #define SPDIF_RX_INT_STATUS_LOCKED_INT_MASK 0x00040000
    #define SPDIF_RX_INT_STATUS_LOCKED_INT_SHIFT 18
    #define SPDIF_RX_INT_STATUS_LOST_LOCKED_INT_MASK 0x00080000
    #define SPDIF_RX_INT_STATUS_LOST_LOCKED_INT_SHIFT 19
#define  SPDIF_RX_MAX 0x172C
    #define SPDIF_RX_MAX_PULSE_WIDTH_MASK 0x000001FF
    #define SPDIF_RX_MAX_PULSE_WIDTH_SHIFT 0
#define  SPDIF_RX_MIN 0x1730
    #define SPDIF_RX_MIN_PULSE_WIDTH_MASK 0x000001FF
    #define SPDIF_RX_MIN_PULSE_WIDTH_SHIFT 0
#define  SPDIF_RX_MIPS_INT_MASK 0x1708
    #define SPDIF_RX_MIPS_INT_MASK_OF_INT_MASK 0x00000001
    #define SPDIF_RX_MIPS_INT_MASK_OF_INT_SHIFT 0
    #define SPDIF_RX_MIPS_INT_MASK_INT_MASK 0x00000100
    #define SPDIF_RX_MIPS_INT_MASK_INT_SHIFT 8
    #define SPDIF_RX_MIPS_INT_MASK_SHORT_PULSE_INT_MASK 0x00010000
    #define SPDIF_RX_MIPS_INT_MASK_SHORT_PULSE_INT_SHIFT 16
    #define SPDIF_RX_MIPS_INT_MASK_SHORT_FRAME_INT_MASK 0x00020000
    #define SPDIF_RX_MIPS_INT_MASK_SHORT_FRAME_INT_SHIFT 17
    #define SPDIF_RX_MIPS_INT_MASK_LOCKED_INT_MASK 0x00040000
    #define SPDIF_RX_MIPS_INT_MASK_LOCKED_INT_SHIFT 18
    #define SPDIF_RX_MIPS_INT_MASK_LOST_LOCKED_INT_MASK 0x00080000
    #define SPDIF_RX_MIPS_INT_MASK_LOST_LOCKED_INT_SHIFT 19
#define  SPDIF_RX_MISS_SUBFRAME 0x1780
    #define NUM_MISS_SUBFRAME_MASK 0x000001FF
    #define NUM_MISS_SUBFRAME_SHIFT 0
#define  SPDIF_RX_NUM 0x1760
    #define SPDIF_RX_NUM_NUM_MASK 0xFFFFFFFF
    #define SPDIF_RX_NUM_NUM_SHIFT 0
#define  SPDIF_RX_ONE_PULSE 0x1738
    #define SPDIF_RX_ONE_PULSE_WIDTH_MASK 0x000001FF
    #define SPDIF_RX_ONE_PULSE_WIDTH_SHIFT 0
#define  SPDIF_RX_PREAMBLE 0x1748
    #define SPDIF_RX_PREAMBLE_B_MASK 0x0000000F
    #define SPDIF_RX_PREAMBLE_B_SHIFT 0
    #define SPDIF_RX_PREAMBLE_M_MASK 0x000000F0
    #define SPDIF_RX_PREAMBLE_M_SHIFT 4
    #define SPDIF_RX_PREAMBLE_W_MASK 0x00000F00
    #define SPDIF_RX_PREAMBLE_W_SHIFT 8
#define  SPDIF_RX_SHORT_PULSE 0x1734
    #define SPDIF_RX_SHORT_PULSE_WIDTH_MASK 0x000001FF
    #define SPDIF_RX_SHORT_PULSE_WIDTH_SHIFT 0
#define  SPDIF_RX_STATUS_SHORT_FRAME 0x1784
    #define SPDIF_RX_STATUS_SHORT_FRAME_ERR_CNT_MASK 0xFFFFFFFF
    #define SPDIF_RX_STATUS_SHORT_FRAME_ERR_CNT_SHIFT 0
#define  SPDIF_RX_STATUS_SHORT_PULSE 0x1788
    #define SPDIF_RX_STATUS_SHORT_PULSE_ERR_CNT_MASK 0xFFFFFFFF
    #define SPDIF_RX_STATUS_SHORT_PULSE_ERR_CNT_SHIFT 0
#define  SPDIF_RX_THREE_PULSE 0x1740
    #define SPDIF_RX_THREE_PULSE_WIDTH_MASK 0x000001FF
    #define SPDIF_RX_THREE_PULSE_WIDTH_SHIFT 0
#define  SPDIF_RX_TIMESTAMP_SEL 0x1758
    #define SPDIF_RX_TIMESTAMP_SEL_TIMESTAMP_SEL_MASK 0x00000007
    #define SPDIF_RX_TIMESTAMP_SEL_TIMESTAMP_SEL_SHIFT 0
#define  SPDIF_RX_TWO_PULSE 0x173C
    #define SPDIF_RX_TWO_PULSE_WIDTH_MASK 0x000001FF
    #define SPDIF_RX_TWO_PULSE_WIDTH_SHIFT 0
#define  SPDIF_TDES0 0x1618
    #define SPDIF_TDES0_NUM_FRAME_MASK 0x000000FF
    #define SPDIF_TDES0_NUM_FRAME_SHIFT 0
    #define SPDIF_TDES0_IOC_MASK 0x00008000
    #define SPDIF_TDES0_IOC_SHIFT 15
    #define SPDIF_TDES0_RDWRN_MASK 0x80000000
    #define SPDIF_TDES0_RDWRN_SHIFT 31
#define  SPDIF_TDES1 0x161C
    #define SPDIF_TDES1_DATA_BUF_ADDR_MASK 0x0FFFFFF8
    #define SPDIF_TDES1_DATA_BUF_ADDR_SHIFT 3
#define  SPDIF_TDES2 0x1620
    #define CODE_BUF_ADDR_MASK 0x0FFFFFF8
    #define CODE_BUF_ADDR_SHIFT 3
#define  SPDIF_TIMESTAMP_FREQ 0x1728
    #define TIMESTAMP_FREQ_MASK 0x000000FF
    #define TIMESTAMP_FREQ_SHIFT 0
#define  SPDIF_TIMESTAMP_WR_ADDR 0x1724
    #define SPDIF_TIMESTAMP_WR_ADDR_CURR_WR_ADDR_MASK 0x0FFFFFF8
    #define SPDIF_TIMESTAMP_WR_ADDR_CURR_WR_ADDR_SHIFT 3
#define  SPDIF_TX_CONFIG 0x1600
    #define SPDIF_TX_CONFIG_CHANNEL_EN_MASK 0x00000001
    #define SPDIF_TX_CONFIG_CHANNEL_EN_SHIFT 0
    #define SPDIF_TX_CONFIG_OPERATE_MODE_MASK 0x00000030
    #define SPDIF_TX_CONFIG_OPERATE_MODE_SHIFT 4
    #define SPDIF_TX_CONFIG_ENDIAN_MASK 0x00000100
    #define SPDIF_TX_CONFIG_ENDIAN_SHIFT 8
    #define SPDIF_TX_CONFIG_UF_CTRL_EN_MASK 0x00200000
    #define SPDIF_TX_CONFIG_UF_CTRL_EN_SHIFT 21
    #define SPDIF_TX_CONFIG_RESETN_MASK 0x80000000
    #define SPDIF_TX_CONFIG_RESETN_SHIFT 31
#define  SPDIF_TX_DEN 0x1634
    #define SPDIF_TX_DEN_DEN_MASK 0xFFFFFFFF
    #define SPDIF_TX_DEN_DEN_SHIFT 0
#define  SPDIF_TX_DESC_STATUS 0x1610
    #define SPDIF_TX_DESC_STATUS_CURR_FRAME_NUM_MASK 0x000000FF
    #define SPDIF_TX_DESC_STATUS_CURR_FRAME_NUM_SHIFT 0
    #define SPDIF_TX_DESC_STATUS_DESC_FULL_MASK 0x40000000
    #define SPDIF_TX_DESC_STATUS_DESC_FULL_SHIFT 30
    #define SPDIF_TX_DESC_STATUS_DESC_EMPTY_MASK 0x80000000
    #define SPDIF_TX_DESC_STATUS_DESC_EMPTY_SHIFT 31
#define  SPDIF_TX_DUMMY_REG 0x16FC
    #define SPDIF_TX_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define SPDIF_TX_DUMMY_REG_DATA_SHIFT 0
#define  SPDIF_TX_GENLOCK_LOWER 0x163C
    #define SPDIF_TX_GENLOCK_LOWER_GENLOCK_L_MASK 0xFFFFFFFF
    #define SPDIF_TX_GENLOCK_LOWER_GENLOCK_L_SHIFT 0
#define  SPDIF_TX_GENLOCK_UPPER 0x1638
    #define SPDIF_TX_GENLOCK_UPPER_GENLOCK_U_MASK 0x000003FF
    #define SPDIF_TX_GENLOCK_UPPER_GENLOCK_U_SHIFT 0
#define  SPDIF_TX_HOST_INT_MASK 0x1604
    #define SPDIF_TX_HOST_INT_MASK_UF_INT_MASK 0x00000001
    #define SPDIF_TX_HOST_INT_MASK_UF_INT_SHIFT 0
    #define SPDIF_TX_HOST_INT_MASK_INT_MASK 0x00000100
    #define SPDIF_TX_HOST_INT_MASK_INT_SHIFT 8
#define  SPDIF_TX_INT_STATUS 0x160C
    #define SPDIF_TX_INT_STATUS_UF_INT_MASK 0x00000001
    #define SPDIF_TX_INT_STATUS_UF_INT_SHIFT 0
    #define SPDIF_TX_INT_STATUS_INT_MASK 0x00000100
    #define SPDIF_TX_INT_STATUS_INT_SHIFT 8
#define  SPDIF_TX_MIPS_INT_MASK 0x1608
    #define SPDIF_TX_MIPS_INT_MASK_UF_INT_MASK 0x00000001
    #define SPDIF_TX_MIPS_INT_MASK_UF_INT_SHIFT 0
    #define SPDIF_TX_MIPS_INT_MASK_INT_MASK 0x00000100
    #define SPDIF_TX_MIPS_INT_MASK_INT_SHIFT 8
#define  SPDIF_TX_NUM 0x1630
    #define SPDIF_TX_NUM_NUM_MASK 0xFFFFFFFF
    #define SPDIF_TX_NUM_NUM_SHIFT 0
#define  SPDIF_TX_PREAMBLE 0x1628
    #define SPDIF_TX_PREAMBLE_B_MASK 0x0000000F
    #define SPDIF_TX_PREAMBLE_B_SHIFT 0
    #define SPDIF_TX_PREAMBLE_M_MASK 0x000000F0
    #define SPDIF_TX_PREAMBLE_M_SHIFT 4
    #define SPDIF_TX_PREAMBLE_W_MASK 0x00000F00
    #define SPDIF_TX_PREAMBLE_W_SHIFT 8
#define  SPI_CFG 0x10AC
    #define HOLD_EN_MASK 0x00000001
    #define HOLD_EN_SHIFT 0
    #define XFER_SIZE_MASK 0x00000006
    #define XFER_SIZE_SHIFT 1
    #define CAP_EDGE_MASK 0x00000008
    #define CAP_EDGE_SHIFT 3
    #define RATE_SEL_MASK 0x00000030
    #define RATE_SEL_SHIFT 4
#define  SPI_RDAT 0x10B4
    #define SPI_RDAT_MASK 0xFFFFFFFF
    #define SPI_RDAT_SHIFT 0
#define  SPI_STATUS 0x10B8
    #define SPI_BUSY_MASK 0x00000001
    #define SPI_BUSY_SHIFT 0
#define  SPI_WDAT 0x10B0
    #define SPI_WDAT_MASK 0xFFFFFFFF
    #define SPI_WDAT_SHIFT 0
#define  SYNC_DET_CRC0 0x6010
    #define SYNC_DET_CRC0_DATA_MASK 0x000000FF
    #define SYNC_DET_CRC0_DATA_SHIFT 0
#define  SYNC_DET_CRC1 0x6014
    #define SYNC_DET_CRC1_DATA_MASK 0x000000FF
    #define SYNC_DET_CRC1_DATA_SHIFT 0
#define  SYNC_DET_CTRL 0x6000
    #define PCK_LENGTH_TS0_MASK 0x00000001
    #define PCK_LENGTH_TS0_SHIFT 0
    #define PCK_LENGTH_TS1_MASK 0x00000002
    #define PCK_LENGTH_TS1_SHIFT 1
    #define SER_PAR_SEL0_MASK 0x00000100
    #define SER_PAR_SEL0_SHIFT 8
    #define SER_PAR_SEL1_MASK 0x00000200
    #define SER_PAR_SEL1_SHIFT 9
    #define DIRECTV_MODE0_MASK 0x00001000
    #define DIRECTV_MODE0_SHIFT 12
    #define DIRECTV_MODE1_MASK 0x00002000
    #define DIRECTV_MODE1_SHIFT 13
    #define USE_SYNCBIT0_MASK 0x00010000
    #define USE_SYNCBIT0_SHIFT 16
    #define USE_SYNCBIT1_MASK 0x00020000
    #define USE_SYNCBIT1_SHIFT 17
    #define SRC_INPUT0_EN_MASK 0x01000000
    #define SRC_INPUT0_EN_SHIFT 24
    #define SRC_INPUT1_EN_MASK 0x02000000
    #define SRC_INPUT1_EN_SHIFT 25
#define  SYNC_DET_EDGE_RST_CTRL 0x6008
    #define OF_AUTORST_DIS_MASK 0x00000003
    #define OF_AUTORST_DIS_SHIFT 0
    #define VAL_ACTIVE_HIGH_MASK 0x00000300
    #define VAL_ACTIVE_HIGH_SHIFT 8
    #define USE_NEGEDGE_MASK 0x03000000
    #define USE_NEGEDGE_SHIFT 24
#define  SYNC_DET_LOCK_SRCH 0x6030
    #define SYNC_DET_LOCK_SRCH_LOCK_MASK 0x0000000F
    #define SYNC_DET_LOCK_SRCH_LOCK_SHIFT 0
    #define SRCH_MASK 0x00000F00
    #define SRCH_SHIFT 8
#define  SYNC_DET_POD_CTRL 0x600C
    #define DES_POD0_MASK 0x00000001
    #define DES_POD0_SHIFT 0
    #define DES_POD1_MASK 0x00000002
    #define DES_POD1_SHIFT 1
    #define DROP_NULL0_MASK 0x00000100
    #define DROP_NULL0_SHIFT 8
    #define DROP_NULL1_MASK 0x00000200
    #define DROP_NULL1_SHIFT 9
    #define POD_ENABLE_MASK 0x00010000
    #define POD_ENABLE_SHIFT 16
#define  SYNC_DET_STATUS 0x6004
    #define SYNCMODE0_MASK 0x00000001
    #define SYNCMODE0_SHIFT 0
    #define SYNCMODE1_MASK 0x00000002
    #define SYNCMODE1_SHIFT 1
#define  SYS_FRM_CNT 0x6138
    #define SYS_FRM_CNT_FRM_CNT_MASK 0xFFFFFFFF
    #define SYS_FRM_CNT_FRM_CNT_SHIFT 0
#define  SYS_FRM_CNT_CTRL 0x613C
    #define SYS_FRM_CNT_CTRL_ENABLE_MASK 0x00000001
    #define SYS_FRM_CNT_CTRL_ENABLE_SHIFT 0
#define  SYS_RTP_TIMERH 0x6134
    #define RTP_DATA_U_MASK 0x00000001
    #define RTP_DATA_U_SHIFT 0
#define  SYS_RTP_TIMERL 0x6130
    #define RTP_DATA_L_MASK 0xFFFFFFFF
    #define RTP_DATA_L_SHIFT 0
#define  TSD_CHANNEL_CTRL 0x6150
    #define CH0_MSTR_EN_MASK 0x00000001
    #define CH0_MSTR_EN_SHIFT 0
    #define CH1_MSTR_EN_MASK 0x00000002
    #define CH1_MSTR_EN_SHIFT 1
    #define CH2_MSTR_EN_MASK 0x00000004
    #define CH2_MSTR_EN_SHIFT 2
    #define CH3_MSTR_EN_MASK 0x00000008
    #define CH3_MSTR_EN_SHIFT 3
    #define CH4_MSTR_EN_MASK 0x00000010
    #define CH4_MSTR_EN_SHIFT 4
    #define CH5_MSTR_EN_MASK 0x00000020
    #define CH5_MSTR_EN_SHIFT 5
    #define CH6_MSTR_EN_MASK 0x00000040
    #define CH6_MSTR_EN_SHIFT 6
    #define CH7_MSTR_EN_MASK 0x00000080
    #define CH7_MSTR_EN_SHIFT 7
    #define CH8_MSTR_EN_MASK 0x00000100
    #define CH8_MSTR_EN_SHIFT 8
    #define CH9_MSTR_EN_MASK 0x00000200
    #define CH9_MSTR_EN_SHIFT 9
    #define CH10_MSTR_EN_MASK 0x00000400
    #define CH10_MSTR_EN_SHIFT 10
    #define CH11_MSTR_EN_MASK 0x00000800
    #define CH11_MSTR_EN_SHIFT 11
    #define CH12_MSTR_EN_MASK 0x00001000
    #define CH12_MSTR_EN_SHIFT 12
    #define CH13_MSTR_EN_MASK 0x00002000
    #define CH13_MSTR_EN_SHIFT 13
    #define CH14_MSTR_EN_MASK 0x00004000
    #define CH14_MSTR_EN_SHIFT 14
    #define CH15_MSTR_EN_MASK 0x00008000
    #define CH15_MSTR_EN_SHIFT 15
#define  TSD_DEN 0x6144
    #define TSD_DEN_DEN_MASK 0xFFFFFFFF
    #define TSD_DEN_DEN_SHIFT 0
#define  TSD_DUMMY_REG 0x63FC
    #define TSD_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define TSD_DUMMY_REG_DATA_SHIFT 0
#define  TSD_GENLOCK_CTRL 0x609C
    #define PCR_TOGGLE_SEL_MASK 0x00000003
    #define PCR_TOGGLE_SEL_SHIFT 0
#define  TSD_GENLOCK_LOWER 0x614C
    #define TSD_GENLOCK_LOWER_GENLOCK_L_MASK 0xFFFFFFFF
    #define TSD_GENLOCK_LOWER_GENLOCK_L_SHIFT 0
#define  TSD_GENLOCK_UPPER 0x6148
    #define TSD_GENLOCK_UPPER_GENLOCK_U_MASK 0x000003FF
    #define TSD_GENLOCK_UPPER_GENLOCK_U_SHIFT 0
#define  TSD_HOST_INT_MASK0 0x6164
    #define TSD_HOST_INT_MASK0_INT_EN_PFBUF_OF0_MASK 0x00000001
    #define TSD_HOST_INT_MASK0_INT_EN_PFBUF_OF0_SHIFT 0
    #define TSD_HOST_INT_MASK0_INT_EN_PFBUF_OF1_MASK 0x00000002
    #define TSD_HOST_INT_MASK0_INT_EN_PFBUF_OF1_SHIFT 1
#define  TSD_HOST_INT_MASK1 0x67B4
    #define TSD_HOST_INT_MASK1_INT_EN_RING0_ERR_MASK 0x00000001
    #define TSD_HOST_INT_MASK1_INT_EN_RING0_ERR_SHIFT 0
    #define TSD_HOST_INT_MASK1_INT_EN_RING1_ERR_MASK 0x00000002
    #define TSD_HOST_INT_MASK1_INT_EN_RING1_ERR_SHIFT 1
    #define TSD_HOST_INT_MASK1_INT_EN_RING2_ERR_MASK 0x00000004
    #define TSD_HOST_INT_MASK1_INT_EN_RING2_ERR_SHIFT 2
    #define TSD_HOST_INT_MASK1_INT_EN_RING3_ERR_MASK 0x00000008
    #define TSD_HOST_INT_MASK1_INT_EN_RING3_ERR_SHIFT 3
    #define TSD_HOST_INT_MASK1_INT_EN_RING4_ERR_MASK 0x00000010
    #define TSD_HOST_INT_MASK1_INT_EN_RING4_ERR_SHIFT 4
    #define TSD_HOST_INT_MASK1_INT_EN_RING5_ERR_MASK 0x00000020
    #define TSD_HOST_INT_MASK1_INT_EN_RING5_ERR_SHIFT 5
    #define TSD_HOST_INT_MASK1_INT_EN_RING6_ERR_MASK 0x00000040
    #define TSD_HOST_INT_MASK1_INT_EN_RING6_ERR_SHIFT 6
    #define TSD_HOST_INT_MASK1_INT_EN_RING7_ERR_MASK 0x00000080
    #define TSD_HOST_INT_MASK1_INT_EN_RING7_ERR_SHIFT 7
    #define TSD_HOST_INT_MASK1_INT_EN_RING8_ERR_MASK 0x00000100
    #define TSD_HOST_INT_MASK1_INT_EN_RING8_ERR_SHIFT 8
    #define TSD_HOST_INT_MASK1_INT_EN_RING9_ERR_MASK 0x00000200
    #define TSD_HOST_INT_MASK1_INT_EN_RING9_ERR_SHIFT 9
    #define TSD_HOST_INT_MASK1_INT_EN_RING10_ERR_MASK 0x00000400
    #define TSD_HOST_INT_MASK1_INT_EN_RING10_ERR_SHIFT 10
    #define TSD_HOST_INT_MASK1_INT_EN_RING11_ERR_MASK 0x00000800
    #define TSD_HOST_INT_MASK1_INT_EN_RING11_ERR_SHIFT 11
    #define TSD_HOST_INT_MASK1_INT_EN_RING12_ERR_MASK 0x00001000
    #define TSD_HOST_INT_MASK1_INT_EN_RING12_ERR_SHIFT 12
    #define TSD_HOST_INT_MASK1_INT_EN_RING13_ERR_MASK 0x00002000
    #define TSD_HOST_INT_MASK1_INT_EN_RING13_ERR_SHIFT 13
    #define TSD_HOST_INT_MASK1_INT_EN_RING14_ERR_MASK 0x00004000
    #define TSD_HOST_INT_MASK1_INT_EN_RING14_ERR_SHIFT 14
    #define TSD_HOST_INT_MASK1_INT_EN_RING15_ERR_MASK 0x00008000
    #define TSD_HOST_INT_MASK1_INT_EN_RING15_ERR_SHIFT 15
#define  TSD_HOST_INT_MASK4 0x67D8
    #define TSD_HOST_INT_MASK4_INT_EN_RING0_DATA_MASK 0x00000001
    #define TSD_HOST_INT_MASK4_INT_EN_RING0_DATA_SHIFT 0
    #define TSD_HOST_INT_MASK4_INT_EN_RING1_DATA_MASK 0x00000002
    #define TSD_HOST_INT_MASK4_INT_EN_RING1_DATA_SHIFT 1
    #define TSD_HOST_INT_MASK4_INT_EN_RING2_DATA_MASK 0x00000004
    #define TSD_HOST_INT_MASK4_INT_EN_RING2_DATA_SHIFT 2
    #define TSD_HOST_INT_MASK4_INT_EN_RING3_DATA_MASK 0x00000008
    #define TSD_HOST_INT_MASK4_INT_EN_RING3_DATA_SHIFT 3
    #define TSD_HOST_INT_MASK4_INT_EN_RING4_DATA_MASK 0x00000010
    #define TSD_HOST_INT_MASK4_INT_EN_RING4_DATA_SHIFT 4
    #define TSD_HOST_INT_MASK4_INT_EN_RING5_DATA_MASK 0x00000020
    #define TSD_HOST_INT_MASK4_INT_EN_RING5_DATA_SHIFT 5
    #define TSD_HOST_INT_MASK4_INT_EN_RING6_DATA_MASK 0x00000040
    #define TSD_HOST_INT_MASK4_INT_EN_RING6_DATA_SHIFT 6
    #define TSD_HOST_INT_MASK4_INT_EN_RING7_DATA_MASK 0x00000080
    #define TSD_HOST_INT_MASK4_INT_EN_RING7_DATA_SHIFT 7
    #define TSD_HOST_INT_MASK4_INT_EN_RING8_DATA_MASK 0x00000100
    #define TSD_HOST_INT_MASK4_INT_EN_RING8_DATA_SHIFT 8
    #define TSD_HOST_INT_MASK4_INT_EN_RING9_DATA_MASK 0x00000200
    #define TSD_HOST_INT_MASK4_INT_EN_RING9_DATA_SHIFT 9
    #define TSD_HOST_INT_MASK4_INT_EN_RING10_DATA_MASK 0x00000400
    #define TSD_HOST_INT_MASK4_INT_EN_RING10_DATA_SHIFT 10
    #define TSD_HOST_INT_MASK4_INT_EN_RING11_DATA_MASK 0x00000800
    #define TSD_HOST_INT_MASK4_INT_EN_RING11_DATA_SHIFT 11
    #define TSD_HOST_INT_MASK4_INT_EN_RING12_DATA_MASK 0x00001000
    #define TSD_HOST_INT_MASK4_INT_EN_RING12_DATA_SHIFT 12
    #define TSD_HOST_INT_MASK4_INT_EN_RING13_DATA_MASK 0x00002000
    #define TSD_HOST_INT_MASK4_INT_EN_RING13_DATA_SHIFT 13
    #define TSD_HOST_INT_MASK4_INT_EN_RING14_DATA_MASK 0x00004000
    #define TSD_HOST_INT_MASK4_INT_EN_RING14_DATA_SHIFT 14
    #define TSD_HOST_INT_MASK4_INT_EN_RING15_DATA_MASK 0x00008000
    #define TSD_HOST_INT_MASK4_INT_EN_RING15_DATA_SHIFT 15
#define  TSD_INT_STATUS0 0x6160
    #define PFBUF_OF0_MASK 0x00000001
    #define PFBUF_OF0_SHIFT 0
    #define PFBUF_OF1_MASK 0x00000002
    #define PFBUF_OF1_SHIFT 1
#define  TSD_INT_STATUS1 0x67B0
    #define RING0_ERR_MASK 0x00000001
    #define RING0_ERR_SHIFT 0
    #define RING1_ERR_MASK 0x00000002
    #define RING1_ERR_SHIFT 1
    #define RING2_ERR_MASK 0x00000004
    #define RING2_ERR_SHIFT 2
    #define RING3_ERR_MASK 0x00000008
    #define RING3_ERR_SHIFT 3
    #define RING4_ERR_MASK 0x00000010
    #define RING4_ERR_SHIFT 4
    #define RING5_ERR_MASK 0x00000020
    #define RING5_ERR_SHIFT 5
    #define RING6_ERR_MASK 0x00000040
    #define RING6_ERR_SHIFT 6
    #define RING7_ERR_MASK 0x00000080
    #define RING7_ERR_SHIFT 7
    #define RING8_ERR_MASK 0x00000100
    #define RING8_ERR_SHIFT 8
    #define RING9_ERR_MASK 0x00000200
    #define RING9_ERR_SHIFT 9
    #define RING10_ERR_MASK 0x00000400
    #define RING10_ERR_SHIFT 10
    #define RING11_ERR_MASK 0x00000800
    #define RING11_ERR_SHIFT 11
    #define RING12_ERR_MASK 0x00001000
    #define RING12_ERR_SHIFT 12
    #define RING13_ERR_MASK 0x00002000
    #define RING13_ERR_SHIFT 13
    #define RING14_ERR_MASK 0x00004000
    #define RING14_ERR_SHIFT 14
    #define RING15_ERR_MASK 0x00008000
    #define RING15_ERR_SHIFT 15
#define  TSD_INT_STATUS4 0x67D4
    #define RING0_DATA_MASK 0x00000001
    #define RING0_DATA_SHIFT 0
    #define RING1_DATA_MASK 0x00000002
    #define RING1_DATA_SHIFT 1
    #define RING2_DATA_MASK 0x00000004
    #define RING2_DATA_SHIFT 2
    #define RING3_DATA_MASK 0x00000008
    #define RING3_DATA_SHIFT 3
    #define RING4_DATA_MASK 0x00000010
    #define RING4_DATA_SHIFT 4
    #define RING5_DATA_MASK 0x00000020
    #define RING5_DATA_SHIFT 5
    #define RING6_DATA_MASK 0x00000040
    #define RING6_DATA_SHIFT 6
    #define RING7_DATA_MASK 0x00000080
    #define RING7_DATA_SHIFT 7
    #define RING8_DATA_MASK 0x00000100
    #define RING8_DATA_SHIFT 8
    #define RING9_DATA_MASK 0x00000200
    #define RING9_DATA_SHIFT 9
    #define RING10_DATA_MASK 0x00000400
    #define RING10_DATA_SHIFT 10
    #define RING11_DATA_MASK 0x00000800
    #define RING11_DATA_SHIFT 11
    #define RING12_DATA_MASK 0x00001000
    #define RING12_DATA_SHIFT 12
    #define RING13_DATA_MASK 0x00002000
    #define RING13_DATA_SHIFT 13
    #define RING14_DATA_MASK 0x00004000
    #define RING14_DATA_SHIFT 14
    #define RING15_DATA_MASK 0x00008000
    #define RING15_DATA_SHIFT 15
#define  TSD_MIPS_INT_MASK0 0x6168
    #define TSD_MIPS_INT_MASK0_INT_EN_PFBUF_OF0_MASK 0x00000001
    #define TSD_MIPS_INT_MASK0_INT_EN_PFBUF_OF0_SHIFT 0
    #define TSD_MIPS_INT_MASK0_INT_EN_PFBUF_OF1_MASK 0x00000002
    #define TSD_MIPS_INT_MASK0_INT_EN_PFBUF_OF1_SHIFT 1
#define  TSD_MIPS_INT_MASK1 0x67B8
    #define TSD_MIPS_INT_MASK1_INT_EN_RING0_ERR_MASK 0x00000001
    #define TSD_MIPS_INT_MASK1_INT_EN_RING0_ERR_SHIFT 0
    #define TSD_MIPS_INT_MASK1_INT_EN_RING1_ERR_MASK 0x00000002
    #define TSD_MIPS_INT_MASK1_INT_EN_RING1_ERR_SHIFT 1
    #define TSD_MIPS_INT_MASK1_INT_EN_RING2_ERR_MASK 0x00000004
    #define TSD_MIPS_INT_MASK1_INT_EN_RING2_ERR_SHIFT 2
    #define TSD_MIPS_INT_MASK1_INT_EN_RING3_ERR_MASK 0x00000008
    #define TSD_MIPS_INT_MASK1_INT_EN_RING3_ERR_SHIFT 3
    #define TSD_MIPS_INT_MASK1_INT_EN_RING4_ERR_MASK 0x00000010
    #define TSD_MIPS_INT_MASK1_INT_EN_RING4_ERR_SHIFT 4
    #define TSD_MIPS_INT_MASK1_INT_EN_RING5_ERR_MASK 0x00000020
    #define TSD_MIPS_INT_MASK1_INT_EN_RING5_ERR_SHIFT 5
    #define TSD_MIPS_INT_MASK1_INT_EN_RING6_ERR_MASK 0x00000040
    #define TSD_MIPS_INT_MASK1_INT_EN_RING6_ERR_SHIFT 6
    #define TSD_MIPS_INT_MASK1_INT_EN_RING7_ERR_MASK 0x00000080
    #define TSD_MIPS_INT_MASK1_INT_EN_RING7_ERR_SHIFT 7
    #define TSD_MIPS_INT_MASK1_INT_EN_RING8_ERR_MASK 0x00000100
    #define TSD_MIPS_INT_MASK1_INT_EN_RING8_ERR_SHIFT 8
    #define TSD_MIPS_INT_MASK1_INT_EN_RING9_ERR_MASK 0x00000200
    #define TSD_MIPS_INT_MASK1_INT_EN_RING9_ERR_SHIFT 9
    #define TSD_MIPS_INT_MASK1_INT_EN_RING10_ERR_MASK 0x00000400
    #define TSD_MIPS_INT_MASK1_INT_EN_RING10_ERR_SHIFT 10
    #define TSD_MIPS_INT_MASK1_INT_EN_RING11_ERR_MASK 0x00000800
    #define TSD_MIPS_INT_MASK1_INT_EN_RING11_ERR_SHIFT 11
    #define TSD_MIPS_INT_MASK1_INT_EN_RING12_ERR_MASK 0x00001000
    #define TSD_MIPS_INT_MASK1_INT_EN_RING12_ERR_SHIFT 12
    #define TSD_MIPS_INT_MASK1_INT_EN_RING13_ERR_MASK 0x00002000
    #define TSD_MIPS_INT_MASK1_INT_EN_RING13_ERR_SHIFT 13
    #define TSD_MIPS_INT_MASK1_INT_EN_RING14_ERR_MASK 0x00004000
    #define TSD_MIPS_INT_MASK1_INT_EN_RING14_ERR_SHIFT 14
    #define TSD_MIPS_INT_MASK1_INT_EN_RING15_ERR_MASK 0x00008000
    #define TSD_MIPS_INT_MASK1_INT_EN_RING15_ERR_SHIFT 15
#define  TSD_MIPS_INT_MASK4 0x67DC
    #define TSD_MIPS_INT_MASK4_INT_EN_RING0_DATA_MASK 0x00000001
    #define TSD_MIPS_INT_MASK4_INT_EN_RING0_DATA_SHIFT 0
    #define TSD_MIPS_INT_MASK4_INT_EN_RING1_DATA_MASK 0x00000002
    #define TSD_MIPS_INT_MASK4_INT_EN_RING1_DATA_SHIFT 1
    #define TSD_MIPS_INT_MASK4_INT_EN_RING2_DATA_MASK 0x00000004
    #define TSD_MIPS_INT_MASK4_INT_EN_RING2_DATA_SHIFT 2
    #define TSD_MIPS_INT_MASK4_INT_EN_RING3_DATA_MASK 0x00000008
    #define TSD_MIPS_INT_MASK4_INT_EN_RING3_DATA_SHIFT 3
    #define TSD_MIPS_INT_MASK4_INT_EN_RING4_DATA_MASK 0x00000010
    #define TSD_MIPS_INT_MASK4_INT_EN_RING4_DATA_SHIFT 4
    #define TSD_MIPS_INT_MASK4_INT_EN_RING5_DATA_MASK 0x00000020
    #define TSD_MIPS_INT_MASK4_INT_EN_RING5_DATA_SHIFT 5
    #define TSD_MIPS_INT_MASK4_INT_EN_RING6_DATA_MASK 0x00000040
    #define TSD_MIPS_INT_MASK4_INT_EN_RING6_DATA_SHIFT 6
    #define TSD_MIPS_INT_MASK4_INT_EN_RING7_DATA_MASK 0x00000080
    #define TSD_MIPS_INT_MASK4_INT_EN_RING7_DATA_SHIFT 7
    #define TSD_MIPS_INT_MASK4_INT_EN_RING8_DATA_MASK 0x00000100
    #define TSD_MIPS_INT_MASK4_INT_EN_RING8_DATA_SHIFT 8
    #define TSD_MIPS_INT_MASK4_INT_EN_RING9_DATA_MASK 0x00000200
    #define TSD_MIPS_INT_MASK4_INT_EN_RING9_DATA_SHIFT 9
    #define TSD_MIPS_INT_MASK4_INT_EN_RING10_DATA_MASK 0x00000400
    #define TSD_MIPS_INT_MASK4_INT_EN_RING10_DATA_SHIFT 10
    #define TSD_MIPS_INT_MASK4_INT_EN_RING11_DATA_MASK 0x00000800
    #define TSD_MIPS_INT_MASK4_INT_EN_RING11_DATA_SHIFT 11
    #define TSD_MIPS_INT_MASK4_INT_EN_RING12_DATA_MASK 0x00001000
    #define TSD_MIPS_INT_MASK4_INT_EN_RING12_DATA_SHIFT 12
    #define TSD_MIPS_INT_MASK4_INT_EN_RING13_DATA_MASK 0x00002000
    #define TSD_MIPS_INT_MASK4_INT_EN_RING13_DATA_SHIFT 13
    #define TSD_MIPS_INT_MASK4_INT_EN_RING14_DATA_MASK 0x00004000
    #define TSD_MIPS_INT_MASK4_INT_EN_RING14_DATA_SHIFT 14
    #define TSD_MIPS_INT_MASK4_INT_EN_RING15_DATA_MASK 0x00008000
    #define TSD_MIPS_INT_MASK4_INT_EN_RING15_DATA_SHIFT 15
#define  TSD_NUM 0x6140
    #define TSD_NUM_NUM_MASK 0xFFFFFFFF
    #define TSD_NUM_NUM_SHIFT 0
#define  TSD_SFT_RSTN 0x6034
    #define M_SFT_RSTN_MASK 0x00000001
    #define M_SFT_RSTN_SHIFT 0
    #define S_SFT_RSTN_MASK 0x00000002
    #define S_SFT_RSTN_SHIFT 1
    #define X_SFT_RSTN_MASK 0x00000004
    #define X_SFT_RSTN_SHIFT 2
    #define B_SFT_RSTN_MASK 0x00000008
    #define B_SFT_RSTN_SHIFT 3
    #define D_SFT_RSTN_MASK 0x00000010
    #define D_SFT_RSTN_SHIFT 4
    #define A_SFT_RSTN_MASK 0x00000020
    #define A_SFT_RSTN_SHIFT 5
    #define TDE_ENABLE_MASK 0x00020000
    #define TDE_ENABLE_SHIFT 17
#define  TSD_SF_DUMMY_REG 0x67FC
    #define TSD_SF_DUMMY_REG_DUMMY_REG_MASK 0xFFFFFFFF
    #define TSD_SF_DUMMY_REG_DUMMY_REG_SHIFT 0
#define  TSD_SYNC_MUX_CTRL 0x6154
    #define TSD_SYNC_MUX_CTRL_FETCH_RATE_EN_MASK 0x00000001
    #define TSD_SYNC_MUX_CTRL_FETCH_RATE_EN_SHIFT 0
    #define TSD_SYNC_MUX_CTRL_FETCH_RATE_MASK 0x0003FF00
    #define TSD_SYNC_MUX_CTRL_FETCH_RATE_SHIFT 8
#define  TSD_SYNC_TMUX_CTRL 0x6158
    #define TSD_SYNC_TMUX_CTRL_FETCH_RATE_EN_MASK 0x00000001
    #define TSD_SYNC_TMUX_CTRL_FETCH_RATE_EN_SHIFT 0
    #define TSD_SYNC_TMUX_CTRL_FETCH_RATE_MASK 0x0003FF00
    #define TSD_SYNC_TMUX_CTRL_FETCH_RATE_SHIFT 8
#define  USBD_DEBUG 0x2580
    #define USBD_DEBUG_DEBUG_DATA_MASK 0x000FFFFF
    #define USBD_DEBUG_DEBUG_DATA_SHIFT 0
#define  USBD_DUMMY_REG 0x2584
    #define USBD_DUMMY_REG_DUMMY_BITS_MASK 0xFFFFFFFF
    #define USBD_DUMMY_REG_DUMMY_BITS_SHIFT 0
#define  USBD_EP0_CTRL 0x2400
    #define REG_ADDR_MASK 0x0000FFFF
    #define REG_ADDR_SHIFT 0
    #define REG_WOP_MASK 0x00010000
    #define REG_WOP_SHIFT 16
    #define REG_CSR_SEL_MASK 0x00020000
    #define REG_CSR_SEL_SHIFT 17
#define  USBD_EP0_RD_DATA 0x240C
    #define EP0_RD_DATA_MASK 0xFFFFFFFF
    #define EP0_RD_DATA_SHIFT 0
#define  USBD_EP0_STATUS 0x2404
    #define OP_BUSY_MASK 0x00000001
    #define OP_BUSY_SHIFT 0
#define  USBD_EP0_WR_DATA 0x2408
    #define EP0_WR_DATA_MASK 0xFFFFFFFF
    #define EP0_WR_DATA_SHIFT 0
#define  USBD_EP10_CTRL 0x2560
    #define USBD_EP10_CTRL_PKT_OFFSET_MASK 0x0000FFFF
    #define USBD_EP10_CTRL_PKT_OFFSET_SHIFT 0
    #define USBD_EP10_CTRL_PKT_SIZE_MASK 0x07FF0000
    #define USBD_EP10_CTRL_PKT_SIZE_SHIFT 16
    #define USBD_EP10_CTRL_ENABLE_MASK 0x10000000
    #define USBD_EP10_CTRL_ENABLE_SHIFT 28
#define  USBD_EP10_CUR_STATUS 0x2574
    #define USBD_EP10_CUR_STATUS_FB_OFFSET_SOP_MASK 0x0FFFFFFF
    #define USBD_EP10_CUR_STATUS_FB_OFFSET_SOP_SHIFT 0
    #define USBD_EP10_CUR_STATUS_DESC_EMPTY_MASK 0x10000000
    #define USBD_EP10_CUR_STATUS_DESC_EMPTY_SHIFT 28
    #define USBD_EP10_CUR_STATUS_ENTRY_FINISH_MASK 0x20000000
    #define USBD_EP10_CUR_STATUS_ENTRY_FINISH_SHIFT 29
    #define USBD_EP10_CUR_STATUS_DESC_FULL_MASK 0x40000000
    #define USBD_EP10_CUR_STATUS_DESC_FULL_SHIFT 30
    #define USBD_EP10_CUR_STATUS_ISOFIFO_EMPTY_MASK 0x80000000
    #define USBD_EP10_CUR_STATUS_ISOFIFO_EMPTY_SHIFT 31
#define  USBD_EP10_DESC_FIFO_ADR_RD 0x256C
    #define USBD_EP10_DESC_FIFO_ADR_RD_FB_OFFSET_MASK 0x0FFFFFFF
    #define USBD_EP10_DESC_FIFO_ADR_RD_FB_OFFSET_SHIFT 0
#define  USBD_EP10_DESC_FIFO_ADR_WR 0x2564
    #define USBD_EP10_DESC_FIFO_ADR_WR_FB_OFFSET_MASK 0x0FFFFFFF
    #define USBD_EP10_DESC_FIFO_ADR_WR_FB_OFFSET_SHIFT 0
#define  USBD_EP10_DESC_FIFO_LOAD 0x2568
    #define USBD_EP10_DESC_FIFO_LOAD_PKT_NUM_MASK 0x0000007F
    #define USBD_EP10_DESC_FIFO_LOAD_PKT_NUM_SHIFT 0
    #define USBD_EP10_DESC_FIFO_LOAD_INT_EN_MASK 0x00000080
    #define USBD_EP10_DESC_FIFO_LOAD_INT_EN_SHIFT 7
#define  USBD_EP10_DESC_FIFO_POP 0x2570
    #define USBD_EP10_DESC_FIFO_POP_PKT_NUM_MASK 0x0000007F
    #define USBD_EP10_DESC_FIFO_POP_PKT_NUM_SHIFT 0
    #define USBD_EP10_DESC_FIFO_POP_INT_EN_MASK 0x00000080
    #define USBD_EP10_DESC_FIFO_POP_INT_EN_SHIFT 7
#define  USBD_EP1_CTRL 0x2440
    #define USBD_EP1_CTRL_PKT_OFFSET_MASK 0x0000FFFF
    #define USBD_EP1_CTRL_PKT_OFFSET_SHIFT 0
    #define USBD_EP1_CTRL_PKT_SIZE_MASK 0x00FF0000
    #define USBD_EP1_CTRL_PKT_SIZE_SHIFT 16
    #define USBD_EP1_CTRL_ENABLE_MASK 0x10000000
    #define USBD_EP1_CTRL_ENABLE_SHIFT 28
#define  USBD_EP1_CUR_STATUS 0x2454
    #define USBD_EP1_CUR_STATUS_FB_OFFSET_SOP_MASK 0x0FFFFFFF
    #define USBD_EP1_CUR_STATUS_FB_OFFSET_SOP_SHIFT 0
    #define USBD_EP1_CUR_STATUS_DESC_EMPTY_MASK 0x10000000
    #define USBD_EP1_CUR_STATUS_DESC_EMPTY_SHIFT 28
    #define USBD_EP1_CUR_STATUS_ENTRY_FB_RE_FINISH_MASK 0x20000000
    #define USBD_EP1_CUR_STATUS_ENTRY_FB_RE_FINISH_SHIFT 29
    #define USBD_EP1_CUR_STATUS_DESC_FULL_MASK 0x40000000
    #define USBD_EP1_CUR_STATUS_DESC_FULL_SHIFT 30
    #define USBD_EP1_CUR_STATUS_BULKBUF_BOTH_EMPTY_MASK 0x80000000
    #define USBD_EP1_CUR_STATUS_BULKBUF_BOTH_EMPTY_SHIFT 31
#define  USBD_EP1_DESC_FIFO_ADR_RD 0x244C
    #define USBD_EP1_DESC_FIFO_ADR_RD_FB_OFFSET_MASK 0x0FFFFFFF
    #define USBD_EP1_DESC_FIFO_ADR_RD_FB_OFFSET_SHIFT 0
#define  USBD_EP1_DESC_FIFO_ADR_WR 0x2444
    #define USBD_EP1_DESC_FIFO_ADR_WR_FB_OFFSET_MASK 0x0FFFFFFF
    #define USBD_EP1_DESC_FIFO_ADR_WR_FB_OFFSET_SHIFT 0
#define  USBD_EP1_DESC_FIFO_LOAD 0x2448
    #define USBD_EP1_DESC_FIFO_LOAD_PKT_NUM_MASK 0x0000007F
    #define USBD_EP1_DESC_FIFO_LOAD_PKT_NUM_SHIFT 0
    #define USBD_EP1_DESC_FIFO_LOAD_INT_EN_MASK 0x00000080
    #define USBD_EP1_DESC_FIFO_LOAD_INT_EN_SHIFT 7
#define  USBD_EP1_DESC_FIFO_POP 0x2450
    #define USBD_EP1_DESC_FIFO_POP_PKT_NUM_MASK 0x0000007F
    #define USBD_EP1_DESC_FIFO_POP_PKT_NUM_SHIFT 0
    #define USBD_EP1_DESC_FIFO_POP_INT_EN_MASK 0x00000080
    #define USBD_EP1_DESC_FIFO_POP_INT_EN_SHIFT 7
#define  USBD_EP2_CTRL 0x2460
    #define USBD_EP2_CTRL_PKT_OFFSET_MASK 0x0000FFFF
    #define USBD_EP2_CTRL_PKT_OFFSET_SHIFT 0
    #define USBD_EP2_CTRL_PKT_SIZE_MASK 0x00FF0000
    #define USBD_EP2_CTRL_PKT_SIZE_SHIFT 16
    #define USBD_EP2_CTRL_ENABLE_MASK 0x10000000
    #define USBD_EP2_CTRL_ENABLE_SHIFT 28
#define  USBD_EP2_CUR_STATUS 0x2474
    #define USBD_EP2_CUR_STATUS_FB_OFFSET_SOP_MASK 0x0FFFFFFF
    #define USBD_EP2_CUR_STATUS_FB_OFFSET_SOP_SHIFT 0
    #define USBD_EP2_CUR_STATUS_DESC_EMPTY_MASK 0x10000000
    #define USBD_EP2_CUR_STATUS_DESC_EMPTY_SHIFT 28
    #define USBD_EP2_CUR_STATUS_ENTRY_FINISH_MASK 0x20000000
    #define USBD_EP2_CUR_STATUS_ENTRY_FINISH_SHIFT 29
    #define USBD_EP2_CUR_STATUS_DESC_FULL_MASK 0x40000000
    #define USBD_EP2_CUR_STATUS_DESC_FULL_SHIFT 30
    #define USBD_EP2_CUR_STATUS_BULKBUF_BOTH_FULL_MASK 0x80000000
    #define USBD_EP2_CUR_STATUS_BULKBUF_BOTH_FULL_SHIFT 31
#define  USBD_EP2_DESC_FIFO_ADR_RD 0x246C
    #define USBD_EP2_DESC_FIFO_ADR_RD_FB_OFFSET_MASK 0x0FFFFFFF
    #define USBD_EP2_DESC_FIFO_ADR_RD_FB_OFFSET_SHIFT 0
#define  USBD_EP2_DESC_FIFO_ADR_WR 0x2464
    #define USBD_EP2_DESC_FIFO_ADR_WR_FB_OFFSET_MASK 0x0FFFFFFF
    #define USBD_EP2_DESC_FIFO_ADR_WR_FB_OFFSET_SHIFT 0
#define  USBD_EP2_DESC_FIFO_LOAD 0x2468
    #define USBD_EP2_DESC_FIFO_LOAD_PKT_NUM_MASK 0x0000007F
    #define USBD_EP2_DESC_FIFO_LOAD_PKT_NUM_SHIFT 0
    #define USBD_EP2_DESC_FIFO_LOAD_INT_EN_MASK 0x00000080
    #define USBD_EP2_DESC_FIFO_LOAD_INT_EN_SHIFT 7
#define  USBD_EP2_DESC_FIFO_POP 0x2470
    #define USBD_EP2_DESC_FIFO_POP_PKT_NUM_MASK 0x0000007F
    #define USBD_EP2_DESC_FIFO_POP_PKT_NUM_SHIFT 0
    #define USBD_EP2_DESC_FIFO_POP_INT_EN_MASK 0x00000080
    #define USBD_EP2_DESC_FIFO_POP_INT_EN_SHIFT 7
#define  USBD_EP3_CTRL 0x2480
    #define USBD_EP3_CTRL_PKT_OFFSET_MASK 0x0000FFFF
    #define USBD_EP3_CTRL_PKT_OFFSET_SHIFT 0
    #define USBD_EP3_CTRL_PKT_SIZE_MASK 0x00FF0000
    #define USBD_EP3_CTRL_PKT_SIZE_SHIFT 16
    #define USBD_EP3_CTRL_ENABLE_MASK 0x10000000
    #define USBD_EP3_CTRL_ENABLE_SHIFT 28
#define  USBD_EP3_CUR_STATUS 0x2494
    #define USBD_EP3_CUR_STATUS_FB_OFFSET_SOP_MASK 0x0FFFFFFF
    #define USBD_EP3_CUR_STATUS_FB_OFFSET_SOP_SHIFT 0
    #define USBD_EP3_CUR_STATUS_DESC_EMPTY_MASK 0x10000000
    #define USBD_EP3_CUR_STATUS_DESC_EMPTY_SHIFT 28
    #define USBD_EP3_CUR_STATUS_ENTRY_FB_RE_FINISH_MASK 0x20000000
    #define USBD_EP3_CUR_STATUS_ENTRY_FB_RE_FINISH_SHIFT 29
    #define USBD_EP3_CUR_STATUS_DESC_FULL_MASK 0x40000000
    #define USBD_EP3_CUR_STATUS_DESC_FULL_SHIFT 30
    #define USBD_EP3_CUR_STATUS_BULKBUF_BOTH_EMPTY_MASK 0x80000000
    #define USBD_EP3_CUR_STATUS_BULKBUF_BOTH_EMPTY_SHIFT 31
#define  USBD_EP3_DESC_FIFO_ADR_RD 0x248C
    #define USBD_EP3_DESC_FIFO_ADR_RD_FB_OFFSET_MASK 0x0FFFFFFF
    #define USBD_EP3_DESC_FIFO_ADR_RD_FB_OFFSET_SHIFT 0
#define  USBD_EP3_DESC_FIFO_ADR_WR 0x2484
    #define USBD_EP3_DESC_FIFO_ADR_WR_FB_OFFSET_MASK 0x0FFFFFFF
    #define USBD_EP3_DESC_FIFO_ADR_WR_FB_OFFSET_SHIFT 0
#define  USBD_EP3_DESC_FIFO_LOAD 0x2488
    #define USBD_EP3_DESC_FIFO_LOAD_PKT_NUM_MASK 0x0000007F
    #define USBD_EP3_DESC_FIFO_LOAD_PKT_NUM_SHIFT 0
    #define USBD_EP3_DESC_FIFO_LOAD_INT_EN_MASK 0x00000080
    #define USBD_EP3_DESC_FIFO_LOAD_INT_EN_SHIFT 7
#define  USBD_EP3_DESC_FIFO_POP 0x2490
    #define USBD_EP3_DESC_FIFO_POP_PKT_NUM_MASK 0x0000007F
    #define USBD_EP3_DESC_FIFO_POP_PKT_NUM_SHIFT 0
    #define USBD_EP3_DESC_FIFO_POP_INT_EN_MASK 0x00000080
    #define USBD_EP3_DESC_FIFO_POP_INT_EN_SHIFT 7
#define  USBD_EP4_CTRL 0x24A0
    #define USBD_EP4_CTRL_PKT_OFFSET_MASK 0x0000FFFF
    #define USBD_EP4_CTRL_PKT_OFFSET_SHIFT 0
    #define USBD_EP4_CTRL_PKT_SIZE_MASK 0x00FF0000
    #define USBD_EP4_CTRL_PKT_SIZE_SHIFT 16
    #define USBD_EP4_CTRL_ENABLE_MASK 0x10000000
    #define USBD_EP4_CTRL_ENABLE_SHIFT 28
#define  USBD_EP4_CUR_STATUS 0x24B4
    #define USBD_EP4_CUR_STATUS_FB_OFFSET_SOP_MASK 0x0FFFFFFF
    #define USBD_EP4_CUR_STATUS_FB_OFFSET_SOP_SHIFT 0
    #define USBD_EP4_CUR_STATUS_DESC_EMPTY_MASK 0x10000000
    #define USBD_EP4_CUR_STATUS_DESC_EMPTY_SHIFT 28
    #define USBD_EP4_CUR_STATUS_ENTRY_FINISH_MASK 0x20000000
    #define USBD_EP4_CUR_STATUS_ENTRY_FINISH_SHIFT 29
    #define USBD_EP4_CUR_STATUS_DESC_FULL_MASK 0x40000000
    #define USBD_EP4_CUR_STATUS_DESC_FULL_SHIFT 30
    #define USBD_EP4_CUR_STATUS_BULKBUF_BOTH_FULL_MASK 0x80000000
    #define USBD_EP4_CUR_STATUS_BULKBUF_BOTH_FULL_SHIFT 31
#define  USBD_EP4_DESC_FIFO_ADR_RD 0x24AC
    #define USBD_EP4_DESC_FIFO_ADR_RD_FB_OFFSET_MASK 0x0FFFFFFF
    #define USBD_EP4_DESC_FIFO_ADR_RD_FB_OFFSET_SHIFT 0
#define  USBD_EP4_DESC_FIFO_ADR_WR 0x24A4
    #define USBD_EP4_DESC_FIFO_ADR_WR_FB_OFFSET_MASK 0x0FFFFFFF
    #define USBD_EP4_DESC_FIFO_ADR_WR_FB_OFFSET_SHIFT 0
#define  USBD_EP4_DESC_FIFO_LOAD 0x24A8
    #define USBD_EP4_DESC_FIFO_LOAD_PKT_NUM_MASK 0x0000007F
    #define USBD_EP4_DESC_FIFO_LOAD_PKT_NUM_SHIFT 0
    #define USBD_EP4_DESC_FIFO_LOAD_INT_EN_MASK 0x00000080
    #define USBD_EP4_DESC_FIFO_LOAD_INT_EN_SHIFT 7
#define  USBD_EP4_DESC_FIFO_POP 0x24B0
    #define USBD_EP4_DESC_FIFO_POP_PKT_NUM_MASK 0x0000007F
    #define USBD_EP4_DESC_FIFO_POP_PKT_NUM_SHIFT 0
    #define USBD_EP4_DESC_FIFO_POP_INT_EN_MASK 0x00000080
    #define USBD_EP4_DESC_FIFO_POP_INT_EN_SHIFT 7
#define  USBD_EP5_CTRL 0x24C0
    #define USBD_EP5_CTRL_PKT_OFFSET_MASK 0x0000FFFF
    #define USBD_EP5_CTRL_PKT_OFFSET_SHIFT 0
    #define USBD_EP5_CTRL_PKT_SIZE_MASK 0x00FF0000
    #define USBD_EP5_CTRL_PKT_SIZE_SHIFT 16
    #define USBD_EP5_CTRL_ENABLE_MASK 0x10000000
    #define USBD_EP5_CTRL_ENABLE_SHIFT 28
#define  USBD_EP5_CUR_STATUS 0x24D4
    #define USBD_EP5_CUR_STATUS_FB_OFFSET_SOP_MASK 0x0FFFFFFF
    #define USBD_EP5_CUR_STATUS_FB_OFFSET_SOP_SHIFT 0
    #define USBD_EP5_CUR_STATUS_DESC_EMPTY_MASK 0x10000000
    #define USBD_EP5_CUR_STATUS_DESC_EMPTY_SHIFT 28
    #define USBD_EP5_CUR_STATUS_ENTRY_FB_RE_FINISH_MASK 0x20000000
    #define USBD_EP5_CUR_STATUS_ENTRY_FB_RE_FINISH_SHIFT 29
    #define USBD_EP5_CUR_STATUS_DESC_FULL_MASK 0x40000000
    #define USBD_EP5_CUR_STATUS_DESC_FULL_SHIFT 30
    #define USBD_EP5_CUR_STATUS_BULKBUF_BOTH_EMPTY_MASK 0x80000000
    #define USBD_EP5_CUR_STATUS_BULKBUF_BOTH_EMPTY_SHIFT 31
#define  USBD_EP5_DESC_FIFO_ADR_RD 0x24CC
    #define USBD_EP5_DESC_FIFO_ADR_RD_FB_OFFSET_MASK 0x0FFFFFFF
    #define USBD_EP5_DESC_FIFO_ADR_RD_FB_OFFSET_SHIFT 0
#define  USBD_EP5_DESC_FIFO_ADR_WR 0x24C4
    #define USBD_EP5_DESC_FIFO_ADR_WR_FB_OFFSET_MASK 0x0FFFFFFF
    #define USBD_EP5_DESC_FIFO_ADR_WR_FB_OFFSET_SHIFT 0
#define  USBD_EP5_DESC_FIFO_LOAD 0x24C8
    #define USBD_EP5_DESC_FIFO_LOAD_PKT_NUM_MASK 0x0000007F
    #define USBD_EP5_DESC_FIFO_LOAD_PKT_NUM_SHIFT 0
    #define USBD_EP5_DESC_FIFO_LOAD_INT_EN_MASK 0x00000080
    #define USBD_EP5_DESC_FIFO_LOAD_INT_EN_SHIFT 7
#define  USBD_EP5_DESC_FIFO_POP 0x24D0
    #define USBD_EP5_DESC_FIFO_POP_PKT_NUM_MASK 0x0000007F
    #define USBD_EP5_DESC_FIFO_POP_PKT_NUM_SHIFT 0
    #define USBD_EP5_DESC_FIFO_POP_INT_EN_MASK 0x00000080
    #define USBD_EP5_DESC_FIFO_POP_INT_EN_SHIFT 7
#define  USBD_EP6_CTRL 0x24E0
    #define USBD_EP6_CTRL_PKT_OFFSET_MASK 0x0000FFFF
    #define USBD_EP6_CTRL_PKT_OFFSET_SHIFT 0
    #define USBD_EP6_CTRL_PKT_SIZE_MASK 0x00FF0000
    #define USBD_EP6_CTRL_PKT_SIZE_SHIFT 16
    #define USBD_EP6_CTRL_ENABLE_MASK 0x10000000
    #define USBD_EP6_CTRL_ENABLE_SHIFT 28
#define  USBD_EP6_CUR_STATUS 0x24F4
    #define USBD_EP6_CUR_STATUS_FB_OFFSET_SOP_MASK 0x0FFFFFFF
    #define USBD_EP6_CUR_STATUS_FB_OFFSET_SOP_SHIFT 0
    #define USBD_EP6_CUR_STATUS_DESC_EMPTY_MASK 0x10000000
    #define USBD_EP6_CUR_STATUS_DESC_EMPTY_SHIFT 28
    #define USBD_EP6_CUR_STATUS_ENTRY_FINISH_MASK 0x20000000
    #define USBD_EP6_CUR_STATUS_ENTRY_FINISH_SHIFT 29
    #define USBD_EP6_CUR_STATUS_DESC_FULL_MASK 0x40000000
    #define USBD_EP6_CUR_STATUS_DESC_FULL_SHIFT 30
    #define USBD_EP6_CUR_STATUS_BULKBUF_BOTH_FULL_MASK 0x80000000
    #define USBD_EP6_CUR_STATUS_BULKBUF_BOTH_FULL_SHIFT 31
#define  USBD_EP6_DESC_FIFO_ADR_RD 0x24EC
    #define USBD_EP6_DESC_FIFO_ADR_RD_FB_OFFSET_MASK 0x0FFFFFFF
    #define USBD_EP6_DESC_FIFO_ADR_RD_FB_OFFSET_SHIFT 0
#define  USBD_EP6_DESC_FIFO_ADR_WR 0x24E4
    #define USBD_EP6_DESC_FIFO_ADR_WR_FB_OFFSET_MASK 0x0FFFFFFF
    #define USBD_EP6_DESC_FIFO_ADR_WR_FB_OFFSET_SHIFT 0
#define  USBD_EP6_DESC_FIFO_LOAD 0x24E8
    #define USBD_EP6_DESC_FIFO_LOAD_PKT_NUM_MASK 0x0000007F
    #define USBD_EP6_DESC_FIFO_LOAD_PKT_NUM_SHIFT 0
    #define USBD_EP6_DESC_FIFO_LOAD_INT_EN_MASK 0x00000080
    #define USBD_EP6_DESC_FIFO_LOAD_INT_EN_SHIFT 7
#define  USBD_EP6_DESC_FIFO_POP 0x24F0
    #define USBD_EP6_DESC_FIFO_POP_PKT_NUM_MASK 0x0000007F
    #define USBD_EP6_DESC_FIFO_POP_PKT_NUM_SHIFT 0
    #define USBD_EP6_DESC_FIFO_POP_INT_EN_MASK 0x00000080
    #define USBD_EP6_DESC_FIFO_POP_INT_EN_SHIFT 7
#define  USBD_EP7_CTRL 0x2500
    #define USBD_EP7_CTRL_PKT_OFFSET_MASK 0x0000FFFF
    #define USBD_EP7_CTRL_PKT_OFFSET_SHIFT 0
    #define USBD_EP7_CTRL_PKT_SIZE_MASK 0x00FF0000
    #define USBD_EP7_CTRL_PKT_SIZE_SHIFT 16
    #define USBD_EP7_CTRL_ENABLE_MASK 0x10000000
    #define USBD_EP7_CTRL_ENABLE_SHIFT 28
#define  USBD_EP7_CUR_STATUS 0x2514
    #define USBD_EP7_CUR_STATUS_FB_OFFSET_SOP_MASK 0x0FFFFFFF
    #define USBD_EP7_CUR_STATUS_FB_OFFSET_SOP_SHIFT 0
    #define USBD_EP7_CUR_STATUS_DESC_EMPTY_MASK 0x10000000
    #define USBD_EP7_CUR_STATUS_DESC_EMPTY_SHIFT 28
    #define USBD_EP7_CUR_STATUS_ENTRY_FB_RE_FINISH_MASK 0x20000000
    #define USBD_EP7_CUR_STATUS_ENTRY_FB_RE_FINISH_SHIFT 29
    #define USBD_EP7_CUR_STATUS_DESC_FULL_MASK 0x40000000
    #define USBD_EP7_CUR_STATUS_DESC_FULL_SHIFT 30
    #define USBD_EP7_CUR_STATUS_BULKBUF_BOTH_EMPTY_MASK 0x80000000
    #define USBD_EP7_CUR_STATUS_BULKBUF_BOTH_EMPTY_SHIFT 31
#define  USBD_EP7_DESC_FIFO_ADR_RD 0x250C
    #define USBD_EP7_DESC_FIFO_ADR_RD_FB_OFFSET_MASK 0x0FFFFFFF
    #define USBD_EP7_DESC_FIFO_ADR_RD_FB_OFFSET_SHIFT 0
#define  USBD_EP7_DESC_FIFO_ADR_WR 0x2504
    #define USBD_EP7_DESC_FIFO_ADR_WR_FB_OFFSET_MASK 0x0FFFFFFF
    #define USBD_EP7_DESC_FIFO_ADR_WR_FB_OFFSET_SHIFT 0
#define  USBD_EP7_DESC_FIFO_LOAD 0x2508
    #define USBD_EP7_DESC_FIFO_LOAD_PKT_NUM_MASK 0x0000007F
    #define USBD_EP7_DESC_FIFO_LOAD_PKT_NUM_SHIFT 0
    #define USBD_EP7_DESC_FIFO_LOAD_INT_EN_MASK 0x00000080
    #define USBD_EP7_DESC_FIFO_LOAD_INT_EN_SHIFT 7
#define  USBD_EP7_DESC_FIFO_POP 0x2510
    #define USBD_EP7_DESC_FIFO_POP_PKT_NUM_MASK 0x0000007F
    #define USBD_EP7_DESC_FIFO_POP_PKT_NUM_SHIFT 0
    #define USBD_EP7_DESC_FIFO_POP_INT_EN_MASK 0x00000080
    #define USBD_EP7_DESC_FIFO_POP_INT_EN_SHIFT 7
#define  USBD_EP8_CTRL 0x2520
    #define USBD_EP8_CTRL_PKT_OFFSET_MASK 0x0000FFFF
    #define USBD_EP8_CTRL_PKT_OFFSET_SHIFT 0
    #define USBD_EP8_CTRL_PKT_SIZE_MASK 0x00FF0000
    #define USBD_EP8_CTRL_PKT_SIZE_SHIFT 16
    #define USBD_EP8_CTRL_ENABLE_MASK 0x10000000
    #define USBD_EP8_CTRL_ENABLE_SHIFT 28
#define  USBD_EP8_CUR_STATUS 0x2534
    #define USBD_EP8_CUR_STATUS_FB_OFFSET_SOP_MASK 0x0FFFFFFF
    #define USBD_EP8_CUR_STATUS_FB_OFFSET_SOP_SHIFT 0
    #define USBD_EP8_CUR_STATUS_DESC_EMPTY_MASK 0x10000000
    #define USBD_EP8_CUR_STATUS_DESC_EMPTY_SHIFT 28
    #define USBD_EP8_CUR_STATUS_ENTRY_FINISH_MASK 0x20000000
    #define USBD_EP8_CUR_STATUS_ENTRY_FINISH_SHIFT 29
    #define USBD_EP8_CUR_STATUS_DESC_FULL_MASK 0x40000000
    #define USBD_EP8_CUR_STATUS_DESC_FULL_SHIFT 30
    #define USBD_EP8_CUR_STATUS_BULKBUF_BOTH_FULL_MASK 0x80000000
    #define USBD_EP8_CUR_STATUS_BULKBUF_BOTH_FULL_SHIFT 31
#define  USBD_EP8_DESC_FIFO_ADR_RD 0x252C
    #define USBD_EP8_DESC_FIFO_ADR_RD_FB_OFFSET_MASK 0x0FFFFFFF
    #define USBD_EP8_DESC_FIFO_ADR_RD_FB_OFFSET_SHIFT 0
#define  USBD_EP8_DESC_FIFO_ADR_WR 0x2524
    #define USBD_EP8_DESC_FIFO_ADR_WR_FB_OFFSET_MASK 0x0FFFFFFF
    #define USBD_EP8_DESC_FIFO_ADR_WR_FB_OFFSET_SHIFT 0
#define  USBD_EP8_DESC_FIFO_LOAD 0x2528
    #define USBD_EP8_DESC_FIFO_LOAD_PKT_NUM_MASK 0x0000007F
    #define USBD_EP8_DESC_FIFO_LOAD_PKT_NUM_SHIFT 0
    #define USBD_EP8_DESC_FIFO_LOAD_INT_EN_MASK 0x00000080
    #define USBD_EP8_DESC_FIFO_LOAD_INT_EN_SHIFT 7
#define  USBD_EP8_DESC_FIFO_POP 0x2530
    #define USBD_EP8_DESC_FIFO_POP_PKT_NUM_MASK 0x0000007F
    #define USBD_EP8_DESC_FIFO_POP_PKT_NUM_SHIFT 0
    #define USBD_EP8_DESC_FIFO_POP_INT_EN_MASK 0x00000080
    #define USBD_EP8_DESC_FIFO_POP_INT_EN_SHIFT 7
#define  USBD_EP9_CTRL 0x2540
    #define USBD_EP9_CTRL_PKT_OFFSET_MASK 0x0000FFFF
    #define USBD_EP9_CTRL_PKT_OFFSET_SHIFT 0
    #define USBD_EP9_CTRL_PKT_SIZE_MASK 0x07FF0000
    #define USBD_EP9_CTRL_PKT_SIZE_SHIFT 16
    #define USBD_EP9_CTRL_ENABLE_MASK 0x10000000
    #define USBD_EP9_CTRL_ENABLE_SHIFT 28
#define  USBD_EP9_CUR_STATUS 0x2554
    #define USBD_EP9_CUR_STATUS_FB_OFFSET_SOP_MASK 0x0FFFFFFF
    #define USBD_EP9_CUR_STATUS_FB_OFFSET_SOP_SHIFT 0
    #define USBD_EP9_CUR_STATUS_DESC_EMPTY_MASK 0x10000000
    #define USBD_EP9_CUR_STATUS_DESC_EMPTY_SHIFT 28
    #define USBD_EP9_CUR_STATUS_ENTRY_FINISH_MASK 0x20000000
    #define USBD_EP9_CUR_STATUS_ENTRY_FINISH_SHIFT 29
    #define USBD_EP9_CUR_STATUS_DESC_FULL_MASK 0x40000000
    #define USBD_EP9_CUR_STATUS_DESC_FULL_SHIFT 30
    #define USBD_EP9_CUR_STATUS_ISOFIFO_EMPTY_MASK 0x80000000
    #define USBD_EP9_CUR_STATUS_ISOFIFO_EMPTY_SHIFT 31
#define  USBD_EP9_DESC_FIFO_ADR_RD 0x254C
    #define USBD_EP9_DESC_FIFO_ADR_RD_FB_OFFSET_MASK 0x0FFFFFFF
    #define USBD_EP9_DESC_FIFO_ADR_RD_FB_OFFSET_SHIFT 0
#define  USBD_EP9_DESC_FIFO_ADR_WR 0x2544
    #define USBD_EP9_DESC_FIFO_ADR_WR_FB_OFFSET_MASK 0x0FFFFFFF
    #define USBD_EP9_DESC_FIFO_ADR_WR_FB_OFFSET_SHIFT 0
#define  USBD_EP9_DESC_FIFO_LOAD 0x2548
    #define USBD_EP9_DESC_FIFO_LOAD_PKT_NUM_MASK 0x0000007F
    #define USBD_EP9_DESC_FIFO_LOAD_PKT_NUM_SHIFT 0
    #define USBD_EP9_DESC_FIFO_LOAD_INT_EN_MASK 0x00000080
    #define USBD_EP9_DESC_FIFO_LOAD_INT_EN_SHIFT 7
#define  USBD_EP9_DESC_FIFO_POP 0x2550
    #define USBD_EP9_DESC_FIFO_POP_PKT_NUM_MASK 0x0000007F
    #define USBD_EP9_DESC_FIFO_POP_PKT_NUM_SHIFT 0
    #define USBD_EP9_DESC_FIFO_POP_INT_EN_MASK 0x00000080
    #define USBD_EP9_DESC_FIFO_POP_INT_EN_SHIFT 7
#define  USBD_EP_TRANS_STATUS 0x2438
    #define EP0_VCI_TRANS_IDLE_MASK 0x00000001
    #define EP0_VCI_TRANS_IDLE_SHIFT 0
    #define EP1_VCI_TRANS_IDLE_MASK 0x00000002
    #define EP1_VCI_TRANS_IDLE_SHIFT 1
    #define EP2_VCI_TRANS_IDLE_MASK 0x00000004
    #define EP2_VCI_TRANS_IDLE_SHIFT 2
    #define EP3_VCI_TRANS_IDLE_MASK 0x00000008
    #define EP3_VCI_TRANS_IDLE_SHIFT 3
    #define EP4_VCI_TRANS_IDLE_MASK 0x00000010
    #define EP4_VCI_TRANS_IDLE_SHIFT 4
    #define EP5_VCI_TRANS_IDLE_MASK 0x00000020
    #define EP5_VCI_TRANS_IDLE_SHIFT 5
    #define EP6_VCI_TRANS_IDLE_MASK 0x00000040
    #define EP6_VCI_TRANS_IDLE_SHIFT 6
    #define EP7_VCI_TRANS_IDLE_MASK 0x00000080
    #define EP7_VCI_TRANS_IDLE_SHIFT 7
    #define EP8_VCI_TRANS_IDLE_MASK 0x00000100
    #define EP8_VCI_TRANS_IDLE_SHIFT 8
    #define EP9_VCI_TRANS_IDLE_MASK 0x00000200
    #define EP9_VCI_TRANS_IDLE_SHIFT 9
    #define EP10_VCI_TRANS_IDLE_MASK 0x00000400
    #define EP10_VCI_TRANS_IDLE_SHIFT 10
    #define EP0_FB_TRANS_IDLE_MASK 0x00000800
    #define EP0_FB_TRANS_IDLE_SHIFT 11
    #define EP1_FB_TRANS_IDLE_MASK 0x00001000
    #define EP1_FB_TRANS_IDLE_SHIFT 12
    #define EP2_FB_TRANS_IDLE_MASK 0x00002000
    #define EP2_FB_TRANS_IDLE_SHIFT 13
    #define EP3_FB_TRANS_IDLE_MASK 0x00004000
    #define EP3_FB_TRANS_IDLE_SHIFT 14
    #define EP4_FB_TRANS_IDLE_MASK 0x00008000
    #define EP4_FB_TRANS_IDLE_SHIFT 15
    #define EP5_FB_TRANS_IDLE_MASK 0x00010000
    #define EP5_FB_TRANS_IDLE_SHIFT 16
    #define EP6_FB_TRANS_IDLE_MASK 0x00020000
    #define EP6_FB_TRANS_IDLE_SHIFT 17
    #define EP7_FB_TRANS_IDLE_MASK 0x00040000
    #define EP7_FB_TRANS_IDLE_SHIFT 18
    #define EP8_FB_TRANS_IDLE_MASK 0x00080000
    #define EP8_FB_TRANS_IDLE_SHIFT 19
    #define EP9_FB_TRANS_IDLE_MASK 0x00100000
    #define EP9_FB_TRANS_IDLE_SHIFT 20
    #define EP10_FB_TRANS_IDLE_MASK 0x00200000
    #define EP10_FB_TRANS_IDLE_SHIFT 21
    #define EP0_REG_TRANS_IDLE_MASK 0x00400000
    #define EP0_REG_TRANS_IDLE_SHIFT 22
#define  USBD_HOST_INT_MASK 0x2414
    #define HOST_EP0_INT_EN_REG_RD_MASK 0x00000001
    #define HOST_EP0_INT_EN_REG_RD_SHIFT 0
    #define HOST_EP0_INT_EN_REG_WR_MASK 0x00000002
    #define HOST_EP0_INT_EN_REG_WR_SHIFT 1
    #define HOST_EP0_INT_EN_MEM_RD_MASK 0x00000004
    #define HOST_EP0_INT_EN_MEM_RD_SHIFT 2
    #define HOST_EP0_INT_EN_MEM_WR_MASK 0x00000008
    #define HOST_EP0_INT_EN_MEM_WR_SHIFT 3
    #define HOST_EP0_INT_EN_GETDEVDES_MASK 0x00000010
    #define HOST_EP0_INT_EN_GETDEVDES_SHIFT 4
    #define HOST_EP0_INT_EN_GETCFGDES_MASK 0x00000020
    #define HOST_EP0_INT_EN_GETCFGDES_SHIFT 5
    #define HOST_EP0_INT_EN_GETSTRINGDES_MASK 0x00000040
    #define HOST_EP0_INT_EN_GETSTRINGDES_SHIFT 6
    #define HOST_EP0_INT_EN_GET_UNK_MASK 0x00000080
    #define HOST_EP0_INT_EN_GET_UNK_SHIFT 7
    #define HOST_EP0_INT_EN_SET_UNK_MASK 0x00000100
    #define HOST_EP0_INT_EN_SET_UNK_SHIFT 8
    #define HOST_EP0_INT_EN_SUSPEND_MASK 0x00000200
    #define HOST_EP0_INT_EN_SUSPEND_SHIFT 9
    #define HOST_EP0_INT_EN_OUT_SUSPEND_MASK 0x00000400
    #define HOST_EP0_INT_EN_OUT_SUSPEND_SHIFT 10
    #define HOST_EP1_INT_EN_TRANS_DONE_MASK 0x00000800
    #define HOST_EP1_INT_EN_TRANS_DONE_SHIFT 11
    #define HOST_EP2_INT_EN_TRANS_DONE_MASK 0x00001000
    #define HOST_EP2_INT_EN_TRANS_DONE_SHIFT 12
    #define HOST_EP3_INT_EN_TRANS_DONE_MASK 0x00002000
    #define HOST_EP3_INT_EN_TRANS_DONE_SHIFT 13
    #define HOST_EP4_INT_EN_TRANS_DONE_MASK 0x00004000
    #define HOST_EP4_INT_EN_TRANS_DONE_SHIFT 14
    #define HOST_EP5_INT_EN_TRANS_DONE_MASK 0x00008000
    #define HOST_EP5_INT_EN_TRANS_DONE_SHIFT 15
    #define HOST_EP6_INT_EN_TRANS_DONE_MASK 0x00010000
    #define HOST_EP6_INT_EN_TRANS_DONE_SHIFT 16
    #define HOST_EP7_INT_EN_TRANS_DONE_MASK 0x00020000
    #define HOST_EP7_INT_EN_TRANS_DONE_SHIFT 17
    #define HOST_EP8_INT_EN_TRANS_DONE_MASK 0x00040000
    #define HOST_EP8_INT_EN_TRANS_DONE_SHIFT 18
    #define HOST_EP9_INT_EN_TRANS_DONE_MASK 0x00080000
    #define HOST_EP9_INT_EN_TRANS_DONE_SHIFT 19
    #define HOST_EP10_INT_EN_TRANS_DONE_MASK 0x00100000
    #define HOST_EP10_INT_EN_TRANS_DONE_SHIFT 20
    #define HOST_EP2_INT_EN_TRANS_ERR_MASK 0x00200000
    #define HOST_EP2_INT_EN_TRANS_ERR_SHIFT 21
    #define HOST_EP4_INT_EN_TRANS_ERR_MASK 0x00400000
    #define HOST_EP4_INT_EN_TRANS_ERR_SHIFT 22
    #define HOST_EP6_INT_EN_TRANS_ERR_MASK 0x00800000
    #define HOST_EP6_INT_EN_TRANS_ERR_SHIFT 23
    #define HOST_EP8_INT_EN_TRANS_ERR_MASK 0x01000000
    #define HOST_EP8_INT_EN_TRANS_ERR_SHIFT 24
    #define HOST_EP9_INT_EN_TRANS_ERR_MASK 0x02000000
    #define HOST_EP9_INT_EN_TRANS_ERR_SHIFT 25
    #define HOST_EP10_INT_EN_TRANS_ERR_MASK 0x04000000
    #define HOST_EP10_INT_EN_TRANS_ERR_SHIFT 26
#define  USBD_INT_STATUS 0x2410
    #define EP0_INT_REG_RD_MASK 0x00000001
    #define EP0_INT_REG_RD_SHIFT 0
    #define EP0_INT_REG_WR_MASK 0x00000002
    #define EP0_INT_REG_WR_SHIFT 1
    #define EP0_INT_MEM_RD_MASK 0x00000004
    #define EP0_INT_MEM_RD_SHIFT 2
    #define EP0_INT_MEM_WR_MASK 0x00000008
    #define EP0_INT_MEM_WR_SHIFT 3
    #define EP0_INT_GETDEVDES_MASK 0x00000010
    #define EP0_INT_GETDEVDES_SHIFT 4
    #define EP0_INT_GETCFGDES_MASK 0x00000020
    #define EP0_INT_GETCFGDES_SHIFT 5
    #define EP0_INT_GETSTRINGDES_MASK 0x00000040
    #define EP0_INT_GETSTRINGDES_SHIFT 6
    #define EP0_INT_GET_UNK_MASK 0x00000080
    #define EP0_INT_GET_UNK_SHIFT 7
    #define EP0_INT_SET_UNK_MASK 0x00000100
    #define EP0_INT_SET_UNK_SHIFT 8
    #define EP0_INT_SUSPEND_MASK 0x00000200
    #define EP0_INT_SUSPEND_SHIFT 9
    #define EP0_INT_OUT_SUSPEND_MASK 0x00000400
    #define EP0_INT_OUT_SUSPEND_SHIFT 10
    #define EP1_INT_TRANS_DONE_MASK 0x00000800
    #define EP1_INT_TRANS_DONE_SHIFT 11
    #define EP2_INT_TRANS_DONE_MASK 0x00001000
    #define EP2_INT_TRANS_DONE_SHIFT 12
    #define EP3_INT_TRANS_DONE_MASK 0x00002000
    #define EP3_INT_TRANS_DONE_SHIFT 13
    #define EP4_INT_TRANS_DONE_MASK 0x00004000
    #define EP4_INT_TRANS_DONE_SHIFT 14
    #define EP5_INT_TRANS_DONE_MASK 0x00008000
    #define EP5_INT_TRANS_DONE_SHIFT 15
    #define EP6_INT_TRANS_DONE_MASK 0x00010000
    #define EP6_INT_TRANS_DONE_SHIFT 16
    #define EP7_INT_TRANS_DONE_MASK 0x00020000
    #define EP7_INT_TRANS_DONE_SHIFT 17
    #define EP8_INT_TRANS_DONE_MASK 0x00040000
    #define EP8_INT_TRANS_DONE_SHIFT 18
    #define EP9_INT_TRANS_DONE_MASK 0x00080000
    #define EP9_INT_TRANS_DONE_SHIFT 19
    #define EP10_INT_TRANS_DONE_MASK 0x00100000
    #define EP10_INT_TRANS_DONE_SHIFT 20
    #define EP2_INT_TRANS_ERR_MASK 0x00200000
    #define EP2_INT_TRANS_ERR_SHIFT 21
    #define EP4_INT_TRANS_ERR_MASK 0x00400000
    #define EP4_INT_TRANS_ERR_SHIFT 22
    #define EP6_INT_TRANS_ERR_MASK 0x00800000
    #define EP6_INT_TRANS_ERR_SHIFT 23
    #define EP8_INT_TRANS_ERR_MASK 0x01000000
    #define EP8_INT_TRANS_ERR_SHIFT 24
    #define EP9_INT_TRANS_ERR_MASK 0x02000000
    #define EP9_INT_TRANS_ERR_SHIFT 25
    #define EP10_INT_TRANS_ERR_MASK 0x04000000
    #define EP10_INT_TRANS_ERR_SHIFT 26
#define  USBD_MIPS_INT_MASK 0x2418
    #define MIPS_EP0_INT_EN_REG_RD_MASK 0x00000001
    #define MIPS_EP0_INT_EN_REG_RD_SHIFT 0
    #define MIPS_EP0_INT_EN_REG_WR_MASK 0x00000002
    #define MIPS_EP0_INT_EN_REG_WR_SHIFT 1
    #define MIPS_EP0_INT_EN_MEM_RD_MASK 0x00000004
    #define MIPS_EP0_INT_EN_MEM_RD_SHIFT 2
    #define MIPS_EP0_INT_EN_MEM_WR_MASK 0x00000008
    #define MIPS_EP0_INT_EN_MEM_WR_SHIFT 3
    #define MIPS_EP0_INT_EN_GETDEVDES_MASK 0x00000010
    #define MIPS_EP0_INT_EN_GETDEVDES_SHIFT 4
    #define MIPS_EP0_INT_EN_GETCFGDES_MASK 0x00000020
    #define MIPS_EP0_INT_EN_GETCFGDES_SHIFT 5
    #define MIPS_EP0_INT_EN_GETSTRINGDES_MASK 0x00000040
    #define MIPS_EP0_INT_EN_GETSTRINGDES_SHIFT 6
    #define MIPS_EP0_INT_EN_GET_UNK_MASK 0x00000080
    #define MIPS_EP0_INT_EN_GET_UNK_SHIFT 7
    #define MIPS_EP0_INT_EN_SET_UNK_MASK 0x00000100
    #define MIPS_EP0_INT_EN_SET_UNK_SHIFT 8
    #define MIPS_EP0_INT_EN_SUSPEND_MASK 0x00000200
    #define MIPS_EP0_INT_EN_SUSPEND_SHIFT 9
    #define MIPS_EP0_INT_EN_OUT_SUSPEND_MASK 0x00000400
    #define MIPS_EP0_INT_EN_OUT_SUSPEND_SHIFT 10
    #define MIPS_EP1_INT_EN_TRANS_DONE_MASK 0x00000800
    #define MIPS_EP1_INT_EN_TRANS_DONE_SHIFT 11
    #define MIPS_EP2_INT_EN_TRANS_DONE_MASK 0x00001000
    #define MIPS_EP2_INT_EN_TRANS_DONE_SHIFT 12
    #define MIPS_EP3_INT_EN_TRANS_DONE_MASK 0x00002000
    #define MIPS_EP3_INT_EN_TRANS_DONE_SHIFT 13
    #define MIPS_EP4_INT_EN_TRANS_DONE_MASK 0x00004000
    #define MIPS_EP4_INT_EN_TRANS_DONE_SHIFT 14
    #define MIPS_EP5_INT_EN_TRANS_DONE_MASK 0x00008000
    #define MIPS_EP5_INT_EN_TRANS_DONE_SHIFT 15
    #define MIPS_EP6_INT_EN_TRANS_DONE_MASK 0x00010000
    #define MIPS_EP6_INT_EN_TRANS_DONE_SHIFT 16
    #define MIPS_EP7_INT_EN_TRANS_DONE_MASK 0x00020000
    #define MIPS_EP7_INT_EN_TRANS_DONE_SHIFT 17
    #define MIPS_EP8_INT_EN_TRANS_DONE_MASK 0x00040000
    #define MIPS_EP8_INT_EN_TRANS_DONE_SHIFT 18
    #define MIPS_EP9_INT_EN_TRANS_DONE_MASK 0x00080000
    #define MIPS_EP9_INT_EN_TRANS_DONE_SHIFT 19
    #define MIPS_EP10_INT_EN_TRANS_DONE_MASK 0x00100000
    #define MIPS_EP10_INT_EN_TRANS_DONE_SHIFT 20
    #define MIPS_EP2_INT_EN_TRANS_ERR_MASK 0x00200000
    #define MIPS_EP2_INT_EN_TRANS_ERR_SHIFT 21
    #define MIPS_EP4_INT_EN_TRANS_ERR_MASK 0x00400000
    #define MIPS_EP4_INT_EN_TRANS_ERR_SHIFT 22
    #define MIPS_EP6_INT_EN_TRANS_ERR_MASK 0x00800000
    #define MIPS_EP6_INT_EN_TRANS_ERR_SHIFT 23
    #define MIPS_EP8_INT_EN_TRANS_ERR_MASK 0x01000000
    #define MIPS_EP8_INT_EN_TRANS_ERR_SHIFT 24
    #define MIPS_EP9_INT_EN_TRANS_ERR_MASK 0x02000000
    #define MIPS_EP9_INT_EN_TRANS_ERR_SHIFT 25
    #define MIPS_EP10_INT_EN_TRANS_ERR_MASK 0x04000000
    #define MIPS_EP10_INT_EN_TRANS_ERR_SHIFT 26
#define  USBD_PHY_CLK_CTRL 0x242C
    #define PHY_CLK_SEL_MASK 0x00000003
    #define PHY_CLK_SEL_SHIFT 0
    #define PHY_XO_ON_N_MASK 0x00000004
    #define PHY_XO_ON_N_SHIFT 2
    #define PHY_XO_REFCLK_ENB_MASK 0x00000008
    #define PHY_XO_REFCLK_ENB_SHIFT 3
    #define PHY_XO_EXT_CLK_ENBN_MASK 0x00000010
    #define PHY_XO_EXT_CLK_ENBN_SHIFT 4
#define  USBD_PHY_CTRL 0x2430
    #define DETECT_VBUS_0_ENABLE_MASK 0x00000001
    #define DETECT_VBUS_0_ENABLE_SHIFT 0
    #define DETECT_VBUS_1_ENABLE_MASK 0x00000002
    #define DETECT_VBUS_1_ENABLE_SHIFT 1
    #define PHY_PORT0_H_D_MASK 0x00000004
    #define PHY_PORT0_H_D_SHIFT 2
    #define PHY_PORT1_H_D_MASK 0x00000008
    #define PHY_PORT1_H_D_SHIFT 3
    #define PHY_COMMON_ON_N_MASK 0x00000010
    #define PHY_COMMON_ON_N_SHIFT 4
    #define PHY_CLK48M_SEL_MASK 0x00000020
    #define PHY_CLK48M_SEL_SHIFT 5
    #define PHY_TX_ENABLE_N_0_MASK 0x00000040
    #define PHY_TX_ENABLE_N_0_SHIFT 6
    #define PHY_TX_BIT_STUFF_EN_0_MASK 0x00000080
    #define PHY_TX_BIT_STUFF_EN_0_SHIFT 7
    #define PHY_TX_BIT_STUFF_EN_H_0_MASK 0x00000100
    #define PHY_TX_BIT_STUFF_EN_H_0_SHIFT 8
    #define PHY_DM_PULLDOWN_0_MASK 0x00000200
    #define PHY_DM_PULLDOWN_0_SHIFT 9
    #define PHY_DP_PULLDOWN_0_MASK 0x00000400
    #define PHY_DP_PULLDOWN_0_SHIFT 10
    #define PHY_LOOPBACK_ENB_0_MASK 0x00000800
    #define PHY_LOOPBACK_ENB_0_SHIFT 11
    #define PHY_WORD_INTERFACE_0_MASK 0x00001000
    #define PHY_WORD_INTERFACE_0_SHIFT 12
    #define PHY_FS_DATA_EXT_0_MASK 0x00002000
    #define PHY_FS_DATA_EXT_0_SHIFT 13
    #define PHY_FS_SE0_EXT_0_MASK 0x00004000
    #define PHY_FS_SE0_EXT_0_SHIFT 14
    #define PHY_FS_XCVR_OWNER_0_MASK 0x00008000
    #define PHY_FS_XCVR_OWNER_0_SHIFT 15
    #define PHY_TX_ENABLE_N_1_MASK 0x00010000
    #define PHY_TX_ENABLE_N_1_SHIFT 16
    #define PHY_TX_BIT_STUFF_EN_1_MASK 0x00020000
    #define PHY_TX_BIT_STUFF_EN_1_SHIFT 17
    #define PHY_TX_BIT_STUFF_EN_H_1_MASK 0x00040000
    #define PHY_TX_BIT_STUFF_EN_H_1_SHIFT 18
    #define PHY_DM_PULLDOWN_1_MASK 0x00080000
    #define PHY_DM_PULLDOWN_1_SHIFT 19
    #define PHY_DP_PULLDOWN_1_MASK 0x00100000
    #define PHY_DP_PULLDOWN_1_SHIFT 20
    #define PHY_LOOPBACK_ENB_1_MASK 0x00200000
    #define PHY_LOOPBACK_ENB_1_SHIFT 21
    #define PHY_WORD_INTERFACE_1_MASK 0x00400000
    #define PHY_WORD_INTERFACE_1_SHIFT 22
    #define PHY_FS_DATA_EXT_1_MASK 0x00800000
    #define PHY_FS_DATA_EXT_1_SHIFT 23
    #define PHY_FS_SE0_EXT_1_MASK 0x01000000
    #define PHY_FS_SE0_EXT_1_SHIFT 24
    #define PHY_FS_XCVR_OWNER_1_MASK 0x02000000
    #define PHY_FS_XCVR_OWNER_1_SHIFT 25
    #define PHY_TX_TUNE_0_MASK 0x0C000000
    #define PHY_TX_TUNE_0_SHIFT 26
    #define PHY_TX_TUNE_1_MASK 0x30000000
    #define PHY_TX_TUNE_1_SHIFT 28
    #define PHY_PORT_RESET_0_MASK 0x40000000
    #define PHY_PORT_RESET_0_SHIFT 30
    #define PHY_PORT_RESET_1_MASK 0x80000000
    #define PHY_PORT_RESET_1_SHIFT 31
#define  USBD_PHY_TEST 0x2434
    #define PHY_TEST_DATA_IN_MASK 0x000000FF
    #define PHY_TEST_DATA_IN_SHIFT 0
    #define PHY_TEST_ADDR_MASK 0x00000F00
    #define PHY_TEST_ADDR_SHIFT 8
    #define PHY_TEST_DATA_OUT_SEL_MASK 0x00001000
    #define PHY_TEST_DATA_OUT_SEL_SHIFT 12
    #define PHY_TEST_CLK_ENABLE_MASK 0x00002000
    #define PHY_TEST_CLK_ENABLE_SHIFT 13
    #define PHY_DEV_PORT0_OPMODE_MASK 0x0000C000
    #define PHY_DEV_PORT0_OPMODE_SHIFT 14
    #define PHY_DEV_PORT0_XVER_SEL_MASK 0x00030000
    #define PHY_DEV_PORT0_XVER_SEL_SHIFT 16
    #define PHY_DEV_PORT0_TERM_SEL_MASK 0x00040000
    #define PHY_DEV_PORT0_TERM_SEL_SHIFT 18
    #define PHY_DEV_PORT0_SUSPENDN_MASK 0x00080000
    #define PHY_DEV_PORT0_SUSPENDN_SHIFT 19
    #define PHY_DP_PULLUP_ESD_MASK 0x00100000
    #define PHY_DP_PULLUP_ESD_SHIFT 20
    #define PHY_WEAK_PULLDOWN_EN_MASK 0x00200000
    #define PHY_WEAK_PULLDOWN_EN_SHIFT 21
    #define PHY_ESD_TEST_MODE_MASK 0x00400000
    #define PHY_ESD_TEST_MODE_SHIFT 22
#define  USBD_SOFT_RST 0x243C
    #define PHY_SOFT_RST_MASK 0x00000001
    #define PHY_SOFT_RST_SHIFT 0
    #define UDC20_SOFT_RST_MASK 0x00000002
    #define UDC20_SOFT_RST_SHIFT 1
    #define EP0_SOFT_RST_MASK 0x00000004
    #define EP0_SOFT_RST_SHIFT 2
    #define EP1_SOFT_RST_MASK 0x00000008
    #define EP1_SOFT_RST_SHIFT 3
    #define EP2_SOFT_RST_MASK 0x00000010
    #define EP2_SOFT_RST_SHIFT 4
    #define EP3_SOFT_RST_MASK 0x00000020
    #define EP3_SOFT_RST_SHIFT 5
    #define EP4_SOFT_RST_MASK 0x00000040
    #define EP4_SOFT_RST_SHIFT 6
    #define EP5_SOFT_RST_MASK 0x00000080
    #define EP5_SOFT_RST_SHIFT 7
    #define EP6_SOFT_RST_MASK 0x00000100
    #define EP6_SOFT_RST_SHIFT 8
    #define EP7_SOFT_RST_MASK 0x00000200
    #define EP7_SOFT_RST_SHIFT 9
    #define EP8_SOFT_RST_MASK 0x00000400
    #define EP8_SOFT_RST_SHIFT 10
    #define EP9_SOFT_RST_MASK 0x00000800
    #define EP9_SOFT_RST_SHIFT 11
    #define EP10_SOFT_RST_MASK 0x00001000
    #define EP10_SOFT_RST_SHIFT 12
    #define VCIF_SOFT_RST_MASK 0x00002000
    #define VCIF_SOFT_RST_SHIFT 13
    #define ARB_SOFT_RST_MASK 0x00004000
    #define ARB_SOFT_RST_SHIFT 14
#define  USBD_UDC20_CTRL 0x2420
    #define APP_EXP_SPEED_MASK 0x00000003
    #define APP_EXP_SPEED_SHIFT 0
    #define APP_PHYIF_8BIT_MASK 0x00000004
    #define APP_PHYIF_8BIT_SHIFT 2
    #define APP_SELF_PWR_MASK 0x00000008
    #define APP_SELF_PWR_SHIFT 3
    #define APP_SYNCCMD_SUP_MASK 0x00000010
    #define APP_SYNCCMD_SUP_SHIFT 4
    #define APP_SETDESC_SUP_MASK 0x00000020
    #define APP_SETDESC_SUP_SHIFT 5
    #define APP_DEV_RMTWKUP_MASK 0x00000040
    #define APP_DEV_RMTWKUP_SHIFT 6
    #define APP_RAM_IF_MASK 0x00000080
    #define APP_RAM_IF_SHIFT 7
    #define APP_TAT_RESP_MASK 0x00000100
    #define APP_TAT_RESP_SHIFT 8
    #define APP_CSRPRG_SUP_MASK 0x00000200
    #define APP_CSRPRG_SUP_SHIFT 9
    #define APP_RESUME_MASK 0x00000400
    #define APP_RESUME_SHIFT 10
    #define APP_STALL_MASK 0x00000800
    #define APP_STALL_SHIFT 11
    #define APP_DONE_CSR_MASK 0x00001000
    #define APP_DONE_CSR_SHIFT 12
    #define APP_DEV_DISCON_MASK 0x00002000
    #define APP_DEV_DISCON_SHIFT 13
    #define APP_SCALE_DOWN_MASK 0x00004000
    #define APP_SCALE_DOWN_SHIFT 14
    #define APP_NZ_LEN_PKT_STALL_MASK 0x00008000
    #define APP_NZ_LEN_PKT_STALL_SHIFT 15
    #define APP_NZ_LEN_PKT_STALL_ALL_MASK 0x00010000
    #define APP_NZ_LEN_PKT_STALL_ALL_SHIFT 16
    #define APP_ENABLE_ERRATIC_ERR_MASK 0x00020000
    #define APP_ENABLE_ERRATIC_ERR_SHIFT 17
    #define APP_STALL_CLR_EP0_HALT_MASK 0x00040000
    #define APP_STALL_CLR_EP0_HALT_SHIFT 18
    #define HS_TIMEOUT_CALIB_MASK 0x00380000
    #define HS_TIMEOUT_CALIB_SHIFT 19
    #define FS_TIMEOUT_CALIB_MASK 0x01C00000
    #define FS_TIMEOUT_CALIB_SHIFT 22
    #define SOFT_DISCON_SEL_MASK 0x10000000
    #define SOFT_DISCON_SEL_SHIFT 28
    #define SOFT_DISCON_TRIG_MASK 0x20000000
    #define SOFT_DISCON_TRIG_SHIFT 29
    #define PHY_SUSPEND_ENABLE_MASK 0x40000000
    #define PHY_SUSPEND_ENABLE_SHIFT 30
#define  USBD_UDC20_STATUS0 0x2424
    #define UDC20_EARLY_SUSPEND_MASK 0x00000001
    #define UDC20_EARLY_SUSPEND_SHIFT 0
    #define UDC20_SUSPEND_MASK 0x00000002
    #define UDC20_SUSPEND_SHIFT 1
    #define UDC20_USBRESET_MASK 0x00000004
    #define UDC20_USBRESET_SHIFT 2
    #define UDC20_CFG_MASK 0x00000078
    #define UDC20_CFG_SHIFT 3
    #define UDC20_INTF_MASK 0x00000780
    #define UDC20_INTF_SHIFT 7
    #define UDC20_ALTINTF_MASK 0x00007800
    #define UDC20_ALTINTF_SHIFT 11
    #define UDC20_HST_SETCFG_MASK 0x00008000
    #define UDC20_HST_SETCFG_SHIFT 15
    #define UDC20_HST_SETINTF_MASK 0x00010000
    #define UDC20_HST_SETINTF_SHIFT 16
    #define UDC20_ENUM_SPEED_MASK 0x00060000
    #define UDC20_ENUM_SPEED_SHIFT 17
    #define UDC20_ENUMON_MASK 0x00080000
    #define UDC20_ENUMON_SHIFT 19
    #define UDC20_SETCSRS_MASK 0x00100000
    #define UDC20_SETCSRS_SHIFT 20
    #define UDC20_ERRATIC_ERR_MASK 0x00200000
    #define UDC20_ERRATIC_ERR_SHIFT 21
    #define UDC20_PHYMODE_MASK 0x00C00000
    #define UDC20_PHYMODE_SHIFT 22
#define  USBD_UDC20_STATUS1 0x2428
    #define UDC20_SETUP_MASK 0x00000001
    #define UDC20_SETUP_SHIFT 0
    #define UDC20_SOF_MASK 0x00000002
    #define UDC20_SOF_SHIFT 1
    #define UDC20_TIMESTAMP_MASK 0x00001FFC
    #define UDC20_TIMESTAMP_SHIFT 2
    #define UDC20_UFRAME_NUM_MASK 0x0000E000
    #define UDC20_UFRAME_NUM_SHIFT 13
    #define PHY_TEST_DATA_OUT_0_MASK 0x000F0000
    #define PHY_TEST_DATA_OUT_0_SHIFT 16
    #define PHY_TEST_DATA_OUT_1_MASK 0x00F00000
    #define PHY_TEST_DATA_OUT_1_SHIFT 20
#define  USBH_CSR_STATUS_REG 0x2000
    #define USBH_CSR_BUSY_MASK 0x00000001
    #define USBH_CSR_BUSY_SHIFT 0
    #define USBH_CSR_ERR_MASK 0x00000002
    #define USBH_CSR_ERR_SHIFT 1
#define  USBH_CTRL_REG 0x2020
    #define MEM_BRIDGE_HALT_MASK 0x00000001
    #define MEM_BRIDGE_HALT_SHIFT 0
    #define SDUH_INT_MASK 0x00000002
    #define SDUH_INT_SHIFT 1
    #define USBH_CTRL_REG_SOFT_RESET_MASK 0x00000004
    #define USBH_CTRL_REG_SOFT_RESET_SHIFT 2
    #define USBH_CTRL_REG_EXT_MEM_ARB_TIMER_MASK 0x000000F0
    #define USBH_CTRL_REG_EXT_MEM_ARB_TIMER_SHIFT 4
    #define OHCI_12_STOP_MASK 0x00000100
    #define OHCI_12_STOP_SHIFT 8
    #define OHCI_48_STOP_MASK 0x00000200
    #define OHCI_48_STOP_SHIFT 9
    #define TSM_WR_MAX_WAIT_MASK 0x003F0000
    #define TSM_WR_MAX_WAIT_SHIFT 16
#define  USBH_DUMMY_REG 0x203C
    #define USBH_DUMMY_REG_DATA_MASK 0xFFFFFFFF
    #define USBH_DUMMY_REG_DATA_SHIFT 0
#define  USBH_EHCI_CSR_CTRL_REG 0x2004
    #define USBH_EHCI_CSR_CTRL_REG_ADDR_MASK 0x000000FC
    #define USBH_EHCI_CSR_CTRL_REG_ADDR_SHIFT 2
    #define USBH_EHCI_CSR_CTRL_REG_WOP_MASK 0x80000000
    #define USBH_EHCI_CSR_CTRL_REG_WOP_SHIFT 31
#define  USBH_HOST_INT_MASK 0x2034
    #define USBH_HOST_INT_MASK_EHCI_INT_STATUS_EN_MASK 0x00000002
    #define USBH_HOST_INT_MASK_EHCI_INT_STATUS_EN_SHIFT 1
    #define USBH_HOST_INT_MASK_OHCI_INT_STATUS_EN_MASK 0x00000004
    #define USBH_HOST_INT_MASK_OHCI_INT_STATUS_EN_SHIFT 2
    #define USBH_HOST_INT_MASK_OHCI_BRIDGE_INT_EN_MASK 0x00000008
    #define USBH_HOST_INT_MASK_OHCI_BRIDGE_INT_EN_SHIFT 3
#define  USBH_MIPS_INT_MASK 0x2038
    #define USBH_MIPS_INT_MASK_EHCI_INT_STATUS_EN_MASK 0x00000002
    #define USBH_MIPS_INT_MASK_EHCI_INT_STATUS_EN_SHIFT 1
    #define USBH_MIPS_INT_MASK_OHCI_INT_STATUS_EN_MASK 0x00000004
    #define USBH_MIPS_INT_MASK_OHCI_INT_STATUS_EN_SHIFT 2
    #define USBH_MIPS_INT_MASK_OHCI_BRIDGE_INT_EN_MASK 0x00000008
    #define USBH_MIPS_INT_MASK_OHCI_BRIDGE_INT_EN_SHIFT 3
#define  USBH_OHCI_INT_EN_REG 0x2028
    #define RMTWKP_EN_MASK 0x00000001
    #define RMTWKP_EN_SHIFT 0
    #define SOF_EN_MASK 0x00000002
    #define SOF_EN_SHIFT 1
    #define GLOBALSUSPEND_EN_MASK 0x00000004
    #define GLOBALSUSPEND_EN_SHIFT 2
    #define DRWE_EN_MASK 0x00000008
    #define DRWE_EN_SHIFT 3
    #define RWE_EN_MASK 0x00000010
    #define RWE_EN_SHIFT 4
    #define CCS_EN_PORT0_MASK 0x00000020
    #define CCS_EN_PORT0_SHIFT 5
    #define CCS_EN_PORT1_MASK 0x00000040
    #define CCS_EN_PORT1_SHIFT 6
#define  USBH_OHCI_OP_CSR_CTRL_REG 0x200C
    #define USBH_OHCI_OP_CSR_CTRL_REG_ADDR_MASK 0x0000007C
    #define USBH_OHCI_OP_CSR_CTRL_REG_ADDR_SHIFT 2
    #define USBH_OHCI_OP_CSR_CTRL_REG_WOP_MASK 0x80000000
    #define USBH_OHCI_OP_CSR_CTRL_REG_WOP_SHIFT 31
#define  USBH_OHCI_STATUS_REG 0x2024
    #define RMTWKP_MASK 0x00000001
    #define RMTWKP_SHIFT 0
    #define SOF_MASK 0x00000002
    #define SOF_SHIFT 1
    #define GLOBALSUSPEND_MASK 0x00000004
    #define GLOBALSUSPEND_SHIFT 2
    #define DRWE_MASK 0x00000008
    #define DRWE_SHIFT 3
    #define RWE_MASK 0x00000010
    #define RWE_SHIFT 4
    #define CCS_PORT0_MASK 0x00000020
    #define CCS_PORT0_SHIFT 5
    #define CCS_PORT1_MASK 0x00000040
    #define CCS_PORT1_SHIFT 6
#define  USBH_OHCI_TRANS_CTRL_REG 0x2018
    #define MAX_TRANS_MASK 0x000003FF
    #define MAX_TRANS_SHIFT 0
    #define MAX_WAIT_MASK 0xFFFF0000
    #define MAX_WAIT_SHIFT 16
#define  USBH_PHY_CTRL_REG 0x2030
    #define USBH_PHY_TUNE_TX_0_MASK 0x00000003
    #define USBH_PHY_TUNE_TX_0_SHIFT 0
    #define USBH_PHY_TUNE_TX_1_MASK 0x0000000C
    #define USBH_PHY_TUNE_TX_1_SHIFT 2
    #define USBH_PHY_POR_MASK 0x00000010
    #define USBH_PHY_POR_SHIFT 4
    #define USBH_PHY_COMMON_ON_N_MASK 0x00000020
    #define USBH_PHY_COMMON_ON_N_SHIFT 5
    #define USBH_PHY_CLK48M_SEL_MASK 0x00000040
    #define USBH_PHY_CLK48M_SEL_SHIFT 6
    #define USBH_PHY_TX_BIT_STUFF_EN_0_MASK 0x00002000
    #define USBH_PHY_TX_BIT_STUFF_EN_0_SHIFT 13
    #define USBH_PHY_TX_BIT_STUFF_EN_H_0_MASK 0x00004000
    #define USBH_PHY_TX_BIT_STUFF_EN_H_0_SHIFT 14
    #define USBH_PHY_DM_PULLDOWN_0_MASK 0x00008000
    #define USBH_PHY_DM_PULLDOWN_0_SHIFT 15
    #define USBH_PHY_DP_PULLDOWN_0_MASK 0x00010000
    #define USBH_PHY_DP_PULLDOWN_0_SHIFT 16
    #define USBH_PHY_LOOPBACK_ENB_0_MASK 0x00020000
    #define USBH_PHY_LOOPBACK_ENB_0_SHIFT 17
    #define USBH_PHY_WORD_INTERFACE_0_MASK 0x00040000
    #define USBH_PHY_WORD_INTERFACE_0_SHIFT 18
    #define USBH_PHY_TX_BIT_STUFF_EN_1_MASK 0x00800000
    #define USBH_PHY_TX_BIT_STUFF_EN_1_SHIFT 23
    #define USBH_PHY_TX_BIT_STUFF_EN_H_1_MASK 0x01000000
    #define USBH_PHY_TX_BIT_STUFF_EN_H_1_SHIFT 24
    #define USBH_PHY_DM_PULLDOWN_1_MASK 0x02000000
    #define USBH_PHY_DM_PULLDOWN_1_SHIFT 25
    #define USBH_PHY_DP_PULLDOWN_1_MASK 0x04000000
    #define USBH_PHY_DP_PULLDOWN_1_SHIFT 26
    #define USBH_PHY_LOOPBACK_ENB_1_MASK 0x08000000
    #define USBH_PHY_LOOPBACK_ENB_1_SHIFT 27
    #define USBH_PHY_WORD_INTERFACE_1_MASK 0x10000000
    #define USBH_PHY_WORD_INTERFACE_1_SHIFT 28
    #define USBH_PHY_PORT_RESET_0_MASK 0x20000000
    #define USBH_PHY_PORT_RESET_0_SHIFT 29
    #define USBH_PHY_PORT_RESET_1_MASK 0x40000000
    #define USBH_PHY_PORT_RESET_1_SHIFT 30
#define  USBH_RDAT_REG 0x2014
    #define USBH_RDAT_MASK 0xFFFFFFFF
    #define USBH_RDAT_SHIFT 0
#define  USBH_STATUS_REG 0x201C
    #define MEM_BRIDGE_IDLE_MASK 0x00000001
    #define MEM_BRIDGE_IDLE_SHIFT 0
    #define EHCI_INT_STATUS_MASK 0x00000002
    #define EHCI_INT_STATUS_SHIFT 1
    #define OHCI_INT_STATUS_MASK 0x00000004
    #define OHCI_INT_STATUS_SHIFT 2
    #define OHCI_BRIDGE_INT_MASK 0x00000008
    #define OHCI_BRIDGE_INT_SHIFT 3
    #define EHCI_USB_STATUS_MASK 0x003F0000
    #define EHCI_USB_STATUS_SHIFT 16
    #define EHCI_LPSMC_STATE_MASK 0x03C00000
    #define EHCI_LPSMC_STATE_SHIFT 22
#define  USBH_STRAPS_AND_CFG_REG 0x202C
    #define FLADJ_VAL_HOST_MASK 0x0000003F
    #define FLADJ_VAL_HOST_SHIFT 0
    #define AUTOPPD_ON_OVERCUR_EN_MASK 0x00000040
    #define AUTOPPD_ON_OVERCUR_EN_SHIFT 6
    #define APP_PRT_OVRCUR_PORT0_MASK 0x00000080
    #define APP_PRT_OVRCUR_PORT0_SHIFT 7
    #define APP_PRT_OVRCUR_PORT1_MASK 0x00000100
    #define APP_PRT_OVRCUR_PORT1_SHIFT 8
    #define EHCI_PRT_PWR0_12MHZ_EN_MASK 0x00000200
    #define EHCI_PRT_PWR0_12MHZ_EN_SHIFT 9
    #define EHCI_PRT_PWR0_60MHZ_EN_MASK 0x00000400
    #define EHCI_PRT_PWR0_60MHZ_EN_SHIFT 10
    #define EHCI_PRT_PWR1_12MHZ_EN_MASK 0x00000800
    #define EHCI_PRT_PWR1_12MHZ_EN_SHIFT 11
    #define EHCI_PRT_PWR1_60MHZ_EN_MASK 0x00001000
    #define EHCI_PRT_PWR1_60MHZ_EN_SHIFT 12
    #define UTMI_BACKWARD_ENB_MASK 0x00002000
    #define UTMI_BACKWARD_ENB_SHIFT 13
    #define RESUME_UTMI_PLS_DIS_MASK 0x00004000
    #define RESUME_UTMI_PLS_DIS_SHIFT 14
#define  USBH_TEST_CONTROL 0x2040
    #define TEST_DATA_OUT_SEL_MASK 0x00000001
    #define TEST_DATA_OUT_SEL_SHIFT 0
    #define TEST_ADDR_MASK 0x000000F0
    #define TEST_ADDR_SHIFT 4
    #define TEST_DATA_IN_MASK 0x0000FF00
    #define TEST_DATA_IN_SHIFT 8
#define  USBH_TEST_DATA_OUT 0x2044
    #define TEST_DATA_OUT_0_MASK 0x0000000F
    #define TEST_DATA_OUT_0_SHIFT 0
    #define TEST_DATA_OUT_1_MASK 0x000000F0
    #define TEST_DATA_OUT_1_SHIFT 4
#define  USBH_WDAT_REG 0x2010
    #define USBH_WDAT_MASK 0xFFFFFFFF
    #define USBH_WDAT_SHIFT 0
#define  VFE0_ACTIVITY_ADR 0x5528
    #define VFE0_ACTIVITY_ADR_BASE_MASK 0x07FFFFC0
    #define VFE0_ACTIVITY_ADR_BASE_SHIFT 6
#define  VFE0_ACTIVITY_DIV 0x5520
    #define VFE0_ACTIVITY_DIV_VALUE_MASK 0x0000FFFF
    #define VFE0_ACTIVITY_DIV_VALUE_SHIFT 0
#define  VFE0_ACTIVITY_SIZE 0x5524
    #define VFE0_ACTIVITY_SIZE_BUF_SIZE_MASK 0x0000FFF0
    #define VFE0_ACTIVITY_SIZE_BUF_SIZE_SHIFT 4
    #define VFE0_ACTIVITY_SIZE_OUTPUT_MODE_MASK 0x00030000
    #define VFE0_ACTIVITY_SIZE_OUTPUT_MODE_SHIFT 16
#define  VFE0_CR_WR_ADR 0x5624
    #define VFE0_CR_WR_ADR_BASE_MASK 0x07FFE000
    #define VFE0_CR_WR_ADR_BASE_SHIFT 13
#define  VFE0_CTRL 0x5500
    #define VFE0_CTRL_BUF_CNT_MASK 0x0000003F
    #define VFE0_CTRL_BUF_CNT_SHIFT 0
    #define VFE0_CTRL_MODE_MASK 0x00000300
    #define VFE0_CTRL_MODE_SHIFT 8
    #define VFE0_CTRL_HS_ENABLE_MASK 0x00001000
    #define VFE0_CTRL_HS_ENABLE_SHIFT 12
    #define VFE0_CTRL_OUT_MEM_TILE_MASK 0x00002000
    #define VFE0_CTRL_OUT_MEM_TILE_SHIFT 13
    #define VFE0_CTRL_RD_SLICE_CNT_MASK 0x007F0000
    #define VFE0_CTRL_RD_SLICE_CNT_SHIFT 16
    #define VFE0_CTRL_VS_TRUNCATE_MASK 0x00800000
    #define VFE0_CTRL_VS_TRUNCATE_SHIFT 23
    #define VFE0_CTRL_8_BIT_MODE_MASK 0x01000000
    #define VFE0_CTRL_8_BIT_MODE_SHIFT 24
    #define VFE0_CTRL_8_BIT_APPEND_MASK 0x06000000
    #define VFE0_CTRL_8_BIT_APPEND_SHIFT 25
    #define VFE0_CTRL_HS_ROUND_MASK 0x08000000
    #define VFE0_CTRL_HS_ROUND_SHIFT 27
    #define VFE0_CTRL_OUTPUT_IDX_EN_MASK 0x10000000
    #define VFE0_CTRL_OUTPUT_IDX_EN_SHIFT 28
    #define VFE0_CTRL_MEM_TILE_MASK 0x20000000
    #define VFE0_CTRL_MEM_TILE_SHIFT 29
    #define VFE0_CTRL_DROP_FLD_MASK 0x40000000
    #define VFE0_CTRL_DROP_FLD_SHIFT 30
    #define VFE0_CTRL_420_CBCR_MASK 0x80000000
    #define VFE0_CTRL_420_CBCR_SHIFT 31
#define  VFE0_C_WR_ADR 0x551C
    #define VFE0_C_WR_ADR_BASE_MASK 0x07FFE000
    #define VFE0_C_WR_ADR_BASE_SHIFT 13
#define  VFE0_FLTR_CTRL 0x5530
    #define VFE0_FLTR_CTRL_EDGE_THRES_MASK 0x001FFFFF
    #define VFE0_FLTR_CTRL_EDGE_THRES_SHIFT 0
    #define VFE0_FLTR_CTRL_FLTR_SET_MASK 0x60000000
    #define VFE0_FLTR_CTRL_FLTR_SET_SHIFT 29
    #define VFE0_FLTR_CTRL_FLTR_EN_MASK 0x80000000
    #define VFE0_FLTR_CTRL_FLTR_EN_SHIFT 31
#define  VFE0_FLTR_SET 0x552C
    #define VFE0_FLTR_SET_DATA_MASK 0x7FFFFFFF
    #define VFE0_FLTR_SET_DATA_SHIFT 0
#define  VFE0_RD_ADR 0x5514
    #define VFE0_RD_ADR_BASE_MASK 0x07FFFFC0
    #define VFE0_RD_ADR_BASE_SHIFT 6
#define  VFE0_RD_BUF 0x550C
    #define VFE0_RD_BUF_PITCH_MASK 0x00000FF0
    #define VFE0_RD_BUF_PITCH_SHIFT 4
    #define VFE0_RD_BUF_SIZE_MASK 0xFFFF0000
    #define VFE0_RD_BUF_SIZE_SHIFT 16
#define  VFE0_RD_CB_ADR 0x5534
    #define VFE0_RD_CB_ADR_BASE_MASK 0x07FFFFC0
    #define VFE0_RD_CB_ADR_BASE_SHIFT 6
#define  VFE0_RD_CR_ADR 0x5538
    #define VFE0_RD_CR_ADR_BASE_MASK 0x07FFFFC0
    #define VFE0_RD_CR_ADR_BASE_SHIFT 6
#define  VFE0_RD_INFO_ADR 0x5504
    #define VFE0_RD_INFO_ADR_BASE_MASK 0x07FFFFC0
    #define VFE0_RD_INFO_ADR_BASE_SHIFT 6
#define  VFE0_SCL_CTRL_A 0x5618
    #define VFE0_SCL_CTRL_A_PHASES_MASK 0x0000001F
    #define VFE0_SCL_CTRL_A_PHASES_SHIFT 0
    #define VFE0_SCL_CTRL_A_SRC_RES_MASK 0x00007F00
    #define VFE0_SCL_CTRL_A_SRC_RES_SHIFT 8
    #define VFE0_SCL_CTRL_A_DST_RES_MASK 0x007F0000
    #define VFE0_SCL_CTRL_A_DST_RES_SHIFT 16
    #define VFE0_SCL_CTRL_A_DST_WIDTH_UPPER_MASK 0x00800000
    #define VFE0_SCL_CTRL_A_DST_WIDTH_UPPER_SHIFT 23
    #define VFE0_SCL_CTRL_A_IDX_SHIFT_MASK 0x03000000
    #define VFE0_SCL_CTRL_A_IDX_SHIFT_SHIFT 24
    #define VFE0_SCL_CTRL_A_DST_WIDTH_MASK 0xFC000000
    #define VFE0_SCL_CTRL_A_DST_WIDTH_SHIFT 26
#define  VFE0_WR_BUF 0x5510
    #define VFE0_WR_BUF_PITCH_MASK 0x00000FF0
    #define VFE0_WR_BUF_PITCH_SHIFT 4
    #define VFE0_WR_BUF_SIZE_Y_MASK 0x001FF000
    #define VFE0_WR_BUF_SIZE_Y_SHIFT 12
    #define VFE0_WR_BUF_SIZE_C_MASK 0xFF000000
    #define VFE0_WR_BUF_SIZE_C_SHIFT 24
#define  VFE0_WR_INFO_ADR 0x5508
    #define VFE0_WR_INFO_ADR_BASE_MASK 0x07FFFFC0
    #define VFE0_WR_INFO_ADR_BASE_SHIFT 6
#define  VFE0_Y_WR_ADR 0x5518
    #define VFE0_Y_WR_ADR_BASE_MASK 0x07FFE000
    #define VFE0_Y_WR_ADR_BASE_SHIFT 13
#define  VFE1_ACTIVITY_ADR 0x5568
    #define VFE1_ACTIVITY_ADR_BASE_MASK 0x07FFFFC0
    #define VFE1_ACTIVITY_ADR_BASE_SHIFT 6
#define  VFE1_ACTIVITY_DIV 0x5560
    #define VFE1_ACTIVITY_DIV_VALUE_MASK 0x0000FFFF
    #define VFE1_ACTIVITY_DIV_VALUE_SHIFT 0
#define  VFE1_ACTIVITY_SIZE 0x5564
    #define VFE1_ACTIVITY_SIZE_BUF_SIZE_MASK 0x0000FFF0
    #define VFE1_ACTIVITY_SIZE_BUF_SIZE_SHIFT 4
    #define VFE1_ACTIVITY_SIZE_OUTPUT_MODE_MASK 0x00030000
    #define VFE1_ACTIVITY_SIZE_OUTPUT_MODE_SHIFT 16
#define  VFE1_CR_WR_ADR 0x5628
    #define VFE1_CR_WR_ADR_BASE_MASK 0x07FFE000
    #define VFE1_CR_WR_ADR_BASE_SHIFT 13
#define  VFE1_CTRL 0x5540
    #define VFE1_CTRL_BUF_CNT_MASK 0x0000003F
    #define VFE1_CTRL_BUF_CNT_SHIFT 0
    #define VFE1_CTRL_MODE_MASK 0x00000300
    #define VFE1_CTRL_MODE_SHIFT 8
    #define VFE1_CTRL_HS_ENABLE_MASK 0x00001000
    #define VFE1_CTRL_HS_ENABLE_SHIFT 12
    #define VFE1_CTRL_OUT_MEM_TILE_MASK 0x00002000
    #define VFE1_CTRL_OUT_MEM_TILE_SHIFT 13
    #define VFE1_CTRL_RD_SLICE_CNT_MASK 0x007F0000
    #define VFE1_CTRL_RD_SLICE_CNT_SHIFT 16
    #define VFE1_CTRL_VS_TRUNCATE_MASK 0x00800000
    #define VFE1_CTRL_VS_TRUNCATE_SHIFT 23
    #define VFE1_CTRL_8_BIT_MODE_MASK 0x01000000
    #define VFE1_CTRL_8_BIT_MODE_SHIFT 24
    #define VFE1_CTRL_8_BIT_APPEND_MASK 0x06000000
    #define VFE1_CTRL_8_BIT_APPEND_SHIFT 25
    #define VFE1_CTRL_HS_ROUND_MASK 0x08000000
    #define VFE1_CTRL_HS_ROUND_SHIFT 27
    #define VFE1_CTRL_OUTPUT_IDX_EN_MASK 0x10000000
    #define VFE1_CTRL_OUTPUT_IDX_EN_SHIFT 28
    #define VFE1_CTRL_MEM_TILE_MASK 0x20000000
    #define VFE1_CTRL_MEM_TILE_SHIFT 29
    #define VFE1_CTRL_DROP_FLD_MASK 0x40000000
    #define VFE1_CTRL_DROP_FLD_SHIFT 30
    #define VFE1_CTRL_420_CBCR_MASK 0x80000000
    #define VFE1_CTRL_420_CBCR_SHIFT 31
#define  VFE1_C_WR_ADR 0x555C
    #define VFE1_C_WR_ADR_BASE_MASK 0x07FFE000
    #define VFE1_C_WR_ADR_BASE_SHIFT 13
#define  VFE1_FLTR_CTRL 0x5570
    #define VFE1_FLTR_CTRL_EDGE_THRES_MASK 0x001FFFFF
    #define VFE1_FLTR_CTRL_EDGE_THRES_SHIFT 0
    #define VFE1_FLTR_CTRL_FLTR_SET_MASK 0x60000000
    #define VFE1_FLTR_CTRL_FLTR_SET_SHIFT 29
    #define VFE1_FLTR_CTRL_FLTR_EN_MASK 0x80000000
    #define VFE1_FLTR_CTRL_FLTR_EN_SHIFT 31
#define  VFE1_FLTR_SET 0x556C
    #define VFE1_FLTR_SET_DATA_MASK 0x7FFFFFFF
    #define VFE1_FLTR_SET_DATA_SHIFT 0
#define  VFE1_RD_ADR 0x5554
    #define VFE1_RD_ADR_BASE_MASK 0x07FFFFC0
    #define VFE1_RD_ADR_BASE_SHIFT 6
#define  VFE1_RD_BUF 0x554C
    #define VFE1_RD_BUF_PITCH_MASK 0x00000FF0
    #define VFE1_RD_BUF_PITCH_SHIFT 4
    #define VFE1_RD_BUF_SIZE_MASK 0xFFFF0000
    #define VFE1_RD_BUF_SIZE_SHIFT 16
#define  VFE1_RD_CB_ADR 0x5574
    #define VFE1_RD_CB_ADR_BASE_MASK 0x07FFFFC0
    #define VFE1_RD_CB_ADR_BASE_SHIFT 6
#define  VFE1_RD_CR_ADR 0x5578
    #define VFE1_RD_CR_ADR_BASE_MASK 0x07FFFFC0
    #define VFE1_RD_CR_ADR_BASE_SHIFT 6
#define  VFE1_RD_INFO_ADR 0x5544
    #define VFE1_RD_INFO_ADR_BASE_MASK 0x07FFFFC0
    #define VFE1_RD_INFO_ADR_BASE_SHIFT 6
#define  VFE1_SCL_CTRL_A 0x5620
    #define VFE1_SCL_CTRL_A_PHASES_MASK 0x0000001F
    #define VFE1_SCL_CTRL_A_PHASES_SHIFT 0
    #define VFE1_SCL_CTRL_A_SRC_RES_MASK 0x00007F00
    #define VFE1_SCL_CTRL_A_SRC_RES_SHIFT 8
    #define VFE1_SCL_CTRL_A_DST_RES_MASK 0x007F0000
    #define VFE1_SCL_CTRL_A_DST_RES_SHIFT 16
    #define VFE1_SCL_CTRL_A_DST_WIDTH_UPPER_MASK 0x00800000
    #define VFE1_SCL_CTRL_A_DST_WIDTH_UPPER_SHIFT 23
    #define VFE1_SCL_CTRL_A_IDX_SHIFT_MASK 0x03000000
    #define VFE1_SCL_CTRL_A_IDX_SHIFT_SHIFT 24
    #define VFE1_SCL_CTRL_A_DST_WIDTH_MASK 0xFC000000
    #define VFE1_SCL_CTRL_A_DST_WIDTH_SHIFT 26
#define  VFE1_WR_BUF 0x5550
    #define VFE1_WR_BUF_PITCH_MASK 0x00000FF0
    #define VFE1_WR_BUF_PITCH_SHIFT 4
    #define VFE1_WR_BUF_SIZE_Y_MASK 0x001FF000
    #define VFE1_WR_BUF_SIZE_Y_SHIFT 12
    #define VFE1_WR_BUF_SIZE_C_MASK 0xFF000000
    #define VFE1_WR_BUF_SIZE_C_SHIFT 24
#define  VFE1_WR_INFO_ADR 0x5548
    #define VFE1_WR_INFO_ADR_BASE_MASK 0x07FFFFC0
    #define VFE1_WR_INFO_ADR_BASE_SHIFT 6
#define  VFE1_Y_WR_ADR 0x5558
    #define VFE1_Y_WR_ADR_BASE_MASK 0x07FFE000
    #define VFE1_Y_WR_ADR_BASE_SHIFT 13
#define  VFE2_FLTR_SET 0x55AC
    #define VFE2_FLTR_SET_DATA_MASK 0x7FFFFFFF
    #define VFE2_FLTR_SET_DATA_SHIFT 0
#define  VFE3_FLTR_SET 0x55EC
    #define VFE3_FLTR_SET_DATA_MASK 0x7FFFFFFF
    #define VFE3_FLTR_SET_DATA_SHIFT 0
#define  VFE_APPEND_DATA 0x5434
    #define VFE_APPEND_DATA_Y_VAL_MASK 0x000000FF
    #define VFE_APPEND_DATA_Y_VAL_SHIFT 0
    #define VFE_APPEND_DATA_CB_VAL_MASK 0x0000FF00
    #define VFE_APPEND_DATA_CB_VAL_SHIFT 8
    #define VFE_APPEND_DATA_CR_VAL_MASK 0x00FF0000
    #define VFE_APPEND_DATA_CR_VAL_SHIFT 16
#define  VFE_BLEND_DATA 0x541C
    #define EDGE0_THRES_MASK 0x0000000F
    #define EDGE0_THRES_SHIFT 0
    #define EDGE1_THRES_MASK 0x000000F0
    #define EDGE1_THRES_SHIFT 4
    #define EDGE2_THRES_MASK 0x00000F00
    #define EDGE2_THRES_SHIFT 8
    #define EDGE3_THRES_MASK 0x0000F000
    #define EDGE3_THRES_SHIFT 12
#define  VFE_DUMMY_REG 0x542C
    #define VFE_DUMMY_REG_DUMMY_BITS_MASK 0xFFFFFFFF
    #define VFE_DUMMY_REG_DUMMY_BITS_SHIFT 0
#define  VFE_FIFO_CMD 0x5424
    #define SCL_TOP_SRC_MASK 0x0000003F
    #define SCL_TOP_SRC_SHIFT 0
    #define OUTPUT_IDX_0_MASK 0x00000040
    #define OUTPUT_IDX_0_SHIFT 6
    #define OUTPUT_IDX_1_MASK 0x00000080
    #define OUTPUT_IDX_1_SHIFT 7
    #define SCL_BOT_SRC_MASK 0x00003F00
    #define SCL_BOT_SRC_SHIFT 8
    #define OUTPUT_IDX_2_MASK 0x00004000
    #define OUTPUT_IDX_2_SHIFT 14
    #define OUTPUT_IDX_3_MASK 0x00008000
    #define OUTPUT_IDX_3_SHIFT 15
    #define VFE_FIFO_CMD_SLICE_SIZE_MASK 0x007F0000
    #define VFE_FIFO_CMD_SLICE_SIZE_SHIFT 16
    #define OUTPUT_IDX_4_MASK 0x00800000
    #define OUTPUT_IDX_4_SHIFT 23
    #define REPEAT_FLD_MASK 0x03000000
    #define REPEAT_FLD_SHIFT 24
    #define OUTPUT_IDX_5_MASK 0x04000000
    #define OUTPUT_IDX_5_SHIFT 26
    #define VFE_FIFO_CMD_PROG_FRM_MASK 0x10000000
    #define VFE_FIFO_CMD_PROG_FRM_SHIFT 28
    #define VFE_FIFO_CMD_UPDATE_MASK 0x20000000
    #define VFE_FIFO_CMD_UPDATE_SHIFT 29
    #define VFE_FIFO_CMD_STREAM_MASK 0xC0000000
    #define VFE_FIFO_CMD_STREAM_SHIFT 30
#define  VFE_FIFO_FREE 0x5420
    #define VFE_FIFO_FREE_CNT_MASK 0x0000000F
    #define VFE_FIFO_FREE_CNT_SHIFT 0
#define  VFE_HOST_INT_MASK 0x5408
    #define VFE0_HOST_INT_MASK_MASK 0x00000001
    #define VFE0_HOST_INT_MASK_SHIFT 0
    #define VFE1_HOST_INT_MASK_MASK 0x00000002
    #define VFE1_HOST_INT_MASK_SHIFT 1
#define  VFE_INT_CTRL 0x5400
    #define VFE0_INT_EN_MASK 0x000000FF
    #define VFE0_INT_EN_SHIFT 0
    #define VFE1_INT_EN_MASK 0x0000FF00
    #define VFE1_INT_EN_SHIFT 8
#define  VFE_INT_STATUS 0x5404
    #define VFE0_INT_MASK 0x00000001
    #define VFE0_INT_SHIFT 0
    #define VFE1_INT_MASK 0x00000002
    #define VFE1_INT_SHIFT 1
#define  VFE_LIMIT 0x5438
    #define C_UPPER_MASK 0x000000FF
    #define C_UPPER_SHIFT 0
    #define C_LOWER_MASK 0x0000FF00
    #define C_LOWER_SHIFT 8
    #define Y_UPPER_MASK 0x00FF0000
    #define Y_UPPER_SHIFT 16
    #define Y_LOWER_MASK 0xFF000000
    #define Y_LOWER_SHIFT 24
#define  VFE_MEMCLI_ARB 0x5430
    #define COUNT_0_MASK 0x0000003F
    #define COUNT_0_SHIFT 0
    #define COUNT_1_MASK 0x00000FC0
    #define COUNT_1_SHIFT 6
    #define COUNT_2_MASK 0x0003F000
    #define COUNT_2_SHIFT 12
    #define COUNT_3_MASK 0x00FC0000
    #define COUNT_3_SHIFT 18
    #define COUNT_4_MASK 0x3F000000
    #define COUNT_4_SHIFT 24
#define  VFE_MIPS_INT_MASK 0x540C
    #define VFE0_MIPS_INT_MASK_MASK 0x00000001
    #define VFE0_MIPS_INT_MASK_SHIFT 0
    #define VFE1_MIPS_INT_MASK_MASK 0x00000002
    #define VFE1_MIPS_INT_MASK_SHIFT 1
#define  VFE_OUTPUT_IDX 0x5428
    #define VFE0_IDX_MASK 0x0000003F
    #define VFE0_IDX_SHIFT 0
    #define VFE1_IDX_MASK 0x00003F00
    #define VFE1_IDX_SHIFT 8
#define  VFE_SCL_ADR 0x5418
    #define VFE_SCL_ADR_BASE_MASK 0x07FFFFC0
    #define VFE_SCL_ADR_BASE_SHIFT 6
#define  VFE_SCL_BOT 0x5414
    #define VFE_SCL_BOT_DATA_MASK 0x01FFFFFF
    #define VFE_SCL_BOT_DATA_SHIFT 0
#define  VFE_SCL_BUF 0x562C
    #define VFE_SCL_BUF_PITCH_MASK 0x00000FF0
    #define VFE_SCL_BUF_PITCH_SHIFT 4
    #define VFE_SCL_BUF_SIZE_MASK 0xFFFF0000
    #define VFE_SCL_BUF_SIZE_SHIFT 16
#define  VFE_SCL_DATA 0x5604
    #define VFE_SCL_DATA_VALUE_MASK 0xFFFFFFFF
    #define VFE_SCL_DATA_VALUE_SHIFT 0
#define  VFE_SCL_IDX 0x5600
    #define VFE_SCL_IDX_FLD_MASK 0x00000003
    #define VFE_SCL_IDX_FLD_SHIFT 0
    #define VFE_SCL_IDX_ADR_MASK 0x0000003C
    #define VFE_SCL_IDX_ADR_SHIFT 2
    #define INPUT_MASK 0x00000080
    #define INPUT_SHIFT 7
    #define READ_OP_MASK 0x80000000
    #define READ_OP_SHIFT 31
#define  VFE_SCL_TOP 0x5410
    #define VFE_SCL_TOP_DATA_MASK 0x01FFFFFF
    #define VFE_SCL_TOP_DATA_SHIFT 0
#define  VHE0_656_CODE 0x5240
    #define VHE0_656_CODE_Y_COORD_INIT_MASK 0x00000FFF
    #define VHE0_656_CODE_Y_COORD_INIT_SHIFT 0
    #define VHE0_656_CODE_FIRST_CODE_MASK 0x003FF000
    #define VHE0_656_CODE_FIRST_CODE_SHIFT 12
    #define VHE0_656_CODE_SECOND_CODE_MASK 0xFFC00000
    #define VHE0_656_CODE_SECOND_CODE_SHIFT 22
#define  VHE0_656_CODE_CTRL 0x523C
    #define VHE0_656_CODE_CTRL_COUNT_MASK 0x00FFFFFF
    #define VHE0_656_CODE_CTRL_COUNT_SHIFT 0
    #define VHE0_656_CODE_CTRL_SECONDARY_CODE_ENABLE_MASK 0x80000000
    #define VHE0_656_CODE_CTRL_SECONDARY_CODE_ENABLE_SHIFT 31
#define  VHE0_656_CODE_SECONDARY 0x5244
    #define VHE0_656_CODE_SECONDARY_Y_COORD_INIT_MASK 0x00000FFF
    #define VHE0_656_CODE_SECONDARY_Y_COORD_INIT_SHIFT 0
    #define VHE0_656_CODE_SECONDARY_FIRST_CODE_MASK 0x003FF000
    #define VHE0_656_CODE_SECONDARY_FIRST_CODE_SHIFT 12
    #define VHE0_656_CODE_SECONDARY_SECOND_CODE_MASK 0xFFC00000
    #define VHE0_656_CODE_SECONDARY_SECOND_CODE_SHIFT 22
#define  VHE0_90KHZ_DEN 0x528C
    #define VHE0_90KHZ_DEN_DEN_MASK 0xFFFFFFFF
    #define VHE0_90KHZ_DEN_DEN_SHIFT 0
#define  VHE0_90KHZ_NUM 0x5288
    #define VHE0_90KHZ_NUM_NUM_MASK 0xFFFFFFFF
    #define VHE0_90KHZ_NUM_NUM_SHIFT 0
#define  VHE0_ACTIVE_X 0x505C
    #define VHE0_ACTIVE_X_END_MASK 0x00000FFF
    #define VHE0_ACTIVE_X_END_SHIFT 0
    #define VHE0_ACTIVE_X_START_MASK 0x0FFF0000
    #define VHE0_ACTIVE_X_START_SHIFT 16
#define  VHE0_ACTIVE_Y_BOT 0x5064
    #define VHE0_ACTIVE_Y_BOT_START_MASK 0x00000FFF
    #define VHE0_ACTIVE_Y_BOT_START_SHIFT 0
    #define VHE0_ACTIVE_Y_BOT_END_MASK 0x0FFF0000
    #define VHE0_ACTIVE_Y_BOT_END_SHIFT 16
#define  VHE0_ACTIVE_Y_TOP 0x5060
    #define VHE0_ACTIVE_Y_TOP_START_MASK 0x00000FFF
    #define VHE0_ACTIVE_Y_TOP_START_SHIFT 0
    #define VHE0_ACTIVE_Y_TOP_END_MASK 0x0FFF0000
    #define VHE0_ACTIVE_Y_TOP_END_SHIFT 16
#define  VHE0_CC_CTRL 0x5074
    #define VHE0_CC_CTRL_CC_EN_MASK 0x00000001
    #define VHE0_CC_CTRL_CC_EN_SHIFT 0
    #define VHE0_CC_CTRL_AUTO_DETECT_MASK 0x00000002
    #define VHE0_CC_CTRL_AUTO_DETECT_SHIFT 1
    #define VHE0_CC_CTRL_START_LOC_MASK 0x000FFF00
    #define VHE0_CC_CTRL_START_LOC_SHIFT 8
    #define VHE0_CC_CTRL_VBI_SAMPLE_EN_MASK 0x80000000
    #define VHE0_CC_CTRL_VBI_SAMPLE_EN_SHIFT 31
#define  VHE0_CC_SAMPLING 0x507C
    #define VHE0_CC_SAMPLING_CC_M_MASK 0x000001FF
    #define VHE0_CC_SAMPLING_CC_M_SHIFT 0
    #define VHE0_CC_SAMPLING_CC_N_MASK 0x01FF0000
    #define VHE0_CC_SAMPLING_CC_N_SHIFT 16
    #define VHE0_CC_SAMPLING_DELTA_MASK 0x70000000
    #define VHE0_CC_SAMPLING_DELTA_SHIFT 28
#define  VHE0_CC_THRES 0x5078
    #define VHE0_CC_THRES_THRES_LOW_MASK 0x000003FF
    #define VHE0_CC_THRES_THRES_LOW_SHIFT 0
    #define VHE0_CC_THRES_THRES_HIGH_MASK 0x03FF0000
    #define VHE0_CC_THRES_THRES_HIGH_SHIFT 16
#define  VHE0_CHROMA_BORDER 0x50B8
    #define VHE0_CHROMA_BORDER_CB_VAL_MASK 0x000003FF
    #define VHE0_CHROMA_BORDER_CB_VAL_SHIFT 0
    #define VHE0_CHROMA_BORDER_CR_VAL_MASK 0x03FF0000
    #define VHE0_CHROMA_BORDER_CR_VAL_SHIFT 16
#define  VHE0_DEN 0x5298
    #define VHE0_DEN_DEN_MASK 0xFFFFFFFF
    #define VHE0_DEN_DEN_SHIFT 0
#define  VHE0_GENLOCK_LOWER 0x52A0
    #define VHE0_GENLOCK_LOWER_GENLOCK_L_MASK 0xFFFFFFFF
    #define VHE0_GENLOCK_LOWER_GENLOCK_L_SHIFT 0
#define  VHE0_GENLOCK_UPPER 0x529C
    #define VHE0_GENLOCK_UPPER_GENLOCK_U_MASK 0x000003FF
    #define VHE0_GENLOCK_UPPER_GENLOCK_U_SHIFT 0
#define  VHE0_INFO_ADR 0x5090
    #define VHE0_INFO_ADR_BASE_MASK 0x07FFFFC0
    #define VHE0_INFO_ADR_BASE_SHIFT 6
#define  VHE0_INPUT_CTRL 0x50A4
    #define VHE0_INPUT_CTRL_INPUT_EN_MASK 0x00000001
    #define VHE0_INPUT_CTRL_INPUT_EN_SHIFT 0
    #define VHE0_INPUT_CTRL_SRC_MASK 0x00000002
    #define VHE0_INPUT_CTRL_SRC_SHIFT 1
    #define VHE0_INPUT_CTRL_TELECINE_EN_MASK 0x00000010
    #define VHE0_INPUT_CTRL_TELECINE_EN_SHIFT 4
    #define VHE0_INPUT_CTRL_BIT_SIZE_MASK 0x00000020
    #define VHE0_INPUT_CTRL_BIT_SIZE_SHIFT 5
    #define VHE0_INPUT_CTRL_CAP_FLD_SEL_MASK 0x000000C0
    #define VHE0_INPUT_CTRL_CAP_FLD_SEL_SHIFT 6
    #define VHE0_INPUT_CTRL_VBI_FLD_SEL_MASK 0x00000300
    #define VHE0_INPUT_CTRL_VBI_FLD_SEL_SHIFT 8
    #define VHE0_INPUT_CTRL_CCIR656_MODE_MASK 0x00000400
    #define VHE0_INPUT_CTRL_CCIR656_MODE_SHIFT 10
    #define VHE0_INPUT_CTRL_BIT_EXTEND_MASK 0x00000800
    #define VHE0_INPUT_CTRL_BIT_EXTEND_SHIFT 11
    #define VHE0_INPUT_CTRL_MEM_LINEAR_MASK 0x00001000
    #define VHE0_INPUT_CTRL_MEM_LINEAR_SHIFT 12
    #define VHE0_INPUT_CTRL_MEM_PACKING_MASK 0x00002000
    #define VHE0_INPUT_CTRL_MEM_PACKING_SHIFT 13
    #define VHE0_INPUT_CTRL_MEM_ROUND_MASK 0x00004000
    #define VHE0_INPUT_CTRL_MEM_ROUND_SHIFT 14
    #define VHE0_INPUT_CTRL_BYPASS_MODE_MASK 0x00008000
    #define VHE0_INPUT_CTRL_BYPASS_MODE_SHIFT 15
    #define VHE0_INPUT_CTRL_PREFETCH_PELS_MASK 0x0FFF0000
    #define VHE0_INPUT_CTRL_PREFETCH_PELS_SHIFT 16
#define  VHE0_INPUT_STATUS 0x5230
    #define VHE0_INPUT_STATUS_WADDR_MASK 0x0000000F
    #define VHE0_INPUT_STATUS_WADDR_SHIFT 0
    #define VHE0_INPUT_STATUS_RADDR_MASK 0x00000F00
    #define VHE0_INPUT_STATUS_RADDR_SHIFT 8
    #define VHE0_INPUT_STATUS_EMPTY_MASK 0x00010000
    #define VHE0_INPUT_STATUS_EMPTY_SHIFT 16
    #define VHE0_INPUT_STATUS_FULL_MASK 0x00100000
    #define VHE0_INPUT_STATUS_FULL_SHIFT 20
    #define VHE0_INPUT_STATUS_NO_IN_FIFO_MASK 0x1F000000
    #define VHE0_INPUT_STATUS_NO_IN_FIFO_SHIFT 24
#define  VHE0_LUMA_BORDER 0x50B4
    #define VHE0_LUMA_BORDER_Y_VAL_MASK 0x000003FF
    #define VHE0_LUMA_BORDER_Y_VAL_SHIFT 0
#define  VHE0_NUM 0x5294
    #define VHE0_NUM_NUM_MASK 0xFFFFFFFF
    #define VHE0_NUM_NUM_SHIFT 0
#define  VHE0_RUN_STATUS 0x5234
    #define VHE0_RUN_STATUS_X_COORD_MASK 0x00000FFF
    #define VHE0_RUN_STATUS_X_COORD_SHIFT 0
    #define VHE0_RUN_STATUS_Y_COORD_MASK 0x0FFF0000
    #define VHE0_RUN_STATUS_Y_COORD_SHIFT 16
#define  VHE0_SCL_ADR 0x5084
    #define VHE0_SCL_ADR_BASE_MASK 0x07FFFFC0
    #define VHE0_SCL_ADR_BASE_SHIFT 6
#define  VHE0_SCL_BUF 0x5080
    #define VHE0_SCL_BUF_PITCH_MASK 0x00000FC0
    #define VHE0_SCL_BUF_PITCH_SHIFT 6
    #define VHE0_SCL_BUF_CNT_MASK 0x0003F000
    #define VHE0_SCL_BUF_CNT_SHIFT 12
    #define VHE0_SCL_BUF_SIZE_MSB_MASK 0x00080000
    #define VHE0_SCL_BUF_SIZE_MSB_SHIFT 19
    #define VHE0_SCL_BUF_SIZE_MASK 0xFFF00000
    #define VHE0_SCL_BUF_SIZE_SHIFT 20
#define  VHE0_SCL_CB_ADR 0x50AC
    #define VHE0_SCL_CB_ADR_BASE_MASK 0x07FFFFC0
    #define VHE0_SCL_CB_ADR_BASE_SHIFT 6
#define  VHE0_SCL_CR_ADR 0x50B0
    #define VHE0_SCL_CR_ADR_BASE_MASK 0x07FFFFC0
    #define VHE0_SCL_CR_ADR_BASE_SHIFT 6
#define  VHE0_TBC_SAMPLE 0x5238
    #define VHE0_TBC_SAMPLE_COUNT_MASK 0x00FFFFFF
    #define VHE0_TBC_SAMPLE_COUNT_SHIFT 0
#define  VHE0_TELECINE_CTRL 0x5094
    #define VHE0_TELECINE_CTRL_THRES_MASK 0x00000FFF
    #define VHE0_TELECINE_CTRL_THRES_SHIFT 0
    #define VHE0_TELECINE_CTRL_VERIFY_MASK 0x0000F000
    #define VHE0_TELECINE_CTRL_VERIFY_SHIFT 12
    #define VHE0_TELECINE_CTRL_MISMATCH_MASK 0x000F0000
    #define VHE0_TELECINE_CTRL_MISMATCH_SHIFT 16
    #define VHE0_TELECINE_CTRL_LINE_DETECT_MASK 0x00F00000
    #define VHE0_TELECINE_CTRL_LINE_DETECT_SHIFT 20
#define  VHE0_TIMESTAMP_CTRL 0x5098
    #define VHE0_TIMESTAMP_CTRL_OFFSET_MASK 0xFFFFFFFF
    #define VHE0_TIMESTAMP_CTRL_OFFSET_SHIFT 0
#define  VHE0_TIMESTAMP_LOWER 0x52C4
    #define VHE0_TIMESTAMP_LOWER_TIMESTAMP_L_MASK 0xFFFFFFFF
    #define VHE0_TIMESTAMP_LOWER_TIMESTAMP_L_SHIFT 0
#define  VHE0_TIMESTAMP_SEL 0x5290
    #define VHE0_TIMESTAMP_SEL_TIMESTAMP_SEL_MASK 0x00000007
    #define VHE0_TIMESTAMP_SEL_TIMESTAMP_SEL_SHIFT 0
#define  VHE0_TIMESTAMP_UPPER 0x52C0
    #define VHE0_TIMESTAMP_UPPER_TIMESTAMP_U_MASK 0x00000001
    #define VHE0_TIMESTAMP_UPPER_TIMESTAMP_U_SHIFT 0
#define  VHE0_VBI_ADR 0x508C
    #define VHE0_VBI_ADR_BASE_MASK 0x07FFFFC0
    #define VHE0_VBI_ADR_BASE_SHIFT 6
#define  VHE0_VBI_BUF 0x5088
    #define VHE0_VBI_BUF_PITCH_MASK 0x00000FE0
    #define VHE0_VBI_BUF_PITCH_SHIFT 5
    #define VHE0_VBI_BUF_CNT_MASK 0x000FF000
    #define VHE0_VBI_BUF_CNT_SHIFT 12
    #define VHE0_VBI_BUF_SIZE_MASK 0xFFF00000
    #define VHE0_VBI_BUF_SIZE_SHIFT 20
#define  VHE0_VBI_SAMPLE 0x50A8
    #define VHE0_VBI_SAMPLE_MIN_SAMPLE_MASK 0x000003FF
    #define VHE0_VBI_SAMPLE_MIN_SAMPLE_SHIFT 0
    #define VHE0_VBI_SAMPLE_MAX_SAMPLE_MASK 0x03FF0000
    #define VHE0_VBI_SAMPLE_MAX_SAMPLE_SHIFT 16
    #define VHE0_VBI_SAMPLE_SAMPLE_VALID_MASK 0x80000000
    #define VHE0_VBI_SAMPLE_SAMPLE_VALID_SHIFT 31
#define  VHE0_VBI_X 0x5050
    #define VHE0_VBI_X_START_MASK 0x00000FFF
    #define VHE0_VBI_X_START_SHIFT 0
    #define VHE0_VBI_X_END_MASK 0x0FFF0000
    #define VHE0_VBI_X_END_SHIFT 16
#define  VHE0_VBI_Y_BOT 0x5058
    #define VHE0_VBI_Y_BOT_START_MASK 0x00000FFF
    #define VHE0_VBI_Y_BOT_START_SHIFT 0
    #define VHE0_VBI_Y_BOT_END_MASK 0x0FFF0000
    #define VHE0_VBI_Y_BOT_END_SHIFT 16
#define  VHE0_VBI_Y_TOP 0x5054
    #define VHE0_VBI_Y_TOP_START_MASK 0x00000FFF
    #define VHE0_VBI_Y_TOP_START_SHIFT 0
    #define VHE0_VBI_Y_TOP_END_MASK 0x0FFF0000
    #define VHE0_VBI_Y_TOP_END_SHIFT 16
#define  VHE0_VIDEO_X 0x5068
    #define VHE0_VIDEO_X_START_MASK 0x00000FFF
    #define VHE0_VIDEO_X_START_SHIFT 0
    #define VHE0_VIDEO_X_END_MASK 0x0FFF0000
    #define VHE0_VIDEO_X_END_SHIFT 16
#define  VHE0_VIDEO_Y_BOT 0x5070
    #define VHE0_VIDEO_Y_BOT_START_MASK 0x00000FFF
    #define VHE0_VIDEO_Y_BOT_START_SHIFT 0
    #define VHE0_VIDEO_Y_BOT_END_MASK 0x0FFF0000
    #define VHE0_VIDEO_Y_BOT_END_SHIFT 16
#define  VHE0_VIDEO_Y_TOP 0x506C
    #define VHE0_VIDEO_Y_TOP_START_MASK 0x00000FFF
    #define VHE0_VIDEO_Y_TOP_START_SHIFT 0
    #define VHE0_VIDEO_Y_TOP_END_MASK 0x0FFF0000
    #define VHE0_VIDEO_Y_TOP_END_SHIFT 16
#define  VHE0_WAIT_FOR_SAMPLES 0x5248
    #define VHE0_WAIT_FOR_SAMPLES_WAIT_FOR_SAMPLES_MASK 0x00000FFF
    #define VHE0_WAIT_FOR_SAMPLES_WAIT_FOR_SAMPLES_SHIFT 0
#define  VHE1_656_CODE 0x5270
    #define VHE1_656_CODE_Y_COORD_INIT_MASK 0x00000FFF
    #define VHE1_656_CODE_Y_COORD_INIT_SHIFT 0
    #define VHE1_656_CODE_FIRST_CODE_MASK 0x003FF000
    #define VHE1_656_CODE_FIRST_CODE_SHIFT 12
    #define VHE1_656_CODE_SECOND_CODE_MASK 0xFFC00000
    #define VHE1_656_CODE_SECOND_CODE_SHIFT 22
#define  VHE1_656_CODE_CTRL 0x526C
    #define VHE1_656_CODE_CTRL_COUNT_MASK 0x00FFFFFF
    #define VHE1_656_CODE_CTRL_COUNT_SHIFT 0
    #define VHE1_656_CODE_CTRL_SECONDARY_CODE_ENABLE_MASK 0x80000000
    #define VHE1_656_CODE_CTRL_SECONDARY_CODE_ENABLE_SHIFT 31
#define  VHE1_656_CODE_SECONDARY 0x5274
    #define VHE1_656_CODE_SECONDARY_Y_COORD_INIT_MASK 0x00000FFF
    #define VHE1_656_CODE_SECONDARY_Y_COORD_INIT_SHIFT 0
    #define VHE1_656_CODE_SECONDARY_FIRST_CODE_MASK 0x003FF000
    #define VHE1_656_CODE_SECONDARY_FIRST_CODE_SHIFT 12
    #define VHE1_656_CODE_SECONDARY_SECOND_CODE_MASK 0xFFC00000
    #define VHE1_656_CODE_SECONDARY_SECOND_CODE_SHIFT 22
#define  VHE1_90KHZ_DEN 0x52A8
    #define VHE1_90KHZ_DEN_DEN_MASK 0xFFFFFFFF
    #define VHE1_90KHZ_DEN_DEN_SHIFT 0
#define  VHE1_90KHZ_NUM 0x52A4
    #define VHE1_90KHZ_NUM_NUM_MASK 0xFFFFFFFF
    #define VHE1_90KHZ_NUM_NUM_SHIFT 0
#define  VHE1_ACTIVE_X 0x50CC
    #define VHE1_ACTIVE_X_END_MASK 0x00000FFF
    #define VHE1_ACTIVE_X_END_SHIFT 0
    #define VHE1_ACTIVE_X_START_MASK 0x0FFF0000
    #define VHE1_ACTIVE_X_START_SHIFT 16
#define  VHE1_ACTIVE_Y_BOT 0x50D4
    #define VHE1_ACTIVE_Y_BOT_START_MASK 0x00000FFF
    #define VHE1_ACTIVE_Y_BOT_START_SHIFT 0
    #define VHE1_ACTIVE_Y_BOT_END_MASK 0x0FFF0000
    #define VHE1_ACTIVE_Y_BOT_END_SHIFT 16
#define  VHE1_ACTIVE_Y_TOP 0x50D0
    #define VHE1_ACTIVE_Y_TOP_START_MASK 0x00000FFF
    #define VHE1_ACTIVE_Y_TOP_START_SHIFT 0
    #define VHE1_ACTIVE_Y_TOP_END_MASK 0x0FFF0000
    #define VHE1_ACTIVE_Y_TOP_END_SHIFT 16
#define  VHE1_CC_CTRL 0x50E4
    #define VHE1_CC_CTRL_CC_EN_MASK 0x00000001
    #define VHE1_CC_CTRL_CC_EN_SHIFT 0
    #define VHE1_CC_CTRL_AUTO_DETECT_MASK 0x00000002
    #define VHE1_CC_CTRL_AUTO_DETECT_SHIFT 1
    #define VHE1_CC_CTRL_START_LOC_MASK 0x000FFF00
    #define VHE1_CC_CTRL_START_LOC_SHIFT 8
    #define VHE1_CC_CTRL_VBI_SAMPLE_EN_MASK 0x80000000
    #define VHE1_CC_CTRL_VBI_SAMPLE_EN_SHIFT 31
#define  VHE1_CC_SAMPLING 0x50EC
    #define VHE1_CC_SAMPLING_CC_M_MASK 0x000001FF
    #define VHE1_CC_SAMPLING_CC_M_SHIFT 0
    #define VHE1_CC_SAMPLING_CC_N_MASK 0x01FF0000
    #define VHE1_CC_SAMPLING_CC_N_SHIFT 16
    #define VHE1_CC_SAMPLING_DELTA_MASK 0x70000000
    #define VHE1_CC_SAMPLING_DELTA_SHIFT 28
#define  VHE1_CC_THRES 0x50E8
    #define VHE1_CC_THRES_THRES_LOW_MASK 0x000003FF
    #define VHE1_CC_THRES_THRES_LOW_SHIFT 0
    #define VHE1_CC_THRES_THRES_HIGH_MASK 0x03FF0000
    #define VHE1_CC_THRES_THRES_HIGH_SHIFT 16
#define  VHE1_CHROMA_BORDER 0x5128
    #define VHE1_CHROMA_BORDER_CB_VAL_MASK 0x000003FF
    #define VHE1_CHROMA_BORDER_CB_VAL_SHIFT 0
    #define VHE1_CHROMA_BORDER_CR_VAL_MASK 0x03FF0000
    #define VHE1_CHROMA_BORDER_CR_VAL_SHIFT 16
#define  VHE1_DEN 0x52B4
    #define VHE1_DEN_DEN_MASK 0xFFFFFFFF
    #define VHE1_DEN_DEN_SHIFT 0
#define  VHE1_GENLOCK_LOWER 0x52BC
    #define VHE1_GENLOCK_LOWER_GENLOCK_L_MASK 0xFFFFFFFF
    #define VHE1_GENLOCK_LOWER_GENLOCK_L_SHIFT 0
#define  VHE1_GENLOCK_UPPER 0x52B8
    #define VHE1_GENLOCK_UPPER_GENLOCK_U_MASK 0x000003FF
    #define VHE1_GENLOCK_UPPER_GENLOCK_U_SHIFT 0
#define  VHE1_INFO_ADR 0x5100
    #define VHE1_INFO_ADR_BASE_MASK 0x07FFFFC0
    #define VHE1_INFO_ADR_BASE_SHIFT 6
#define  VHE1_INPUT_CTRL 0x5114
    #define VHE1_INPUT_CTRL_INPUT_EN_MASK 0x00000001
    #define VHE1_INPUT_CTRL_INPUT_EN_SHIFT 0
    #define VHE1_INPUT_CTRL_SRC_MASK 0x00000002
    #define VHE1_INPUT_CTRL_SRC_SHIFT 1
    #define VHE1_INPUT_CTRL_TELECINE_EN_MASK 0x00000010
    #define VHE1_INPUT_CTRL_TELECINE_EN_SHIFT 4
    #define VHE1_INPUT_CTRL_BIT_SIZE_MASK 0x00000020
    #define VHE1_INPUT_CTRL_BIT_SIZE_SHIFT 5
    #define VHE1_INPUT_CTRL_CAP_FLD_SEL_MASK 0x000000C0
    #define VHE1_INPUT_CTRL_CAP_FLD_SEL_SHIFT 6
    #define VHE1_INPUT_CTRL_VBI_FLD_SEL_MASK 0x00000300
    #define VHE1_INPUT_CTRL_VBI_FLD_SEL_SHIFT 8
    #define VHE1_INPUT_CTRL_CCIR656_MODE_MASK 0x00000400
    #define VHE1_INPUT_CTRL_CCIR656_MODE_SHIFT 10
    #define VHE1_INPUT_CTRL_BIT_EXTEND_MASK 0x00000800
    #define VHE1_INPUT_CTRL_BIT_EXTEND_SHIFT 11
    #define VHE1_INPUT_CTRL_MEM_LINEAR_MASK 0x00001000
    #define VHE1_INPUT_CTRL_MEM_LINEAR_SHIFT 12
    #define VHE1_INPUT_CTRL_MEM_PACKING_MASK 0x00002000
    #define VHE1_INPUT_CTRL_MEM_PACKING_SHIFT 13
    #define VHE1_INPUT_CTRL_MEM_ROUND_MASK 0x00004000
    #define VHE1_INPUT_CTRL_MEM_ROUND_SHIFT 14
    #define VHE1_INPUT_CTRL_BYPASS_MODE_MASK 0x00008000
    #define VHE1_INPUT_CTRL_BYPASS_MODE_SHIFT 15
    #define VHE1_INPUT_CTRL_PREFETCH_PELS_MASK 0x0FFF0000
    #define VHE1_INPUT_CTRL_PREFETCH_PELS_SHIFT 16
#define  VHE1_INPUT_STATUS 0x5260
    #define VHE1_INPUT_STATUS_WADDR_MASK 0x0000000F
    #define VHE1_INPUT_STATUS_WADDR_SHIFT 0
    #define VHE1_INPUT_STATUS_RADDR_MASK 0x00000F00
    #define VHE1_INPUT_STATUS_RADDR_SHIFT 8
    #define VHE1_INPUT_STATUS_EMPTY_MASK 0x00010000
    #define VHE1_INPUT_STATUS_EMPTY_SHIFT 16
    #define VHE1_INPUT_STATUS_FULL_MASK 0x00100000
    #define VHE1_INPUT_STATUS_FULL_SHIFT 20
    #define VHE1_INPUT_STATUS_NO_IN_FIFO_MASK 0x1F000000
    #define VHE1_INPUT_STATUS_NO_IN_FIFO_SHIFT 24
#define  VHE1_LUMA_BORDER 0x5124
    #define VHE1_LUMA_BORDER_Y_VAL_MASK 0x000003FF
    #define VHE1_LUMA_BORDER_Y_VAL_SHIFT 0
#define  VHE1_NUM 0x52B0
    #define VHE1_NUM_NUM_MASK 0xFFFFFFFF
    #define VHE1_NUM_NUM_SHIFT 0
#define  VHE1_RUN_STATUS 0x5264
    #define VHE1_RUN_STATUS_X_COORD_MASK 0x00000FFF
    #define VHE1_RUN_STATUS_X_COORD_SHIFT 0
    #define VHE1_RUN_STATUS_Y_COORD_MASK 0x0FFF0000
    #define VHE1_RUN_STATUS_Y_COORD_SHIFT 16
#define  VHE1_SCL_ADR 0x50F4
    #define VHE1_SCL_ADR_BASE_MASK 0x07FFFFC0
    #define VHE1_SCL_ADR_BASE_SHIFT 6
#define  VHE1_SCL_BUF 0x50F0
    #define VHE1_SCL_BUF_PITCH_MASK 0x00000FC0
    #define VHE1_SCL_BUF_PITCH_SHIFT 6
    #define VHE1_SCL_BUF_CNT_MASK 0x0003F000
    #define VHE1_SCL_BUF_CNT_SHIFT 12
    #define VHE1_SCL_BUF_SIZE_MSB_MASK 0x00080000
    #define VHE1_SCL_BUF_SIZE_MSB_SHIFT 19
    #define VHE1_SCL_BUF_SIZE_MASK 0xFFF00000
    #define VHE1_SCL_BUF_SIZE_SHIFT 20
#define  VHE1_SCL_CB_ADR 0x511C
    #define VHE1_SCL_CB_ADR_BASE_MASK 0x07FFFFC0
    #define VHE1_SCL_CB_ADR_BASE_SHIFT 6
#define  VHE1_SCL_CR_ADR 0x5120
    #define VHE1_SCL_CR_ADR_BASE_MASK 0x07FFFFC0
    #define VHE1_SCL_CR_ADR_BASE_SHIFT 6
#define  VHE1_TBC_SAMPLE 0x5268
    #define VHE1_TBC_SAMPLE_COUNT_MASK 0x00FFFFFF
    #define VHE1_TBC_SAMPLE_COUNT_SHIFT 0
#define  VHE1_TELECINE_CTRL 0x5104
    #define VHE1_TELECINE_CTRL_THRES_MASK 0x00000FFF
    #define VHE1_TELECINE_CTRL_THRES_SHIFT 0
    #define VHE1_TELECINE_CTRL_VERIFY_MASK 0x0000F000
    #define VHE1_TELECINE_CTRL_VERIFY_SHIFT 12
    #define VHE1_TELECINE_CTRL_MISMATCH_MASK 0x000F0000
    #define VHE1_TELECINE_CTRL_MISMATCH_SHIFT 16
    #define VHE1_TELECINE_CTRL_LINE_DETECT_MASK 0x00F00000
    #define VHE1_TELECINE_CTRL_LINE_DETECT_SHIFT 20
#define  VHE1_TIMESTAMP_CTRL 0x5108
    #define VHE1_TIMESTAMP_CTRL_OFFSET_MASK 0xFFFFFFFF
    #define VHE1_TIMESTAMP_CTRL_OFFSET_SHIFT 0
#define  VHE1_TIMESTAMP_LOWER 0x52D0
    #define VHE1_TIMESTAMP_LOWER_TIMESTAMP_L_MASK 0xFFFFFFFF
    #define VHE1_TIMESTAMP_LOWER_TIMESTAMP_L_SHIFT 0
#define  VHE1_TIMESTAMP_SEL 0x52AC
    #define VHE1_TIMESTAMP_SEL_TIMESTAMP_SEL_MASK 0x00000007
    #define VHE1_TIMESTAMP_SEL_TIMESTAMP_SEL_SHIFT 0
#define  VHE1_TIMESTAMP_UPPER 0x52C8
    #define VHE1_TIMESTAMP_UPPER_TIMESTAMP_U_MASK 0x00000001
    #define VHE1_TIMESTAMP_UPPER_TIMESTAMP_U_SHIFT 0
#define  VHE1_VBI_ADR 0x50FC
    #define VHE1_VBI_ADR_BASE_MASK 0x07FFFFC0
    #define VHE1_VBI_ADR_BASE_SHIFT 6
#define  VHE1_VBI_BUF 0x50F8
    #define VHE1_VBI_BUF_PITCH_MASK 0x00000FE0
    #define VHE1_VBI_BUF_PITCH_SHIFT 5
    #define VHE1_VBI_BUF_CNT_MASK 0x000FF000
    #define VHE1_VBI_BUF_CNT_SHIFT 12
    #define VHE1_VBI_BUF_SIZE_MASK 0xFFF00000
    #define VHE1_VBI_BUF_SIZE_SHIFT 20
#define  VHE1_VBI_SAMPLE 0x5118
    #define VHE1_VBI_SAMPLE_MIN_SAMPLE_MASK 0x000003FF
    #define VHE1_VBI_SAMPLE_MIN_SAMPLE_SHIFT 0
    #define VHE1_VBI_SAMPLE_MAX_SAMPLE_MASK 0x03FF0000
    #define VHE1_VBI_SAMPLE_MAX_SAMPLE_SHIFT 16
    #define VHE1_VBI_SAMPLE_SAMPLE_VALID_MASK 0x80000000
    #define VHE1_VBI_SAMPLE_SAMPLE_VALID_SHIFT 31
#define  VHE1_VBI_X 0x50C0
    #define VHE1_VBI_X_START_MASK 0x00000FFF
    #define VHE1_VBI_X_START_SHIFT 0
    #define VHE1_VBI_X_END_MASK 0x0FFF0000
    #define VHE1_VBI_X_END_SHIFT 16
#define  VHE1_VBI_Y_BOT 0x50C8
    #define VHE1_VBI_Y_BOT_START_MASK 0x00000FFF
    #define VHE1_VBI_Y_BOT_START_SHIFT 0
    #define VHE1_VBI_Y_BOT_END_MASK 0x0FFF0000
    #define VHE1_VBI_Y_BOT_END_SHIFT 16
#define  VHE1_VBI_Y_TOP 0x50C4
    #define VHE1_VBI_Y_TOP_START_MASK 0x00000FFF
    #define VHE1_VBI_Y_TOP_START_SHIFT 0
    #define VHE1_VBI_Y_TOP_END_MASK 0x0FFF0000
    #define VHE1_VBI_Y_TOP_END_SHIFT 16
#define  VHE1_VIDEO_X 0x50D8
    #define VHE1_VIDEO_X_START_MASK 0x00000FFF
    #define VHE1_VIDEO_X_START_SHIFT 0
    #define VHE1_VIDEO_X_END_MASK 0x0FFF0000
    #define VHE1_VIDEO_X_END_SHIFT 16
#define  VHE1_VIDEO_Y_BOT 0x50E0
    #define VHE1_VIDEO_Y_BOT_START_MASK 0x00000FFF
    #define VHE1_VIDEO_Y_BOT_START_SHIFT 0
    #define VHE1_VIDEO_Y_BOT_END_MASK 0x0FFF0000
    #define VHE1_VIDEO_Y_BOT_END_SHIFT 16
#define  VHE1_VIDEO_Y_TOP 0x50DC
    #define VHE1_VIDEO_Y_TOP_START_MASK 0x00000FFF
    #define VHE1_VIDEO_Y_TOP_START_SHIFT 0
    #define VHE1_VIDEO_Y_TOP_END_MASK 0x0FFF0000
    #define VHE1_VIDEO_Y_TOP_END_SHIFT 16
#define  VHE1_WAIT_FOR_SAMPLES 0x5278
    #define VHE1_WAIT_FOR_SAMPLES_WAIT_FOR_SAMPLES_MASK 0x00000FFF
    #define VHE1_WAIT_FOR_SAMPLES_WAIT_FOR_SAMPLES_SHIFT 0
#define  VHE_CORING 0x527C
    #define CB_CR_LOCKED_MASK 0x00000001
    #define CB_CR_LOCKED_SHIFT 0
    #define VHE_CORING_ENABLE_VBI_MASK 0x00000010
    #define VHE_CORING_ENABLE_VBI_SHIFT 4
    #define VHE_CORING_RANGE_MASK 0x001F0000
    #define VHE_CORING_RANGE_SHIFT 16
#define  VHE_CORING_X 0x5284
    #define VHE_CORING_X_START_MASK 0x00000FFF
    #define VHE_CORING_X_START_SHIFT 0
    #define VHE_CORING_X_END_MASK 0x0FFF0000
    #define VHE_CORING_X_END_SHIFT 16
#define  VHE_CTRL 0x5014
    #define SEGMENTS_MASK 0x00000003
    #define SEGMENTS_SHIFT 0
    #define URGENT_THRES_MASK 0x000003F0
    #define URGENT_THRES_SHIFT 4
    #define BYPASS_COUNT_MASK 0x001F0000
    #define BYPASS_COUNT_SHIFT 16
    #define INPUT_TYPE_MASK 0x01000000
    #define INPUT_TYPE_SHIFT 24
    #define VHE_CTRL_DUPLICATE_CODE_MASK 0x02000000
    #define VHE_CTRL_DUPLICATE_CODE_SHIFT 25
    #define VHE_CTRL_DDR_MODE_MASK 0x10000000
    #define VHE_CTRL_DDR_MODE_SHIFT 28
#define  VHE_DUMMY_REG 0x5028
    #define CLAMP_SAD_MASK 0x00000001
    #define CLAMP_SAD_SHIFT 0
    #define MOV_TH_TAKE_MAX_MASK 0x00000002
    #define MOV_TH_TAKE_MAX_SHIFT 1
    #define USE_HW_FIELD_FIX_MASK 0x00000004
    #define USE_HW_FIELD_FIX_SHIFT 2
    #define LOCK_INFO_CNT_MASK 0x00000008
    #define LOCK_INFO_CNT_SHIFT 3
    #define DUMP_CC_DEBUG_MASK 0x00000010
    #define DUMP_CC_DEBUG_SHIFT 4
    #define VHE_DUMMY_REG_DUMMY_BITS_MASK 0xFFFFFFE0
    #define VHE_DUMMY_REG_DUMMY_BITS_SHIFT 5
#define  VHE_HOST_INT_MASK 0x500C
    #define VHE0_HOST_INT_MASK_MASK 0x00000001
    #define VHE0_HOST_INT_MASK_SHIFT 0
    #define VHE1_HOST_INT_MASK_MASK 0x00000002
    #define VHE1_HOST_INT_MASK_SHIFT 1
    #define VBI0_HOST_INT_MASK_MASK 0x00010000
    #define VBI0_HOST_INT_MASK_SHIFT 16
    #define VBI1_HOST_INT_MASK_MASK 0x00020000
    #define VBI1_HOST_INT_MASK_SHIFT 17
#define  VHE_INT_CTRL 0x5000
    #define VHE0_INT_EN_MASK 0x000000FF
    #define VHE0_INT_EN_SHIFT 0
    #define VHE1_INT_EN_MASK 0x0000FF00
    #define VHE1_INT_EN_SHIFT 8
#define  VHE_INT_STATUS 0x5008
    #define VHE0_INT_MASK 0x00000001
    #define VHE0_INT_SHIFT 0
    #define VHE1_INT_MASK 0x00000002
    #define VHE1_INT_SHIFT 1
    #define VBI0_INT_MASK 0x00010000
    #define VBI0_INT_SHIFT 16
    #define VBI1_INT_MASK 0x00020000
    #define VBI1_INT_SHIFT 17
#define  VHE_MIPS_INT_MASK 0x5010
    #define VHE0_MIPS_INT_MASK_MASK 0x00000001
    #define VHE0_MIPS_INT_MASK_SHIFT 0
    #define VHE1_MIPS_INT_MASK_MASK 0x00000002
    #define VHE1_MIPS_INT_MASK_SHIFT 1
    #define VBI0_MIPS_INT_MASK_MASK 0x00010000
    #define VBI0_MIPS_INT_MASK_SHIFT 16
    #define VBI1_MIPS_INT_MASK_MASK 0x00020000
    #define VBI1_MIPS_INT_MASK_SHIFT 17
#define  VHE_OUTPUT_IDX 0x5020
    #define VHE0_IDX_MASK 0x0000007F
    #define VHE0_IDX_SHIFT 0
    #define VHE1_IDX_MASK 0x00007F00
    #define VHE1_IDX_SHIFT 8
#define  VHE_STATUS 0x503C
    #define VHE0_DONE_MASK 0x00000001
    #define VHE0_DONE_SHIFT 0
    #define VHE1_DONE_MASK 0x00000002
    #define VHE1_DONE_SHIFT 1
#define  VHE_VBI_IDX 0x5024
    #define VBI0_IDX_MASK 0x000000FF
    #define VBI0_IDX_SHIFT 0
    #define VBI1_IDX_MASK 0x0000FF00
    #define VBI1_IDX_SHIFT 8
#define  VHE_VBI_INT_CTRL 0x5004
    #define VBI0_INT_EN_MASK 0x000000FF
    #define VBI0_INT_EN_SHIFT 0
    #define VBI1_INT_EN_MASK 0x0000FF00
    #define VBI1_INT_EN_SHIFT 8
#define  VHE_Y_CORING 0x5280
    #define Y_CB_CR_LOCKED_MASK 0x00000001
    #define Y_CB_CR_LOCKED_SHIFT 0
    #define VHE_Y_CORING_ENABLE_VBI_MASK 0x00000010
    #define VHE_Y_CORING_ENABLE_VBI_SHIFT 4
    #define VHE_Y_CORING_RANGE_MASK 0x00007F00
    #define VHE_Y_CORING_RANGE_SHIFT 8
    #define VHE_Y_CORING_VALUE_MASK 0x03FF0000
    #define VHE_Y_CORING_VALUE_SHIFT 16
#define  VNE0_BLK_C_MTN_THRESH 0x58B4
    #define VNE0_BLK_C_MTN_THRESH_CB_THRESH_MASK 0x00003FFF
    #define VNE0_BLK_C_MTN_THRESH_CB_THRESH_SHIFT 0
    #define VNE0_BLK_C_MTN_THRESH_CR_THRESH_MASK 0x3FFF0000
    #define VNE0_BLK_C_MTN_THRESH_CR_THRESH_SHIFT 16
#define  VNE0_BLK_Y_MTN_THRESH 0x58B0
    #define VNE0_BLK_Y_MTN_THRESH_Y_THRESH_MASK 0x00003FFF
    #define VNE0_BLK_Y_MTN_THRESH_Y_THRESH_SHIFT 0
#define  VNE0_BUF 0x584C
    #define VNE0_BUF_SRC_SIZE_MASK 0x00007FFF
    #define VNE0_BUF_SRC_SIZE_SHIFT 0
    #define VNE0_BUF_DST_SIZE_MASK 0x7FFF0000
    #define VNE0_BUF_DST_SIZE_SHIFT 16
#define  VNE0_BUF_PITCH 0x5848
    #define VNE0_BUF_PITCH_SRC_PITCH_MASK 0x00000FE0
    #define VNE0_BUF_PITCH_SRC_PITCH_SHIFT 5
    #define VNE0_BUF_PITCH_DST_PITCH_MASK 0x0FE00000
    #define VNE0_BUF_PITCH_DST_PITCH_SHIFT 21
#define  VNE0_BUF_SIZE 0x5844
    #define VNE0_BUF_SIZE_WIDTH_MASK 0x000007FE
    #define VNE0_BUF_SIZE_WIDTH_SHIFT 1
    #define VNE0_BUF_SIZE_HEIGHT_MASK 0x07FE0000
    #define VNE0_BUF_SIZE_HEIGHT_SHIFT 17
#define  VNE0_CB_COMB_ADR 0x5878
    #define VNE0_CB_COMB_ADR_BASE_MASK 0x07FFFFC0
    #define VNE0_CB_COMB_ADR_BASE_SHIFT 6
#define  VNE0_CB_CUR_ADR 0x5854
    #define VNE0_CB_CUR_ADR_BASE_MASK 0x07FFFFC0
    #define VNE0_CB_CUR_ADR_BASE_SHIFT 6
#define  VNE0_CB_DST_ADR 0x5860
    #define VNE0_CB_DST_ADR_BASE_MASK 0x07FFFFC0
    #define VNE0_CB_DST_ADR_BASE_SHIFT 6
#define  VNE0_CB_MTNFLAG_ADR 0x586C
    #define VNE0_CB_MTNFLAG_ADR_BASE_MASK 0x07FFFFC0
    #define VNE0_CB_MTNFLAG_ADR_BASE_SHIFT 6
#define  VNE0_COMB_COEF 0x58D8
    #define VNE0_COMB_COEF_INDEX0_MASK 0x00000003
    #define VNE0_COMB_COEF_INDEX0_SHIFT 0
    #define VNE0_COMB_COEF_INDEX1_MASK 0x00000030
    #define VNE0_COMB_COEF_INDEX1_SHIFT 4
    #define VNE0_COMB_COEF_INDEX2_MASK 0x00000300
    #define VNE0_COMB_COEF_INDEX2_SHIFT 8
    #define VNE0_COMB_COEF_CFLAG_THRESH_MASK 0x000F0000
    #define VNE0_COMB_COEF_CFLAG_THRESH_SHIFT 16
#define  VNE0_COMB_FLAG 0x58D4
    #define VNE0_COMB_FLAG_Y_THRESH_MASK 0x00003FFF
    #define VNE0_COMB_FLAG_Y_THRESH_SHIFT 0
    #define VNE0_COMB_FLAG_C_THRESH_MASK 0x3FFF0000
    #define VNE0_COMB_FLAG_C_THRESH_SHIFT 16
#define  VNE0_CR_COMB_ADR 0x587C
    #define VNE0_CR_COMB_ADR_BASE_MASK 0x07FFFFC0
    #define VNE0_CR_COMB_ADR_BASE_SHIFT 6
#define  VNE0_CR_CUR_ADR 0x5858
    #define VNE0_CR_CUR_ADR_BASE_MASK 0x07FFFFC0
    #define VNE0_CR_CUR_ADR_BASE_SHIFT 6
#define  VNE0_CR_DST_ADR 0x5864
    #define VNE0_CR_DST_ADR_BASE_MASK 0x07FFFFC0
    #define VNE0_CR_DST_ADR_BASE_SHIFT 6
#define  VNE0_CR_MTNFLAG_ADR 0x5870
    #define VNE0_CR_MTNFLAG_ADR_BASE_MASK 0x07FFFFC0
    #define VNE0_CR_MTNFLAG_ADR_BASE_SHIFT 6
#define  VNE0_CTRL 0x5840
    #define VNE0_CTRL_CUR_8_BIT_MASK 0x00000001
    #define VNE0_CTRL_CUR_8_BIT_SHIFT 0
    #define VNE0_CTRL_DST_8_BIT_MASK 0x00000002
    #define VNE0_CTRL_DST_8_BIT_SHIFT 1
    #define VNE0_CTRL_FLD_FORMAT_MASK 0x00000004
    #define VNE0_CTRL_FLD_FORMAT_SHIFT 2
    #define VNE0_CTRL_Y_ONLY_MASK 0x00000010
    #define VNE0_CTRL_Y_ONLY_SHIFT 4
    #define VNE0_CTRL_COMB_DIS_MASK 0x00000020
    #define VNE0_CTRL_COMB_DIS_SHIFT 5
    #define VNE0_CTRL_SF_DIS_MASK 0x00000040
    #define VNE0_CTRL_SF_DIS_SHIFT 6
    #define VNE0_CTRL_TF_DIS_MASK 0x00000080
    #define VNE0_CTRL_TF_DIS_SHIFT 7
    #define VNE0_CTRL_8_TO_10_MASK 0x00000300
    #define VNE0_CTRL_8_TO_10_SHIFT 8
    #define VNE0_CTRL_10_TO_8_MASK 0x00000400
    #define VNE0_CTRL_10_TO_8_SHIFT 10
    #define VNE0_CTRL_FILT_DIS_MASK 0x00000800
    #define VNE0_CTRL_FILT_DIS_SHIFT 11
    #define VNE0_CTRL_ALPHA_EN_MASK 0x00001000
    #define VNE0_CTRL_ALPHA_EN_SHIFT 12
    #define VNE0_CTRL_COMB_Y_DIS_MASK 0x00002000
    #define VNE0_CTRL_COMB_Y_DIS_SHIFT 13
    #define VNE0_CTRL_COMB_C_DIS_MASK 0x00004000
    #define VNE0_CTRL_COMB_C_DIS_SHIFT 14
    #define VNE0_CTRL_MF_PITCH_MASK 0x03F00000
    #define VNE0_CTRL_MF_PITCH_SHIFT 20
#define  VNE0_ED_C_THRESH 0x58CC
    #define VNE0_ED_C_THRESH_CB_THRESH_MASK 0x00003FFF
    #define VNE0_ED_C_THRESH_CB_THRESH_SHIFT 0
    #define VNE0_ED_C_THRESH_CR_THRESH_MASK 0x3FFF0000
    #define VNE0_ED_C_THRESH_CR_THRESH_SHIFT 16
#define  VNE0_ED_Y_THRESH 0x58C8
    #define VNE0_ED_Y_THRESH_Y_THRESH_MASK 0x00003FFF
    #define VNE0_ED_Y_THRESH_Y_THRESH_SHIFT 0
#define  VNE0_IIRCOEF_0_7 0x5890
    #define VNE0_IIRCOEF_0_7_INDEX_0_MASK 0x0000000F
    #define VNE0_IIRCOEF_0_7_INDEX_0_SHIFT 0
    #define VNE0_IIRCOEF_0_7_INDEX_1_MASK 0x000000F0
    #define VNE0_IIRCOEF_0_7_INDEX_1_SHIFT 4
    #define VNE0_IIRCOEF_0_7_INDEX_2_MASK 0x00000F00
    #define VNE0_IIRCOEF_0_7_INDEX_2_SHIFT 8
    #define VNE0_IIRCOEF_0_7_INDEX_3_MASK 0x0000F000
    #define VNE0_IIRCOEF_0_7_INDEX_3_SHIFT 12
    #define VNE0_IIRCOEF_0_7_INDEX_4_MASK 0x000F0000
    #define VNE0_IIRCOEF_0_7_INDEX_4_SHIFT 16
    #define VNE0_IIRCOEF_0_7_INDEX_5_MASK 0x00F00000
    #define VNE0_IIRCOEF_0_7_INDEX_5_SHIFT 20
    #define VNE0_IIRCOEF_0_7_INDEX_6_MASK 0x0F000000
    #define VNE0_IIRCOEF_0_7_INDEX_6_SHIFT 24
    #define VNE0_IIRCOEF_0_7_INDEX_7_MASK 0xF0000000
    #define VNE0_IIRCOEF_0_7_INDEX_7_SHIFT 28
#define  VNE0_IIRCOEF_8_16 0x5894
    #define VNE0_IIRCOEF_8_16_INDEX_8_MASK 0x0000000F
    #define VNE0_IIRCOEF_8_16_INDEX_8_SHIFT 0
    #define VNE0_IIRCOEF_8_16_INDEX_9_MASK 0x000000F0
    #define VNE0_IIRCOEF_8_16_INDEX_9_SHIFT 4
    #define VNE0_IIRCOEF_8_16_INDEX_10_MASK 0x00000F00
    #define VNE0_IIRCOEF_8_16_INDEX_10_SHIFT 8
    #define VNE0_IIRCOEF_8_16_INDEX_11_MASK 0x0000F000
    #define VNE0_IIRCOEF_8_16_INDEX_11_SHIFT 12
    #define VNE0_IIRCOEF_8_16_INDEX_12_MASK 0x000F0000
    #define VNE0_IIRCOEF_8_16_INDEX_12_SHIFT 16
    #define VNE0_IIRCOEF_8_16_INDEX_13_MASK 0x00F00000
    #define VNE0_IIRCOEF_8_16_INDEX_13_SHIFT 20
    #define VNE0_IIRCOEF_8_16_INDEX_14_MASK 0x0F000000
    #define VNE0_IIRCOEF_8_16_INDEX_14_SHIFT 24
    #define VNE0_IIRCOEF_8_16_INDEX_15_MASK 0xF0000000
    #define VNE0_IIRCOEF_8_16_INDEX_15_SHIFT 28
#define  VNE0_MD_C_THRESH 0x58C4
    #define VNE0_MD_C_THRESH_CB_THRESH_MASK 0x00003FFF
    #define VNE0_MD_C_THRESH_CB_THRESH_SHIFT 0
    #define VNE0_MD_C_THRESH_CR_THRESH_MASK 0x3FFF0000
    #define VNE0_MD_C_THRESH_CR_THRESH_SHIFT 16
#define  VNE0_MD_Y_THRESH 0x58C0
    #define VNE0_MD_Y_THRESH_Y_THRESH_MASK 0x00003FFF
    #define VNE0_MD_Y_THRESH_Y_THRESH_SHIFT 0
#define  VNE0_NE_CTRL 0x589C
    #define VNE0_NE_CTRL_BLK_HEIGHT_MASK 0x0000000F
    #define VNE0_NE_CTRL_BLK_HEIGHT_SHIFT 0
#define  VNE0_NE_C_BLK 0x58BC
    #define VNE0_NE_C_BLK_CB_BLK_MASK 0x00007FFF
    #define VNE0_NE_C_BLK_CB_BLK_SHIFT 0
    #define VNE0_NE_C_BLK_CR_BLK_MASK 0x7FFF0000
    #define VNE0_NE_C_BLK_CR_BLK_SHIFT 16
#define  VNE0_NE_ENRGY_C_HI 0x58AC
    #define VNE0_NE_ENRGY_C_HI_CB_ENRGY_MASK 0x0000FFFF
    #define VNE0_NE_ENRGY_C_HI_CB_ENRGY_SHIFT 0
    #define VNE0_NE_ENRGY_C_HI_CR_ENRGY_MASK 0xFFFF0000
    #define VNE0_NE_ENRGY_C_HI_CR_ENRGY_SHIFT 16
#define  VNE0_NE_ENRGY_C_LO 0x58A4
    #define VNE0_NE_ENRGY_C_LO_CB_ENRGY_MASK 0x0000FFFF
    #define VNE0_NE_ENRGY_C_LO_CB_ENRGY_SHIFT 0
    #define VNE0_NE_ENRGY_C_LO_CR_ENRGY_MASK 0xFFFF0000
    #define VNE0_NE_ENRGY_C_LO_CR_ENRGY_SHIFT 16
#define  VNE0_NE_ENRGY_Y_HI 0x58A8
    #define VNE0_NE_ENRGY_Y_HI_Y_ENRGY_MASK 0x0000FFFF
    #define VNE0_NE_ENRGY_Y_HI_Y_ENRGY_SHIFT 0
#define  VNE0_NE_ENRGY_Y_LO 0x58A0
    #define VNE0_NE_ENRGY_Y_LO_Y_ENRGY_MASK 0x0000FFFF
    #define VNE0_NE_ENRGY_Y_LO_Y_ENRGY_SHIFT 0
#define  VNE0_NE_INFO_ADR 0x5880
    #define VNE0_NE_INFO_ADR_BASE_MASK 0x07FFFFC0
    #define VNE0_NE_INFO_ADR_BASE_SHIFT 6
#define  VNE0_NE_Y_BLK 0x58B8
    #define VNE0_NE_Y_BLK_Y_BLK_MASK 0x00007FFF
    #define VNE0_NE_Y_BLK_Y_BLK_SHIFT 0
#define  VNE0_RD_INFO_ADR 0x5884
    #define VNE0_RD_INFO_ADR_BASE_MASK 0x07FFFFC0
    #define VNE0_RD_INFO_ADR_BASE_SHIFT 6
#define  VNE0_SPATCOEF 0x5898
    #define VNE0_SPATCOEF_INDEX_0_MASK 0x0000003F
    #define VNE0_SPATCOEF_INDEX_0_SHIFT 0
    #define VNE0_SPATCOEF_INDEX_1_MASK 0x00003F00
    #define VNE0_SPATCOEF_INDEX_1_SHIFT 8
    #define VNE0_SPATCOEF_INDEX_2_MASK 0x003F0000
    #define VNE0_SPATCOEF_INDEX_2_SHIFT 16
    #define VNE0_SPATCOEF_INDEX_MAX_MASK 0xF0000000
    #define VNE0_SPATCOEF_INDEX_MAX_SHIFT 28
#define  VNE0_SPTL_MTN 0x58D0
    #define VNE0_SPTL_MTN_SAD_THRESH_MASK 0x00001FFF
    #define VNE0_SPTL_MTN_SAD_THRESH_SHIFT 0
    #define VNE0_SPTL_MTN_Y_RATIO0_MASK 0x00030000
    #define VNE0_SPTL_MTN_Y_RATIO0_SHIFT 16
    #define VNE0_SPTL_MTN_Y_RATIO1_MASK 0x000C0000
    #define VNE0_SPTL_MTN_Y_RATIO1_SHIFT 18
    #define VNE0_SPTL_MTN_Y_RATIO2_MASK 0x00300000
    #define VNE0_SPTL_MTN_Y_RATIO2_SHIFT 20
    #define VNE0_SPTL_MTN_C_RATIO0_MASK 0x03000000
    #define VNE0_SPTL_MTN_C_RATIO0_SHIFT 24
    #define VNE0_SPTL_MTN_C_RATIO1_MASK 0x0C000000
    #define VNE0_SPTL_MTN_C_RATIO1_SHIFT 26
    #define VNE0_SPTL_MTN_C_RATIO2_MASK 0x30000000
    #define VNE0_SPTL_MTN_C_RATIO2_SHIFT 28
#define  VNE0_TMP_ADR 0x588C
    #define VNE0_TMP_ADR_BASE_MASK 0x07FFFFC0
    #define VNE0_TMP_ADR_BASE_SHIFT 6
#define  VNE0_WR_INFO_ADR 0x5888
    #define VNE0_WR_INFO_ADR_BASE_MASK 0x07FFFFC0
    #define VNE0_WR_INFO_ADR_BASE_SHIFT 6
#define  VNE0_Y_COMB_ADR 0x5874
    #define VNE0_Y_COMB_ADR_BASE_MASK 0x07FFFFC0
    #define VNE0_Y_COMB_ADR_BASE_SHIFT 6
#define  VNE0_Y_CUR_ADR 0x5850
    #define VNE0_Y_CUR_ADR_BASE_MASK 0x07FFFFC0
    #define VNE0_Y_CUR_ADR_BASE_SHIFT 6
#define  VNE0_Y_DST_ADR 0x585C
    #define VNE0_Y_DST_ADR_BASE_MASK 0x07FFFFC0
    #define VNE0_Y_DST_ADR_BASE_SHIFT 6
#define  VNE0_Y_MTNFLAG_ADR 0x5868
    #define VNE0_Y_MTNFLAG_ADR_BASE_MASK 0x07FFFFC0
    #define VNE0_Y_MTNFLAG_ADR_BASE_SHIFT 6
#define  VNE1_BLK_C_MTN_THRESH 0x59B4
    #define VNE1_BLK_C_MTN_THRESH_CB_THRESH_MASK 0x00003FFF
    #define VNE1_BLK_C_MTN_THRESH_CB_THRESH_SHIFT 0
    #define VNE1_BLK_C_MTN_THRESH_CR_THRESH_MASK 0x3FFF0000
    #define VNE1_BLK_C_MTN_THRESH_CR_THRESH_SHIFT 16
#define  VNE1_BLK_Y_MTN_THRESH 0x59B0
    #define VNE1_BLK_Y_MTN_THRESH_Y_THRESH_MASK 0x00003FFF
    #define VNE1_BLK_Y_MTN_THRESH_Y_THRESH_SHIFT 0
#define  VNE1_BUF 0x594C
    #define VNE1_BUF_SRC_SIZE_MASK 0x00007FFF
    #define VNE1_BUF_SRC_SIZE_SHIFT 0
    #define VNE1_BUF_DST_SIZE_MASK 0x7FFF0000
    #define VNE1_BUF_DST_SIZE_SHIFT 16
#define  VNE1_BUF_PITCH 0x5948
    #define VNE1_BUF_PITCH_SRC_PITCH_MASK 0x00000FE0
    #define VNE1_BUF_PITCH_SRC_PITCH_SHIFT 5
    #define VNE1_BUF_PITCH_DST_PITCH_MASK 0x0FE00000
    #define VNE1_BUF_PITCH_DST_PITCH_SHIFT 21
#define  VNE1_BUF_SIZE 0x5944
    #define VNE1_BUF_SIZE_WIDTH_MASK 0x000007FE
    #define VNE1_BUF_SIZE_WIDTH_SHIFT 1
    #define VNE1_BUF_SIZE_HEIGHT_MASK 0x07FE0000
    #define VNE1_BUF_SIZE_HEIGHT_SHIFT 17
#define  VNE1_CB_COMB_ADR 0x5978
    #define VNE1_CB_COMB_ADR_BASE_MASK 0x07FFFFC0
    #define VNE1_CB_COMB_ADR_BASE_SHIFT 6
#define  VNE1_CB_CUR_ADR 0x5954
    #define VNE1_CB_CUR_ADR_BASE_MASK 0x07FFFFC0
    #define VNE1_CB_CUR_ADR_BASE_SHIFT 6
#define  VNE1_CB_DST_ADR 0x5960
    #define VNE1_CB_DST_ADR_BASE_MASK 0x07FFFFC0
    #define VNE1_CB_DST_ADR_BASE_SHIFT 6
#define  VNE1_CB_MTNFLAG_ADR 0x596C
    #define VNE1_CB_MTNFLAG_ADR_BASE_MASK 0x07FFFFC0
    #define VNE1_CB_MTNFLAG_ADR_BASE_SHIFT 6
#define  VNE1_COMB_COEF 0x59D8
    #define VNE1_COMB_COEF_INDEX0_MASK 0x00000003
    #define VNE1_COMB_COEF_INDEX0_SHIFT 0
    #define VNE1_COMB_COEF_INDEX1_MASK 0x00000030
    #define VNE1_COMB_COEF_INDEX1_SHIFT 4
    #define VNE1_COMB_COEF_INDEX2_MASK 0x00000300
    #define VNE1_COMB_COEF_INDEX2_SHIFT 8
    #define VNE1_COMB_COEF_CFLAG_THRESH_MASK 0x000F0000
    #define VNE1_COMB_COEF_CFLAG_THRESH_SHIFT 16
#define  VNE1_COMB_FLAG 0x59D4
    #define VNE1_COMB_FLAG_Y_THRESH_MASK 0x00003FFF
    #define VNE1_COMB_FLAG_Y_THRESH_SHIFT 0
    #define VNE1_COMB_FLAG_C_THRESH_MASK 0x3FFF0000
    #define VNE1_COMB_FLAG_C_THRESH_SHIFT 16
#define  VNE1_CR_COMB_ADR 0x597C
    #define VNE1_CR_COMB_ADR_BASE_MASK 0x07FFFFC0
    #define VNE1_CR_COMB_ADR_BASE_SHIFT 6
#define  VNE1_CR_CUR_ADR 0x5958
    #define VNE1_CR_CUR_ADR_BASE_MASK 0x07FFFFC0
    #define VNE1_CR_CUR_ADR_BASE_SHIFT 6
#define  VNE1_CR_DST_ADR 0x5964
    #define VNE1_CR_DST_ADR_BASE_MASK 0x07FFFFC0
    #define VNE1_CR_DST_ADR_BASE_SHIFT 6
#define  VNE1_CR_MTNFLAG_ADR 0x5970
    #define VNE1_CR_MTNFLAG_ADR_BASE_MASK 0x07FFFFC0
    #define VNE1_CR_MTNFLAG_ADR_BASE_SHIFT 6
#define  VNE1_CTRL 0x5940
    #define VNE1_CTRL_CUR_8_BIT_MASK 0x00000001
    #define VNE1_CTRL_CUR_8_BIT_SHIFT 0
    #define VNE1_CTRL_DST_8_BIT_MASK 0x00000002
    #define VNE1_CTRL_DST_8_BIT_SHIFT 1
    #define VNE1_CTRL_FLD_FORMAT_MASK 0x00000004
    #define VNE1_CTRL_FLD_FORMAT_SHIFT 2
    #define VNE1_CTRL_Y_ONLY_MASK 0x00000010
    #define VNE1_CTRL_Y_ONLY_SHIFT 4
    #define VNE1_CTRL_COMB_DIS_MASK 0x00000020
    #define VNE1_CTRL_COMB_DIS_SHIFT 5
    #define VNE1_CTRL_SF_DIS_MASK 0x00000040
    #define VNE1_CTRL_SF_DIS_SHIFT 6
    #define VNE1_CTRL_TF_DIS_MASK 0x00000080
    #define VNE1_CTRL_TF_DIS_SHIFT 7
    #define VNE1_CTRL_8_TO_10_MASK 0x00000300
    #define VNE1_CTRL_8_TO_10_SHIFT 8
    #define VNE1_CTRL_10_TO_8_MASK 0x00000400
    #define VNE1_CTRL_10_TO_8_SHIFT 10
    #define VNE1_CTRL_FILT_DIS_MASK 0x00000800
    #define VNE1_CTRL_FILT_DIS_SHIFT 11
    #define VNE1_CTRL_ALPHA_EN_MASK 0x00001000
    #define VNE1_CTRL_ALPHA_EN_SHIFT 12
    #define VNE1_CTRL_COMB_Y_DIS_MASK 0x00002000
    #define VNE1_CTRL_COMB_Y_DIS_SHIFT 13
    #define VNE1_CTRL_COMB_C_DIS_MASK 0x00004000
    #define VNE1_CTRL_COMB_C_DIS_SHIFT 14
    #define VNE1_CTRL_MF_PITCH_MASK 0x03F00000
    #define VNE1_CTRL_MF_PITCH_SHIFT 20
#define  VNE1_ED_C_THRESH 0x59CC
    #define VNE1_ED_C_THRESH_CB_THRESH_MASK 0x00003FFF
    #define VNE1_ED_C_THRESH_CB_THRESH_SHIFT 0
    #define VNE1_ED_C_THRESH_CR_THRESH_MASK 0x3FFF0000
    #define VNE1_ED_C_THRESH_CR_THRESH_SHIFT 16
#define  VNE1_ED_Y_THRESH 0x59C8
    #define VNE1_ED_Y_THRESH_Y_THRESH_MASK 0x00003FFF
    #define VNE1_ED_Y_THRESH_Y_THRESH_SHIFT 0
#define  VNE1_IIRCOEF_0_7 0x5990
    #define VNE1_IIRCOEF_0_7_INDEX_0_MASK 0x0000000F
    #define VNE1_IIRCOEF_0_7_INDEX_0_SHIFT 0
    #define VNE1_IIRCOEF_0_7_INDEX_1_MASK 0x000000F0
    #define VNE1_IIRCOEF_0_7_INDEX_1_SHIFT 4
    #define VNE1_IIRCOEF_0_7_INDEX_2_MASK 0x00000F00
    #define VNE1_IIRCOEF_0_7_INDEX_2_SHIFT 8
    #define VNE1_IIRCOEF_0_7_INDEX_3_MASK 0x0000F000
    #define VNE1_IIRCOEF_0_7_INDEX_3_SHIFT 12
    #define VNE1_IIRCOEF_0_7_INDEX_4_MASK 0x000F0000
    #define VNE1_IIRCOEF_0_7_INDEX_4_SHIFT 16
    #define VNE1_IIRCOEF_0_7_INDEX_5_MASK 0x00F00000
    #define VNE1_IIRCOEF_0_7_INDEX_5_SHIFT 20
    #define VNE1_IIRCOEF_0_7_INDEX_6_MASK 0x0F000000
    #define VNE1_IIRCOEF_0_7_INDEX_6_SHIFT 24
    #define VNE1_IIRCOEF_0_7_INDEX_7_MASK 0xF0000000
    #define VNE1_IIRCOEF_0_7_INDEX_7_SHIFT 28
#define  VNE1_IIRCOEF_8_16 0x5994
    #define VNE1_IIRCOEF_8_16_INDEX_8_MASK 0x0000000F
    #define VNE1_IIRCOEF_8_16_INDEX_8_SHIFT 0
    #define VNE1_IIRCOEF_8_16_INDEX_9_MASK 0x000000F0
    #define VNE1_IIRCOEF_8_16_INDEX_9_SHIFT 4
    #define VNE1_IIRCOEF_8_16_INDEX_10_MASK 0x00000F00
    #define VNE1_IIRCOEF_8_16_INDEX_10_SHIFT 8
    #define VNE1_IIRCOEF_8_16_INDEX_11_MASK 0x0000F000
    #define VNE1_IIRCOEF_8_16_INDEX_11_SHIFT 12
    #define VNE1_IIRCOEF_8_16_INDEX_12_MASK 0x000F0000
    #define VNE1_IIRCOEF_8_16_INDEX_12_SHIFT 16
    #define VNE1_IIRCOEF_8_16_INDEX_13_MASK 0x00F00000
    #define VNE1_IIRCOEF_8_16_INDEX_13_SHIFT 20
    #define VNE1_IIRCOEF_8_16_INDEX_14_MASK 0x0F000000
    #define VNE1_IIRCOEF_8_16_INDEX_14_SHIFT 24
    #define VNE1_IIRCOEF_8_16_INDEX_15_MASK 0xF0000000
    #define VNE1_IIRCOEF_8_16_INDEX_15_SHIFT 28
#define  VNE1_MD_C_THRESH 0x59C4
    #define VNE1_MD_C_THRESH_CB_THRESH_MASK 0x00003FFF
    #define VNE1_MD_C_THRESH_CB_THRESH_SHIFT 0
    #define VNE1_MD_C_THRESH_CR_THRESH_MASK 0x3FFF0000
    #define VNE1_MD_C_THRESH_CR_THRESH_SHIFT 16
#define  VNE1_MD_Y_THRESH 0x59C0
    #define VNE1_MD_Y_THRESH_Y_THRESH_MASK 0x00003FFF
    #define VNE1_MD_Y_THRESH_Y_THRESH_SHIFT 0
#define  VNE1_NE_CTRL 0x599C
    #define VNE1_NE_CTRL_BLK_HEIGHT_MASK 0x0000000F
    #define VNE1_NE_CTRL_BLK_HEIGHT_SHIFT 0
#define  VNE1_NE_C_BLK 0x59BC
    #define VNE1_NE_C_BLK_CB_BLK_MASK 0x00007FFF
    #define VNE1_NE_C_BLK_CB_BLK_SHIFT 0
    #define VNE1_NE_C_BLK_CR_BLK_MASK 0x7FFF0000
    #define VNE1_NE_C_BLK_CR_BLK_SHIFT 16
#define  VNE1_NE_ENRGY_C_HI 0x59AC
    #define VNE1_NE_ENRGY_C_HI_CB_ENRGY_MASK 0x0000FFFF
    #define VNE1_NE_ENRGY_C_HI_CB_ENRGY_SHIFT 0
    #define VNE1_NE_ENRGY_C_HI_CR_ENRGY_MASK 0xFFFF0000
    #define VNE1_NE_ENRGY_C_HI_CR_ENRGY_SHIFT 16
#define  VNE1_NE_ENRGY_C_LO 0x59A4
    #define VNE1_NE_ENRGY_C_LO_CB_ENRGY_MASK 0x0000FFFF
    #define VNE1_NE_ENRGY_C_LO_CB_ENRGY_SHIFT 0
    #define VNE1_NE_ENRGY_C_LO_CR_ENRGY_MASK 0xFFFF0000
    #define VNE1_NE_ENRGY_C_LO_CR_ENRGY_SHIFT 16
#define  VNE1_NE_ENRGY_Y_HI 0x59A8
    #define VNE1_NE_ENRGY_Y_HI_Y_ENRGY_MASK 0x0000FFFF
    #define VNE1_NE_ENRGY_Y_HI_Y_ENRGY_SHIFT 0
#define  VNE1_NE_ENRGY_Y_LO 0x59A0
    #define VNE1_NE_ENRGY_Y_LO_Y_ENRGY_MASK 0x0000FFFF
    #define VNE1_NE_ENRGY_Y_LO_Y_ENRGY_SHIFT 0
#define  VNE1_NE_INFO_ADR 0x5980
    #define VNE1_NE_INFO_ADR_BASE_MASK 0x07FFFFC0
    #define VNE1_NE_INFO_ADR_BASE_SHIFT 6
#define  VNE1_NE_Y_BLK 0x59B8
    #define VNE1_NE_Y_BLK_Y_BLK_MASK 0x00007FFF
    #define VNE1_NE_Y_BLK_Y_BLK_SHIFT 0
#define  VNE1_RD_INFO_ADR 0x5984
    #define VNE1_RD_INFO_ADR_BASE_MASK 0x07FFFFC0
    #define VNE1_RD_INFO_ADR_BASE_SHIFT 6
#define  VNE1_SPATCOEF 0x5998
    #define VNE1_SPATCOEF_INDEX_0_MASK 0x0000003F
    #define VNE1_SPATCOEF_INDEX_0_SHIFT 0
    #define VNE1_SPATCOEF_INDEX_1_MASK 0x00003F00
    #define VNE1_SPATCOEF_INDEX_1_SHIFT 8
    #define VNE1_SPATCOEF_INDEX_2_MASK 0x003F0000
    #define VNE1_SPATCOEF_INDEX_2_SHIFT 16
    #define VNE1_SPATCOEF_INDEX_MAX_MASK 0xF0000000
    #define VNE1_SPATCOEF_INDEX_MAX_SHIFT 28
#define  VNE1_SPTL_MTN 0x59D0
    #define VNE1_SPTL_MTN_SAD_THRESH_MASK 0x00001FFF
    #define VNE1_SPTL_MTN_SAD_THRESH_SHIFT 0
    #define VNE1_SPTL_MTN_Y_RATIO0_MASK 0x00030000
    #define VNE1_SPTL_MTN_Y_RATIO0_SHIFT 16
    #define VNE1_SPTL_MTN_Y_RATIO1_MASK 0x000C0000
    #define VNE1_SPTL_MTN_Y_RATIO1_SHIFT 18
    #define VNE1_SPTL_MTN_Y_RATIO2_MASK 0x00300000
    #define VNE1_SPTL_MTN_Y_RATIO2_SHIFT 20
    #define VNE1_SPTL_MTN_C_RATIO0_MASK 0x03000000
    #define VNE1_SPTL_MTN_C_RATIO0_SHIFT 24
    #define VNE1_SPTL_MTN_C_RATIO1_MASK 0x0C000000
    #define VNE1_SPTL_MTN_C_RATIO1_SHIFT 26
    #define VNE1_SPTL_MTN_C_RATIO2_MASK 0x30000000
    #define VNE1_SPTL_MTN_C_RATIO2_SHIFT 28
#define  VNE1_TMP_ADR 0x598C
    #define VNE1_TMP_ADR_BASE_MASK 0x07FFFFC0
    #define VNE1_TMP_ADR_BASE_SHIFT 6
#define  VNE1_WR_INFO_ADR 0x5988
    #define VNE1_WR_INFO_ADR_BASE_MASK 0x07FFFFC0
    #define VNE1_WR_INFO_ADR_BASE_SHIFT 6
#define  VNE1_Y_COMB_ADR 0x5974
    #define VNE1_Y_COMB_ADR_BASE_MASK 0x07FFFFC0
    #define VNE1_Y_COMB_ADR_BASE_SHIFT 6
#define  VNE1_Y_CUR_ADR 0x5950
    #define VNE1_Y_CUR_ADR_BASE_MASK 0x07FFFFC0
    #define VNE1_Y_CUR_ADR_BASE_SHIFT 6
#define  VNE1_Y_DST_ADR 0x595C
    #define VNE1_Y_DST_ADR_BASE_MASK 0x07FFFFC0
    #define VNE1_Y_DST_ADR_BASE_SHIFT 6
#define  VNE1_Y_MTNFLAG_ADR 0x5968
    #define VNE1_Y_MTNFLAG_ADR_BASE_MASK 0x07FFFFC0
    #define VNE1_Y_MTNFLAG_ADR_BASE_SHIFT 6
#define  VNE_DEBUG_STAT 0x5820
    #define DEBUG_BUS_MASK 0x000FFFFF
    #define DEBUG_BUS_SHIFT 0
#define  VNE_DUMMY_REG 0x5830
    #define VNE_DUMMY_REG_DUMMY_BITS_MASK 0xFFFFFFFF
    #define VNE_DUMMY_REG_DUMMY_BITS_SHIFT 0
#define  VNE_FIFO_CMD 0x5810
    #define FLD_CUR_IDX_MASK 0x0000000F
    #define FLD_CUR_IDX_SHIFT 0
    #define FLD_FWD_IDX_MASK 0x000000F0
    #define FLD_FWD_IDX_SHIFT 4
    #define FLD_FFD_IDX_MASK 0x00000F00
    #define FLD_FFD_IDX_SHIFT 8
    #define FLD_PRV_IDX_MASK 0x0000F000
    #define FLD_PRV_IDX_SHIFT 12
    #define FLD_DST_IDX_MASK 0x000F0000
    #define FLD_DST_IDX_SHIFT 16
    #define MF_SRC_IDX_MASK 0x00700000
    #define MF_SRC_IDX_SHIFT 20
    #define MF_DST_IDX_MASK 0x03800000
    #define MF_DST_IDX_SHIFT 23
    #define COMB_IDX_MASK 0x0C000000
    #define COMB_IDX_SHIFT 26
    #define MFLAG_INIT_MASK 0x10000000
    #define MFLAG_INIT_SHIFT 28
    #define VNE_FIFO_CMD_UPDATE_MASK 0x20000000
    #define VNE_FIFO_CMD_UPDATE_SHIFT 29
    #define VNE_FIFO_CMD_STREAM_MASK 0xC0000000
    #define VNE_FIFO_CMD_STREAM_SHIFT 30
#define  VNE_HOST_INT_MASK 0x5808
    #define VNE0_HOST_INT_MASK_MASK 0x00000001
    #define VNE0_HOST_INT_MASK_SHIFT 0
    #define VNE1_HOST_INT_MASK_MASK 0x00000002
    #define VNE1_HOST_INT_MASK_SHIFT 1
#define  VNE_INT_CTRL 0x5800
    #define VNE0_INT_EN_MASK 0x000000FF
    #define VNE0_INT_EN_SHIFT 0
    #define VNE1_INT_EN_MASK 0x0000FF00
    #define VNE1_INT_EN_SHIFT 8
#define  VNE_INT_STATUS 0x5804
    #define VNE0_INT_MASK 0x00000001
    #define VNE0_INT_SHIFT 0
    #define VNE1_INT_MASK 0x00000002
    #define VNE1_INT_SHIFT 1
#define  VNE_MIPS_INT_MASK 0x580C
    #define VNE0_MIPS_INT_MASK_MASK 0x00000001
    #define VNE0_MIPS_INT_MASK_SHIFT 0
    #define VNE1_MIPS_INT_MASK_MASK 0x00000002
    #define VNE1_MIPS_INT_MASK_SHIFT 1
#define  VNE_PWR_CTRL 0x5818
    #define VNE_RST_SOFT_MASK 0x00000001
    #define VNE_RST_SOFT_SHIFT 0
    #define CF_FLUSH_MASK 0x00000100
    #define CF_FLUSH_SHIFT 8
#define  VNE_STATUS 0x5814
    #define VNE_STATUS_FIFO_FREE_MASK 0x0000001F
    #define VNE_STATUS_FIFO_FREE_SHIFT 0
    #define STRM0_BUSY_MASK 0x00000100
    #define STRM0_BUSY_SHIFT 8
    #define STRM1_BUSY_MASK 0x00000200
    #define STRM1_BUSY_SHIFT 9
    #define STRM0_IDX_MASK 0x000F0000
    #define STRM0_IDX_SHIFT 16
    #define STRM1_IDX_MASK 0x00F00000
    #define STRM1_IDX_SHIFT 20
    #define VNE_BUSY_MASK 0x80000000
    #define VNE_BUSY_SHIFT 31
#endif
